US3543239A - Frequency responsive anticoincident remote control system - Google Patents

Frequency responsive anticoincident remote control system Download PDF

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US3543239A
US3543239A US656150A US3543239DA US3543239A US 3543239 A US3543239 A US 3543239A US 656150 A US656150 A US 656150A US 3543239D A US3543239D A US 3543239DA US 3543239 A US3543239 A US 3543239A
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control
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Jacob L Wallace Jr
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Susquehanna Corp
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    • GPHYSICS
    • G08SIGNALLING
    • G08CTRANSMISSION SYSTEMS FOR MEASURED VALUES, CONTROL OR SIMILAR SIGNALS
    • G08C19/00Electric signal transmission systems
    • G08C19/12Electric signal transmission systems in which the signal transmitted is frequency or phase of ac
    • G08C19/14Electric signal transmission systems in which the signal transmitted is frequency or phase of ac using combination of fixed frequencies

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  • the present invention provides an improved remote control system which is responsive to the receipt and detection of multi-frequency signals.
  • the system contains a plurality of channels, each of which is capable of providing an output control signal in response to a particular multi-frequency signal.
  • An interlock is provided between the channels so that all channels are prevented from providing output control signals when more than a predetermined number of channels are actuated in response to multi-frequ ency signals.
  • a significant advantage of the present invention is the marked improvement in security in a remote control system.
  • the interlock functions to prevent any channel from operating.
  • the present invention also guards against transmission errors originating at the control station. If more than one signal is transmitted and is subsequently received and processed, the interlock will again prevent any channel from operating. The equipment being controlled remains unaffected. This technique avoids improper operation caused by What might be a false signal. Similarly, if a true input signal arrives simultaneously with a false signal, the interlock will again block all channels. Once again the equipment being controlled will await the receipt and processing of a true signal unaccompanied by such a false signal.
  • the interlock is designed to permit simultaneous outputs from those channels where such outputs are desired; however, if any other channel attempts to provide an output in response to incoming signals, then all channels are blocked by the action of the interlock.
  • an object of the present invention is to provide an improved multi-channel remote control sys tem which is responsive to multi-frequency signals.
  • Another object of the present invention is to provide such a system having improved interlocking means between the channels of said system.
  • a further object of the invention is to provide such a system having an improved interlocking means between the channels of said system for effectively preventing outputs from all said channels when more than a prede termined number of channels attempt to respond to the incoming multi-frequency signals.
  • Still another object of the present invention is to provide such a system having improved interlocking means between the channels of said system for effectively preventing outputs from all channels when simultaneous input signals are present but which thereafter permits a true input signal to activate the responsive control channel.
  • FIG. 1 is an embodiment of the invention in block diagram form showing a two-channel system including interlocking means
  • FIGS. 2 and 3 are additional embodiments of the present invention, also in block diagram form, showing additional control system arrangements including their interlocking means.
  • FIG. 1 there is shown a remote control system for receiving multi-frequency input control signals and having two output control channels indicated generally by the arrows 10 and 12.
  • the input signals to the remote control system which can be applied by any preferred means such as a wire or radio link, are received at amplifier 14.
  • AGC feedback can be provided at amplifier 14 to put its output at a substantially constant level.
  • Connected to the output of the amplifier 14 are three filters 16, 18 and 20, each of which is designed to selectively pass one frequency in the incoming signal.
  • the output of these three filters are connected respectively to detectors 22, 24 and 26.
  • the output of each of these detectors is a DC level. If desired, voltage doublets or amplifiers (not shown) can be connected to the output of the detectors to increase the DC level.
  • Each of the channels and 12 has at its input a coincidence or AND gate 28 and 30, respectively.
  • the two inputs to AND gate 28 are connected from the outputs of detectors 22 and 24.
  • the output of AND gate 28 is connected to one input of another AND gate 32, and the output of this latter AND gate is connected to amplifier 34.
  • the output control signal for channel 10 is taken from the output of amplifier 34.
  • AND gate 30 is applied to one input of AND gate 36, and the output of this latter AND gate is applied to amplifier 38.
  • the output control signal from control channel 12 is taken at the output of amplifier 38.
  • An interlock is provided between channels 10 and 12. This is accomplished by connecting the output of AND gate 28 in channel 10 via line 40 to the inhibit input of AND gate 36 in channel 12. Likewise, the output of AND gate 30 in channel 12 is applied as an inhibit input via line 42 to AND gate 32 in channel 10.
  • control channel 10 is designed to provide an output control signal from amplifier 34 when the control system receives and processes an input control signal containing frequencies f1 and f2.
  • control channel 12 is designed to be responsive to the receipt of input signals containing frequencies f2 and 3 in order to provide an output control signal from amplifier 38.
  • an input control signal is generated remotely by means not shown and applied to the system of FIG. 1.
  • This signal contains the frequencies f1 and f2.
  • These signals are amplified at 10 and applied to all three filter circuits 16, 18, and 20. However, only the filter circuits 16 and 18 respond, respectively, to the frequencies f1 and f2; and accordingly, these frequencies are applied to detectors 22 and 24.
  • a delay circuit can be imposed in each channel after the AND gates 32 and 36 to provide a slight delay to prevent actuation of any channel by shortterm signals.
  • the system of FIG. 1 has found particular utility with pre-pay, coin-operated telephones.
  • the coins are deposited at the beginning of the call but are not collected at that time.
  • the operator back at the central oflice sends a signal on the telephone line to collect the coins.
  • this signal contains the frequencies f1 and 2
  • channel 10 responds to this multi-frequency signal to provide an output control signal to collect the coins.
  • the operator can transmit a control signal containing the frequencies f2 and 3.
  • channel 12 responds to this multi-frequency signal and provides an output control signal which will actuate the coin-return mechanism.
  • the interlocking arrangement effectively guards against the inadvertent or improper collection or return of the coins.
  • FIG. 2 there is shown a four-channel control system.
  • the input and output amplifiers have not been shown but can, of course, be included if the signal-level conditions so dictate.
  • six frequencies are used to control the four channels 50, 52, 54, and 56.
  • Each channel is here made responsive to input control signals formed of three frequencies.
  • the interlocking arrangement has been expanded to accommodate the increased number of channels.
  • Input signals are applied to the six filters 58a through 58], and the output of each filter is applied to detectors 60a through 60 respectively.
  • Each control channel is again headed by an AND gate 62, 64, 66, 68.
  • the output of AND gate 62 is applied to the input of a second AND gate 70.
  • the output of AND gate 64 is applied to the input of a second gate 72.
  • the output of AND gate 66 is applied to gate 74; and in channel 56, the output of AND gate 68 is applied to gate 76.
  • the output control signals come from these second gates and are used to perform the desired control functions.
  • Each of the AND gates at the beginning of each channel has three inputs and thus makes each channel responsive to the reception of three-frequencies in the incoming control signal. If the incoming control signals contain frequencies f1, f2, and f3, AND gate 62 opens and channel 5 0 responds. Similarly, channel 52 responds to the reception of frequencies f2, f3, and f4; channel 54 responds to the reception of frequencies f4, f5, and f6; and channel 56 responds to the reception of frequencies f1, f5, and f6 in the incoming signals.
  • each of the AND gates 62, 64, 66 and 68 is applied as in inhibit input to each of the second gates 70, 72, 74, and 76, other than the second gate in its own channel.
  • channel 56 is actuated due to the reception of frequencies 11, f5, and f6, the inhibit input out of AND gate 68 prevents any out put signals from being generated in the other three channels 50, 52, and 54.
  • AND gate 66 now opens and an inhibit input is applied by this AND gate to the gates 70, 72, and 76.
  • Channel 56 thus also becomes inhibited, and no output signal is thereafter derived from any channel in the system so long as both AND gates remain open.
  • FIG. 3 four frequencies are used to actuate four output control channels.
  • the input and output amplifiers have again for brevity been omitted from the drawing.
  • the four channels 80, 82, 84, and 86 are headed by AND gates 88, 90, 92, and 94, respectively.
  • Channel 80 is responsive to the receipt of frequencies f1 and 2 in the incoming remote. control signals.
  • Channel 82 is responsive to the receipt of frequencies 2 and f3 in such signals.
  • Channel 84 is responsive to the receipt of frequencies f1 and f4; and channel 86 is responsive to the receipt of frequencies f3 and f4.
  • the multi-channel control system of FIG. 3 is designed to permit simultaneous outputs from channels 80 and 82 without actuating the interlocking arrangement.
  • the second set of AND gates 96, 98, 100, and 102 each of which is connected to the output of the AND gate in its associated channel.
  • the output of AND gates 88 and 90 are also connected via lines 104 and 106 to OR gate 108, and the output of this OR gate is connected as an inhibit input to each of the gates 100 and 102 in channels 84 and 86, respectively.
  • the output of AND gates 92 and 94 are connected via lines 110 and 112 to OR gate 114, with the output of this OR gate being connected as an inhibit input to the gates 96 and 98 in channels 80 and 82, respectively.
  • the output of AND gate 92 is also connected as an additional inhibit input to the gate 102 of channel 86, and the output of AND gate 94 is connected as an additional inhibit input to the gate 100 in channel 84.
  • channels 84 and 86 only will be inhibited from passing a control signal because there is no interlock between channel 80 and 82.
  • channel 80 is actuated due to the receipt of the frequency pair to which AND gate 88 is responsive, an inhibit input is applied from AND gate 88 by line 104 and OR gate 108 to the inhibit inputs of gates 100 and 102 in channels 84 and 86, respectively.
  • no inhibit input is applied to channel 82.
  • AND gate 90 opens, and an output control signal is provided by channel 82 simultaneously with that of channel 80.
  • control channel 84 or 86 In the situation where either control channel 84 or 86 is actuated in response to receipt of its frequency pair, then the interlock functions as in FIGS. 1 and 2. In-
  • hibit inputs are applied to the other three channels to prevent their actuation and control signals emanate from only one channel. For example, if AND gate 92 is open by virtue of frequencies )1 and f4 being present in the incoming control signals, channel 84 is actuated; and an inhibit signal is applied to channel 86 at gate 102, and to the two channels and 82 through OR gate 114 to the inhibit inputs of gates 96 and 98. An output control signal is obtianed only from channel 84. If any of the other three AND gates becomes enabled by virtue of its two critical frequencies appearing in the input signal, channel 84 will also be restrained from passing any further output control signals due to the inhibiting of gate 100. In such case, no output control signals are derived from the system.
  • a remote control system responsive to the input of multi-frequency signals comprising a plurality of control channels, means at the input of each control channel which is actuated in response to the simultaneous receipt by said system of a predetermined input multi-frequency signal for providing an output control signal, means for inhibiting the generation of output control signals from all channels upon receipt by said system of input signals containing frequencies which would actuate greater than a predetermined number of control channels, gating means in each control channel, said inhibiting means including interconnections between each control channel input means and selected gating means in the other chan nels, which upon receipt of normal multi-frequency input signals by said remote control system become effective to inhibit the actuation of said gating means except in predetermined control channels, and upon receipt of abnormal input signals by said remote control system which would actuate greater than the predetermined number of control channels become effective to inhibit the actuation of said gating means in all of said control channels.
  • a remote control system as claimed in claim 1 wherein there are 12 control channels and the input signals contain m selective frequencies, and each of said control channels is responsive to a pair of said m frequencies.
  • a remote control system as claimed in claim 2 further comprising in means for selecting signals of one of said In frequencies and means for detecting the output of each said selecting means to provide a DC level input to said control channels.
  • each said control channel input means is formed as a coincidence gate, the input to each coincidence gate being connected to the output of two of said detecting means, each coincidence gate being enabled upon receipt of DC output signals from said detecting means, thereby to actuate the associated control channel to provide an output control signal.
  • a remote control system as claimed in claim 4 wherein n 2 and m
  • 3, and said inhibiting means in each channel connects the output of its associated coincidence gate as an inhibit input to the gating means in the other channel.
  • a remote control system responsive to the'input of multi-frequency signals comprising at least three control channels, each of said control channels responsive to the simultaneous receipt of at least two predetermined fre quencies, means for inhibiting the generation of output control signals from all of said channels upon receipt by said system of input signals containing frequencies which would actuate greater than one channel, a gate in each control channel, said inhibiting means including interconnections between each channel and the gate in selected ones of said other channels, said inhibiting means being effective to inhibit enabling of each said gate except the gate in one control channel during receipt of normal multi-frequency input signals, and being effective to inhibit the actuation of all said gates in all control channels upon receipt of multi-frequency input signals which would actuate greater than one control channel.

Description

Nov. 24, 1970 WALLACE, JR 3,543,239
- FREQUENCY RESPONSIVE ANTICOINCIDENT REMOTE CONTROL SYSTEM .Filed July 26, 1967 AND KIA/D AND Z 4 zrzrxr k M; 7 fi m k kakofi rum/mi u w m F F F 7% M 5 AND AND AND 68 'DET'.
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United States Patent Oificc 3,543,239 Patented Nov. 24, 1970 3,543,239 FREQUENCY RESPONSIVE ANTICOINCIDENT REMOTE CONTROL SYSTEM Jacob L. Wallace, Jr., Springfield, Va., assignor to The Susquehanna Corporation, a corporation of Delaware Filed July 26, 1967, Ser. No. 656,150 Int. Cl. H04q 9/00 U.S. Cl. 340-171 8 Claims ABSTRACT OF THE DISCLOSURE BACKGROUND OF THE INVENTION The present invention relates to a system for controlling remote apparatus by the receipt and detection of multifrequency signals.
It is a common practice to use multi-frequency signals, such as frequency pairs, to control the remote operation of various equipment, as desired. In such situations the control system at the remote station is made selectively responsive to the frequency pairs to produce the desired remote function. For satisfactory operation this remote system must provide a high degree of discrimination against spurious signals such as noise or abnormal transmission.
While the use of multi-frequency signals in itself lends some security, it has sometimes been the practice to provide additional circuitry to guard against false operation due to spurious signals. In its simplest form, where there is a single control channel responsive to the receipt and detection of two frequencies, a third frequency detector is used which blocks the control channel in response to spurious signals containing all three frequencies. This design is shown in US. Pat. No. 2,513,342. In a multichannel system, there has been proposed a detection system which requires a timed and sequential arrival of two frequencies to provide an output from any one channel. This approach is taught by US. Pat. No. 3,057,964.
There are other techniques available but none so far have been directed to providing an effective interlock against the energization of a plurality of channels in a multi-channel control system. More particularly, in a multi-channel control system, when a plurality of frequency pairs cause control signals to attempt to emanate from more than the desired number of channels, none of the prior art techniques presents an effective way to prevent such control signals from emanating from any channel in the system.
SUMMARY OF THE INVENTION The present invention provides an improved remote control system which is responsive to the receipt and detection of multi-frequency signals. The system contains a plurality of channels, each of which is capable of providing an output control signal in response to a particular multi-frequency signal. An interlock is provided between the channels so that all channels are prevented from providing output control signals when more than a predetermined number of channels are actuated in response to multi-frequ ency signals.
A significant advantage of the present invention is the marked improvement in security in a remote control system. In the event that spurious signals are received and processed and attempt to activate more than one channel, the interlock functions to prevent any channel from operating. The present invention also guards against transmission errors originating at the control station. If more than one signal is transmitted and is subsequently received and processed, the interlock will again prevent any channel from operating. The equipment being controlled remains unaffected. This technique avoids improper operation caused by What might be a false signal. Similarly, if a true input signal arrives simultaneously with a false signal, the interlock will again block all channels. Once again the equipment being controlled will await the receipt and processing of a true signal unaccompanied by such a false signal.
In some multi-channel remote control systems, there is a need for simultaneous outputs from certain channels as where compatible control functions need to be effected. However, control signals from other channels would at this time be undesirable. The advantages afforded by this invention apply equally as well to this type of remote control arrangement. The interlock is designed to permit simultaneous outputs from those channels where such outputs are desired; however, if any other channel attempts to provide an output in response to incoming signals, then all channels are blocked by the action of the interlock.
Accordingly, an object of the present invention is to provide an improved multi-channel remote control sys tem which is responsive to multi-frequency signals.
Another object of the present invention is to provide such a system having improved interlocking means between the channels of said system.
A further object of the invention is to provide such a system having an improved interlocking means between the channels of said system for effectively preventing outputs from all said channels when more than a prede termined number of channels attempt to respond to the incoming multi-frequency signals.
Still another object of the present invention is to provide such a system having improved interlocking means between the channels of said system for effectively preventing outputs from all channels when simultaneous input signals are present but which thereafter permits a true input signal to activate the responsive control channel.
Other objects and advantages of the present invention will become apparent from a reading of the following specification in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an embodiment of the invention in block diagram form showing a two-channel system including interlocking means; and
FIGS. 2 and 3 are additional embodiments of the present invention, also in block diagram form, showing additional control system arrangements including their interlocking means.
DESCRIPTION OF THE PREFERRED EMBODIMENT In FIG. 1 there is shown a remote control system for receiving multi-frequency input control signals and having two output control channels indicated generally by the arrows 10 and 12. The input signals to the remote control system, which can be applied by any preferred means such as a wire or radio link, are received at amplifier 14. AGC feedback can be provided at amplifier 14 to put its output at a substantially constant level. Connected to the output of the amplifier 14 are three filters 16, 18 and 20, each of which is designed to selectively pass one frequency in the incoming signal. The output of these three filters are connected respectively to detectors 22, 24 and 26. The output of each of these detectors is a DC level. If desired, voltage doublets or amplifiers (not shown) can be connected to the output of the detectors to increase the DC level.
Each of the channels and 12 has at its input a coincidence or AND gate 28 and 30, respectively. In channel 10, the two inputs to AND gate 28 are connected from the outputs of detectors 22 and 24. The output of AND gate 28 is connected to one input of another AND gate 32, and the output of this latter AND gate is connected to amplifier 34. The output control signal for channel 10 is taken from the output of amplifier 34.
In channel 12, the inputs to AND gate are taken from the output of detectors 24 and 26. The output of AND gate 30 is applied to one input of AND gate 36, and the output of this latter AND gate is applied to amplifier 38. The output control signal from control channel 12 is taken at the output of amplifier 38.
An interlock is provided between channels 10 and 12. This is accomplished by connecting the output of AND gate 28 in channel 10 via line 40 to the inhibit input of AND gate 36 in channel 12. Likewise, the output of AND gate 30 in channel 12 is applied as an inhibit input via line 42 to AND gate 32 in channel 10.
In the operation of FIG. 1, control channel 10 is designed to provide an output control signal from amplifier 34 when the control system receives and processes an input control signal containing frequencies f1 and f2. Similarly, control channel 12 is designed to be responsive to the receipt of input signals containing frequencies f2 and 3 in order to provide an output control signal from amplifier 38. Assuming that a control function is desired to be eifected by channel 10, an input control signal is generated remotely by means not shown and applied to the system of FIG. 1. This signal contains the frequencies f1 and f2. These signals are amplified at 10 and applied to all three filter circuits 16, 18, and 20. However, only the filter circuits 16 and 18 respond, respectively, to the frequencies f1 and f2; and accordingly, these frequencies are applied to detectors 22 and 24. The outputs from these two detectors are applied to AND gate 28 to open this gate, and the output of this gate is now applied to the input of AND gate 32. Because the output of AND gate 30 in channel 12 is unchanged, AND gate 32 is enabled and a signal will pass to amplifier 34 and from this amplifier to effect the desired control function.
Thus, in response to the application of a control signal containing frequencies f1 and 2, only channel 10 will respond to provide the desired output control signal. Note that with AND gate 28 open, an inhibit input is applied via line 40 to AND gate 36. This inhibits the operation of AND gate 36, and thereby channel 12, in the event that AND gate 30 should open While control channel 10 is actuated.
Assume now that a spurious signal containing the frequency 73 appears at the input to the remote control system. This signal is amplified in amplifier 14 and frequency f3 passes through filter 3 to detector 26. The output of detector 26 is applied to AND gate 30. Because the output of detector 24 is now at a DC level, AND gate 30 is enabled and applies an output to AND gate 36. However, with an inhibit signal present at the inhibit input of this AND gate, the output from AND gate 30 is prevented from passing through AND gate 36. Thus, no output control signal is derived from channel 12. Furthermore, with AND gate 30 now open an inhibit signal is applied via line 42 to the inhibit input of AND gate 32. Gate 32 will close and no further signals can pass at this time. The output control signal at amplifier 34 will terminate. Thus, the interlock feature is effective to block outputs from both of the channels 10 and 12.
Assuming next that neither channel 10 or 12 is actuated, and that input signals containing all three frequencies 1, f2, and 13 are simultaneously applied to amplifier 14. This type of signal can be the result of noise, faulty operation of the transmission equipment, or caused by other reasons. In any event, the filter circuits each pass their frequency causing each of the three detectors to generate a DC output level. The result is that both of the AND gates 28 and 30 are opened, and apply a signal to AND gates 32 and 36, respectively. However, the output of AND gate 28 in channel 10 inhibits AND gate 36 in channel 12 while AND gate 30 in that channel simultaneously inhibits AND gate 32 in channel 10. The result is that this interlock successfully blocks any output from the remote control system.
The blocking of all channels by the interlock when more than one channel attempts to actuate, prevents the system from responding to what might be a false signal. Once the false signal terminates, the system is then again in condition to respond to a true signal, when it is applied. If desired, a delay circuit can be imposed in each channel after the AND gates 32 and 36 to provide a slight delay to prevent actuation of any channel by shortterm signals.
The system of FIG. 1 has found particular utility with pre-pay, coin-operated telephones. In such telephones the coins are deposited at the beginning of the call but are not collected at that time. Once the call is completed, the operator back at the central oflice sends a signal on the telephone line to collect the coins. Assuming this signal contains the frequencies f1 and 2, channel 10 responds to this multi-frequency signal to provide an output control signal to collect the coins. Alternatively, if the call is not completed, the operator can transmit a control signal containing the frequencies f2 and 3. In this case, channel 12 responds to this multi-frequency signal and provides an output control signal which will actuate the coin-return mechanism. The interlocking arrangement effectively guards against the inadvertent or improper collection or return of the coins.
In FIG. 2 there is shown a four-channel control system. In this figure the input and output amplifiers have not been shown but can, of course, be included if the signal-level conditions so dictate. In this embodiment six frequencies are used to control the four channels 50, 52, 54, and 56. Each channel is here made responsive to input control signals formed of three frequencies. The interlocking arrangement has been expanded to accommodate the increased number of channels.
Input signals are applied to the six filters 58a through 58], and the output of each filter is applied to detectors 60a through 60 respectively. Each control channel is again headed by an AND gate 62, 64, 66, 68. In channel 50 the output of AND gate 62 is applied to the input of a second AND gate 70. In channel 52 the output of AND gate 64 is applied to the input of a second gate 72. In channel 54, the output of AND gate 66 is applied to gate 74; and in channel 56, the output of AND gate 68 is applied to gate 76. The output control signals come from these second gates and are used to perform the desired control functions.
Each of the AND gates at the beginning of each channel has three inputs and thus makes each channel responsive to the reception of three-frequencies in the incoming control signal. If the incoming control signals contain frequencies f1, f2, and f3, AND gate 62 opens and channel 5 0 responds. Similarly, channel 52 responds to the reception of frequencies f2, f3, and f4; channel 54 responds to the reception of frequencies f4, f5, and f6; and channel 56 responds to the reception of frequencies f1, f5, and f6 in the incoming signals.
If the incoming signals due to noise, interference, faulty transmission, or any other reason, contain frequencies to which more than one channel is responsive, the interlock feature described with regard to FIG. 1 above again comes into play to block outputs from all channels. To this end, the output of each of the AND gates 62, 64, 66 and 68 is applied as in inhibit input to each of the second gates 70, 72, 74, and 76, other than the second gate in its own channel. Thus, if channel 56 is actuated due to the reception of frequencies 11, f5, and f6, the inhibit input out of AND gate 68 prevents any out put signals from being generated in the other three channels 50, 52, and 54. If at this time frequency f4 appears, at the input, AND gate 66 now opens and an inhibit input is applied by this AND gate to the gates 70, 72, and 76. Channel 56 thus also becomes inhibited, and no output signal is thereafter derived from any channel in the system so long as both AND gates remain open.
In FIG. 3, four frequencies are used to actuate four output control channels. In this embodiment the input and output amplifiers have again for brevity been omitted from the drawing. The four channels 80, 82, 84, and 86 are headed by AND gates 88, 90, 92, and 94, respectively. Channel 80 is responsive to the receipt of frequencies f1 and 2 in the incoming remote. control signals. Channel 82 is responsive to the receipt of frequencies 2 and f3 in such signals. Channel 84 is responsive to the receipt of frequencies f1 and f4; and channel 86 is responsive to the receipt of frequencies f3 and f4.
The multi-channel control system of FIG. 3 is designed to permit simultaneous outputs from channels 80 and 82 without actuating the interlocking arrangement. To this end there is again provided the second set of AND gates 96, 98, 100, and 102, each of which is connected to the output of the AND gate in its associated channel. The output of AND gates 88 and 90 are also connected via lines 104 and 106 to OR gate 108, and the output of this OR gate is connected as an inhibit input to each of the gates 100 and 102 in channels 84 and 86, respectively. The output of AND gates 92 and 94 are connected via lines 110 and 112 to OR gate 114, with the output of this OR gate being connected as an inhibit input to the gates 96 and 98 in channels 80 and 82, respectively. The output of AND gate 92 is also connected as an additional inhibit input to the gate 102 of channel 86, and the output of AND gate 94 is connected as an additional inhibit input to the gate 100 in channel 84.
When either AND gate 88 or 90 is enabled, channels 84 and 86 only will be inhibited from passing a control signal because there is no interlock between channel 80 and 82. For example, if channel 80 is actuated due to the receipt of the frequency pair to which AND gate 88 is responsive, an inhibit input is applied from AND gate 88 by line 104 and OR gate 108 to the inhibit inputs of gates 100 and 102 in channels 84 and 86, respectively. However, no inhibit input is applied to channel 82. Thus, if a second control signal is applied to the input of this system containing frequencies f2 and f3, AND gate 90 opens, and an output control signal is provided by channel 82 simultaneously with that of channel 80.
It should be noted that whenever one or both of channels 80 and 82 are actuated, and either of channels 84 or 86 attempts to actuate because of the presence at the input of the frequencies to which either of these channels is responsive; the interlock arrangement, as shown, becomes elfective to block all further outputs from all channels in the system. This interlock is provided by either lines 110 or 112, depending on whether gate 92 or 94 is open, through the OR gate 114 to the inhibit inputs of gates 96 and 98. Gates 100 and 102 are also inhibited at this time because of the inhibiting signal being applied to those AND gates by the OR gate 108.
In the situation where either control channel 84 or 86 is actuated in response to receipt of its frequency pair, then the interlock functions as in FIGS. 1 and 2. In-
hibit inputs are applied to the other three channels to prevent their actuation and control signals emanate from only one channel. For example, if AND gate 92 is open by virtue of frequencies )1 and f4 being present in the incoming control signals, channel 84 is actuated; and an inhibit signal is applied to channel 86 at gate 102, and to the two channels and 82 through OR gate 114 to the inhibit inputs of gates 96 and 98. An output control signal is obtianed only from channel 84. If any of the other three AND gates becomes enabled by virtue of its two critical frequencies appearing in the input signal, channel 84 will also be restrained from passing any further output control signals due to the inhibiting of gate 100. In such case, no output control signals are derived from the system.
It is to be understood that the above-described arrangements are illustrative of the applications of the principles of the invention. The output control signals can obviously be used for any of a variety of control functions. Numerous other arrangements may be devised by those skilled in the art without departing from the spirit and scope of the invention.
What is claimed is:
1. A remote control system responsive to the input of multi-frequency signals comprising a plurality of control channels, means at the input of each control channel which is actuated in response to the simultaneous receipt by said system of a predetermined input multi-frequency signal for providing an output control signal, means for inhibiting the generation of output control signals from all channels upon receipt by said system of input signals containing frequencies which would actuate greater than a predetermined number of control channels, gating means in each control channel, said inhibiting means including interconnections between each control channel input means and selected gating means in the other chan nels, which upon receipt of normal multi-frequency input signals by said remote control system become effective to inhibit the actuation of said gating means except in predetermined control channels, and upon receipt of abnormal input signals by said remote control system which would actuate greater than the predetermined number of control channels become effective to inhibit the actuation of said gating means in all of said control channels.
2. A remote control system as claimed in claim 1 wherein there are 12 control channels and the input signals contain m selective frequencies, and each of said control channels is responsive to a pair of said m frequencies.
3. A remote control system as claimed in claim 2 further comprising in means for selecting signals of one of said In frequencies and means for detecting the output of each said selecting means to provide a DC level input to said control channels.
4. A remote control system as claimed in claim 3 wherein each said control channel input means is formed as a coincidence gate, the input to each coincidence gate being connected to the output of two of said detecting means, each coincidence gate being enabled upon receipt of DC output signals from said detecting means, thereby to actuate the associated control channel to provide an output control signal.
5. A remote control system as claimed in claim 4 wherein said m selecting means are m filters, each filter being selective of signals of one of the m frequencies in the input signals applied to said system.
6. A remote control system as claimed in claim 4 wherein n=2 and m|=3, and said inhibiting means in each channel connects the output of its associated coincidence gate as an inhibit input to the gating means in the other channel.
7. A remote control system as claimed in claim 4 wherein the ratio of m to n equals 3/2.
8. A remote control system responsive to the'input of multi-frequency signals comprising at least three control channels, each of said control channels responsive to the simultaneous receipt of at least two predetermined fre quencies, means for inhibiting the generation of output control signals from all of said channels upon receipt by said system of input signals containing frequencies which would actuate greater than one channel, a gate in each control channel, said inhibiting means including interconnections between each channel and the gate in selected ones of said other channels, said inhibiting means being effective to inhibit enabling of each said gate except the gate in one control channel during receipt of normal multi-frequency input signals, and being effective to inhibit the actuation of all said gates in all control channels upon receipt of multi-frequency input signals which would actuate greater than one control channel.
References Cited 10 DONALD J. YUSKO, Primary Examiner US. Cl. X.R.
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3629713A (en) * 1970-06-01 1971-12-21 Stanislaw Szpilka Method of obtaining the signal dependent upon the percentage asymmetry of a 3-phase system
US3758864A (en) * 1970-11-28 1973-09-11 Matsushita Electric Ind Co Ltd Remote-control tuning system
FR2207396A1 (en) * 1972-11-17 1974-06-14 Charbonnages De France
US4577333A (en) * 1984-09-13 1986-03-18 Gridcomm Inc. Composite shift keying communication system
US5563537A (en) * 1995-02-02 1996-10-08 Fujitsu Limited Frequency-controlled circuit

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US2954545A (en) * 1958-04-10 1960-09-27 Zenith Radio Corp Remote control system
US3128451A (en) * 1959-09-16 1964-04-07 Philco Corp Electrical systems
US3278758A (en) * 1962-12-17 1966-10-11 Int Standard Electric Corp Anti-coincidence logic circuits
US3413608A (en) * 1964-06-12 1968-11-26 Warwick Electronics Inc Noise immune detector

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2954545A (en) * 1958-04-10 1960-09-27 Zenith Radio Corp Remote control system
US3128451A (en) * 1959-09-16 1964-04-07 Philco Corp Electrical systems
US3278758A (en) * 1962-12-17 1966-10-11 Int Standard Electric Corp Anti-coincidence logic circuits
US3413608A (en) * 1964-06-12 1968-11-26 Warwick Electronics Inc Noise immune detector

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3629713A (en) * 1970-06-01 1971-12-21 Stanislaw Szpilka Method of obtaining the signal dependent upon the percentage asymmetry of a 3-phase system
US3758864A (en) * 1970-11-28 1973-09-11 Matsushita Electric Ind Co Ltd Remote-control tuning system
FR2207396A1 (en) * 1972-11-17 1974-06-14 Charbonnages De France
US4577333A (en) * 1984-09-13 1986-03-18 Gridcomm Inc. Composite shift keying communication system
US5563537A (en) * 1995-02-02 1996-10-08 Fujitsu Limited Frequency-controlled circuit

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