US20220084948A1 - Semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor structure and manufacturing method thereof Download PDFInfo
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- US20220084948A1 US20220084948A1 US17/024,344 US202017024344A US2022084948A1 US 20220084948 A1 US20220084948 A1 US 20220084948A1 US 202017024344 A US202017024344 A US 202017024344A US 2022084948 A1 US2022084948 A1 US 2022084948A1
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- conductive pad
- semiconductor
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- semiconductor device
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 225
- 238000004519 manufacturing process Methods 0.000 title description 18
- 239000000758 substrate Substances 0.000 claims abstract description 55
- 239000000126 substance Substances 0.000 claims abstract description 34
- 230000009257 reactivity Effects 0.000 claims abstract description 32
- 239000010931 gold Substances 0.000 claims description 10
- 239000007769 metal material Substances 0.000 claims description 10
- 239000010949 copper Substances 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 5
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 5
- 229910052709 silver Inorganic materials 0.000 claims description 5
- 239000004332 silver Substances 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 238000000034 method Methods 0.000 abstract description 17
- 239000010410 layer Substances 0.000 description 42
- 239000004020 conductor Substances 0.000 description 12
- 229910052751 metal Inorganic materials 0.000 description 12
- 239000002184 metal Substances 0.000 description 12
- 238000007254 oxidation reaction Methods 0.000 description 12
- 239000000463 material Substances 0.000 description 10
- 230000003247 decreasing effect Effects 0.000 description 9
- 230000008569 process Effects 0.000 description 7
- 235000012431 wafers Nutrition 0.000 description 7
- 230000004888 barrier function Effects 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 3
- 229910021480 group 4 element Inorganic materials 0.000 description 3
- 229910021478 group 5 element Inorganic materials 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 239000012790 adhesive layer Substances 0.000 description 2
- 230000004075 alteration Effects 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910003437 indium oxide Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- -1 tungsten nitride Chemical class 0.000 description 1
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- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05644—Gold [Au] as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05684—Tungsten [W] as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/081—Disposition
- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/08146—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bonding area connecting to a via connection in the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
Definitions
- the present disclosure relates to a semiconductor structure and a manufacturing method thereof, and more particularly, to a semiconductor structure employing a via structure and a manufacturing method thereof.
- TSV electrodes In a 3D wafer package, two wafers are bonded to conductive pads, and through silicon via (TSV) electrodes are then formed to connect conductive pads on the first and second wafers.
- TSV electrode is usually made of copper or other conductive material to provide electrical connections between conductive pads.
- the present disclosure provides a semiconductor structure including a first semiconductor device and a second semiconductor device.
- the first semiconductor device includes a first semiconductor substrate, a first conductive pad and a second conductive pad.
- the first conductive pad is disposed on the first semiconductor substrate.
- the second conductive pad is disposed on the first conductive pad.
- the second semiconductor device is disposed on the first semiconductor device and comprises a second semiconductor substrate and a via structure.
- the via structure is disposed in the second semiconductor substrate and contacts the second conductive pad. Chemical reactivity of the second conductive pad is less than chemical reactivity of the first conductive pad.
- a thickness of the second conductive pad is less than a thickness of the first conductive pad.
- the first conductive pad comprises copper (Cu), aluminum (Al), or a combination thereof.
- the second conductive pad comprises tungsten (W), gold (Au), silver (Ag), or a combination thereof.
- an upper surface of the second conductive pad is substantially coplanar with an upper surface of the first semiconductor device.
- the via structure is a through silicon via (TSV).
- TSV through silicon via
- the present disclosure provides a semiconductor structure including a first chip and a second chip.
- the first chip includes a first semiconductor substrate and a conductive pad.
- the conductive pad is disposed on the first semiconductor substrate.
- the second chip includes a second substrate and a via structure.
- the via structure is disposed in the second semiconductor substrate and contacts the conductive pad. Chemical reactivity of the conductive pad increases at positions along a direction from the via structure to the first semiconductor substrate.
- the conductive pad comprises a first portion and a second portion, and the second portion is located between the first portion and the via structure.
- a thickness of the second portion is less than a thickness of the first portion.
- the first portion and the second portion are formed of different metal materials.
- chemical reactivity of the second portion is less than chemical reactivity of the first portion.
- the conductive pad comprises a step structure, wherein a step height of the step structure is less than 1 ⁇ m.
- an aspect ratio of the via structure is less than 10:1.
- Another aspect of the present disclosure provides a method of manufacturing a semiconductor structure including following operations: forming a first conductive pad on a first semiconductor device; forming a second conductive pad on the first conductive pad; connecting a second semiconductor device to the first semiconductor device; and forming a via structure in the second semiconductor device, wherein the via structure contacts the second conductive pad.
- the first conductive pad and the second conductive pad are formed of different metal materials.
- the forming of the second conductive pad on the first conductive pad includes forming a dielectric layer on the first conductive pad, and forming an opening in the dielectric layer to expose the first conductive pad.
- the forming of the second conductive pad on the first conductive pad includes forming the second conductive pad in the opening.
- the method further includes forming the first conductive pad and the second conductive pad such that each of the first conductive pad and the second conductive pad has chemical reactivity increasing at positions along a direction from the via structure to the first semiconductor device.
- the method further includes forming the second conductive pad with a thickness that is less than a thickness of the first conductive pad.
- the method further includes forming a step structure between the first conductive pad and the second conductive pad.
- a step height of the step structure is less than 1 ⁇ m.
- the method further includes forming the via structure with an aspect ratio less than 10:1.
- FIG. 1 is a top view of a semiconductor structure in accordance with some embodiments of the present disclosure.
- FIG. 2 is a cross-sectional view of the semiconductor structure along a line A-A in FIG. 1 .
- FIG. 3 is a cross-sectional view of a conventional semiconductor structure.
- FIG. 4 is a cross-sectional view of a semiconductor structure in accordance with some embodiments of the present disclosure.
- FIG. 5 and FIG. 6 are cross-sectional views of semiconductor structures in accordance with some embodiments of the present disclosure.
- FIG. 7 and FIG. 8 are cross-sectional views of semiconductor structures in accordance with some embodiments of the present disclosure.
- FIG. 9 is a top view of a semiconductor structure in accordance with some embodiments of the present disclosure.
- FIG. 10 is a cross-sectional view of the semiconductor structure along a line A-A in FIG. 9 .
- FIG. 11 and FIG. 12 are cross-sectional views of semiconductor structures in accordance with some embodiments of the present disclosure.
- FIG. 13 is a top view of a semiconductor structure in accordance with some embodiments of the present disclosure.
- FIG. 14 is a cross-sectional view of the semiconductor structure along a line A-A in FIG. 13 .
- FIG. 15 is a flowchart illustrating a method of manufacturing a semiconductor structure in accordance with some embodiments of the present disclosure.
- FIG. 16 , FIG. 17 , FIG. 18 , FIG. 19 and FIG. 20 are cross-sectional views of the semiconductor structure along the line A-A in FIG. 1 at various stages of manufacture.
- first, second, third, etc. may be used herein to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections are not limited by these terms. Rather, these terms are merely used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present inventive concept.
- FIGS. 4 to 8 and 10 to 14 are identified by the same reference numerals for clarity and simplicity. Furthermore, similar elements in. FIGS. 4 to 8 and 10 to 14 can include similar materials, and thus descriptions of such details are omitted in the interest of brevity.
- the semiconductor structure of the present disclosure may include a conductive pad having different levels of chemical reactivity at different positions of the conductive pad. For example, chemical reactivity of an upper portion of the conductive pad is less than chemical reactivity of a lower portion of the conductive pad. Thus, the upper portion is less easily oxidized than the lower portion and the oxidization of the conductive pad may be prevented. As a result, the conductivity between the conductive pad and the via structure may be increased, and the device stability of the semiconductor structure may be improved.
- the aspect ratio of the via structure in the semiconductor device may be decreased.
- the via structure may be relatively short in a vertical dimension and wide in a horizontal dimension.
- a yield rate of the via structure may be increased.
- the semiconductor structure of the present disclosure may improve the device stability and increase the yield rate compared to the conventional semiconductor structure.
- FIG. 1 is a top view of a semiconductor structure 100 and FIG. 2 is a cross-sectional view of the semiconductor structure 100 along a line A-A in FIG. 1 .
- the semiconductor structure 100 includes a first semiconductor device 110 and a second semiconductor device 120 .
- the first semiconductor device 110 may be referred to as a first chip.
- the first semiconductor device 110 may include a logic device, a memory device (e.g., SRAM), an RF device, an input/output (I/O) device, a system-on-chip (SOC) device, a system-in-chip (SIC) device, another suitable type of device, or a combination thereof.
- a logic device e.g., SRAM
- RF RF device
- I/O input/output
- SOC system-on-chip
- SIC system-in-chip
- the first semiconductor device 110 includes a first semiconductor substrate 1 . 11 , a first conductive pad 112 , and a second conductive pad 113 .
- the first semiconductor substrate 111 may be made of semiconductor materials, including, but not limited to, bulk silicon, a semiconductor wafer, a silicon-on-insulator (SOI) substrate, or a silicon germanium substrate. Other semiconductor materials including group III, group IV, and group V elements may also be used.
- the first conductive pad 112 is disposed on the first semiconductor substrate 111 .
- the first conductive pad 112 may be a metal pad.
- the first conductive pad 112 includes conductive material such as copper (Cu), aluminum (Al), another suitable conductive material, or a combination thereof. It should be noted that the quantity of the first conductive pads 112 on the first semiconductor substrate 111 is not limited.
- the second conductive pad 113 is disposed on the first conductive pad 112 .
- the second conductive pad 113 may be a metal pad.
- the first conductive pad 112 includes conductive material such as tungsten (W), gold (Au), silver (Ag), another suitable conductive material, or a combination thereof. It should be noted that the quantity of the second conductive pads 113 on the first semiconductor substrate 111 is not limited.
- the first conductive pad 112 and the second conductive pad 113 are formed of different metal materials.
- chemical reactivity of the second conductive pad 113 is less than chemical reactivity of the first conductive pad 112 .
- the second conductive pad 113 is less easily oxidized than the first conductive pad 112 .
- the second conductive pad 113 may be used as a protective layer for the first conductive pad 112 .
- the first conductive pad 112 may be oxidized when an upper surface of the first conductive pad 112 is exposed through the layer formed thereon.
- the second conductive pad 113 may protect the first conductive pad 112 from oxidization. In other words, the second conductive pad 113 may mitigate the effect of the oxidization of the first conductive pad 112 .
- the second conductive pad 113 may be used as a layer for filling the gap between an upper surface 112 a of the first conductive pad 112 and an upper surface 110 a of the first semiconductor device 110 .
- a thickness of the first conductive pad 112 may be decreased during different manufacturing operations, for example but not limited to, etching operations, probing operations, or other operations performed during manufacturing.
- the second conductive pad 113 may be used to fill in a space caused by the decreased portion of the first conductive pad 112 . In other words, the second conductive pad 113 may mitigate the effect of the reduction of the first conductive pad 112 .
- an upper surface 113 a of the second conductive pad 113 is substantially coplanar with the upper surface 110 a of the first semiconductor device 110 .
- a thickness of the second conductive pad 113 may be less than the thickness of the first conductive pad 112 . In some embodiments, the thickness of the second conductive pad 113 may be less than 1 ⁇ m.
- a dielectric layer 114 may be disposed on the first conductive pad 112 before the second conductive pad 113 is formed. In the subsequent manufacturing operations, an opening is formed in the dielectric layer 114 to expose a portion of the first conductive pad 112 . The second conductive pad 113 is formed in the opening and on the first conductive pad 112 .
- the dielectric layer 114 may include dielectric materials, such as oxide, nitride, polymer or the like.
- the second semiconductor device 120 may be referred to as a second chip.
- the second semiconductor device 120 may include a logic device, a memory device (e.g., an SRAM), an RF device, an input/output (I/O) device, a system-on-chip (SOC) device, a system-in-chip (SIC) device, another suitable type of device, or a combination thereof.
- the first semiconductor device 110 and the second semiconductor device 120 may be the same or different devices.
- the first semiconductor device 110 may be a system-on-chip (SOC) device and the second semiconductor device 120 may be a memory device. It should be understood that the application is not limited to a particular type of device.
- the second semiconductor device 120 is disposed on the first semiconductor device 110 . In some embodiments, the second semiconductor device 120 is connected to the first semiconductor device 110 by an adhesive layer 130 .
- the second semiconductor device 120 may include a second semiconductor substrate 121 and a via structure 122 .
- the second semiconductor substrate 121 may be made of semiconductor materials, including, but not limited to, bulk silicon, a semiconductor wafer, a silicon-on-insulator (SOI) substrate, or a silicon germanium substrate. Other semiconductor materials including group III, group IV, and group V elements may also be used.
- the via structure 122 is disposed in the second semiconductor substrate 121 and contacts the second conductive pad 113 .
- the via structure 122 is formed of conductive material.
- the via structure 122 may be a through substrate via or through silicon via (TSV).
- TSV through substrate via or through silicon via
- the via structure 122 may directly or indirectly contact the second conductive pad 113 .
- the second semiconductor device 120 is electrically connected to the first semiconductor device 110 through the via structure 122 . It should be noted that the shape and quantity of the via structures 122 are not limited.
- FIG. 3 is a cross-sectional view of a conventional semiconductor structure 300 .
- the semiconductor structure 300 includes semiconductor chips 310 and 320 .
- the semiconductor chip 310 has a metal pad 312 formed on a substrate 311 .
- the semiconductor chip 320 is electrically connected to the semiconductor chip 310 through a via structure 322 .
- the metal pad 312 of the semiconductor structure 300 is a single-layered metal pad.
- the via structure 322 of the second chip 320 contacts the single-layered metal pad 312 .
- the semiconductor structure 300 may have some issues, as described below.
- the single-layered metal pad 312 may be over-etched or oxidized.
- the thickness of the metal pad 312 may be decreased due to the etching operation.
- the aspect ratio of the via structure 322 may be increased.
- the aspect ratio of the via structure 322 may be as high as 10:1, which means a shape of the via structure 322 is relatively tall in a vertical dimension and narrow in a horizontal dimension. Accordingly, the via structure 322 may be difficult to form and a yield rate of the via structure 322 may be decreased.
- the metal pad 312 may be oxidized during the manufacturing operation.
- the conductivity between the metal pad 312 and the via structure 322 may be reduced due to the oxidization of the metal pad 312 .
- the device stability of the semiconductor structure 300 may be decreased.
- the semiconductor structure 100 of the present disclosure includes the first conductive pad 112 and the second conductive pad 113 .
- chemical reactivity of the second conductive pad 113 is less than chemical reactivity of the first conductive pad 112 .
- the second conductive pad 113 is less easily oxidized than the first conductive pad 112 , and the second conductive pad 113 may protect the first conductive pad 112 from oxidization.
- the conductivity between the first conductive pad 112 , the second conductive pad 113 and the via structure 122 may be increased, and the device stability of the semiconductor structure 100 may be improved.
- the second conductive pad 113 may be used as an intermediate layer between the via structure 122 and the first conductive pad 112 .
- the second conductive pad 113 is provided for connecting the via structure 122 to the first conductive pad 112 .
- an aspect ratio of the via structure 122 is less than an aspect ratio of the via structure 322 of the semiconductor structure 300 in FIG. 3 .
- the aspect ratio of the via structure 122 may be as low as 10:1.
- the aspect ratio of the via structure 122 may be as low as 8:1.
- the via structure 122 is relatively short in the vertical dimension and wide in the horizontal dimension. As a result, a yield rate of the via structure 122 may be increased.
- the semiconductor structure 100 of the present disclosure may improve the device stability and increase the yield rate compared to the conventional semiconductor structure 300 in FIG. 3 .
- FIG. 4 is a cross-sectional view of a semiconductor structure 400 .
- the semiconductor structure 400 includes a first chip 410 and a second chip 420 .
- the first chip 410 and the second chip 420 may be referred to as the first semiconductor device and the second semiconductor device.
- embodiments of the first chip 410 and the second chip 420 are similar to embodiments of the first semiconductor device 110 and the second semiconductor device 120 in FIG. 1 and FIG. 2 , and repeated descriptions thereof are omitted for brevity.
- the first chip 410 includes a first semiconductor substrate 411 and a conductive pad 412 .
- the second chip 420 includes a second semiconductor substrate 421 and a via structure 422 .
- the semiconductor material of the first semiconductor substrate 411 and the second semiconductor substrate 421 are similar to that of the first semiconductor substrate 111 and the second semiconductor substrate 121 in FIG. 2 , and repeated descriptions are omitted herein for brevity.
- the via structure 422 is similar to the via structure 122 in FIG. 2 , and repeated description thereof is omitted for brevity.
- the conductive pad 412 is disposed on the first semiconductor substrate 411 .
- chemical reactivity of the conductive pad 412 increases at positions along a direction D 1 from the via structure 422 to the first semiconductor substrate 411 .
- the conductive pad 412 may include a conductive material with different chemical reactivity at different positions. For example, the conductive material has a smaller amount of chemical activity at the portion near the via structure 422 than at the portion near the first semiconductor substrate 411 .
- the conductive pad 412 includes a first portion 412 a and a second portion 412 b.
- the second portion 412 b is located between the first portion 412 a and the via structure 422 .
- Chemical reactivity of the second portion 412 b is less than chemical reactivity of the first portion 412 a.
- the first portion 412 a and the second portion 412 b may be formed of different metal materials.
- the first portion 412 a may include metal material such as copper (Cu), aluminum (Al), another suitable conductive material, or a combination thereof.
- the second portion 412 b may include metal material such as tungsten (W), gold (Au), silver (Ag), another suitable conductive material, or a combination thereof.
- the conductive pad 412 has a step structure.
- a step height H of the step structure is less than 1 ⁇ m.
- a thickness (or the step height H) of the second portion 412 b is less than a thickness of the first portion. 412 a.
- a width of the second portion 412 b may be less than a width of the first portion 412 a.
- FIG. 5 and FIG. 6 are cross-sectional views of semiconductor structures 400 a and 400 b, respectively.
- the thickness of the second portion 412 b may be substantially the same as the thickness of the first portion 412 a. It should be noted that the step height H 1 (or the thickness) of the second portion 412 b is less than 1 ⁇ m. As shown in FIG. 6 , in some embodiments, the thickness of the second portion 412 b may be greater than the thickness of the first portion 412 a. It should be noted that the step height H 2 (or the thickness) of the second portion 412 b is less than 1 ⁇ m. It should be understood that the relative thicknesses of the first portion 412 a and the second portion 412 b are not limited.
- FIG. 7 and FIG. 8 are cross-sectional views of semiconductor structures 400 c and 400 d.
- the width of the second portion 412 b may be greater than the width of the first portion 412 a.
- the width of the second portion 412 b may be substantially the same as the width of the first portion 412 a.
- the conductive pad 412 may be formed in a non-stepped structure. It should be noted that the relative widths of the first portion 412 a and the second portion 412 b are not limited.
- the semiconductor structure 400 of the present disclosure includes the conductive pad 412 , in which chemical reactivity increases at positions along the direction D 1 from the via structure 422 to the first semiconductor substrate 411 .
- the second portion 412 b of the conductive pad 412 near the via structure 422 is less easily oxidized and thus may protect the conductive pad 412 from oxidization.
- the conductivity between the conductive pad 412 and the via structure 422 may be increased, and the device stability of the semiconductor structure 400 may be improved.
- the second portion 412 b of the conductive pad 412 is provided for connecting the via structure 422 to the conductive pad 412 .
- the aspect ratio of the via structure 422 is less than the aspect ratio of the via structure 322 of the semiconductor structure 300 in FIG. 3 .
- the via structure 422 is relatively short in the vertical dimension and wide in the horizontal dimension. As a result, a yield rate of the via structure 422 may be increased.
- the semiconductor structure 400 of the present disclosure may improve the device stability and increase the yield rate compared to the conventional semiconductor structure 300 in FIG. 3 .
- FIG. 9 is a top view of a semiconductor structure 900 and FIG. 10 is a cross-sectional view of the semiconductor structure 900 along a line A-A in FIG. 9 .
- the semiconductor structure 900 includes a first semiconductor device 910 and a second semiconductor device 920 .
- embodiments of the first semiconductor device 910 and the second semiconductor device 920 are similar to those of the first semiconductor device 110 and the second semiconductor device 120 in FIG. 1 and FIG. 2 , and repeated details thereof are omitted for brevity.
- the difference between the first semiconductor device 910 and the first semiconductor device 110 is that the first semiconductor device 910 includes a plurality of first conductive pads 912 and a plurality of second conductive pads 913 , in contrast to the first semiconductor device 110 , which includes a single first conductive pad 112 and a single second conductive pad 113 .
- the difference between the second semiconductor device 920 and the second semiconductor device 120 is that the second semiconductor device 920 includes a plurality of via structures 922 , in contrast to the second semiconductor device 120 , which includes a single via structure 122 .
- the semiconductor material of the first semiconductor substrate 911 and the second semiconductor substrate 921 are similar to that of the first semiconductor substrate 111 and the second semiconductor substrate 121 in FIG. 2 , and repeated descriptions thereof are omitted for brevity.
- the via structures 922 are similar to the via structure 122 in FIG. 2 , and repeated description thereof is omitted for brevity.
- the quantities of the first conductive pads 912 , the second conductive pads 913 and the via structures 922 are not limited. Moreover, the quantities of the first conductive pads 912 , the second conductive pads 913 and the via structures 922 may be the same or different.
- the embodiment illustrated in FIGS. 9 and 10 uses two first conductive pads 912 , two second conductive pads 913 and two via structures 922 as an example. It should be noted that in other embodiments, some first conductive pads 912 may connect to the via structures 922 without the second conductive pad 913 disposed therebetween.
- chemical reactivity of the second conductive pads 913 is less than chemical reactivity of the first conductive pads 912 .
- the second conductive pads 913 are less easily oxidized than the first conductive pads 912 .
- the second conductive pads 913 serve as a layer for filling the gap between the first conductive pads 912 and the via structures 922 .
- FIG. 11 and FIG. 12 are cross-sectional views of semiconductor structures 900 a and 900 b, respectively.
- upper surfaces of second conductive pads 913 a may be lower than an upper surface of a dielectric layer 914 .
- the dielectric layer 914 may cover a portion of the upper surfaces of the second conductive pads 913 a.
- the dielectric layer 914 is similar to the dielectric layer 114 in FIG. 2 .
- the dielectric layer 914 may protect the second conductive pads 913 a from oxidization.
- upper surfaces of second conductive pads 913 b may be higher than the upper surface of the dielectric layer 914 .
- the second conductive pads 913 b may protrude from the dielectric layer 914 .
- the protruding second conductive pads 913 b may reduce the aspect ratio of the via structure 922 .
- FIG. 4 may be adapted to the embodiments described in reference to FIG. 10 , FIG. 11 and FIG. 12 , and vice versa.
- the second conductive pads 913 are less easily oxidized than the first conductive pads 912 and the second conductive pads 913 may protect the first conductive pads 912 from oxidization.
- conductivity between the first conductive pads 912 , the second conductive pads 912 and the via structures 922 may be increased, and the device stability of the semiconductor structure 900 is improved.
- aspect ratios of the via structures 922 are less than the aspect ratio of the via structure 322 of the semiconductor structure 300 in FIG. 3 .
- the via structures 922 are relatively short in the vertical dimension and wide in the horizontal dimension. As a result, a yield rate of the via structures 922 is increased.
- FIG. 13 is a top view of a semiconductor structure 1300 and FIG. 14 is a cross-sectional view of the semiconductor structure 1300 along a line A-A in FIG. 13 .
- the semiconductor structure 1300 includes a first semiconductor device 1310 and a second semiconductor device 1320 .
- Embodiments of the first semiconductor device 1310 and the second semiconductor device 1320 are similar to those of the first semiconductor device 110 and the second semiconductor device 120 in FIG. 1 and FIG. 2 , and repeated descriptions thereof are omitted for brevity.
- a via structure 1322 of the second semiconductor device 1320 may have a conductive layer 1322 a and a barrier layer 1322 b, in contrast to the via structure 922 , which includes only a conductive material.
- the barrier layer 1322 b is disposed on the conductive layer 1322 a.
- the barrier material for forming the barrier layer 1322 b includes titanium nitride, tungsten nitride, tantalum nitride, indium oxide, cobalt, ruthenium, tantalum, or a combination thereof.
- the barrier layer 1322 b covers the conductive layer 1322 a to protect an underlying conductive pad (for example, a second conductive pad 1313 ) from electromigration.
- first conductive pad 1312 and the second conductive pad 1313 are similar to the first conductive pads and the second conductive pads described in reference to FIG. 2 , FIG. 10 , FIG. 11 , FIG. 12 , and repeated descriptions thereof are omitted for brevity. It should also be understood that the embodiments described in reference to FIG. 4 , FIG. 5 , FIG. 6 , FIG. 7 and FIG. 8 may be adapted to the embodiments described in reference to FIG. 13 and FIG. 14 , and vice versa.
- the second conductive pads 1313 are less easily oxidized than the first conductive pads 1212 and the second conductive pads 1313 may protect the first conductive pads 1312 from oxidization.
- the conductivity between the first conductive pads 1312 , the second conductive pads 1313 and the via structures 1322 may be increased, and the device stability of the semiconductor structure 1300 is improved.
- the aspect ratio of the via structures 1322 is less than that of the semiconductor structure 300 in FIG. 3 .
- the via structures 1322 are relatively short in the vertical dimension and wide in the horizontal dimension. As a result, a yield rate of the via structures 1322 is increased.
- the barrier layer 1322 b may protect the second conductive pad 1313 from electromigration.
- FIG. 15 is a flowchart illustrating a method of manufacturing the semiconductor structure 100 .
- the method 10 includes operations S 11 to S 14 .
- a first conductive pad is formed on a first semiconductor device.
- a second conductive pad is formed on the first conductive pad, wherein the first conductive pad and the second conductive pad are formed of different metal materials.
- a second semiconductor device is connected to the first semiconductor device.
- a via structure is formed in the second semiconductor device, wherein the via structure contacts the second conductive pad.
- FIG. 16 , FIG. 17 , FIG. 18 , FIG. 19 and FIG. 20 are cross-sectional views of the semiconductor structure 100 along a line A-A in FIG. 1 at various stages of manufacture.
- the first conductive pad 112 is formed on the first semiconductor device 110 .
- An embodiment of the first semiconductor device 110 is described in reference to FIG. 1 and FIG. 2 , and repeated descriptions thereof are omitted for brevity.
- the first semiconductor device 110 includes a first semiconductor substrate 111 and a dielectric layer 114 .
- the first semiconductor substrate 111 may be made of semiconductor materials, including, but not limited to, bulk silicon, a semiconductor wafer, a silicon-on-insulator (SOI) substrate, or a silicon germanium substrate. Other semiconductor materials including group III, group IV, and group V elements may also be used.
- the dielectric layer 114 may include dielectric materials, such as oxide, nitride, polymer or the like.
- the dielectric layer 114 is formed on the first conductive pad 112 . Subsequently, an opening 115 is formed in the dielectric layer 114 to expose the first conductive pad 112 . It should be understood that a size and shape of the opening 115 are not limited. It should be noted that after the first conductive pad 112 is exposed through the dielectric layer 114 , the first conductive pad 112 may be connected to a test apparatus for testing operation.
- a conductive layer 116 is formed on the first conductive pad 112 and the dielectric layer 114 .
- the first conductive pad 112 and the conductive layer 116 are formed of different metal materials.
- the second conductive pad 11 . 3 is formed on the first conductive pad 112 .
- the second conductive pad 113 may be formed by planarizing the conductive layer 116 in FIG. 16 to be coplanar with the dielectric layer 114 .
- the second conductive pad 113 may be planarized using a chemical mechanical planarization (CMP) process.
- CMP chemical mechanical planarization
- the first conductive pad 112 and the second conductive pad 113 are formed of different metal materials.
- chemical reactivity of the second conductive pad 113 is less than chemical reactivity of the first conductive pad 112 . In other words, the second conductive pad 113 is less easily oxidized than the first conductive pad 112 .
- the second conductive pad 113 may be used as a protective layer for the first conductive pad 112 .
- the first conductive pad 112 may be oxidized when an upper surface of the first conductive pad 112 is exposed through the layer formed thereon.
- the second conductive pad 113 may protect the first conductive pad 112 from oxidization. In other words, the second conductive pad 113 may mitigate the effect of the oxidization of the first conductive pad 112 .
- the second conductive pad 113 may serve as a layer for filling the gap between an upper surface 112 a of the first conductive pad 112 and an upper surface 110 a of the first semiconductor device 110 .
- a thickness of the first conductive pad 112 may be decreased during different manufacturing operations, for example but not limited to, an etching operation, a probing operation, or another operation during manufacturing.
- the second conductive pad 113 may fill a space created by the decreased thickness of the first conductive pad 112 . In other words, the second conductive pad 113 may mitigate the effect of the decreased thickness of the first conductive pad 112 .
- an upper surface 113 a of the second conductive pad 113 is substantially coplanar with the upper surface 110 a of the first semiconductor device 110 .
- a thickness of the second conductive pad 113 may be less than the thickness of the first conductive pad 112 . In some embodiments, the thickness of the second conductive pad 113 may be less than 1 ⁇ m.
- the second semiconductor device 120 is connected to the first semiconductor device 110 .
- An embodiment of the second semiconductor device 120 is described in reference to FIG. 1 and FIG. 2 , and repeated descriptions thereof are omitted for brevity.
- the second semiconductor device 120 is connected to the first semiconductor device 110 by the adhesive layer 130 .
- a via 122 or a trench 123 may be formed in the second semiconductor device 120 .
- an aspect ratio of the via 122 is less than 10:1.
- the aspect ratio of the via 122 may be as low as 8:1.
- the via 122 is relatively short in the vertical dimension and wide in the horizontal dimension.
- the via structure 122 is formed in the second semiconductor device 120 .
- the via structure 122 contacts the second conductive pad 113 .
- the via structure 122 is formed of conductive material.
- the via structure 122 may be a through substrate via or a through silicon via (TSV).
- FIG. 4 it should be understood that the embodiments described in reference to FIG. 4 , FIG. 5 , FIG. 6 , FIG. 7 , FIG. 8 , FIG. 9 , FIG. 10 , FIG. 11 , FIG. 12 , FIG. 13 and FIG. 14 may also be realized based on the embodiments described in reference to FIG. 15 .
- the semiconductor structure of the present disclosure may include a conductive pad having different chemical reactivity at different positions.
- chemical reactivity of an upper portion (for example, the second conductive pad 113 ) in the conductive pad is less than chemical reactivity of a lower portion (for example, the first conductive pad 112 ) in the conductive pad.
- the upper portion is less easily oxidized than the lower portion and the oxidization of the first conductive pad may be prevented.
- the conductivity between the first conductive pad and the via structure may be increased, and the device stability of the semiconductor structure may be improved.
- the aspect ratio of the via structure in the semiconductor device may be reduced.
- the via structure may be relatively short in the vertical dimension and wide in the horizontal dimension.
- a yield rate of the via structure may be increased.
- the semiconductor structure of the present disclosure may improve the device stability and increase the yield rate compared to the conventional semiconductor structure.
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Abstract
Description
- The present disclosure relates to a semiconductor structure and a manufacturing method thereof, and more particularly, to a semiconductor structure employing a via structure and a manufacturing method thereof.
- With increasing demand for higher performance in semiconductor industries, package technology has evolved from two-dimensional (2D) to three-dimensional (3D) wafer packages, so as to improve the density and performance of circuits in integrated circuit devices.
- In a 3D wafer package, two wafers are bonded to conductive pads, and through silicon via (TSV) electrodes are then formed to connect conductive pads on the first and second wafers. The TSV electrode is usually made of copper or other conductive material to provide electrical connections between conductive pads.
- This Discussion of the Background section is provided for background information only. The statements in this Discussion of the Background are not an admission that the subject matter disclosed in this section constitutes prior art to the present disclosure, and no part of this Discussion of the Background section may be used as an admission that any part of this application, including this Discussion of the Background section, constitutes prior art to the present disclosure.
- One aspect of the present disclosure provides a semiconductor structure including a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first semiconductor substrate, a first conductive pad and a second conductive pad. The first conductive pad is disposed on the first semiconductor substrate. The second conductive pad is disposed on the first conductive pad. The second semiconductor device is disposed on the first semiconductor device and comprises a second semiconductor substrate and a via structure. The via structure is disposed in the second semiconductor substrate and contacts the second conductive pad. Chemical reactivity of the second conductive pad is less than chemical reactivity of the first conductive pad.
- In some embodiments, a thickness of the second conductive pad is less than a thickness of the first conductive pad.
- In some embodiments, the first conductive pad comprises copper (Cu), aluminum (Al), or a combination thereof.
- In some embodiments, the second conductive pad comprises tungsten (W), gold (Au), silver (Ag), or a combination thereof.
- In some embodiments, an upper surface of the second conductive pad is substantially coplanar with an upper surface of the first semiconductor device.
- In some embodiments, the via structure is a through silicon via (TSV).
- Another aspect of the present disclosure provides a semiconductor structure including a first chip and a second chip. The first chip includes a first semiconductor substrate and a conductive pad. The conductive pad is disposed on the first semiconductor substrate. The second chip includes a second substrate and a via structure. The via structure is disposed in the second semiconductor substrate and contacts the conductive pad. Chemical reactivity of the conductive pad increases at positions along a direction from the via structure to the first semiconductor substrate.
- In some embodiments, the conductive pad comprises a first portion and a second portion, and the second portion is located between the first portion and the via structure.
- In some embodiments, a thickness of the second portion is less than a thickness of the first portion.
- In some embodiments, the first portion and the second portion are formed of different metal materials.
- In some embodiments, chemical reactivity of the second portion is less than chemical reactivity of the first portion.
- In some embodiments, the conductive pad comprises a step structure, wherein a step height of the step structure is less than 1 μm.
- In some embodiments, an aspect ratio of the via structure is less than 10:1.
- Another aspect of the present disclosure provides a method of manufacturing a semiconductor structure including following operations: forming a first conductive pad on a first semiconductor device; forming a second conductive pad on the first conductive pad; connecting a second semiconductor device to the first semiconductor device; and forming a via structure in the second semiconductor device, wherein the via structure contacts the second conductive pad. The first conductive pad and the second conductive pad are formed of different metal materials.
- In some embodiments, the forming of the second conductive pad on the first conductive pad includes forming a dielectric layer on the first conductive pad, and forming an opening in the dielectric layer to expose the first conductive pad.
- In some embodiments, the forming of the second conductive pad on the first conductive pad includes forming the second conductive pad in the opening.
- In some embodiments, the method further includes forming the first conductive pad and the second conductive pad such that each of the first conductive pad and the second conductive pad has chemical reactivity increasing at positions along a direction from the via structure to the first semiconductor device.
- In some embodiments, the method further includes forming the second conductive pad with a thickness that is less than a thickness of the first conductive pad.
- In some embodiments, the method further includes forming a step structure between the first conductive pad and the second conductive pad. A step height of the step structure is less than 1 μm.
- In some embodiments, the method further includes forming the via structure with an aspect ratio less than 10:1.
- The foregoing has outlined rather broadly the features and technical advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Additional features and advantages of the disclosure will be described hereinafter, and form the subject of the claims of the disclosure. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the disclosure as set forth in the appended claims.
- A more complete understanding of the present disclosure may be derived by referring to the detailed description and claims when considered in connection with the Figures, where like reference numbers refer to similar elements throughout the Figures, and:
-
FIG. 1 is a top view of a semiconductor structure in accordance with some embodiments of the present disclosure. -
FIG. 2 is a cross-sectional view of the semiconductor structure along a line A-A inFIG. 1 . -
FIG. 3 is a cross-sectional view of a conventional semiconductor structure. -
FIG. 4 is a cross-sectional view of a semiconductor structure in accordance with some embodiments of the present disclosure. -
FIG. 5 andFIG. 6 are cross-sectional views of semiconductor structures in accordance with some embodiments of the present disclosure. -
FIG. 7 andFIG. 8 are cross-sectional views of semiconductor structures in accordance with some embodiments of the present disclosure. -
FIG. 9 is a top view of a semiconductor structure in accordance with some embodiments of the present disclosure. -
FIG. 10 is a cross-sectional view of the semiconductor structure along a line A-A inFIG. 9 . -
FIG. 11 andFIG. 12 are cross-sectional views of semiconductor structures in accordance with some embodiments of the present disclosure. -
FIG. 13 is a top view of a semiconductor structure in accordance with some embodiments of the present disclosure. -
FIG. 14 is a cross-sectional view of the semiconductor structure along a line A-A inFIG. 13 . -
FIG. 15 is a flowchart illustrating a method of manufacturing a semiconductor structure in accordance with some embodiments of the present disclosure. -
FIG. 16 ,FIG. 17 ,FIG. 18 ,FIG. 19 andFIG. 20 are cross-sectional views of the semiconductor structure along the line A-A inFIG. 1 at various stages of manufacture. - Embodiments, or examples, of the disclosure illustrated in the drawings are now described using specific language. It shall be understood that no limitation of the scope of the disclosure is hereby intended. Any alteration or modification of the described embodiments, and any further applications of principles described in this document, are to be considered as normally occurring to one of ordinary skill in the art to which the disclosure relates. Reference numerals may be repeated throughout the embodiments, but this does not necessarily mean that feature(s) of one embodiment apply to another embodiment, even if they share the same reference numeral.
- It shall be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections are not limited by these terms. Rather, these terms are merely used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present inventive concept.
- The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limited to the present inventive concept. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It shall be further understood that the terms “comprises” and “comprising,” when used in this specification, point out the presence of stated features, integers, steps, operations, elements, or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof.
- It should be understood that similar features in
FIGS. 4 to 8 and 10 to 14 are identified by the same reference numerals for clarity and simplicity. Furthermore, similar elements in.FIGS. 4 to 8 and 10 to 14 can include similar materials, and thus descriptions of such details are omitted in the interest of brevity. - The semiconductor structure of the present disclosure may include a conductive pad having different levels of chemical reactivity at different positions of the conductive pad. For example, chemical reactivity of an upper portion of the conductive pad is less than chemical reactivity of a lower portion of the conductive pad. Thus, the upper portion is less easily oxidized than the lower portion and the oxidization of the conductive pad may be prevented. As a result, the conductivity between the conductive pad and the via structure may be increased, and the device stability of the semiconductor structure may be improved.
- Moreover, the aspect ratio of the via structure in the semiconductor device may be decreased. In other words, the via structure may be relatively short in a vertical dimension and wide in a horizontal dimension. As a result, a yield rate of the via structure may be increased. In summary, the semiconductor structure of the present disclosure may improve the device stability and increase the yield rate compared to the conventional semiconductor structure.
- The detailed semiconductor structure of the present disclosure is described below.
- In accordance with some embodiments of the disclosure,
FIG. 1 is a top view of asemiconductor structure 100 andFIG. 2 is a cross-sectional view of thesemiconductor structure 100 along a line A-A inFIG. 1 . With reference toFIG. 1 andFIG. 2 , in some embodiments, thesemiconductor structure 100 includes afirst semiconductor device 110 and asecond semiconductor device 120. - In some embodiments, the
first semiconductor device 110 may be referred to as a first chip. Thefirst semiconductor device 110 may include a logic device, a memory device (e.g., SRAM), an RF device, an input/output (I/O) device, a system-on-chip (SOC) device, a system-in-chip (SIC) device, another suitable type of device, or a combination thereof. - In some embodiments, the
first semiconductor device 110 includes a first semiconductor substrate 1.11, a firstconductive pad 112, and a secondconductive pad 113. Thefirst semiconductor substrate 111 may be made of semiconductor materials, including, but not limited to, bulk silicon, a semiconductor wafer, a silicon-on-insulator (SOI) substrate, or a silicon germanium substrate. Other semiconductor materials including group III, group IV, and group V elements may also be used. - In some embodiments, the first
conductive pad 112 is disposed on thefirst semiconductor substrate 111. In some embodiments, the firstconductive pad 112 may be a metal pad. In some embodiments, the firstconductive pad 112 includes conductive material such as copper (Cu), aluminum (Al), another suitable conductive material, or a combination thereof. It should be noted that the quantity of the firstconductive pads 112 on thefirst semiconductor substrate 111 is not limited. - In some embodiments, the second
conductive pad 113 is disposed on the firstconductive pad 112. In some embodiments, the secondconductive pad 113 may be a metal pad. In some embodiments, the firstconductive pad 112 includes conductive material such as tungsten (W), gold (Au), silver (Ag), another suitable conductive material, or a combination thereof. It should be noted that the quantity of the secondconductive pads 113 on thefirst semiconductor substrate 111 is not limited. - The first
conductive pad 112 and the secondconductive pad 113 are formed of different metal materials. In some embodiments, chemical reactivity of the secondconductive pad 113 is less than chemical reactivity of the firstconductive pad 112. In other words, the secondconductive pad 113 is less easily oxidized than the firstconductive pad 112. - In some embodiments, the second
conductive pad 113 may be used as a protective layer for the firstconductive pad 112. The firstconductive pad 112 may be oxidized when an upper surface of the firstconductive pad 112 is exposed through the layer formed thereon. In some embodiments, the secondconductive pad 113 may protect the firstconductive pad 112 from oxidization. In other words, the secondconductive pad 113 may mitigate the effect of the oxidization of the firstconductive pad 112. - In some embodiments, the second
conductive pad 113 may be used as a layer for filling the gap between anupper surface 112 a of the firstconductive pad 112 and anupper surface 110 a of thefirst semiconductor device 110. A thickness of the firstconductive pad 112 may be decreased during different manufacturing operations, for example but not limited to, etching operations, probing operations, or other operations performed during manufacturing. In some embodiments, the secondconductive pad 113 may be used to fill in a space caused by the decreased portion of the firstconductive pad 112. In other words, the secondconductive pad 113 may mitigate the effect of the reduction of the firstconductive pad 112. - In some embodiments, an
upper surface 113 a of the secondconductive pad 113 is substantially coplanar with theupper surface 110 a of thefirst semiconductor device 110. A thickness of the secondconductive pad 113 may be less than the thickness of the firstconductive pad 112. In some embodiments, the thickness of the secondconductive pad 113 may be less than 1 μm. - In some embodiments, a
dielectric layer 114 may be disposed on the firstconductive pad 112 before the secondconductive pad 113 is formed. In the subsequent manufacturing operations, an opening is formed in thedielectric layer 114 to expose a portion of the firstconductive pad 112. The secondconductive pad 113 is formed in the opening and on the firstconductive pad 112. In some embodiments, thedielectric layer 114 may include dielectric materials, such as oxide, nitride, polymer or the like. - In some embodiments, the
second semiconductor device 120 may be referred to as a second chip. Thesecond semiconductor device 120 may include a logic device, a memory device (e.g., an SRAM), an RF device, an input/output (I/O) device, a system-on-chip (SOC) device, a system-in-chip (SIC) device, another suitable type of device, or a combination thereof. Thefirst semiconductor device 110 and thesecond semiconductor device 120 may be the same or different devices. For example, thefirst semiconductor device 110 may be a system-on-chip (SOC) device and thesecond semiconductor device 120 may be a memory device. It should be understood that the application is not limited to a particular type of device. - In some embodiments, the
second semiconductor device 120 is disposed on thefirst semiconductor device 110. In some embodiments, thesecond semiconductor device 120 is connected to thefirst semiconductor device 110 by anadhesive layer 130. Thesecond semiconductor device 120 may include asecond semiconductor substrate 121 and a viastructure 122. - The
second semiconductor substrate 121 may be made of semiconductor materials, including, but not limited to, bulk silicon, a semiconductor wafer, a silicon-on-insulator (SOI) substrate, or a silicon germanium substrate. Other semiconductor materials including group III, group IV, and group V elements may also be used. - In some embodiments, the via
structure 122 is disposed in thesecond semiconductor substrate 121 and contacts the secondconductive pad 113. The viastructure 122 is formed of conductive material. In some embodiments, the viastructure 122 may be a through substrate via or through silicon via (TSV). The viastructure 122 may directly or indirectly contact the secondconductive pad 113. Thesecond semiconductor device 120 is electrically connected to thefirst semiconductor device 110 through the viastructure 122. It should be noted that the shape and quantity of the viastructures 122 are not limited. -
FIG. 3 is a cross-sectional view of aconventional semiconductor structure 300. With reference toFIG. 3 , thesemiconductor structure 300 includessemiconductor chips semiconductor chip 310 has ametal pad 312 formed on asubstrate 311. Thesemiconductor chip 320 is electrically connected to thesemiconductor chip 310 through a viastructure 322. Themetal pad 312 of thesemiconductor structure 300 is a single-layered metal pad. The viastructure 322 of thesecond chip 320 contacts the single-layeredmetal pad 312. - The
semiconductor structure 300 may have some issues, as described below. During manufacturing operations, the single-layeredmetal pad 312 may be over-etched or oxidized. For example, when themetal pad 312 is over-etched during the etching operation, the thickness of themetal pad 312 may be decreased due to the etching operation. As a result, the aspect ratio of the viastructure 322 may be increased. For example, the aspect ratio of the viastructure 322 may be as high as 10:1, which means a shape of the viastructure 322 is relatively tall in a vertical dimension and narrow in a horizontal dimension. Accordingly, the viastructure 322 may be difficult to form and a yield rate of the viastructure 322 may be decreased. - Moreover, the
metal pad 312 may be oxidized during the manufacturing operation. The conductivity between themetal pad 312 and the viastructure 322 may be reduced due to the oxidization of themetal pad 312. As a result, the device stability of thesemiconductor structure 300 may be decreased. - Referring back to
FIG. 1 andFIG. 2 , compared to theconventional semiconductor structure 300 inFIG. 3 , thesemiconductor structure 100 of the present disclosure includes the firstconductive pad 112 and the secondconductive pad 113. In some embodiments, chemical reactivity of the secondconductive pad 113 is less than chemical reactivity of the firstconductive pad 112. In other words, the secondconductive pad 113 is less easily oxidized than the firstconductive pad 112, and the secondconductive pad 113 may protect the firstconductive pad 112 from oxidization. As a result, the conductivity between the firstconductive pad 112, the secondconductive pad 113 and the viastructure 122 may be increased, and the device stability of thesemiconductor structure 100 may be improved. - Moreover, the second
conductive pad 113 may be used as an intermediate layer between the viastructure 122 and the firstconductive pad 112. In other words, after the thickness of the firstconductive pad 112 is reduced during the etching operation, the secondconductive pad 113 is provided for connecting the viastructure 122 to the firstconductive pad 112. As a result, an aspect ratio of the viastructure 122 is less than an aspect ratio of the viastructure 322 of thesemiconductor structure 300 inFIG. 3 . For example, but not limited thereto, the aspect ratio of the viastructure 122 may be as low as 10:1. In some embodiments, the aspect ratio of the viastructure 122 may be as low as 8:1. In other words, the viastructure 122 is relatively short in the vertical dimension and wide in the horizontal dimension. As a result, a yield rate of the viastructure 122 may be increased. - In summary, the
semiconductor structure 100 of the present disclosure may improve the device stability and increase the yield rate compared to theconventional semiconductor structure 300 inFIG. 3 . - In accordance with some embodiments of the disclosure,
FIG. 4 is a cross-sectional view of asemiconductor structure 400. Thesemiconductor structure 400 includes afirst chip 410 and asecond chip 420. Thefirst chip 410 and thesecond chip 420 may be referred to as the first semiconductor device and the second semiconductor device. In some embodiments, embodiments of thefirst chip 410 and thesecond chip 420 are similar to embodiments of thefirst semiconductor device 110 and thesecond semiconductor device 120 inFIG. 1 andFIG. 2 , and repeated descriptions thereof are omitted for brevity. - The
first chip 410 includes afirst semiconductor substrate 411 and aconductive pad 412. Thesecond chip 420 includes asecond semiconductor substrate 421 and a viastructure 422. The semiconductor material of thefirst semiconductor substrate 411 and thesecond semiconductor substrate 421 are similar to that of thefirst semiconductor substrate 111 and thesecond semiconductor substrate 121 inFIG. 2 , and repeated descriptions are omitted herein for brevity. The viastructure 422 is similar to the viastructure 122 inFIG. 2 , and repeated description thereof is omitted for brevity. - The
conductive pad 412 is disposed on thefirst semiconductor substrate 411. In some embodiments, chemical reactivity of theconductive pad 412 increases at positions along a direction D1 from the viastructure 422 to thefirst semiconductor substrate 411. In some embodiments, theconductive pad 412 may include a conductive material with different chemical reactivity at different positions. For example, the conductive material has a smaller amount of chemical activity at the portion near the viastructure 422 than at the portion near thefirst semiconductor substrate 411. - In some embodiments, the
conductive pad 412 includes afirst portion 412 a and asecond portion 412 b. Thesecond portion 412 b is located between thefirst portion 412 a and the viastructure 422. Chemical reactivity of thesecond portion 412 b is less than chemical reactivity of thefirst portion 412 a. - The
first portion 412 a and thesecond portion 412 b may be formed of different metal materials. In some embodiments, thefirst portion 412 a may include metal material such as copper (Cu), aluminum (Al), another suitable conductive material, or a combination thereof. In some embodiments, thesecond portion 412 b may include metal material such as tungsten (W), gold (Au), silver (Ag), another suitable conductive material, or a combination thereof. - As shown in
FIG. 4 , theconductive pad 412 has a step structure. In some embodiments, a step height H of the step structure is less than 1 μm. In some embodiments, a thickness (or the step height H) of thesecond portion 412 b is less than a thickness of the first portion. 412 a. Moreover, a width of thesecond portion 412 b may be less than a width of thefirst portion 412 a. -
FIG. 5 andFIG. 6 are cross-sectional views ofsemiconductor structures FIG. 5 , in some embodiments, the thickness of thesecond portion 412 b may be substantially the same as the thickness of thefirst portion 412 a. It should be noted that the step height H1 (or the thickness) of thesecond portion 412 b is less than 1 μm. As shown inFIG. 6 , in some embodiments, the thickness of thesecond portion 412 b may be greater than the thickness of thefirst portion 412 a. It should be noted that the step height H2 (or the thickness) of thesecond portion 412 b is less than 1 μm. It should be understood that the relative thicknesses of thefirst portion 412 a and thesecond portion 412 b are not limited. -
FIG. 7 andFIG. 8 are cross-sectional views ofsemiconductor structures 400 c and 400 d. As shown inFIG. 7 , in some embodiments, the width of thesecond portion 412 b may be greater than the width of thefirst portion 412 a. As shown inFIG. 8 , in some embodiments, the width of thesecond portion 412 b may be substantially the same as the width of thefirst portion 412 a. In other words, theconductive pad 412 may be formed in a non-stepped structure. It should be noted that the relative widths of thefirst portion 412 a and thesecond portion 412 b are not limited. - Referring back to
FIG. 4 , as described in reference toFIG. 1 andFIG. 2 , in contrast to theconventional semiconductor structure 300 inFIG. 3 , thesemiconductor structure 400 of the present disclosure includes theconductive pad 412, in which chemical reactivity increases at positions along the direction D1 from the viastructure 422 to thefirst semiconductor substrate 411. In other words, thesecond portion 412 b of theconductive pad 412 near the viastructure 422 is less easily oxidized and thus may protect theconductive pad 412 from oxidization. As a result, the conductivity between theconductive pad 412 and the viastructure 422 may be increased, and the device stability of thesemiconductor structure 400 may be improved. - Moreover, when the thickness of the
conductive pad 412 is reduced during the etching operation, thesecond portion 412 b of theconductive pad 412 is provided for connecting the viastructure 422 to theconductive pad 412. Thus, the aspect ratio of the viastructure 422 is less than the aspect ratio of the viastructure 322 of thesemiconductor structure 300 inFIG. 3 . In other words, the viastructure 422 is relatively short in the vertical dimension and wide in the horizontal dimension. As a result, a yield rate of the viastructure 422 may be increased. - In summary, the
semiconductor structure 400 of the present disclosure may improve the device stability and increase the yield rate compared to theconventional semiconductor structure 300 inFIG. 3 . - In accordance with some embodiments of the disclosure,
FIG. 9 is a top view of asemiconductor structure 900 andFIG. 10 is a cross-sectional view of thesemiconductor structure 900 along a line A-A inFIG. 9 . With reference toFIG. 9 andFIG. 10 , in some embodiments, thesemiconductor structure 900 includes afirst semiconductor device 910 and asecond semiconductor device 920. In some embodiments, embodiments of thefirst semiconductor device 910 and thesecond semiconductor device 920 are similar to those of thefirst semiconductor device 110 and thesecond semiconductor device 120 inFIG. 1 andFIG. 2 , and repeated details thereof are omitted for brevity. - The difference between the
first semiconductor device 910 and thefirst semiconductor device 110 is that thefirst semiconductor device 910 includes a plurality of firstconductive pads 912 and a plurality of secondconductive pads 913, in contrast to thefirst semiconductor device 110, which includes a single firstconductive pad 112 and a single secondconductive pad 113. The difference between thesecond semiconductor device 920 and thesecond semiconductor device 120 is that thesecond semiconductor device 920 includes a plurality of viastructures 922, in contrast to thesecond semiconductor device 120, which includes a single viastructure 122. It should be noted that the semiconductor material of thefirst semiconductor substrate 911 and thesecond semiconductor substrate 921 are similar to that of thefirst semiconductor substrate 111 and thesecond semiconductor substrate 121 inFIG. 2 , and repeated descriptions thereof are omitted for brevity. The viastructures 922 are similar to the viastructure 122 inFIG. 2 , and repeated description thereof is omitted for brevity. - It should be understood that the quantities of the first
conductive pads 912, the secondconductive pads 913 and the viastructures 922 are not limited. Moreover, the quantities of the firstconductive pads 912, the secondconductive pads 913 and the viastructures 922 may be the same or different. The embodiment illustrated inFIGS. 9 and 10 uses two firstconductive pads 912, two secondconductive pads 913 and two viastructures 922 as an example. It should be noted that in other embodiments, some firstconductive pads 912 may connect to the viastructures 922 without the secondconductive pad 913 disposed therebetween. - Similar to the embodiment illustrated in
FIG. 2 , chemical reactivity of the secondconductive pads 913 is less than chemical reactivity of the firstconductive pads 912. In other words, the secondconductive pads 913 are less easily oxidized than the firstconductive pads 912. Moreover, in some embodiments, the secondconductive pads 913 serve as a layer for filling the gap between the firstconductive pads 912 and the viastructures 922. -
FIG. 11 andFIG. 12 are cross-sectional views ofsemiconductor structures FIG. 11 , in some embodiments, upper surfaces of secondconductive pads 913 a may be lower than an upper surface of adielectric layer 914. In other words, thedielectric layer 914 may cover a portion of the upper surfaces of the secondconductive pads 913 a. It should be noted that thedielectric layer 914 is similar to thedielectric layer 114 in FIG. 2. Thedielectric layer 914 may protect the secondconductive pads 913 a from oxidization. - As shown in
FIG. 12 , in some embodiments, upper surfaces of secondconductive pads 913 b may be higher than the upper surface of thedielectric layer 914. In other words, the secondconductive pads 913 b may protrude from thedielectric layer 914. The protruding secondconductive pads 913 b may reduce the aspect ratio of the viastructure 922. - It should be understood that the embodiments described in reference to
FIG. 4 ,FIG. 5 ,FIG. 6 ,FIG. 7 andFIG. 8 may be adapted to the embodiments described in reference toFIG. 10 ,FIG. 11 andFIG. 12 , and vice versa. - In summary, referring back to
FIG. 10 , the secondconductive pads 913 are less easily oxidized than the firstconductive pads 912 and the secondconductive pads 913 may protect the firstconductive pads 912 from oxidization. As a result, conductivity between the firstconductive pads 912, the secondconductive pads 912 and the viastructures 922 may be increased, and the device stability of thesemiconductor structure 900 is improved. - In addition, aspect ratios of the via
structures 922 are less than the aspect ratio of the viastructure 322 of thesemiconductor structure 300 inFIG. 3 . In other words, the viastructures 922 are relatively short in the vertical dimension and wide in the horizontal dimension. As a result, a yield rate of the viastructures 922 is increased. - In accordance with some embodiments of the disclosure,
FIG. 13 is a top view of asemiconductor structure 1300 andFIG. 14 is a cross-sectional view of thesemiconductor structure 1300 along a line A-A inFIG. 13 . With reference toFIG. 13 andFIG. 14 , in some embodiments, thesemiconductor structure 1300 includes afirst semiconductor device 1310 and asecond semiconductor device 1320. Embodiments of thefirst semiconductor device 1310 and thesecond semiconductor device 1320 are similar to those of thefirst semiconductor device 110 and thesecond semiconductor device 120 inFIG. 1 andFIG. 2 , and repeated descriptions thereof are omitted for brevity. - Differences between the
semiconductor structure 1300 and thesemiconductor structure 900 inFIG. 9 are that a viastructure 1322 of thesecond semiconductor device 1320 may have aconductive layer 1322 a and abarrier layer 1322 b, in contrast to the viastructure 922, which includes only a conductive material. Thebarrier layer 1322 b is disposed on theconductive layer 1322 a. In some embodiments, the barrier material for forming thebarrier layer 1322 b includes titanium nitride, tungsten nitride, tantalum nitride, indium oxide, cobalt, ruthenium, tantalum, or a combination thereof. Thebarrier layer 1322 b covers theconductive layer 1322 a to protect an underlying conductive pad (for example, a second conductive pad 1313) from electromigration. - It should be noted that a first
conductive pad 1312 and the secondconductive pad 1313 are similar to the first conductive pads and the second conductive pads described in reference toFIG. 2 ,FIG. 10 ,FIG. 11 ,FIG. 12 , and repeated descriptions thereof are omitted for brevity. It should also be understood that the embodiments described in reference toFIG. 4 ,FIG. 5 ,FIG. 6 ,FIG. 7 andFIG. 8 may be adapted to the embodiments described in reference toFIG. 13 andFIG. 14 , and vice versa. - In summary, the second
conductive pads 1313 are less easily oxidized than the first conductive pads 1212 and the secondconductive pads 1313 may protect the firstconductive pads 1312 from oxidization. As a result, the conductivity between the firstconductive pads 1312, the secondconductive pads 1313 and the viastructures 1322 may be increased, and the device stability of thesemiconductor structure 1300 is improved. - In addition, the aspect ratio of the via
structures 1322 is less than that of thesemiconductor structure 300 inFIG. 3 . In other words, the viastructures 1322 are relatively short in the vertical dimension and wide in the horizontal dimension. As a result, a yield rate of the viastructures 1322 is increased. Moreover, thebarrier layer 1322 b may protect the secondconductive pad 1313 from electromigration. - In accordance with some embodiments of the present disclosure,
FIG. 15 is a flowchart illustrating a method of manufacturing thesemiconductor structure 100. - Referring to
FIG. 15 , in some embodiments, themethod 10 includes operations S11 to S14. In operation S11, a first conductive pad is formed on a first semiconductor device. In operation S12, a second conductive pad is formed on the first conductive pad, wherein the first conductive pad and the second conductive pad are formed of different metal materials. In operation S13, a second semiconductor device is connected to the first semiconductor device. In operation S14, a via structure is formed in the second semiconductor device, wherein the via structure contacts the second conductive pad. - In accordance with some embodiments of the present disclosure,
FIG. 16 ,FIG. 17 ,FIG. 18 ,FIG. 19 andFIG. 20 are cross-sectional views of thesemiconductor structure 100 along a line A-A inFIG. 1 at various stages of manufacture. Referring toFIG. 16 and operation S11 inFIG. 15 , in operation S11, the firstconductive pad 112 is formed on thefirst semiconductor device 110. An embodiment of thefirst semiconductor device 110 is described in reference toFIG. 1 andFIG. 2 , and repeated descriptions thereof are omitted for brevity. - In some embodiments, the
first semiconductor device 110 includes afirst semiconductor substrate 111 and adielectric layer 114. Thefirst semiconductor substrate 111 may be made of semiconductor materials, including, but not limited to, bulk silicon, a semiconductor wafer, a silicon-on-insulator (SOI) substrate, or a silicon germanium substrate. Other semiconductor materials including group III, group IV, and group V elements may also be used. Thedielectric layer 114 may include dielectric materials, such as oxide, nitride, polymer or the like. - In some embodiments, after the first
conductive pad 112 is formed, thedielectric layer 114 is formed on the firstconductive pad 112. Subsequently, anopening 115 is formed in thedielectric layer 114 to expose the firstconductive pad 112. It should be understood that a size and shape of theopening 115 are not limited. It should be noted that after the firstconductive pad 112 is exposed through thedielectric layer 114, the firstconductive pad 112 may be connected to a test apparatus for testing operation. - Referring to
FIG. 17 , aconductive layer 116 is formed on the firstconductive pad 112 and thedielectric layer 114. In some embodiments, the firstconductive pad 112 and theconductive layer 116 are formed of different metal materials. - Referring to
FIG. 18 and operation S12 inFIG. 15 , in operation S12, the second conductive pad 11.3 is formed on the firstconductive pad 112. In some embodiments, the secondconductive pad 113 may be formed by planarizing theconductive layer 116 inFIG. 16 to be coplanar with thedielectric layer 114. The secondconductive pad 113 may be planarized using a chemical mechanical planarization (CMP) process. As described above, the firstconductive pad 112 and the secondconductive pad 113 are formed of different metal materials. In some embodiments, chemical reactivity of the secondconductive pad 113 is less than chemical reactivity of the firstconductive pad 112. In other words, the secondconductive pad 113 is less easily oxidized than the firstconductive pad 112. - In some embodiments, the second
conductive pad 113 may be used as a protective layer for the firstconductive pad 112. The firstconductive pad 112 may be oxidized when an upper surface of the firstconductive pad 112 is exposed through the layer formed thereon. In some embodiments, the secondconductive pad 113 may protect the firstconductive pad 112 from oxidization. In other words, the secondconductive pad 113 may mitigate the effect of the oxidization of the firstconductive pad 112. - In some embodiments, the second
conductive pad 113 may serve as a layer for filling the gap between anupper surface 112 a of the firstconductive pad 112 and anupper surface 110 a of thefirst semiconductor device 110. A thickness of the firstconductive pad 112 may be decreased during different manufacturing operations, for example but not limited to, an etching operation, a probing operation, or another operation during manufacturing. In some embodiments, the secondconductive pad 113 may fill a space created by the decreased thickness of the firstconductive pad 112. In other words, the secondconductive pad 113 may mitigate the effect of the decreased thickness of the firstconductive pad 112. - In some embodiments, an
upper surface 113 a of the secondconductive pad 113 is substantially coplanar with theupper surface 110 a of thefirst semiconductor device 110. A thickness of the secondconductive pad 113 may be less than the thickness of the firstconductive pad 112. In some embodiments, the thickness of the secondconductive pad 113 may be less than 1 μm. - Referring to
FIG. 19 and operation S13 inFIG. 15 , in operation S13, thesecond semiconductor device 120 is connected to thefirst semiconductor device 110. An embodiment of thesecond semiconductor device 120 is described in reference toFIG. 1 andFIG. 2 , and repeated descriptions thereof are omitted for brevity. In some embodiments, thesecond semiconductor device 120 is connected to thefirst semiconductor device 110 by theadhesive layer 130. - A via 122 or a
trench 123 may be formed in thesecond semiconductor device 120. In some embodiments, an aspect ratio of thevia 122 is less than 10:1. In other embodiments, the aspect ratio of the via 122 may be as low as 8:1. In other words, the via 122 is relatively short in the vertical dimension and wide in the horizontal dimension. - Referring to
FIG. 20 and operation S14 inFIG. 15 , in operation S14, the viastructure 122 is formed in thesecond semiconductor device 120. The viastructure 122 contacts the secondconductive pad 113. The viastructure 122 is formed of conductive material. In some embodiments, the viastructure 122 may be a through substrate via or a through silicon via (TSV). - It should be understood that the embodiments described in reference to
FIG. 4 ,FIG. 5 ,FIG. 6 ,FIG. 7 ,FIG. 8 ,FIG. 9 ,FIG. 10 ,FIG. 11 ,FIG. 12 ,FIG. 13 andFIG. 14 may also be realized based on the embodiments described in reference toFIG. 15 . - In summary, the semiconductor structure of the present disclosure may include a conductive pad having different chemical reactivity at different positions. For example, chemical reactivity of an upper portion (for example, the second conductive pad 113) in the conductive pad is less than chemical reactivity of a lower portion (for example, the first conductive pad 112) in the conductive pad. Thus, the upper portion is less easily oxidized than the lower portion and the oxidization of the first conductive pad may be prevented. As a result, the conductivity between the first conductive pad and the via structure may be increased, and the device stability of the semiconductor structure may be improved.
- Moreover, the aspect ratio of the via structure in the semiconductor device (for example, the second semiconductor device 120) may be reduced. In other words, the via structure may be relatively short in the vertical dimension and wide in the horizontal dimension. As a result, a yield rate of the via structure may be increased. In summary, the semiconductor structure of the present disclosure may improve the device stability and increase the yield rate compared to the conventional semiconductor structure.
- Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes discussed above can be implemented in different methodologies and replaced by other processes, or a combination thereof.
- Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein, may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, and steps.
Claims (14)
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US20090218691A1 (en) * | 2008-02-28 | 2009-09-03 | International Business Machines Corporation | Bilayer metal capping layer for interconnect applications |
US20170110369A1 (en) * | 2011-10-17 | 2017-04-20 | Fujitsu Limited | Electronic device and method for producing same |
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