US20210298184A1 - Method of manufacturing circuit board structure - Google Patents
Method of manufacturing circuit board structure Download PDFInfo
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- US20210298184A1 US20210298184A1 US17/338,709 US202117338709A US2021298184A1 US 20210298184 A1 US20210298184 A1 US 20210298184A1 US 202117338709 A US202117338709 A US 202117338709A US 2021298184 A1 US2021298184 A1 US 2021298184A1
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- United States
- Prior art keywords
- layer
- stopper
- conductive bump
- circuit board
- chip
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- Abandoned
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/01—Tools for processing; Objects used during processing
- H05K2203/0147—Carriers and holders
- H05K2203/0156—Temporary polymeric carrier or foil, e.g. for processing or transferring
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/14—Related to the order of processing steps
- H05K2203/1461—Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
- H05K2203/1469—Circuit made after mounting or encapsulation of the components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/16—Inspection; Monitoring; Aligning
- H05K2203/167—Using mechanical means for positioning, alignment or registration, e.g. using rod-in-hole alignment
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
Definitions
- the present disclosure relates to a circuit board structure having an electronic component, particularly a circuit board structure having an embedded electronic component.
- FIGS. 1A and 1B are respectively a cross-sectional view and a top view illustrating a circuit board structure made by the conventional technique.
- FIG. 1A when a chip 12 is mounted on a substrate 14 by a mounting device, offset occurs.
- FIG. 1B shows the alignment deviation between the chip 12 and the chip placement area 16 on the substrate 14 .
- Some embodiments of the present disclosure provide a circuit board structure comprising a circuit layer structure, an electronic component, and a stopper.
- the circuit layer structure includes a plurality of dielectric layers and circuits in the dielectric layers.
- the electronic component is disposed in the circuit layer structure; the electronic component includes a chip and a conductive bump; the chip has a first surface and a second surface that are oppositely disposed, and the first surface of the chip contacts one of the dielectric layers; the conductive bump is on the second surface of the chip.
- the stopper is within the circuit layer structure and abuts against the conductive bump.
- the stopper has a first portion and a second portion that is perpendicular to the first portion.
- the stopper abuts against the conductive bump in a first direction and a second direction that is perpendicular to the first direction.
- the circuit layer structure further includes an insulating layer and a via in the insulating layer, the insulating layer is over the second surface of the chip, and the via is electrically connected to the conductive bump.
- the circuit board structure further includes an adhesive layer which is positioned between the second surface of the chip and the insulating layer and adheres to the conductive bumps.
- Some embodiments of the present disclosure also provide a method for manufacturing a circuit board structure; the method comprises: providing a carrier board having a release layer; forming a stopper over the carrier board; disposing an adhesive layer over the carrier board; abutting the conductive bump of an electronic component against the stopper and placing the electronic component over the carrier board; performing build-up process; and removing the carrier board.
- the electronic component comprises a chip having a first surface and a second surface that are oppositely disposed, and the conductive bump is located on the second surface; wherein the performing the build-up process comprising: forming a plurality of dielectric layers and circuits in the dielectric layers over the first surface of the chip.
- the method further comprises forming an outer layer over the second surface of the chip and the conductive bump, and the outer layer comprises an insulating layer, a via, and a patterned circuit layer.
- the via is within the insulating layer and is electrically connected to the conductive bump.
- the patterned circuit layer is over the insulating layer and is electrically connected to the via.
- the operation of abutting the conductive bump of the electronic component against the stopper and placing the electronic component over the carrier board comprises: abutting the conductive bump against the first portion of the stopper; and abutting the conductive bump against the second portion of the stopper, wherein the second portion is perpendicular to the first portion.
- the operation of disposing an adhesive layer over the carrier board comprises covering the stopper with the adhesive layer.
- FIG. 1A is a cross-sectional view illustrating a conventional circuit board structure.
- FIG. 1B is a top view illustrating a conventional circuit board structure.
- FIG. 2 shows a flow chart of a method of fabricating a circuit board structure in accordance with embodiments of the present disclosure.
- FIG. 3A is a cross-sectional view illustrating a circuit board structure at one of the manufacturing stages in accordance with embodiments of the present disclosure.
- FIG. 3B is a top view illustrating a circuit board structure at one of the manufacturing stages in accordance with embodiments of the present disclosure.
- FIG. 4A is a cross-sectional view illustrating a circuit board structure at one of the manufacturing stages in accordance with embodiments of the present disclosure.
- FIG. 4B is a top view illustrating a circuit board structure at one of the manufacturing stages in accordance with embodiments of the present disclosure.
- FIG. 5A is a cross-sectional view illustrating a circuit board structure at one of the manufacturing stages in accordance with embodiments of the present disclosure.
- FIG. 5B is a top view illustrating a circuit board structure at one of the manufacturing stages in accordance with embodiments of the present disclosure.
- FIG. 6A is a cross-sectional view illustrating a circuit board structure at one of the manufacturing stages in accordance with embodiments of the present disclosure.
- FIG. 6B is a top view illustrating a circuit board structure at one of the manufacturing stages in accordance with embodiments of the present disclosure.
- FIG. 7A is a cross-sectional view illustrating a circuit board structure at one of the manufacturing stages in accordance with embodiments of the present disclosure.
- FIG. 7B is a partial enlarged view of FIG. 7A .
- FIG. 7C is a cross-sectional view illustrating a circuit board structure at one of the manufacturing stages in accordance with embodiments of the present disclosure.
- FIG. 7D is a partial enlarged view of FIG. 7C .
- FIG. 7E is a cross-sectional view illustrating a circuit board structure at one of the manufacturing stages in accordance with embodiments of the present disclosure.
- FIG. 7F is a partial enlarged view of FIG. 7E .
- FIG. 7G is a cross-sectional view illustrating a circuit board structure at one of the manufacturing stages in accordance with embodiments of the present disclosure.
- FIG. 7H is a partial enlarged view of FIG. 7G .
- FIGS. 8 to 11 are cross-sectional views illustrating a circuit board structure respectively at one of the various manufacturing stages in accordance with embodiments of the present disclosure.
- FIG. 12 is a cross-sectional view illustrating a circuit board structure in accordance with embodiments of the present disclosure.
- FIG. 13 is a top view illustrating a circuit board structure at one of the manufacturing stages in accordance with embodiments of the present disclosure.
- FIG. 14 is a top view illustrating a circuit board structure in accordance with embodiments of the present disclosure.
- first and second features are formed in direct contact
- additional features may be formed between the first and second features, such that the first and second features may not be in direct contact
- present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures.
- the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
- the apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- circuit board structure and a manufacturing method thereof; the circuit board structure can be applied to, but not limited to, a package carrier board, or a printed circuit board.
- FIG. 2 shows a flow chart of a method 100 for fabricating a circuit board structure, including operations 102 through 118 , in accordance with some embodiments of the present disclosure. It is noted that the method 100 is merely exemplary and is not intended to limit the disclosure.
- FIGS. 3A through 11 are schematic views illustrating the circuit board structure at one of the various manufacturing stages, respectively.
- FIG. 3A is a cross-sectional view of the carrier board 200
- FIG. 3B is a top view of the carrier board 200
- the carrier board 200 includes a support layer 202 , a release layer 204 over the support layer 202 , and a metal layer 206 over the release layer 204 .
- the release layer 204 is configured to facilitate separation of the carrier board 200 from the precursor structure formed thereon in a later step, which will be described in more detail below.
- the support layer 202 may be made of organic polymeric material such as epoxy, polyimide (PI), polyethylene terephthalate (PET), and/or bismaleimide triazine (BT), or the like.
- the release layer 204 may be formed, for example, by treating a plastic film with plasma or coating with fluorine, or by coating a silicone release agent on the surface of a thin membranous material such as polyethylene terephthalate (PET), polyethylene (PE) or oriented polypropylene (OPP).
- the material of the metal layer 206 may be, for example, copper, aluminum, or other suitable electrically conductive material.
- FIG. 4A illustrates a stopper 300 is formed over the metal layer 206 .
- FIG. 4B is a top view illustrating the stopper 300 containing a first portion 302 and a second portion 304 that is perpendicular to the first portion 302 .
- the stopper 300 has a right-angle shape structure.
- the first portion and the second portion may be spaced apart; in other words, the first portion and the second portion are not joined together.
- the material of the stopper 300 may be metal, plastic material, resin, or the like.
- the material of the stopper 300 is prepreg, Ajinomoto Build-up Film (ABF), photoimageable dielectric (PID), phenolic resin, epoxy resin, polyamide resin, polytetrafluoroethylene (Teflon), or the like.
- the stopper 300 may be formed by using, for example, electroplating, electroless plating, sputtering, coating, printing, etc., or maybe in combination with lithography.
- FIGS. 2, 5A, and 5B a patterned metal layer is formed over the carrier board.
- FIG. 5A illustrates a patterned metal layer 208 is formed over the metal layer 206 .
- FIG. 5B is a top view illustrating the patterned metal layer 208 distributed over the surface of the metal layer 206 .
- the patterned metal layer 208 may include conductive plugs and conductive circuits.
- Formation of the patterned metal layer 208 may be performed by the following steps; firstly, a photoresist layer such as a dry film (not shown) is formed on the metal layer 206 ; then, the photoresist layer is patterned to expose portions of the metal layer 206 through lithography process. Thereafter, processes such as electroplating and a removal process for the photoresist layer are performed to form the patterned metal layer 208 .
- a photoresist layer such as a dry film (not shown) is formed on the metal layer 206 ; then, the photoresist layer is patterned to expose portions of the metal layer 206 through lithography process. Thereafter, processes such as electroplating and a removal process for the photoresist layer are performed to form the patterned metal layer 208 .
- FIGS. 2, 6A, and 6B illustrate an adhesive layer 220 is disposed over the carrier board.
- FIGS. 6A and 6B illustrate an adhesive layer 220 is disposed over the metal layer 206 .
- the adhesive layer 220 may be disposed through lamination, printing, coating, or the like.
- the material of the adhesive layer 220 may comprise, for example, resin or other suitable material. In some embodiments, the material of the adhesive layer 220 may be a thermal curing adhesive.
- the adhesive layer 220 is configured to adhere and secure the conductive bumps of the electronic component in the subsequent processes. As shown in FIGS. 6A and 6B , in some embodiments, the adhesive layer 220 covers the stopper 300 . In some embodiments, the thickness T 220 of the adhesive layer 220 is smaller than the thickness T 208 of the patterned metal layer 208 . In some embodiments, the thickness T 220 of the adhesive layer 220 is not greater than the height of the conductive bumps of the electronic component to be mounted later.
- FIGS. 7A, 7C, 7E, and 7G illustrate an exemplary process for placing an electronic component.
- FIGS. 7B, 7D, 7F, and 7H are corresponding partial enlarged views, respectively.
- the electronic component 310 includes a chip 320 and a conductive bump 330 .
- the chip 320 has a first surface 322 and a second surface 324 that are oppositely disposed, and the conductive bump 330 is located on the second surface 324 of the chip 320 .
- the mounting device 20 can absorb the first surface 322 of the chip 320 using, for example, vacuum suction, to make the conductive bump 330 facing the surface of the metal layer 206 of the carrier board 200 .
- the electronic component 310 is moved downward until the conductive bump 330 is located within the adhesive layer 220 and the bottom surface 332 of the conductive bump 330 is lower than the top surface 306 of the stopper 300 .
- the electronic component 310 is moved in the first direction x until the conductive bump 330 touches the first portion 302 of the stopper 300 . Therefore, the position of the conductive bump 330 in the first direction x is determined.
- the electronic component 310 is moved in a second direction y perpendicular to the first direction x until the conductive bump 330 touches the second portion 304 (which is perpendicular to the first portion 302 and is not shown in this figure) of the stopper 300 . Therefore, the position of the conductive bump 330 in the second direction y is determined.
- the electronic component 310 is moved downward again until the conductive bump 330 contacts (either directly or indirectly contacts) the metal layer 206 of the carrier board 200 .
- the adhesive layer 220 surrounds the conductive bump 330 .
- the adhesive layer 220 is positioned between the metal layer 206 and the chip 320 and fills the space between the plurality of conductive bumps 330 .
- the conductive bumps 330 of the electronic component 310 can be fixed by a baking process.
- the stopper 300 can guide the electronic component 310 to be accurately placed at a predetermined position on the carrier board 200 during the mounting process.
- a laminar circuit structure 400 may be formed by performing build-up process and laser-drilling techniques; the laminar circuit structure 400 comprises: dielectric layers, for example, a first dielectric layer 402 a, a second dielectric layer 402 b, and a third dielectric layer 402 c ; patterned circuit layers, for example, the first patterned circuit layer 404 in the second dielectric layer 402 b, the second patterned circuit layer 406 in the third dielectric layer 402 c, the third patterned circuit layer 408 on the third dielectric layer 402 c ; and vias, for example, a plurality of first vias 410 in the first dielectric layer 402 a, a plurality of second vias 412 in the second dielectric layer 402 b, and a
- the material of the first, second, and third dielectric layers 402 a, 402 b, and 402 c may include prepreg, Ajinomoto Build-up Film (ABF), photosensitive dielectric (PID), resin, or the like.
- the resin may be phenolic resin, epoxy resin, polyimide resin, or polytetrafluoroethylene.
- the materials of the first, second, and the third patterned circuit layers 404 , 406 , and 408 may be, for example, copper, aluminum, or other suitable electrically conductive material.
- the materials of the first, second, and third vias 410 , 412 , and 414 may be, for example, copper, aluminum, or other suitable electrically conductive material.
- FIG. 8 illustrates a precursor structure 402 is formed over the carrier board 200 ; the precursor structure 420 includes the patterned metal layer 208 , the adhesive layer 220 , the electronic component 310 , the stopper 300 , and the laminar circuit structure 400 .
- the patterned metal layer 208 is electrically connected to the circuits of the laminar circuit structure 400 , for example, the first via 410 , the first patterned circuit layer 404 , the second via 412 , the second patterned circuit layer 406 , the third via 414 , and the third patterned circuit layer 408 . Further, a portion of the circuits of the third patterned circuit layer 408 can serve as an electrically conductive pad 408 a.
- the carrier board is removed. Since the carrier board 200 includes the release layer 204 , the precursor structure 420 can be separated from the carrier board 200 by lifting off or other stripping techniques. The metal layer 206 may be also removed during or after the separation of the carrier board 200 .
- FIG. 9 is a schematic view showing the carrier board 200 has been removed and the precursor structure 420 is turned upside down. After the carrier board 200 is removed, the patterned metal layer 208 , the adhesive layer 220 , the stopper 300 , and the conductive bumps 330 are exposed. In addition, the upper surfaces of the patterned metal layer 208 , the adhesive layer 220 , the stopper 300 , and the conductive bumps 330 are substantially even.
- an outer layer is formed.
- an insulating layer 432 is formed over the patterned metal layer 208 , the adhesive layer 220 , the stopper 300 , and the conductive bump 330 .
- a plurality of via openings can be formed in the insulating layer 432 by using, for example, laser-drilling or lithography techniques; the via openings expose portions of the surfaces of the patterned metal layer 208 and the conductive bumps 330 .
- a photoresist layer (now shown) such as a dry film is formed on the insulating layer 432 , and the photoresist layer is patterned to expose portions of the insulating layer 432 and the via openings by lithography process. Then, a deposition process such as electroplating and a removal process of the photoresist layer are performed to form fourth vias 434 , fifth vias 436 , and a fourth patterned circuit layer 438 .
- FIG. 10 illustrates the outer layer 430 is formed over the patterned metal layer 208 , the adhesive layer 220 , the stopper 300 , and the conductive bump 330 .
- the outer layer 430 includes the insulating layer 432 , the forth via 434 , the fifth via 436 , and the fourth patterned circuit layer 438 .
- the insulating layer 432 covers the patterned metal layer 208 , the adhesive layer 220 , the stopper 300 , and the conductive bump 330 .
- the fourth via 434 is within the insulating layer 432 and is electrically connected to the patterned metal layer 208 .
- the fifth via 436 is within the insulating layer 432 and is electrically connected to the conductive bump 330 .
- the fourth patterned circuit layer 438 is located over the insulating layer 432 and electrically connected to the fourth via 434 and the fifth via 436 . Further, a portion of the circuits of the fourth patterned circuit layer 438 can serve as an electrically conductive pad 438 a.
- the material of the insulating layer 432 may include prepreg, Ajinomoto Build-up Film (ABF), photoimageable dielectric (PID), resin, or the like.
- the resin may be phenolic resin, epoxy resin, polyamide resin, or polytetrafluoroethylene.
- the material of the fourth via 434 and the fifth via 435 may be, for example, copper, aluminum, or other suitable electrically conductive material.
- the material of the fourth patterned circuit layer 438 may be, for example, copper, aluminum, or other suitable electrically conductive material.
- the outer layer 430 , the patterned metal layer 208 , and the laminar circuit structure 400 can be collectively referred to as a circuit layer structure 431 .
- a solder mask layer is formed.
- a first solder mask layer 440 is formed on the outer side of the laminar circuit structure 400 ; the first solder mask layer 440 has openings exposing the electrically conductive pads 408 a of the third patterned circuit layer 408 .
- the second solder mask layer 442 is formed on the outer side of the outer layer 430 ; the second solder mask layer 442 has openings exposing the electrically conductive pads 438 a of the fourth patterned circuit layer 438 .
- the material of the first solder mask layer 440 and the second solder mask layer 442 may be, for example, green lacquer or other suitable material.
- the first solder mask layer 440 and the second solder mask layer 442 may be formed by coating, printing, or the like.
- the circuit board structure 500 includes a circuit layer structure 510 , an electronic component 520 , and a stopper 530 .
- the circuit layer structure 510 includes a plurality of dielectric layers 512 (e.g., the first, second, and third dielectric layers 512 a, 512 b, and 512 c ) and the circuits 514 in the dielectric layers 512 ; the circuit layer structure 510 further comprises an insulating layer 513 located over the dielectric layers 512 .
- the electronic component 520 is disposed in the circuit layer structure 510 and between the first dielectric layer 512 a and the insulating layer 513 ; the electronic component 520 includes a chip 522 and a conductive bump 524 , and the chip 522 has a first surface 522 a and a second surface 522 b that are oppositely disposed to each other; the conductive bump 524 is on the second surface 522 b of the chip 522 .
- the stopper 530 is within the circuit layer structure 510 and abuts against the conductive bump 524 .
- the circuit layer structure 510 further includes vias 516 within the insulating layer 513 and electrically connected to the conductive bump 524 .
- the circuit board structure 500 further includes an adhesive layer 518 which is located between the second surface 522 b of the chip 522 and the first dielectric layer 512 a and adheres to the conductive bump 524 .
- solder mask layers 540 and 542 are respectively disposed on the two opposite outer sides of the circuit layer structure 510 to protect the circuit layer structure 510 .
- an aspect of the present disclosure provides a circuit board structure 500 for embedded electronic components, including a circuit layer structure 510 , an electronic component 520 , and a stopper 530 .
- the circuit layer structure 510 includes a plurality of dielectric layers 512 and circuits 514 in the dielectric layers 512 .
- the electronic component 520 is disposed within the circuit layer structure 510 ; the electronic component 520 includes a chip 522 and a conductive bump 524 ; the chip 522 has a first surface 522 a and a second surface 522 b that are oppositely disposed; the first surface 522 a of the chip 522 contacts a dielectric layer 512 a of the dielectric layers 512 ; the conductive bump 524 is located on the second surface 522 b of the chip 522 .
- the stopper 530 is within the circuit layer structure 510 and abuts against the conductive bump 524 .
- FIG. 13 is a top view of a circuit board structure 600 at one of the manufacturing stages in accordance with some embodiments.
- FIG. 13 illustrates the relative positional relationship between the conductive bumps 624 , the chip 622 , and the stopper 630 .
- a plurality of conductive plugs 610 are distributed in the circuit board structure 600 .
- the first portion 632 and the second portion 634 of the stopper 630 are at right angles, and one of the conductive bumps 624 abuts against the first portion 632 of the stopper 630 in a first direction x, and the one of the conductive bumps 624 abuts against the second portion 634 of the stopper 630 in a second direction y perpendicular to the first direction x.
- the circuit board structure illustrated in FIG. 13 is merely an example; in other embodiments, the stopper 630 may not be seen from the top view, or the stopper 630 may be disposed at other positions relative to the chip 622 . In fact, the stopper 630 can be disposed at any location that abuts any of the conductive bumps 624 of the electronic components, preferably abuts the conductive bump 624 located at a corner of the rectangular shape of the chip 622 .
- FIG. 14 is a top view of a circuit board structure 700 in accordance with some embodiments, and the figure shows that the chips 722 are accurately mounted in the chip placement areas 702 in the circuit board structure 700 .
- the present disclosure provides a circuit board structure for embedded electronic components and a method thereof, which improve the mounting accuracy of the electronic component by guiding the conductive bump of the electronic component to the predetermined positions of the substrate with a stopper.
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Abstract
A circuit board structure includes a circuit layer structure, an electronic component, and a stopper. The circuit layer structure includes a plurality of dielectric layers and circuits in the dielectric layers. The electronic component is disposed in the circuit layer structure; the electronic component includes a chip and a conductive bump; the chip has a first surface and a second surface that are oppositely disposed, and the first surface of the chip contacts one of the dielectric layers; the conductive bump is on the second surface of the chip and is electrically connected to the chip. The stopper is within the circuit layer structure and abuts against the conductive bump. A method for fabricating a circuit board structure is also provided herein.
Description
- The present application is a Divisional Application of the U.S. Application Ser. No. 16/544,936, filed Aug. 20, 2019, which claims priority to Taiwan Application Serial Number 108124560, filed Jul. 11, 2019, all of which are herein incorporated by reference in their entireties.
- The present disclosure relates to a circuit board structure having an electronic component, particularly a circuit board structure having an embedded electronic component.
- In the conventional manufacturing technology relates to circuit boards having embedded electronic components, when the electronic components are mounted on the substrate, the mounting accuracy of the electronic components is affected by the mounting device, and each of the electronic components has a random offset.
- Referring to
FIGS. 1A and 1B , which are respectively a cross-sectional view and a top view illustrating a circuit board structure made by the conventional technique. As shown inFIG. 1A , when achip 12 is mounted on asubstrate 14 by a mounting device, offset occurs.FIG. 1B shows the alignment deviation between thechip 12 and thechip placement area 16 on thesubstrate 14. - The electronic components offset at the predetermined positions in the carrier board, and such condition will result in inaccurate processing of the vias or the circuit layers formed by the subsequent process. Therefore, the offset mounting of electronic components is a critical issue that needs to be solved.
- Some embodiments of the present disclosure provide a circuit board structure comprising a circuit layer structure, an electronic component, and a stopper. The circuit layer structure includes a plurality of dielectric layers and circuits in the dielectric layers. The electronic component is disposed in the circuit layer structure; the electronic component includes a chip and a conductive bump; the chip has a first surface and a second surface that are oppositely disposed, and the first surface of the chip contacts one of the dielectric layers; the conductive bump is on the second surface of the chip. The stopper is within the circuit layer structure and abuts against the conductive bump.
- In some embodiments, the stopper has a first portion and a second portion that is perpendicular to the first portion.
- In some embodiments, the stopper abuts against the conductive bump in a first direction and a second direction that is perpendicular to the first direction.
- In some embodiments, the circuit layer structure further includes an insulating layer and a via in the insulating layer, the insulating layer is over the second surface of the chip, and the via is electrically connected to the conductive bump.
- In some embodiments, the circuit board structure further includes an adhesive layer which is positioned between the second surface of the chip and the insulating layer and adheres to the conductive bumps.
- Some embodiments of the present disclosure also provide a method for manufacturing a circuit board structure; the method comprises: providing a carrier board having a release layer; forming a stopper over the carrier board; disposing an adhesive layer over the carrier board; abutting the conductive bump of an electronic component against the stopper and placing the electronic component over the carrier board; performing build-up process; and removing the carrier board.
- In some embodiments, wherein the electronic component comprises a chip having a first surface and a second surface that are oppositely disposed, and the conductive bump is located on the second surface; wherein the performing the build-up process comprising: forming a plurality of dielectric layers and circuits in the dielectric layers over the first surface of the chip.
- In some embodiments, the method further comprises forming an outer layer over the second surface of the chip and the conductive bump, and the outer layer comprises an insulating layer, a via, and a patterned circuit layer. The via is within the insulating layer and is electrically connected to the conductive bump. The patterned circuit layer is over the insulating layer and is electrically connected to the via.
- In some embodiments, the operation of abutting the conductive bump of the electronic component against the stopper and placing the electronic component over the carrier board comprises: abutting the conductive bump against the first portion of the stopper; and abutting the conductive bump against the second portion of the stopper, wherein the second portion is perpendicular to the first portion.
- In some embodiments, the operation of disposing an adhesive layer over the carrier board comprises covering the stopper with the adhesive layer.
- Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
-
FIG. 1A is a cross-sectional view illustrating a conventional circuit board structure. -
FIG. 1B is a top view illustrating a conventional circuit board structure. -
FIG. 2 shows a flow chart of a method of fabricating a circuit board structure in accordance with embodiments of the present disclosure. -
FIG. 3A is a cross-sectional view illustrating a circuit board structure at one of the manufacturing stages in accordance with embodiments of the present disclosure. -
FIG. 3B is a top view illustrating a circuit board structure at one of the manufacturing stages in accordance with embodiments of the present disclosure. -
FIG. 4A is a cross-sectional view illustrating a circuit board structure at one of the manufacturing stages in accordance with embodiments of the present disclosure. -
FIG. 4B is a top view illustrating a circuit board structure at one of the manufacturing stages in accordance with embodiments of the present disclosure. -
FIG. 5A is a cross-sectional view illustrating a circuit board structure at one of the manufacturing stages in accordance with embodiments of the present disclosure. -
FIG. 5B is a top view illustrating a circuit board structure at one of the manufacturing stages in accordance with embodiments of the present disclosure. -
FIG. 6A is a cross-sectional view illustrating a circuit board structure at one of the manufacturing stages in accordance with embodiments of the present disclosure. -
FIG. 6B is a top view illustrating a circuit board structure at one of the manufacturing stages in accordance with embodiments of the present disclosure. -
FIG. 7A is a cross-sectional view illustrating a circuit board structure at one of the manufacturing stages in accordance with embodiments of the present disclosure. -
FIG. 7B is a partial enlarged view ofFIG. 7A . -
FIG. 7C is a cross-sectional view illustrating a circuit board structure at one of the manufacturing stages in accordance with embodiments of the present disclosure. -
FIG. 7D is a partial enlarged view ofFIG. 7C . -
FIG. 7E is a cross-sectional view illustrating a circuit board structure at one of the manufacturing stages in accordance with embodiments of the present disclosure. -
FIG. 7F is a partial enlarged view ofFIG. 7E . -
FIG. 7G is a cross-sectional view illustrating a circuit board structure at one of the manufacturing stages in accordance with embodiments of the present disclosure. -
FIG. 7H is a partial enlarged view ofFIG. 7G . -
FIGS. 8 to 11 are cross-sectional views illustrating a circuit board structure respectively at one of the various manufacturing stages in accordance with embodiments of the present disclosure. -
FIG. 12 is a cross-sectional view illustrating a circuit board structure in accordance with embodiments of the present disclosure. -
FIG. 13 is a top view illustrating a circuit board structure at one of the manufacturing stages in accordance with embodiments of the present disclosure. -
FIG. 14 is a top view illustrating a circuit board structure in accordance with embodiments of the present disclosure. - The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- While the method of the present disclosure is described below as a series of operations or steps, it will be appreciated that the illustrated order of such operations or steps should not be interpreted to be limiting for the present disclosure. For example, some operations or steps may be performed in a different order and/or concurrently with other operations or steps. In addition, not all of the illustrated operations, steps, and/or characteristics are required to implement the embodiments of the present disclosure. Further, each of the operations or steps depicted herein may include several sub-steps or actions.
- Some embodiments of the present disclosure provide a circuit board structure and a manufacturing method thereof; the circuit board structure can be applied to, but not limited to, a package carrier board, or a printed circuit board.
-
FIG. 2 shows a flow chart of amethod 100 for fabricating a circuit board structure, includingoperations 102 through 118, in accordance with some embodiments of the present disclosure. It is noted that themethod 100 is merely exemplary and is not intended to limit the disclosure.FIGS. 3A through 11 are schematic views illustrating the circuit board structure at one of the various manufacturing stages, respectively. - Referring to
FIGS. 2, 3A, and 3B , inoperation 102 of themethod 100, the carrier board having a release layer is provided.FIG. 3A is a cross-sectional view of thecarrier board 200, andFIG. 3B is a top view of thecarrier board 200. Thecarrier board 200 includes asupport layer 202, arelease layer 204 over thesupport layer 202, and ametal layer 206 over therelease layer 204. Therelease layer 204 is configured to facilitate separation of thecarrier board 200 from the precursor structure formed thereon in a later step, which will be described in more detail below. - The
support layer 202 may be made of organic polymeric material such as epoxy, polyimide (PI), polyethylene terephthalate (PET), and/or bismaleimide triazine (BT), or the like. Therelease layer 204 may be formed, for example, by treating a plastic film with plasma or coating with fluorine, or by coating a silicone release agent on the surface of a thin membranous material such as polyethylene terephthalate (PET), polyethylene (PE) or oriented polypropylene (OPP). The material of themetal layer 206 may be, for example, copper, aluminum, or other suitable electrically conductive material. - Referring to
FIGS. 2, 4A, 4B , inoperation 104 of themethod 100, a stopper is formed over the carrier board.FIG. 4A illustrates astopper 300 is formed over themetal layer 206.FIG. 4B is a top view illustrating thestopper 300 containing afirst portion 302 and asecond portion 304 that is perpendicular to thefirst portion 302. In other words, thestopper 300 has a right-angle shape structure. In other embodiments, the first portion and the second portion may be spaced apart; in other words, the first portion and the second portion are not joined together. - The material of the
stopper 300 may be metal, plastic material, resin, or the like. For example, the material of thestopper 300 is prepreg, Ajinomoto Build-up Film (ABF), photoimageable dielectric (PID), phenolic resin, epoxy resin, polyamide resin, polytetrafluoroethylene (Teflon), or the like. Thestopper 300 may be formed by using, for example, electroplating, electroless plating, sputtering, coating, printing, etc., or maybe in combination with lithography. - Please refer to
FIGS. 2, 5A, and 5B . Inoperation 106 ofmethod 100, a patterned metal layer is formed over the carrier board.FIG. 5A illustrates a patternedmetal layer 208 is formed over themetal layer 206.FIG. 5B is a top view illustrating the patternedmetal layer 208 distributed over the surface of themetal layer 206. The patternedmetal layer 208 may include conductive plugs and conductive circuits. - Formation of the patterned
metal layer 208 may be performed by the following steps; firstly, a photoresist layer such as a dry film (not shown) is formed on themetal layer 206; then, the photoresist layer is patterned to expose portions of themetal layer 206 through lithography process. Thereafter, processes such as electroplating and a removal process for the photoresist layer are performed to form the patternedmetal layer 208. - Please refer to
FIGS. 2, 6A, and 6B . Inoperation 108 of themethod 100, an adhesive layer is disposed over the carrier board.FIGS. 6A and 6B illustrate anadhesive layer 220 is disposed over themetal layer 206. Theadhesive layer 220 may be disposed through lamination, printing, coating, or the like. The material of theadhesive layer 220 may comprise, for example, resin or other suitable material. In some embodiments, the material of theadhesive layer 220 may be a thermal curing adhesive. - The
adhesive layer 220 is configured to adhere and secure the conductive bumps of the electronic component in the subsequent processes. As shown inFIGS. 6A and 6B , in some embodiments, theadhesive layer 220 covers thestopper 300. In some embodiments, the thickness T220 of theadhesive layer 220 is smaller than the thickness T208 of the patternedmetal layer 208. In some embodiments, the thickness T220 of theadhesive layer 220 is not greater than the height of the conductive bumps of the electronic component to be mounted later. - Please refer to
FIGS. 2, and 7A through 7H . Inoperation 110 of themethod 100, the conductive bump of the electronic component is disposed to abut against the stopper and the electronic component is placed over the carrier board.FIGS. 7A, 7C, 7E, and 7G illustrate an exemplary process for placing an electronic component.FIGS. 7B, 7D, 7F, and 7H are corresponding partial enlarged views, respectively. Theelectronic component 310 includes achip 320 and aconductive bump 330. Thechip 320 has afirst surface 322 and asecond surface 324 that are oppositely disposed, and theconductive bump 330 is located on thesecond surface 324 of thechip 320. The mountingdevice 20 can absorb thefirst surface 322 of thechip 320 using, for example, vacuum suction, to make theconductive bump 330 facing the surface of themetal layer 206 of thecarrier board 200. - As shown in
FIGS. 7A and 7B , firstly, theelectronic component 310 is moved downward until theconductive bump 330 is located within theadhesive layer 220 and thebottom surface 332 of theconductive bump 330 is lower than thetop surface 306 of thestopper 300. - Next, as shown in
FIGS. 7C and 7D , theelectronic component 310 is moved in the first direction x until theconductive bump 330 touches thefirst portion 302 of thestopper 300. Therefore, the position of theconductive bump 330 in the first direction x is determined. - Next, as shown in
FIGS. 7E and 7F , theelectronic component 310 is moved in a second direction y perpendicular to the first direction x until theconductive bump 330 touches the second portion 304 (which is perpendicular to thefirst portion 302 and is not shown in this figure) of thestopper 300. Therefore, the position of theconductive bump 330 in the second direction y is determined. - Next, as shown in
FIGS. 7G and 7H , theelectronic component 310 is moved downward again until theconductive bump 330 contacts (either directly or indirectly contacts) themetal layer 206 of thecarrier board 200. In addition, theadhesive layer 220 surrounds theconductive bump 330. In other words, theadhesive layer 220 is positioned between themetal layer 206 and thechip 320 and fills the space between the plurality ofconductive bumps 330. - In some embodiments, when the
adhesive layer 220 is a thermal curing adhesive, theconductive bumps 330 of theelectronic component 310 can be fixed by a baking process. - As shown in
FIGS. 7A through 7H , when theelectronic component 310 is placed, thefirst portion 302 of thestopper 300 abuts against the conductive bump in the first direction x, thesecond portion 304 of thestopper 300 abuts against the conductive bump in the second direction y (refers toFIG. 4B ), and theconductive bump 330 is adhered and fixed in theadhesive layer 220. Therefore, thestopper 300 can guide theelectronic component 310 to be accurately placed at a predetermined position on thecarrier board 200 during the mounting process. - Next, referring to
FIGS. 2 and 8 , inoperation 112 of themethod 100, build-up process is performed to form a precursor structure.FIG. 8 illustrates the build-up process is performed over thefirst surface 322 of thechip 320. Alaminar circuit structure 400 may be formed by performing build-up process and laser-drilling techniques; thelaminar circuit structure 400 comprises: dielectric layers, for example, a firstdielectric layer 402 a, asecond dielectric layer 402 b, and a thirddielectric layer 402 c; patterned circuit layers, for example, the first patternedcircuit layer 404 in thesecond dielectric layer 402 b, the secondpatterned circuit layer 406 in the thirddielectric layer 402 c, the thirdpatterned circuit layer 408 on the thirddielectric layer 402 c; and vias, for example, a plurality offirst vias 410 in thefirst dielectric layer 402 a, a plurality ofsecond vias 412 in thesecond dielectric layer 402 b, and a plurality ofthird vias 414 in the thirddielectric layer 402 c. In the present disclosure, the number of the circuit layers by the build-up process is not limited, and the number can be adjusted as needed. - The material of the first, second, and third
dielectric layers third vias -
FIG. 8 illustrates aprecursor structure 402 is formed over thecarrier board 200; theprecursor structure 420 includes the patternedmetal layer 208, theadhesive layer 220, theelectronic component 310, thestopper 300, and thelaminar circuit structure 400. - As shown in
FIG. 8 , the patternedmetal layer 208 is electrically connected to the circuits of thelaminar circuit structure 400, for example, the first via 410, the first patternedcircuit layer 404, the second via 412, the secondpatterned circuit layer 406, the third via 414, and the thirdpatterned circuit layer 408. Further, a portion of the circuits of the thirdpatterned circuit layer 408 can serve as an electricallyconductive pad 408 a. - Next, referring to
FIGS. 2 and 9 , inoperation 114 of themethod 100, the carrier board is removed. Since thecarrier board 200 includes therelease layer 204, theprecursor structure 420 can be separated from thecarrier board 200 by lifting off or other stripping techniques. Themetal layer 206 may be also removed during or after the separation of thecarrier board 200.FIG. 9 is a schematic view showing thecarrier board 200 has been removed and theprecursor structure 420 is turned upside down. After thecarrier board 200 is removed, the patternedmetal layer 208, theadhesive layer 220, thestopper 300, and theconductive bumps 330 are exposed. In addition, the upper surfaces of the patternedmetal layer 208, theadhesive layer 220, thestopper 300, and theconductive bumps 330 are substantially even. - Next, referring to
FIGS. 2 and 10 , inoperation 116 of themethod 100, an outer layer is formed. First, an insulatinglayer 432 is formed over the patternedmetal layer 208, theadhesive layer 220, thestopper 300, and theconductive bump 330. Then, a plurality of via openings can be formed in the insulatinglayer 432 by using, for example, laser-drilling or lithography techniques; the via openings expose portions of the surfaces of the patternedmetal layer 208 and theconductive bumps 330. Thereafter, a photoresist layer (now shown) such as a dry film is formed on the insulatinglayer 432, and the photoresist layer is patterned to expose portions of the insulatinglayer 432 and the via openings by lithography process. Then, a deposition process such as electroplating and a removal process of the photoresist layer are performed to formfourth vias 434,fifth vias 436, and a fourthpatterned circuit layer 438. -
FIG. 10 illustrates theouter layer 430 is formed over the patternedmetal layer 208, theadhesive layer 220, thestopper 300, and theconductive bump 330. Theouter layer 430 includes the insulatinglayer 432, the forth via 434, the fifth via 436, and the fourthpatterned circuit layer 438. The insulatinglayer 432 covers the patternedmetal layer 208, theadhesive layer 220, thestopper 300, and theconductive bump 330. The fourth via 434 is within the insulatinglayer 432 and is electrically connected to the patternedmetal layer 208. The fifth via 436 is within the insulatinglayer 432 and is electrically connected to theconductive bump 330. The fourthpatterned circuit layer 438 is located over the insulatinglayer 432 and electrically connected to the fourth via 434 and the fifth via 436. Further, a portion of the circuits of the fourthpatterned circuit layer 438 can serve as an electricallyconductive pad 438 a. - The material of the insulating
layer 432 may include prepreg, Ajinomoto Build-up Film (ABF), photoimageable dielectric (PID), resin, or the like. For example, the resin may be phenolic resin, epoxy resin, polyamide resin, or polytetrafluoroethylene. The material of the fourth via 434 and the fifth via 435 may be, for example, copper, aluminum, or other suitable electrically conductive material. The material of the fourthpatterned circuit layer 438 may be, for example, copper, aluminum, or other suitable electrically conductive material. - As shown in
FIG. 10 , theouter layer 430, the patternedmetal layer 208, and thelaminar circuit structure 400 can be collectively referred to as acircuit layer structure 431. - Next, please refer to
FIGS. 2 and 11 , inoperation 118 of themethod 100, a solder mask layer is formed. As shown inFIG. 11 , a firstsolder mask layer 440 is formed on the outer side of thelaminar circuit structure 400; the firstsolder mask layer 440 has openings exposing the electricallyconductive pads 408 a of the thirdpatterned circuit layer 408. The secondsolder mask layer 442 is formed on the outer side of theouter layer 430; the secondsolder mask layer 442 has openings exposing the electricallyconductive pads 438 a of the fourthpatterned circuit layer 438. The material of the firstsolder mask layer 440 and the secondsolder mask layer 442 may be, for example, green lacquer or other suitable material. The firstsolder mask layer 440 and the secondsolder mask layer 442 may be formed by coating, printing, or the like. - Some embodiments of the present disclosure also provide a circuit board structure; referring to
FIG. 12 , thecircuit board structure 500 includes acircuit layer structure 510, anelectronic component 520, and astopper 530. Thecircuit layer structure 510 includes a plurality of dielectric layers 512 (e.g., the first, second, and thirddielectric layers circuits 514 in thedielectric layers 512; thecircuit layer structure 510 further comprises an insulatinglayer 513 located over the dielectric layers 512. Theelectronic component 520 is disposed in thecircuit layer structure 510 and between thefirst dielectric layer 512 a and the insulatinglayer 513; theelectronic component 520 includes achip 522 and aconductive bump 524, and thechip 522 has afirst surface 522 a and asecond surface 522 b that are oppositely disposed to each other; theconductive bump 524 is on thesecond surface 522 b of thechip 522. Thestopper 530 is within thecircuit layer structure 510 and abuts against theconductive bump 524. - As shown in
FIG. 12 , thecircuit layer structure 510 further includesvias 516 within the insulatinglayer 513 and electrically connected to theconductive bump 524. - As shown in
FIG. 12 , thecircuit board structure 500 further includes anadhesive layer 518 which is located between thesecond surface 522 b of thechip 522 and thefirst dielectric layer 512 a and adheres to theconductive bump 524. - In addition, solder mask layers 540 and 542 are respectively disposed on the two opposite outer sides of the
circuit layer structure 510 to protect thecircuit layer structure 510. - As shown in
FIG. 12 , an aspect of the present disclosure provides acircuit board structure 500 for embedded electronic components, including acircuit layer structure 510, anelectronic component 520, and astopper 530. Thecircuit layer structure 510 includes a plurality ofdielectric layers 512 andcircuits 514 in the dielectric layers 512. Theelectronic component 520 is disposed within thecircuit layer structure 510; theelectronic component 520 includes achip 522 and aconductive bump 524; thechip 522 has afirst surface 522 a and asecond surface 522 b that are oppositely disposed; thefirst surface 522 a of thechip 522 contacts adielectric layer 512 a of thedielectric layers 512; theconductive bump 524 is located on thesecond surface 522 b of thechip 522. Thestopper 530 is within thecircuit layer structure 510 and abuts against theconductive bump 524. -
FIG. 13 is a top view of acircuit board structure 600 at one of the manufacturing stages in accordance with some embodiments.FIG. 13 illustrates the relative positional relationship between theconductive bumps 624, thechip 622, and thestopper 630. In addition, a plurality ofconductive plugs 610 are distributed in thecircuit board structure 600. Thefirst portion 632 and thesecond portion 634 of thestopper 630 are at right angles, and one of theconductive bumps 624 abuts against thefirst portion 632 of thestopper 630 in a first direction x, and the one of theconductive bumps 624 abuts against thesecond portion 634 of thestopper 630 in a second direction y perpendicular to the first direction x. It is noted that the circuit board structure illustrated inFIG. 13 is merely an example; in other embodiments, thestopper 630 may not be seen from the top view, or thestopper 630 may be disposed at other positions relative to thechip 622. In fact, thestopper 630 can be disposed at any location that abuts any of theconductive bumps 624 of the electronic components, preferably abuts theconductive bump 624 located at a corner of the rectangular shape of thechip 622. -
FIG. 14 is a top view of acircuit board structure 700 in accordance with some embodiments, and the figure shows that thechips 722 are accurately mounted in thechip placement areas 702 in thecircuit board structure 700. - The present disclosure provides a circuit board structure for embedded electronic components and a method thereof, which improve the mounting accuracy of the electronic component by guiding the conductive bump of the electronic component to the predetermined positions of the substrate with a stopper.
- The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims (5)
1. A method of manufacturing a circuit board structure, comprising:
providing a carrier board comprising a release layer;
forming a stopper over the carrier board;
disposing an adhesive layer over the carrier board;
abutting a conductive bump of an electronic component against the stopper and placing the electronic component over the carrier board;
performing a build-up process; and
removing the carrier board.
2. The method of manufacturing the circuit board structure of claim 1 , wherein the electronic component comprises a chip, the chip has a first surface and a second surface that are oppositely disposed, and the conductive bump is located on the second surface, wherein the build-up process comprises:
forming a plurality of dielectric layers and circuits in the dielectric layers over the first surface of the chip.
3. The method of manufacturing the circuit board structure of claim 2 , further comprising forming an outer layer over the second surface of the chip and the conductive bump, and the outer layer comprises:
an insulating layer;
a via within the insulating layer and electrically connected to the conductive bump; and
a patterned circuit layer disposed over the insulating layer and electrically connected to the via.
4. The method of manufacturing the circuit board structure of claim 1 , wherein the abutting the conductive bump of the electronic component against the stopper and placing the electronic component over the carrier board comprises:
abutting the conductive bump against a first portion of the stopper; and
abutting the conductive bump against a second portion of the stopper, wherein the second portion is perpendicular to the first portion.
5. The method of manufacturing the circuit board structure of claim 1 , wherein the disposing the adhesive layer over the carrier board comprises: covering the stopper with the adhesive layer.
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US17/338,709 US20210298184A1 (en) | 2019-07-11 | 2021-06-04 | Method of manufacturing circuit board structure |
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TW108124560A TWI711346B (en) | 2019-07-11 | 2019-07-11 | Circuit board structure and manufacturing method thereof |
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US16/544,936 US11058012B2 (en) | 2019-07-11 | 2019-08-20 | Circuit board structure and manufacturing method thereof |
US17/338,709 US20210298184A1 (en) | 2019-07-11 | 2021-06-04 | Method of manufacturing circuit board structure |
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US16/544,936 Division US11058012B2 (en) | 2019-07-11 | 2019-08-20 | Circuit board structure and manufacturing method thereof |
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US8225503B2 (en) * | 2008-02-11 | 2012-07-24 | Ibiden Co., Ltd. | Method for manufacturing board with built-in electronic elements |
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US9087847B2 (en) * | 2012-08-14 | 2015-07-21 | Bridge Semiconductor Corporation | Thermally enhanced interconnect substrate with embedded semiconductor device and built-in stopper and method of making the same |
US20160234941A1 (en) * | 2015-02-10 | 2016-08-11 | Samsung Electro-Mechanics Co., Ltd. | Printed circuit board, semiconductor package and method of manufacturing the same |
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JP2005180930A (en) * | 2003-12-16 | 2005-07-07 | Ricoh Co Ltd | Semiconductor sensor device and its manufacturing method |
KR20050116760A (en) * | 2004-06-08 | 2005-12-13 | (주) 윈팩 | Package for image sensor |
TWI501376B (en) * | 2009-10-07 | 2015-09-21 | Xintec Inc | Chip package and fabrication method thereof |
TWI517312B (en) | 2012-10-17 | 2016-01-11 | 鈺橋半導體股份有限公司 | Wiring board with shielding lid and shielding slots as electromagnetic shields for embedded device |
-
2019
- 2019-07-11 TW TW108124560A patent/TWI711346B/en active
- 2019-08-20 US US16/544,936 patent/US11058012B2/en active Active
-
2021
- 2021-06-04 US US17/338,709 patent/US20210298184A1/en not_active Abandoned
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Publication number | Priority date | Publication date | Assignee | Title |
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US8225503B2 (en) * | 2008-02-11 | 2012-07-24 | Ibiden Co., Ltd. | Method for manufacturing board with built-in electronic elements |
US8415792B2 (en) * | 2010-08-04 | 2013-04-09 | International Business Machines Corporation | Electrical contact alignment posts |
US9087847B2 (en) * | 2012-08-14 | 2015-07-21 | Bridge Semiconductor Corporation | Thermally enhanced interconnect substrate with embedded semiconductor device and built-in stopper and method of making the same |
US20160234941A1 (en) * | 2015-02-10 | 2016-08-11 | Samsung Electro-Mechanics Co., Ltd. | Printed circuit board, semiconductor package and method of manufacturing the same |
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US20210014975A1 (en) | 2021-01-14 |
TW202103525A (en) | 2021-01-16 |
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TWI711346B (en) | 2020-11-21 |
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