US20210257539A1

US20210257539A1 - Semiconductor Strain Gauge and Method for Manufacturing Same

Info

Publication number: US20210257539A1
Application number: US17/111,507
Authority: US
Inventors: Nihat Okulan
Original assignee: Advanced Nanostructures LLC
Current assignee: Advanced Nanostructures LLC
Priority date: 2017-05-11
Filing date: 2020-12-04
Publication date: 2021-08-19
Also published as: US20190383677A1; US10879449B2

Abstract

Semiconductor strain gages fabricated on Silicon-on-insulator (SOI) material, and the method of making them. Force sensing elements are uniformly batch-fabricated at wafer level and singulated individually by a wire bonding method. In another method, they are singulated by plucking them off the wafer from their attachment site.

Description

RELATED APPLICATIONS

This patent application is a continuation of U.S. patent application Ser. No. 15/592,796, filed May 11, 2017, the entirety of which is incorporated by reference.

FIELD OF THE INVENTION

The present invention relates to semiconductor strain gages. More particularly, the present invention relates to semiconductor strain gages fabricated on Silicon-oninsulator (SOI) material, and the method of making such gages.

BACKGROUND OF THE INVENTION

Objects subject to external forces undergo strain. In numerous circumstances, it is desirable to know the strain a particular object is experiencing in order to preserve the structural integrity of the object, and/or the overall device of which the object is a part. Examples include automobile parts, airplane parts, highway and bridge components, railway components and components of devices used in the aerospace industry.
An object experiencing strain will typically experience a deformation in its shape. Strain gages serve to measure such strain, by measuring the deformation of the object. Strain gages are typically bonded to the objects in order to best detect changes in physical property of the object.
An ideal strain gage will be small such that it does not add to the bulk of the device. In addition, an ideal strain gage will not undergo physical changes itself and/or will not have its performance altered as a result of temperature variations or other environmental variations. Semiconductors are commonly used as strain gages as they are sensitive to many physical and electrical effects and signals. Semiconductor strain gages depend on the piezoresistive effects of silicon or germanium. As an electrical conductor is stretched, it becomes longer and narrower, thus increasing its resistance. This piezo resistance effect is used as a measure of applied stress.
Semiconductor strain gages consist, in general, of a thin and strain sensitive crystal element that has leads attached to it to measure resistance change. They offer many advantages to conventional foil gages and metal wires, such as smaller size, higher sensitivities, and higher resistance values. Many of the currently available strain gages are based on bulk single crystal silicon, utilizing conventional etching and photolithography. Batch fabrication of sensors based on silicon is nowadays very cost efficient. For example, thousands of sensors can be micro-fabricated on one silicon wafer. The reduced fabrication cost allows those sensors to be implemented onto devices that were too expensive to be monitored in the past. Further, the reduction in sensor size increases the numbers of sensors that can be fabricated in one batch. However, the post fabrication and packaging steps become more complicated because smaller sensors are more difficult to handle.
Moreover, the performance and resistance change of strain gages depend immensely on the thickness of the gage. The current methods of bulk manufacturing strain gages present a major disadvantage in achieving a uniform thickness of sensors across a given wafer, resulting in higher yield loss and cost. The thickness of the fabricated gages is highly dependent on the uniformity of the etching process used in the formation of the sensors. One drawback of currently available strain gages is that when conventional manufacturing techniques are applied, the uniformity in thickness is in general poor across the wafer.
In addition, that performance and resistance change of strain gages also depends strongly on dimensional variations on the wafer, such as different exposed etch areas. Considering that the sensor thickness relies upon the thinning of a silicon substrate that could be up to 300 times the desired thickness, the achieved resistance value of the gage can easily vary by 30% or more. Furthermore, once the sensors are fabricated on a wafer, the singulation of individual sensors is difficult because of their small size. Current methods require picking individual sensors out of a solution, which is difficult and time consuming.
What is required is a semiconductor strain gage with a method to precisely control the gage thickness, resulting in improved strain gage resistance uniformity. Further, an easy way for post fabrication handling and packaging of singulated strain gages is needed.

SUMMARY OF THE INVENTION

The current invention addresses the foregoing issues and drawbacks. In one embodiment, the current invention consists of strain gages with an electrically resistive device layer and contact pads that measure dynamic and static strain. The present invention also provides a method of manufacturing such device on a wafer in a uniform manner, and a method of freeing such device from substrates for post-manufacturing processing.
The wafer is preferably comprised of silicon, which takes advantage of the piezoresistive characteristic of semiconductors. The strain gages are preferably fabricated on pre-doped Silicon-On-Insulator (SOI) wafers, wherein the device layer thickness and handle wafer thickness is precisely controlled by wafer manufacturers.
In one preferred embodiment, the strain gages are first lithographically fabricated on the device layer. This can be followed by wire bonding the gages and then singulating the gages by etching the handle wafer without attacking the gages on the device layer.
In another preferred embodiment of this invention, the strain gages are first lithographically fabricated on the device layer. The gages are designed to be attached to the frame after the release etch. In this way the gages can be plucked from the wafer for post fabrication handling and packaging.

BRIEF DESCRIPTION OF DRAWINGS

The reasoning and advantages of this invention will appear clearer when considering the detailed descriptions in connection with the figures. These drawings are not to scale and are for the purpose of concept illustration. For example, the thickness and width of the device layer in some figures are purposely enhanced to illustrate sensor characteristics, such as active sensing area and connecting pads, compared to the sacrificial handle wafer.

FIG. 1A shows a perspective view of a SOI wafer that is holding thousands of strain gages. FIG. 1B shows a zoomed in drawing identifying several dies. FIG. 1C illustrates a further zoomed in version of the wafer, indicating several parts of a given die. FIG. 1D shows a cross-sectional view of a preferred embodiment of this invention.

FIGS. 2A-2C show different possible designs of strain gages packed on dies.

FIGS. 3A-3D show fabrication steps of strain gages made out of the device layer of a SOI wafer, in one embodiment of the device of the present invention.

FIGS. 4A-4D illustrate another embodiment in which a different method of fabricating strain gages out of the device layer of a SOI wafer is employed.

FIGS. 5A-5F illustrate fabrication steps to release strain gages from the substrate wafer in one embodiment of the present invention.

FIGS. 6A-6F illustrate the progression of strain gages fabricated from the device layer of a SOI wafer from wafer level to die level, from die level to individual nonspecific gage. In this embodiment, gages are still attached to the frame and can be plucked from the wafer.

FIGS. 7A-7F illustrate steps taken in order to release strain gages from the substrate wafer in one embodiment of the present invention In this embodiment, gages are still attached to the frame to be plucked out from the wafer.

FIG. 7A shows a cross-sectional view of a strain gage. FIG. 7B shows a cross-sectional view of a strain gage and passivation layer. FIG. 7C illustrates a cross-sectional view of a strain gage with BOX layer. FIG. 7D shows a cross-sectional view of a strain gage with BOX layer removed. FIG. 7E shows a cross-sectional view of a strain gage freed from the passivation layer and carrier material. FIG. 7F shows a wafer-level view of a SOI wafer,

DETAILED DESCRIPTION OF THE INVENTION

The current invention is now described with reference to the figures. Components appearing in more than one figure bear the same reference numerals.
Preferred embodiments of the present invention are described herein. Other variations of the present invention may also be performed and are claimed in the present patent, as referenced herein. The invention is described in combination with particular embodiments, but it is not the intention to limit the invention to the described embodiments. Rather, it is intended to encompass alternatives, equivalents and modifications as described by the scope of the presented claims.
Typically, when fabricating semiconductor devices, many devices are fabricated on one wafer. As devices become smaller, and thus typically cheaper, it becomes more difficult to free the devices from the wafer in a clean and high yielding way once the fabrication is finished. This invention describes a method of making high yielding semiconductor strain gages and methods to free them from the wafer for post packaging and handling.
FIG. 1A shows a perspective view of a SOI wafer that is holding thousands of strain gages.
FIG. 1B shows a zoomed in drawing identifying several dies. These dies are separate clusters of strain gages.
FIG. 1C illustrates a further zoomed in version of the wafer, indicating several parts of a given die.
FIG. 1D shows a cross-sectional view of a preferred embodiment of this invention. The reactive part of the strain gage 110 is made out of the device layer of the SOI wafer. It sits on top of the buried oxide (BOX) layer 140 and the carrier wafer 130. These two pieces of the invention and the frame 100 are essential in the fabrication process and will be described herein in detail.
Metallic interconnects 120 are formed on the reactive part of the strain gage and are needed to gather an electrical signal that is proportional to the stress applied to the gages. Electrical wires are attached to those interconnections, or pads, of the gage in order to connect the gage to e.g. supporting electronics.
FIG. 2A shows one possible design of strain gages. This design type is a straight gage with two metallic connection pads on the opposing ends. FIG. 2B shows another possible design of strain gauges. This type is a U-shaped design. This type of strain gage can be used if there is a desire to keep the electrical contacts away from the stressible part of the object to be measured. For example, the U-shaped sensor can be attached to a diaphragm of a pressure sensor in such a way that only the reactive part of the gage is exposed and attached to the flexible part of the diaphragm, and where the electrical contacts are kept outside the diaphragm area.
FIG. 2C show another straight gage design, packed differently on a die as compared to the embodiment depicted in FIG. 2A.
The gages depicted in FIG. 2 are preferred embodiments of the present invention, and as such, illustrate possible designs of strain gages of the present invention. However, the present invention is not limited to the depicted embodiments. All of depicted embodiments are made from the device layer of a SOI wafer, with at least two metal connections.
FIG. 3A depicts the starting material for making the strain gages. The SOI wafer shown consists of a device layer 300 with a typical, although not required, thickness of 10 um. This thickness is essential in attaining the target resistance value of the strain gage and thus a high yielding gage production. The target resistance value is inversely proportional to the device layer thickness. If, for example, a desired target resistance of 10 kOhm requires a thickness of say 10 um and a maximum allowable variation of ±5000 hm, the thickness cannot vary more than ±0.5 um. The device layer thickness can be precisely controlled by the wafer manufacturer, such as SOITEC or ULTRASIL, and the variation can be specified to be less than 5 percent. The buried oxide layer 310 (BOX) separates the device layer from the carrier wafer 330 and serves as an etch stop for the gage fabrication and the release process.
FIG. 3B shows lithographically formed metallic interconnects between the strain gage and the environment. A typical metallic pad 340 may be aluminum, however, other materials may also be employed. A typical thickness is approximately 1 um. The metallic pad may be patterned on the device layer by a standard wet etch or a lift-off technique.
FIG. 3C shows a trench 350 that has been lithographically formed into the device layer. This trench forms the outline of a strain gage and may be created by a standard wet or dry etch process. The preferred method, although not required, to form this trench is a straight dry etch process, such as the BOSCH etch process.
FIG. 3D depicts a sintering process to increase the metal adhesion to the device layer and to form an improved, ohmic contact. The sintering temperature may be anywhere from 200C to 600C. The preferred temperature for the use with aluminum is 450C. When other materials are employed in the place of aluminum, the preferred temperature may differ.
The sequence of images shown in FIGS. 4A to 4D presents an alternative way of fabricating strain gages from the device layer. In this sequence, the trench is patterned before the metal pads are formed. FIG. 4A indicates the starting SOI material, which is identical to that depicted in FIG. 3A.
FIG. 4B shows a trench that has been lithographically formed into the device layer. This trench forms the outline of a strain gage and can be created by a standard wet or dry etch process. The preferred method, although not required, to form this trench is a straight dry etch process, such as the BOSCH etch process.
FIG. 4C shows lithographically formed metallic interconnects between the strain gage and the environment. A typical metallic pad can be, although not required, aluminum. A typical thickness in this embodiment may be approximately 1 um. It may be patterned on the device layer by a standard wet etch or a lift-off technique.
FIG. 4D indicates a sintering process to increase the metal adhesion to the device layer and to form an improved, ohmic contact. The sintering temperature may preferably be anywhere from 200C to 600C. The preferred temperature for the use with aluminum is 450C. When other materials are employed, the preferred temperature may vary.
After the strain gages are formed on the device layer of the SOI wafer, the gages may be released (or freed) from the substrate wafer. The sequence of FIGS. 5A to 5F depict one method of freeing the strain gages. The shown sequence may be performed at wafer level, or the wafer may be diced or cleaved into smaller pieces.
FIG. 5A shows the cross-sectional view of one strain gage after the gages have been fabricated on a device layer of a SOI wafer, as described above. Wires 510 are attached to the pads. This may be done by wire bonding gold or aluminum to the pads. Other methods may alternatively be employed.
FIG. 5B shows the step of bonding gold or aluminum wires to the pads. In order to protect the strain gages and wires during the release process, the strain gages and wires are passivated and attached to a carrier. One preferred passivation material 520, is black wax from Apiezon. Other materials may alternatively be employed. The passivation material may be melted and attached to a stainless steel plate or any other inert material 530 that is not attacked by the removal process of the SOI handle wafer 540. A typical method, but not limited to this method, is using a wet etchants such as Potassium Hydroxide or HNA mixtures. Those etchants are etching the handle wafer at a rate that is much larger than the etch rate of the BOX 550.
FIG. 5D shows the remaining parts of the gage fabrication after the handle wafer has been etched away. As illustrated in FIG. 5E, the BOX layer may be removed, for example by using a buffered hydrofluoric acid solution, which does not attack the exposed gages. The final step is indicated in FIG. 5F, wherein the gages are freed from the passivation layer and the carrier material. A preferred method is by immersion into solvents, such as Xylene, Acetone and Methanol. Other methods may alternatively be employed.
Another method of making the strain gages and releasing them from the SOI wafer, as covered in this invention, is by designing the strain gages such that they are attached to the frame of the device layer of the SOI wafer. After removing the handle wafer of the SOI wafer, the gages can be plugged from the frame and placed into the desired location.
FIGS. 6A and 6B show the design of straight strain gages. As can be seen, the endings of the gages 610 are designed to be attached to the frame. FIGS. 6C and 6D show another way of attaching previously mentioned gages. Those gages are designed such that they are attached to the frame via frame extensions 620. Another way, 630, of attaching previously described gages is indicated in FIG. 6E. The method of making those gages on the device layer of a SOI wafer is identical as to the way described in FIGS. 3 and/or FIG. 4. The cross-sectional view can be seen in FIG. 6F. As described earlier, the strain gages are lithographically fabricated from the device layer of an SOI wafer. However, in comparison with FIG. 3D, at least one end of the gage 640 is attached to the frame.
One preferred method of releasing gages that are attached to the frame, is illustrated in FIGS. 7A to 7E. The shown sequence may be effectuated on a wafer level, or the wafer may be diced, or cleaved, into smaller pieces. FIG. 7A shows the cross-sectional view of one strain gage after the gages have been fabricated on a device layer of a SOI wafer. The fabrication has been described in FIGS. 3 and 4. In order to protect the strain gages and pads during the release process, the strain gages and pads may preferably be passivated, as shown in FIG. 7B. One preferred passivation material 710, is black wax from Apiezon. Other materials may alternatively be employed. The passivation material may be melted and attached to a stainless steel plate or any other inert material 720 that is not attacked by the removal process of the SOI handle wafer 730. The steel plate serves as mechanical support and is not needed when alternative, firmer, passivation layers, such as polyimides, are used.
FIG. 7C illustrates the removal of the handle wafer. A typical method that may be employed is using a wet etchants such as Potassium Hydroxide or HNA mixtures. Those etchants are etching the handle wafer at a rate that is much larger than the etch rate of the BOX 740. However, other known methods may alternatively be employed.
As illustrated in FIG. 7D, the BOX layer is removed, for example, by using a buffered hydrofluoric acid solution, which does not attack the exposed gages.
The final step is shown in FIG. 7E, wherein the gages are freed from the passivation layer and the carrier material. A preferred method is by immersion into solvents, such as Xylene, Acetone and Methanol. However, other methods may alternatively be employed. As shown, the gages are still attached to the frame of the device layer and the location of the attachment 750 creates a mechanical stress point that breaks off when plugged, e.g. with vacuum tweezers.
Preferred embodiments have been used to describe the present invention. However, persons familiar in the art will understand that variations are possible within the scope of this invention. For example, different shape of gages may be made or alternative process steps, such as sinter temperature or etch solutions may be used. Nonetheless, it should be recognized that alterations may be made without departing from the scope and spirit of the invention. Consequently, the scope and spirit of the invention should be established by the appended claims and not limited by the specific embodiments described above.

Claims

1) A method of manufacturing semiconductor strain gauges comprising:

forming an electrically resistive path including at least two metallic pads for electrical connection; fabricating an electrically resistive element by photo-lithographically patterning a device layer of a SOI wafer; and etching the device layer; wherein said metallic pads are generated on top of said electrically resistive element by photo-lithographically patterning the pads via metal deposition and metal etching; and said gages are located on top of a BOX of the SOI wafer.

2) The method of claim 1, wherein said metallic pads are patterned using a lift-off technique.

3) The method of claim 1, wherein each gage is physically attached at least at one location to the frame of the device layer.

4) A method of freeing the semiconductor strain gauges of claim 1 comprising:

attaching metal wires to said metallic pads; protecting the device layer of said semiconductor strain gages and said metal wires by using a passivation substance and an inert substrate for mechanical support; etching said carrier wafer of said semiconductor strain gage;

etching the BOX of the SOI wafer; and freeing the Individual guages by Immersion in solvents to remove passivation substance.

5) A method of singulating the devices of claim 3 comprising protecting said device layer through the use of a passivation substance and an inert substrate for mechanical support; etching said carrier wafer; etching said BOX of the SOI wafer; clearing gages by immersion of the remaining portion of said SOI wafer in solvents to remove said passivation substance.

6) A semiconductor strain gage semiconductor comprising an electrically resistive path including at least two metallic pads for electrical connection; and a photo-lithographically patterned device layer of a SOI wafer.