US20200357634A1 - Method for Manufacturing a Semiconductor Device - Google Patents
Method for Manufacturing a Semiconductor Device Download PDFInfo
- Publication number
- US20200357634A1 US20200357634A1 US16/939,702 US202016939702A US2020357634A1 US 20200357634 A1 US20200357634 A1 US 20200357634A1 US 202016939702 A US202016939702 A US 202016939702A US 2020357634 A1 US2020357634 A1 US 2020357634A1
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- Prior art keywords
- layer
- dielectric layer
- film
- underlayer
- dielectric
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 59
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 238000000034 method Methods 0.000 title claims description 174
- 239000002243 precursor Substances 0.000 claims abstract description 147
- 238000000151 deposition Methods 0.000 claims abstract description 111
- 239000000758 substrate Substances 0.000 claims abstract description 66
- 238000000059 patterning Methods 0.000 claims abstract description 27
- 239000010410 layer Substances 0.000 claims description 348
- 230000008569 process Effects 0.000 claims description 135
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- 238000005530 etching Methods 0.000 claims description 61
- 239000001301 oxygen Substances 0.000 claims description 34
- 229910052760 oxygen Inorganic materials 0.000 claims description 34
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 33
- 229920002120 photoresistant polymer Polymers 0.000 claims description 30
- 230000000873 masking effect Effects 0.000 claims description 16
- 229920000642 polymer Polymers 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
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- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
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- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 2
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
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- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
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- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 2
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- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
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- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 2
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 2
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- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
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- MNWRORMXBIWXCI-UHFFFAOYSA-N tetrakis(dimethylamido)titanium Chemical compound CN(C)[Ti](N(C)C)(N(C)C)N(C)C MNWRORMXBIWXCI-UHFFFAOYSA-N 0.000 description 2
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- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 1
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- OWKFQWAGPHVFRF-UHFFFAOYSA-N n-(diethylaminosilyl)-n-ethylethanamine Chemical compound CCN(CC)[SiH2]N(CC)CC OWKFQWAGPHVFRF-UHFFFAOYSA-N 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
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- 230000002441 reversible effect Effects 0.000 description 1
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- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
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- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- GIRKRMUMWJFNRI-UHFFFAOYSA-N tris(dimethylamino)silicon Chemical compound CN(C)[Si](N(C)C)N(C)C GIRKRMUMWJFNRI-UHFFFAOYSA-N 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0335—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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- C23C16/40—Oxides
- C23C16/401—Oxides containing silicon
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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- C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
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- C23C16/45525—Atomic layer deposition [ALD]
- C23C16/45527—Atomic layer deposition [ALD] characterized by the ALD cycle, e.g. different flows or temperatures during half-reactions, unusual pulsing sequence, use of precursor mixtures or auxiliary reactants or activations
- C23C16/45529—Atomic layer deposition [ALD] characterized by the ALD cycle, e.g. different flows or temperatures during half-reactions, unusual pulsing sequence, use of precursor mixtures or auxiliary reactants or activations specially adapted for making a layer stack of alternating different compositions or gradient compositions
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- C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
- C23C16/45523—Pulsed gas flow or change of composition over time
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- C23C16/45536—Use of plasma, radiation or electromagnetic fields
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- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
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- C23C16/45553—Atomic layer deposition [ALD] characterized by the use of precursors specially adapted for ALD
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
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- H01L29/66409—Unipolar field-effect transistors
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- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
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- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
- C23C14/228—Gas flow assisted PVD deposition
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- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
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- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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Definitions
- Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a semiconductor substrate, and patterning the various material layers using lithography and etching processes to form circuit components and elements thereon.
- FIGS. 1A-1H illustrate cross-sectional views of various intermediary stages of manufacturing conductive lines in a semiconductor device using a low-temperature dielectric film in accordance with some embodiments.
- FIG. 2 illustrates a deposition system for depositing a low-temperature dielectric film in accordance with some embodiments.
- FIG. 3 illustrates a control unit for a deposition system in accordance with some embodiments.
- FIG. 4 illustrates experimental results reflecting the relationship between underlayer damage and low-temperature dielectric film thicknesses in accordance with some embodiments.
- FIGS. 5A-5C illustrate cross-sectional views of various intermediary stages of manufacturing a semiconductor device using a low-temperature dielectric film in accordance with some embodiments.
- FIGS. 6A-6J illustrate cross-sectional views or plan views of various intermediary stages of manufacturing conductive lines in a semiconductor device using a low-temperature dielectric film in accordance with some embodiments.
- FIGS. 7A-15B illustrate cross-sectional views, plan views, or perspective views of various intermediary stages of manufacturing conductive lines in a semiconductor device using a low-temperature dielectric film in accordance with some embodiments.
- FIGS. 16-25 illustrate cross-sectional views of various intermediary stages of manufacturing a FinFET semiconductor device using a low-temperature dielectric film in accordance with some embodiments.
- first and second features are formed in direct contact
- additional features may be formed between the first and second features, such that the first and second features may not be in direct contact
- present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures.
- the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
- the apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- a low-temperature dielectric (LTD) film used during processing semiconductor devices.
- the LTD film described herein and the process, method, or materials described herein can be used in many applications, including fin-type field effect transistors (FinFETs).
- the fins may be patterned to produce a relatively close spacing between features, for which this disclosure is well-suited.
- spacers used in forming fins of FinFETs also referred to as mandrels, can be formed using techniques or materials described herein.
- the LTD film may be used as part of a multi-layer photoresist, in a multi-patterning process, or as a film to decrease feature size during patterning.
- the embodiments are not intended to be limited to such uses.
- the term “LTD” refers to a dielectric deposited using a relatively low process temperature (e.g., 200° C. or less). In some cases, depositing a dielectric material at lower process temperatures can reduce the possibility of damage to layers beneath the dielectric material during the deposition.
- FIGS. 1A-1H illustrate cross-sectional views of intermediate stages of forming conductive lines 120 in an inter-layer dielectric (ILD) layer 112 on a semiconductor substrate 102 .
- ILD inter-layer dielectric
- an LTD film 116 is used as an etching mask for patterning of an ILD layer 112 during formation of conductive lines 120 .
- the embodiment shown in FIGS. 1A-1H may, for example, be part of forming conductive lines in a Back End of Line (BEOL) process.
- the ILD layer 112 and an underlayer 114 are formed in semiconductor device 100 .
- ILD layer 112 may be formed over a semiconductor substrate 102 .
- the semiconductor substrate 102 may be formed of a semiconductor material such as silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate.
- SOI semiconductor-on-insulator
- the semiconductor substrate 102 may include other semiconductor materials, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof.
- Other substrates such as multi-layered or gradient substrates, may also be used.
- Devices (not illustrated), such as transistors, diodes, capacitors, resistors, etc., may be formed in and/or on an active surface of semiconductor substrate 102 .
- the devices may include a variety of active devices such as transistors and the like and passive devices such as capacitors, resistors, inductors and the like.
- the active devices and passive devices may be formed using any suitable methods either within or else on the substrate 102 . In some cases, the semiconductor substrate 102 may be omitted.
- the ILD layer 112 may include a dielectric material formed using, for example, spin-on coating, CVD, flowable CVD, plasma-enhanced CVD (PECVD), or other deposition methods.
- the ILD layer 112 may be formed of Phospho-Silicate glass (PSG), Boro-Silicate Glass (BSG), Boron-Doped Phospho-Silicate Glass (BPSG), undoped Silicate Glass (USG), Tetra Ethyl Ortho Silicate (TEOS) oxide, or the like.
- FIG. 1A also illustrates the formation of an underlayer 114 over ILD layer 112 .
- underlayer 114 may be a photoresist layer or a polymer layer.
- Underlayer 114 may be formed by a spin-on process or another suitable process.
- underlayer 114 may be formed to an initial thickness T 1 , which in some cases is between about 10 nm and about 600 nm.
- T 1 initial thickness
- these thicknesses are meant to be illustrative only, and are not intended to limit the scope of the embodiments, as the precise thickness of the as-deposited layer may be any suitable desired thickness.
- FIGS. 1A-1G illustrate ILD layer 112 being in physical contact with semiconductor substrate 102 or underlayer 114 being in physical contact with ILD layer 112
- intervening layers may include another ILD layer comprising a low-k dielectric and having contact plugs formed therein, IMD layers having conductive lines and/or vias formed therein, one or more intermediary layers (e.g., etch stop layers, adhesion layers, anti-reflective coating (ARC) layers, etc.), combinations thereof, and the like.
- an optional etch stop layer (not illustrated) may be disposed directly under ILD layer 112 .
- An etch stop layer may act as a stop for an etching process subsequently performed on the ILD layer 112 .
- the material and process used to form the etch stop layer may depend on the material of ILD layer 112 .
- a low-temperature dielectric (LTD) film 116 is formed over underlayer 114 .
- LTD film 116 may be part of a multi-layer photoresist.
- LTD film 116 may be a middle layer of a multi-layer photoresist stack, and underlayer 114 may be the bottom layer of a multi-layer photoresist stack.
- LTD film 116 may be formed of SiN, SiON, SiCON, SiC, SiOC, SiO, TiO, an oxide, other dielectrics, combinations thereof, or the like.
- LTD film 116 may be formed by a deposition process such as plasma enhanced chemical vapor deposition (PECVD), low pressure CVD (LPCVD), plasma vapor deposition (PVD), plasma-enhanced atomic layer deposition (PEALD), or the like.
- PECVD plasma enhanced chemical vapor deposition
- LPCVD low pressure CVD
- PVD plasma vapor deposition
- PEALD plasma-enhanced atomic layer deposition
- LTD film 116 may be formed to a thickness between about 10 ⁇ and about 50 nm.
- these thicknesses are meant to be illustrative only, and are not intended to limit the scope of the embodiments, as the precise thickness of the as-deposited layer may be any suitable desired thickness.
- FIGS. 2-3 illustrate a deposition system 200 that may be used to form a low-temperature dielectric (LTD) film such as LTD film 116 .
- deposition system 200 forms the LTD film using a PEALD process.
- deposition system 200 receives a first precursor material from a first precursor delivery system 205 and a second precursor material from a second precursor delivery system 206 to form layers of materials onto substrate 102 .
- first precursor delivery system 205 and second precursor delivery system 206 may work in conjunction with one another to supply the various different precursor materials to a deposition chamber 203 in which substrate 102 is placed.
- first precursor delivery system 205 and second precursor delivery system 206 may have physical components that are similar with each other.
- other precursor delivery systems may be part of deposition system 200 , and may be similar to first precursor delivery system 205 or second precursor delivery system 206 .
- first precursor delivery system 205 and second precursor delivery system 206 may each include a gas supply 207 and a flow controller 209 (labeled in FIG. 2 with regards to first precursor delivery system 205 but not labeled for clarity with respect to second precursor delivery system 206 ).
- gas supply 207 may supply the first precursor material to deposition chamber 203 .
- Gas supply 207 may be a vessel, such as a gas storage tank, that is located either locally to deposition chamber 203 or else may be located remotely from deposition chamber 203 .
- gas supply 207 may be a facility that independently prepares and delivers the first precursor material to flow controller 209 . Any suitable source for the first precursor material may be utilized as gas supply 207 , and all such sources are fully intended to be included within the scope of the embodiments.
- Gas supply 207 may supply the desired first precursor material to flow controller 209 .
- Flow controller 209 may be utilized to control the flow of the first precursor material to precursor gas controller 213 and, eventually, to deposition chamber 203 , thereby also helping to control the pressure within deposition chamber 203 .
- Flow controller 209 may be, e.g., a proportional valve, a modulating valve, a needle valve, a pressure regulator, a mass flow controller, combinations of these, or the like.
- any suitable method for controlling and regulating the flow of the carrier gas to precursor canister 211 may be utilized, and all such components and methods are fully intended to be included within the scope of the embodiments.
- first precursor delivery system 205 and second precursor delivery system 206 have been described herein as having identical components, this is merely an illustrative example and is not intended to limit the embodiments in any fashion. Any type of suitable precursor delivery system, with any type and number of individual components identical to or different from any of the other precursor delivery systems within deposition system 200 , may alternatively be utilized. All such precursor systems are fully intended to be included within the scope of the embodiments.
- gas supply 207 may store a carrier gas and the carrier gas may be introduced into a precursor canister (not separately illustrated), which stores the first precursor material in the solid or liquid state.
- the carrier gas is then used to push and carry the first precursor material as the first precursor material either evaporates or sublimates into a gaseous section of the precursor canister before being sent to precursor gas controller 213 .
- a carrier gas may be an inert gas such as Ar, He, or another gas. Any suitable method and combination of units may be utilized to provide the first precursor material, and all such combination of units are fully intended to be included within the scope of the embodiments.
- First precursor delivery system 205 and second precursor delivery system 206 may supply their individual precursor materials into a precursor gas controller 213 .
- Precursor gas controller 213 connects and isolates first precursor delivery system 205 and second precursor delivery system 206 from deposition chamber 203 in order to deliver the desired precursor materials to deposition chamber 203 .
- Precursor gas controller 213 may include such devices as valves, flow meters, sensors, and the like to control the delivery rates of each of the precursors, and may be controlled by instructions received from a control unit 215 (described further below with respect to FIG. 3 ).
- Precursor gas controller 213 upon receiving instructions from control unit 215 , may open and close valves so as to connect one or more of first precursor delivery system 205 and second precursor delivery system 206 to deposition chamber 203 and direct a desired precursor material through a manifold 216 , into deposition chamber 203 , and to a showerhead 217 .
- showerhead 217 may be utilized to disperse the chosen precursor material(s) into deposition chamber 203 and may be designed to evenly disperse the precursor material in order to minimize undesired process conditions that may arise from uneven dispersal.
- showerhead 217 may have a circular design with openings dispersed evenly around showerhead 217 to allow for the dispersal of the desired precursor material into deposition chamber 203 .
- Deposition chamber 203 may receive the desired precursor materials and expose the precursor materials to underlayer 114 , and deposition chamber 203 may be any desired shape that may be suitable for dispersing the precursor materials and contacting the precursor materials with underlayer 114 .
- deposition chamber 203 has a cylindrical sidewall and a bottom.
- deposition chamber 203 is not limited to a cylindrical shape, and any other suitable shape, such as a hollow square tube, an octagonal shape, or the like, may be utilized.
- deposition chamber 203 may be surrounded by a housing 219 made of material that is inert to the various process materials.
- housing 219 may be any suitable material that can withstand the chemistries and pressures involved in the deposition process, in an embodiment housing 219 may be steel, stainless steel, nickel, aluminum, alloys of these, combinations of these, and like.
- substrate 102 may be placed on a mounting platform 221 in order to position and control substrate 102 and underlayer 114 during the deposition processes.
- Mounting platform 221 may be disposed on the bottom of deposition chamber 203 , and may include heating mechanisms in order to heat substrate 102 during the deposition processes.
- any number of mounting platforms 221 may additionally be included within deposition chamber 203 .
- mounting platform 221 may also include a first electrode 230 coupled to a first RF generator 232 .
- First electrode 220 may be electrically biased by first RF generator 232 (under control of control unit 215 ) at a RF voltage during a deposition process such as a PEALD process.
- first electrode 230 is used to provide a bias to the incoming gases (e.g., precursor materials and/or carrier gases) and assist to ignite them into a plasma.
- a carrier gas may be ignited into a plasma along with a precursor material.
- first electrode 230 is also used to maintain a plasma during a deposition by maintaining the bias.
- Deposition chamber 203 also includes an upper electrode 231 , for use as a plasma generator.
- the plasma generator may be a transformer coupled plasma generator and may be, e.g., a coil.
- the coil may be attached to a RF generator 233 that is used to provide power to the upper electrode 231 (under control of control unit 215 ) in order to ignite gases into a plasma.
- the upper electrode 231 is described above as a transformer coupled plasma generator, embodiments are not intended to be limited to a transformer coupled plasma generator. Rather, any suitable method of generating the plasma, such as inductively coupled plasma systems, magnetically enhanced reactive ion etching, electron cyclotron resonance, a remote plasma generator, or the like, may alternatively be utilized.
- incoming gases may be ignited into a plasma by a plasma generator located in a separate chamber that is connected to deposition chamber 203 , or incoming gases may be ignited into a plasma in deposition chamber 203 by a plasma generator that is not coupled to mounting platform 221 . All such methods are fully intended to be included within the scope of the embodiments.
- deposition chamber 203 and mounting platform 221 may be part of a cluster tool system (not shown).
- the cluster tool system may be used in conjunction with an automated handling system in order to position and place substrate 102 into deposition chamber 203 prior to the deposition processes, position, hold substrate 102 during deposition processes, and remove substrate 102 from deposition chamber 203 after the deposition processes.
- Deposition chamber 203 may also have an exhaust outlet 225 for exhaust gases to exit deposition chamber 203 .
- a vacuum pump 223 may be connected to exhaust outlet 225 of deposition chamber 203 in order to help evacuate the exhaust gases.
- Vacuum pump 223 under control of control unit 215 , may also be utilized to reduce and control the pressure within deposition chamber 203 to a desired pressure and may also be utilized to evacuate precursor materials from deposition chamber 203 in preparation for the introduction of the next precursor material.
- FIG. 3 illustrates an embodiment of control unit 215 that may be utilized to control precursor gas controller 213 , vacuum pump 223 , or RF generators 232 , 233 .
- Control unit 215 may be any form of computer processor that can be used in an industrial setting for controlling process machines.
- control unit 215 may include a processing unit 301 , such as a desktop computer, a workstation, a laptop computer, the like, or a dedicated unit customized for a particular application.
- Control unit 215 may be equipped with a display 303 and one or more input/output components 305 , such as instruction outputs, sensor inputs, a mouse, a keyboard, printer, combinations of these, or the like.
- Processing unit 301 may include a central processing unit (CPU) 306 , memory 308 , a mass storage device 310 , a video adapter 314 , and an I/O interface 316 connected to a bus 312 .
- CPU central processing unit
- Bus 312 may be one or more of any type of several bus architectures including a memory bus or memory controller, a peripheral bus, or video bus.
- CPU 306 may include any type of electronic data processor
- memory 308 may include any type of system memory, such as static random access memory (SRAM), dynamic random access memory (DRAM), or read-only memory (ROM).
- Mass storage device 310 may include any type of storage device configured to store data, programs, or other information and configured to make the data, programs, or other information accessible via bus 312 .
- Mass storage device 310 may include, for example, one or more of a hard disk drive, a magnetic disk drive, or an optical disc drive.
- the video adapter 314 and the I/O interface 316 provide interfaces to couple external input and output devices to the processing unit 301 .
- input and output devices include the display 303 coupled to the video adapter 314 and the I/O component 305 , such as a mouse, keyboard, printer, and the like, coupled to the I/O interface 316 .
- Other devices may be coupled to the processing unit 301 , and additional or fewer interface cards may be utilized.
- a serial interface card (not shown) may be used to provide a serial interface for a printer.
- the processing unit 301 also may include a network interface 318 that may be a wired link to a local area network (LAN) or a wide area network (WAN) 320 and/or a wireless link.
- control unit 215 may include other components.
- control unit 215 may include power supplies, cables, a motherboard, removable storage media, cases, and the like. These other components, although not shown in FIG. 3 , are considered part of control unit 215 .
- an oxygen plasma presenuring deposition of a material over a photoresist or polymer underlayer can damage the underlayer surface.
- the underlayer is damaged or consumed as oxygen radicals (O*) formed in the plasma break carbon-carbon bonds (C—C, C ⁇ C) or carbon-hydrogen bonds (C—H) within the underlayer.
- the oxygen plasma may react with the underlayer according to:
- the use of oxygen-containing precursor materials for the deposition of an oxygen-containing film can form an oxygen plasma during deposition that damages the underlayer.
- the oxygen plasma consumes or etches part of the underlayer, which can result in a reduction of the thickness of the underlayer with respect to the as-deposited thickness.
- oxygen plasma damage to underlayer 114 due to the deposition of LTD film 116 may reduce the thickness of underlayer 114 from its initial as-deposited thickness T 1 to a smaller thickness T 2 .
- This underlayer 114 thickness change is shown representatively in FIG. 1B by thickness change DT 1 .
- the amount of thickness change DT 1 is determined by the material of underlayer 114 and the characteristics of the oxygen plasma and the PEALD process. This damage can result in reduced process uniformity or reproducibility, and in some cases may affect the dimensions of patterned structures or other features.
- an oxygen-containing precursor other than an allotrope of oxygen e.g., gaseous oxygen O 2 , ozone O 3 , etc.
- an oxygen allotrope precursor e.g., gaseous oxygen O 2 , ozone O 3 , etc.
- precursors such as CO 2 , N 2 O, or N 2 O 2 may be used.
- one or more alcohols may be used as a precursor, such as ethanol or other alcohols or combinations of alcohols.
- more than one precursor may be used, and in some embodiments more than one precursor may be used in combination with or without the use of an oxygen allotrope precursor as another precursor material.
- the use of precursors with less oxygen content e.g., precursors without gaseous oxygen O 2 , ozone O 3 , etc.
- FIG. 4 illustrates a graph 400 showing example results of experiments of depositing an LTD film on an underlayer, producing a multilayer structure similar to the structure shown in FIG. 1B .
- Graph 400 shows curves 410 , 420 , 430 plotting the changes in the thickness of an underlayer against the thicknesses of different LTD films deposited directly on that underlayer. In some cases, the amount of change in underlayer thickness may be indicative of the amount of underlayer damage due to an oxygen plasma.
- three different LTD films are deposited, represented by curves 410 , 420 , and 430 . Curves 410 , 420 , and 430 show that deposition of the LTD films cause the underlayer thickness to decrease.
- the change in underlayer thickness becomes greater as the thickness of the deposited LTD film increases.
- the LTD films of curves 410 and 420 were deposited using O 2 as a precursor.
- the LTD film of curve 430 was deposited using CO 2 as a precursor instead of O 2 , and curve 430 indicates that less underlayer damage has occurred during its LTD film deposition than for curves 410 and 420 .
- the underlayer thickness change of curve 430 is at least approximately half of the underlayer thickness change of curve 410 .
- graph 400 shows an example of how the techniques described by some embodiments herein may reduce damage to a photoresist or polymer underlayer when an oxygen-containing dielectric film is deposited directly on the underlayer.
- a deposition system such as deposition system 200 may be utilized to deposit LTD film 116 onto underlayer 114 .
- the formation of LTD film 116 may be initiated by introducing precursor materials into the first precursor delivery system 205 or the second precursor delivery system 206 .
- first precursor materials include CO 2 , N 2 O, N 2 O 2 , one or more alcohols, other materials, or a combination.
- second precursor materials include tris(dimethylamino)silane (3DMAS), tetrakis(dimethylamino)titanium (TDMAT), bis(tertiary-butyl-amino) silane (BTBAS), bis(diethylamino)silane (BDEAS), other materials, or a combination.
- an oxygen allotrope precursor may be used as a third precursor material in combination with another first precursor material.
- first precursor delivery system 205 and second precursor delivery system 206 can deliver the first precursor material and the second precursor material to showerhead 217 through precursor gas controller 213 and manifold 216 .
- showerhead 217 can then disperse the first precursor material and the second precursor material into deposition chamber 203 , in which the first precursor material and the second precursor material can form LTD film 116 on underlayer 114 .
- Control unit 215 can also ignite a precursor material into a plasma within deposition chamber 203 , for example, using RF generators 232 , 233 .
- a first precursor material such as those described above may be ignited into a plasma during deposition of LTD film 116 .
- LTD film 116 may be deposited in the same deposition chamber 203 as other processing steps such as deposition processes or etching processes. For example, a plasma etching process or another plasma-enhanced deposition process may also be performed on semiconductor device 100 within deposition chamber 203 .
- first precursor material may be flowed into deposition chamber 203 at a flow rate of between about 10 sccm and about 5000 sccm
- second precursor material may be flowed into deposition chamber 203 at a flow rate of between about 10 sccm and about 5000 sccm.
- CO 2 as a first precursor material may be flowed into deposition chamber 203 at a flow rate of between about 10 sccm and about 5000 sccm.
- deposition chamber 203 may be held at a pressure of between about 0.1 Torr and about 10 Torr and a temperature of between about 0° C. and about 200° C., such as about 90° C.
- LTD film 116 is formed using an RF power of between about 1 Watt and about 2000 Watts. In some embodiments, LTD film 116 is formed using a DC power of between about 1 Watt and about 2000 Watts.
- RF power between about 1 Watt and about 2000 Watts.
- DC power between about 1 Watt and about 2000 Watts.
- an upper layer 118 is formed over LTD film 116 .
- upper layer 118 may be a photoresist.
- upper layer 118 may be part of a multi-layer photoresist stack.
- upper layer 118 may be the uppermost layer of a multi-layer photoresist stack and LTD film 116 may be a middle layer of the multi-layer photoresist stack.
- Upper layer 118 may be formed by a spin-on process or another suitable process.
- an additional layer such as an adhesion layer may be formed over LTD film 116 prior to forming upper layer 118 .
- upper layer 118 is patterned using a photolithographic process to form openings within upper layer 118 .
- the patterned upper layer 118 is used as an etching mask for patterning of LTD film 116 .
- the pattern of upper layer 118 may be transferred to LTD film 116 via an etching process.
- the etching process is anisotropic, so that the openings in upper layer 118 are extended through LTD film 116 and have about the same sizes in LTD film 116 as they do in upper layer 118 .
- one or more etching processes are performed in the same chamber (e.g., deposition chamber 203 ) as the deposition of LTD film 116 .
- patterned LTD film 116 is used as an etching mask for patterning of underlayer 114 .
- the pattern of LTD film 116 may be transferred to underlayer 114 via an etching process.
- the etching process is anisotropic, so that the openings in LTD film 116 are extended through underlayer 114 and have about the same sizes in underlayer 114 as they do in LTD film 116 .
- some of or all of upper layer 118 may be consumed.
- patterned underlayer 114 is then used as an etching mask for patterning of ILD layer 112 .
- the pattern of underlayer 114 may be transferred to ILD layer 112 via an etching process. In some cases, as part of etching ILD layer 112 , some of or all of LTD film 116 or underlayer 114 may be consumed. In embodiments when underlayer 114 is not completely consumed while etching ILD layer 112 , an ashing process may be performed to remove remaining residue of the underlayer 114 .
- etched portions of ILD layer 112 are filled with a conductive material.
- a conductive material Any suitable conductive material may be used, such as copper, aluminum, or another metal, and the conductive material may be formed using a plating process or another suitable process.
- one or more additional layers may be deposited over the etched portions of ILD layer 112 before forming the conductive material, such as barrier layers, adhesion layers, seed layers, or other layers.
- a planarization process such as a chemical mechanical polish (CMP) may be performed to remove excess portions of the conductive material over the ILD layer 112 to form conductive lines 120 .
- CMP chemical mechanical polish
- ILD layer 112 may be another type of layer.
- ILD layer 112 may be a semiconductor substrate used to form devices such as FinFETs rather than an ILD layer.
- ILD layer 112 includes one or more layers, such as additional inter-layer dielectric layers, other types of dielectric layers, semiconductor layers, conductive layers, etc.
- ILD layer 112 is an example layer representative of one or more different kinds of layers that may be present during the formation of a semiconductor device 100 .
- the presence of LTD film 116 may improve adhesion of an overlying layer such as upper layer 118 . In some cases, the presence of LTD film 116 may reduce the chance of peeling of patterned features formed in upper layer 118 . For example, using LTD film 116 may improve adhesion of patterned upper layer 118 , shown in FIG. 1D .
- the techniques described herein allow for the deposition of an oxide LTD film on an underlayer with less damage to the underlayer.
- oxygen plasma damage to a photoresist or polymer underlayer may be reduced.
- the use of an LTD film as described may allow for critical dimension shrinkage for patterned structures to enable smaller feature sizes.
- the deposition of an LTD film as described can enable finely patterned features to be formed with greater process control, decreased feature size, and increased yield.
- FIGS. 5A-5C illustrate cross-sectional views of intermediate stages of forming a semiconductor device 500 using an LTD film 516 as a gap-fill material.
- an optional bottom layer 512 is formed over a substrate 502 .
- substrate 502 may be similar to substrate 102 and bottom layer 512 may be similar to ILD layer 112 , described above with respect to FIGS. 1A-1G .
- FIG. 5A also illustrates an underlayer 514 formed over bottom layer 512 .
- underlayer 514 is a photoresist or polymer material, and underlayer 514 may be similar to underlayer 114 described previously with respect to FIGS. 1A-1G .
- underlayer 514 is formed to have an as-deposited thickness T 3 between about 5 nm and about 1000 nm. Underlayer 514 may be formed by a spin-on process or another suitable process.
- FIG. 5A also illustrates an upper layer 518 formed over underlayer 514 .
- upper layer 518 has been patterned using a photolithographic process to form openings within upper layer 518 .
- upper layer 518 is an oxygen-containing dielectric material similar to LTD film 116 , but upper layer 518 may be another dielectric material in other embodiments.
- patterned upper layer 518 is used as an etching mask for a patterning of underlayer 514 .
- the pattern of upper layer 518 may be transferred to underlayer 514 via an etching process, forming openings 522 within underlayer 514 .
- the etching process is anisotropic, so that openings in upper layer 518 are extended through underlayer 514 as openings 522 and have about the same sizes in underlayer 514 as they do in upper layer 518 .
- some of or all of upper layer 518 may be consumed, as shown in FIG. 5B .
- FIG. 5B also illustrates that openings 522 patterned into underlayer 514 may have an initial width W 1 .
- the initial width W 1 may be between about 5 nm and about 100 nm.
- openings 522 may be considered recesses in underlayer 514 .
- an LTD film 516 is deposited over the underlayer 514 and into the openings 522 as a gap-fill material.
- LTD film 516 is also deposited over remaining portions of upper layer 518 .
- LTD film 516 may be used as a gap-fill material, sacrificial material, or a reverse material.
- LTD film 516 may be deposited conformally to form on sidewalls and a bottom surface of openings 522 , but in other embodiments film 516 is not deposited conformally. As deposition continues, portions of LTD film 516 on opposing sidewalls of the openings 522 may merge, which fills the openings 522 .
- a top surface of LTD film 516 may not be planar, as shown in FIG. 5C .
- LTD film 516 may be similar to LTD film 116 described previously with respect to FIG. 1A through 4 .
- LTD film 516 may be deposited by a PEALD process without using O 2 as a precursor material in order to reduce possible damage to underlayer 514 .
- O 2 a precursor material
- LTD film 516 may be deposited by a PEALD process without using O 2 as a precursor material in order to reduce possible damage to underlayer 514 .
- damage to the underlayer 514 can be reduced during formation of LTD film 516 .
- the formation of LTD film 516 over underlayer 514 may reduce the thickness of underlayer 514 from a thickness T 3 to a smaller thickness T 4 , shown representatively in FIG. 5C as thickness change DT 3 .
- the thickness change DT 3 may be less than using other techniques in which more oxygen plasma is present during deposition.
- deposition of LTD film 516 may also consume portions of the underlayer 514 sidewalls of openings 522 .
- the initial width W 1 of openings 522 may increase to W 2 after deposition of LTD film 516 .
- the increase in width from W 1 to W 2 during formation of LTD film 516 may be less than about 5 nm, such as about 3 nm.
- the change in width after depositing an LTD film as described herein may be as much as about 5 nm less than the change in width after depositing a dielectric film using an O 2 precursor.
- the device 500 shown in FIGS. 5A-5C may be processed further.
- LTD film 516 may be subsequently planarized using a CMP process.
- the remaining portions of underlayer 514 may then be removed, leaving portions of LTD film 516 remaining on the bottom layer 512 .
- the remaining portions of LTD film 516 may then be used as an etch mask for the patterning of the bottom layer 512 .
- a conductive material may be deposited over the patterned bottom layer 512 to form conductive lines, contacts, vias, or the like. This is an example process, and other processes using an LTD film as a gap-fill material are within the scope of this disclosure.
- FIGS. 6A-6J illustrate cross-sectional views of intermediate stages of forming conductive lines in a semiconductor device 600 .
- FIGS. 6A-6J illustrate an embodiment in which a LTD film 616 is used as a conformal material to decrease patterned feature size during processing of semiconductor device 600 .
- ILD layer 612 is formed over a substrate 602 .
- substrate 602 may be similar to substrate 102 or substrate 502 and ILD layer 612 may be similar to ILD layer 112 or bottom layer 512 , described above with respect to FIGS. 1A-1H and FIGS. 5A-5C .
- substrate 602 may be a partially processed semiconductor device.
- the embodiment shown in FIGS. 6A through 6J may, for example, be part of a BEOL process or part of another process.
- FIG. 6A also illustrates an underlayer 614 formed over ILD layer 612 .
- underlayer 614 is a photoresist material, and underlayer 614 may be similar to underlayer 114 or underlayer 514 described previously with respect to FIGS. 1A-1H and FIG. 5A-5C .
- underlayer 614 is formed to have an as-deposited thickness T 5 between about 5 nm and about 1000 nm. Underlayer 614 may be formed by a spin-on process or another suitable process.
- FIG. 6A also illustrates an upper layer 618 formed over underlayer 614 .
- upper layer 618 has been patterned using a photolithographic process to form openings within upper layer 618 .
- upper layer 618 is an oxygen-containing dielectric material similar to LTD film 116 , but upper layer 618 may be another dielectric material in other embodiments.
- patterned upper layer 618 is used as an etching mask for patterning of underlayer 614 .
- the pattern of upper layer 618 may be transferred to underlayer 614 via an etching process, forming first openings 622 within underlayer 614 .
- the etching process is anisotropic, so that openings in upper layer 618 are extended through underlayer 614 as openings 622 and have about the same sizes in underlayer 614 as they do in upper layer 618 .
- some of or all of upper layer 618 may be consumed, as shown in FIG. 6B .
- FIG. 6B also illustrates that openings 622 patterned into underlayer 614 may have an initial width W 3 .
- openings 622 may be considered recesses in underlayer 614 .
- the sidewalls of openings 622 may have rough surfaces after patterning.
- FIG. 6C shows a cross-sectional view of an example opening 622 , similar to openings 622 shown in FIG. 6B .
- FIG. 6D shows the opening 622 of FIG. 6C in a plan view, and the cross-sectional view of FIG. 6C is along line 6 C- 6 C′ shown in the plan view of FIG. 6D .
- the opening 622 sidewalls also exhibit roughness in a plan view.
- the roughness may be characterized from one or more measurements of the deviation of the opening 622 sidewall edge from a fixed position, shown as Edge Roughness ER 1 in FIG. 6D .
- the roughness may be characterized from one or more measurements of the distance across the opening 622 , shown as Width Roughness WR 1 in FIG. 6D .
- the use of LTD film 616 may allow for improved width roughness or improved edge roughness of openings, patterned layers, or subsequently formed features. An example is described below in FIGS. 6F-6J .
- an LTD film 616 is deposited over the underlayer 614 and into first openings 622 .
- LTD film 616 is also deposited over remaining portions of upper layer 618 (when present).
- LTD film 616 may be deposited conformally to form on sidewalls and a bottom surface of openings 622 .
- LTD film 616 may have a thickness between about 0.1 nm and about 100 nm.
- LTD film 516 may be similar to LTD film 116 or LTD film 516 described previously with respect to FIGS. 1A-4 and FIGS. 5A-5C .
- LTD film 616 may be deposited by a PEALD process without using O 2 as a precursor material in order to reduce possible damage to underlayer 614 .
- Second openings 624 have a width W 5 that is smaller than the initial width W 3 of first openings 622 .
- the use of LTD 616 in this manner may allow for smaller feature sizes to be patterned into target layer 612 , described below in greater detail with respect to FIG. 6D .
- LTD film 616 by forming LTD film 616 using one or more precursors that reduce oxygen plasma during deposition as described herein, damage to the underlayer 614 can be reduced during formation of LTD film 616 .
- the formation of LTD film 616 over underlayer 614 may reduce the thickness of underlayer 614 from a thickness T 5 to a smaller thickness T 6 , similar to underlayer 514 as described above with respect to FIGS. 5A-5C .
- deposition of LTD film 616 may also consume portions of the underlayer 614 sidewalls of openings 622 .
- the initial width W 3 of openings 622 may increase to W 4 after deposition of LTD film 616 .
- the increase in width from W 3 to W 4 may be less than about 50 nm, such as about 3 nm.
- the thickness of an LTD film 616 deposited on a surface of the underlayer 614 may be less than, greater than, or about the same as the thickness of underlayer 614 at that surface that is consumed during the deposition of the LTD film 616 .
- openings 624 may be formed having smaller widths W 5 , which can reduce subsequently patterned feature sizes and allow for improved process control.
- FIGS. 6F-6G show a cross-sectional view and a plan view of the example opening 622 shown in FIGS. 6C-6D after forming an LTD film 616 within the opening 622 , forming opening 624 .
- the opening 624 shown in FIGS. 6F-6G is similar to openings 624 shown in FIG. 6E .
- the cross-sectional view of FIG. 6F is along line 6 F- 6 F′ shown in the plan view of FIG. 6G .
- the LTD film 616 may fill small recesses in the rough sidewalls of the underlayer 614 and may have a smoother surface as deposited than the rough sidewalls of the underlayer 614 .
- the LTD film 616 of the sidewalls of openings 624 may be less rough than the sidewalls of the underlayer 614 .
- an Edge Roughness ER 2 of a sidewall of an opening 624 may be less than an Edge Roughness ER 1 of a sidewall of an opening 622 .
- a Width Roughness WR 2 of a sidewall of an opening 624 may be less than a Width Roughness WR 1 of a sidewall of an opening 622 .
- the use of an LTD film to reduce sidewall roughness in this manner may allow subsequently formed features to have less roughness or more uniformity.
- openings 624 may be transferred to target layer 612 via an etching process.
- the etching process is anisotropic, so that the openings 624 are extended through target layer 612 and have about the same sizes in target layer 612 as they do in openings 624 .
- the etching process may also etch top surfaces of LTD film 616 over underlayer 614 , as shown in FIG. 6H .
- the use of an LTD film deposition process as described herein can allow for smaller feature sizes when used to decrease the size of openings formed in a previous patterning step.
- a planarization process (e.g., a chemical mechanical polish (CMP), dry etching, combinations thereof, or the like) may optionally be performed to remove portions of LTD film 616 covering underlayer 614 . In some cases, upper portions of underlayer 614 may also be removed by the planarization process.
- CMP chemical mechanical polish
- the openings 624 in target layer 612 may subsequently be filled with a conductive material to form vias, conductive lines, or other conductive features.
- the openings 624 in target layer 612 are filled with a conductive material 630 to form conductive lines 632 .
- the cross-sectional view of FIG. 61 is along line 61 - 61 ′ shown in the plan view of FIG. 6J .
- the LTD film 616 , underlayer 614 , and excess portions of conductive material 630 may be removed by a planarization process such as CMP or by an etching process.
- the LTD film 616 is removed before forming the conductive material 630 .
- the LTD film 616 may be used to form features having smaller dimensions, such as conductive lines 632 .
- the embodiment shown in FIGS. 6A-6J is for illustrative purposes, and other embodiments may include additional layers, features, or process steps.
- LTD film 616 to improve the roughness of openings 622 may then also reduce roughness of features patterned from the openings 622 .
- using LTD film 616 to reduce sidewall roughness of openings 622 may reduce a Line Edge Roughness LER or a Line Width Roughness LWR of conductive lines 632 , shown in FIG. 6J .
- the use of an LTD film to reduce the roughness of patterned features may allow subsequently formed features to have less roughness or more uniformity.
- FIGS. 7A through 15B illustrate cross-sectional views and/or plan views of intermediate stages in the formation of conductive features in an ILD layer 702 of a semiconductor device 700 .
- the process shown in FIGS. 7A through 15B illustrate an embodiment in which an LTD film 736 may be used as a gap-fill material, and LTD film 736 may be used as a gap-fill material similar to LTD film 516 described above with respect to FIGS. 5A-5C .
- the semiconductor device 700 is shown in FIG. 7A (in cross-sectional view) and FIG. 7B (in plan view).
- FIG. 7A The cross-sectional view of FIG. 7A is along line A-A′ shown in the plan view of FIG. 7B .
- ILD layer 702 is formed over a substrate 704 .
- substrate 704 may be similar to other substrates described above, or ILD layer 702 may be similar to other layers described above, such as ILD layer 112 as described with respect to FIG. 1A , or may be another type of layer.
- the embodiment shown in FIGS. 7A through 15B may, for example, be part of a BEOL process or part of another process.
- FIGS. 7A-7B illustrate mask regions 724 formed over ILD layer 702 .
- the mask regions 724 may be formed, for example, by patterning a blanket dielectric layer using a photolithographic process. In a plan view, gaps between mask regions 724 define regions in which conductive features may be formed in ILD layer 702 .
- masking layer 728 is formed over mask regions 724 and ILD layer 702 .
- masking layer 728 is a photoresist or polymer material, and may be similar to underlayer 114 , underlayer 514 , or underlayer 614 described previously with respect to FIGS. 1A-1G , FIGS. 5A-5C , or FIGS. 6A-6J .
- masking layer 728 includes multiple layers and multiple materials.
- FIGS. 9A-9C masking layer 728 is patterned using a photolithographic process to form openings 734 .
- the cross-sectional view of FIG. 9A is along line A-A′ shown in the plan view of FIG. 9B , which is also shown in the perspective view of FIG. 9C .
- portions of masking layer 728 have been shown as transparent so that an opening 734 may be more clearly displayed.
- LTD material 736 is formed in openings 734 and over masking layer 728 .
- the cross-sectional view of FIG. 10A is along line A-A′ shown in the plan view of FIG. 10B , which is also shown in the perspective view of FIG. 10C .
- portions of masking layer 728 have been shown as transparent so that the LTD material 736 formed within an opening 734 may be more clearly displayed.
- LTD material 736 may be used as a gap-fill material or as a sacrificial material.
- LTD material 736 may be similar to LTD film 116 , LTD film 516 , or LTD film 616 described previously with respect to FIGS.
- LTD material 736 may be deposited by a PEALD process without using O 2 as a precursor material in order to reduce possible damage to underlayer 728 .
- LTD material 736 may be deposited conformally to fill opening 734 .
- the LTD material 736 will be further patterned, and the patterned LTD material 736 may be used to define a line cut between two adjacent conductive lines that will be formed in the ILD layer 702 .
- FIG. 10 depicts the forming of LTD material 736 in a single opening 734 , in some embodiments only one or more than two openings 734 may be present and LTD material 736 may be formed in the one or more than two openings 734 (for example, to form less line cuts or additional line cuts).
- a planarization process (e.g., CMP, dry etching, combinations thereof, or the like) may be performed to remove excess portions of LTD material 736 outside of openings 734 .
- FIGS. 12A-12B remaining portions of masking layer 728 are removed.
- the cross-sectional view of FIG. 12A is along line A-A′ shown in the plan view of FIG. 12B .
- the masking layer 728 may be removed using an ashing process. After the masking layer 728 is removed, LTD material 736 remains and covers a portion of the mask regions 724 and ILD layer 702 .
- a planarization process is performed to remove excess portions of LTD material 736 and planarize a top surface of LTD material 736 to be level with top surfaces of the mask regions 724 .
- the cross-sectional view of FIG. 13A is along line A-A′ shown in the plan view of FIG. 13B , which is also shown in the perspective view of FIG. 13C .
- the planarization process includes one or more etching processes. For example, a dry etching process or a wet etching process may be used. In other embodiments, a grinding process such as CMP may be used.
- the resulting structure is depicted in FIGS. 13A and 13B . As can be seen in FIGS.
- the planarization of LTD material 736 has created discrete portions of the LTD material 736 , where each discrete portion overlies a gap between two adjacent mask regions 724 . In some embodiments, each discrete portion overlies a region in which a line cut between two adjacent portions of conductive line will be formed.
- LTD material 736 and mask regions 724 are used as an etching mask to form openings 750 into the ILD layer 702 .
- Etching the ILD layer 702 may include an anisotropic dry etch process or a wet etch process. Remaining portions of the ILD layer 702 may have a same pattern as the mask regions 724 and the LTD material 736 of FIGS. 14A-14B .
- Conductive material 764 may be used, such as copper, aluminum, or another metal, and conductive material 764 may be formed using a plating process or another suitable process. In some cases, conductive material 764 may be initially deposited to overfill openings 750 . After filling the openings 750 , a planarization process, such as a chemical mechanical polish (CMP), may be performed to remove excess portions of conductive material 764 . In some embodiments, a liner material may be formed within openings 750 before forming the conductive material 764 .
- CMP chemical mechanical polish
- a planarization process may be performed to remove excess portions of the conductive material 764 over the ILD layer 702 .
- conductive features may be formed in the ILD layer 702 .
- areas that are underneath the portions of LTD material 736 when ILD layer 702 is patterned are areas where the conductive lines have gaps, or “line cuts.”
- line cut 770 separates first conductive line 772 from second conductive line 774 .
- the use of LTD material 736 as described may allow for improved line width variation or improved line edge roughness, which may allow for smaller conductive features and smaller line cuts between conductive features.
- FIGS. 16-25 illustrate intermediate stages in a FEOL process using an LTD layer 862 to form fins 868 of a FinFET device.
- FIG. 16 illustrates an example of a FinFET in a three-dimensional view, according to some embodiments.
- FIGS. 17 through 25 illustrate cross-sectional views of intermediate stages of forming fins of FinFETs according to some embodiments. The cross-sectional views of FIGS. 17 through 25 are taken along the line B-B′ shown in the three-dimensional view of FIG. 16 .
- FIGS. 16 includes a fin 874 on a substrate 850 .
- Isolation regions 872 are on substrate 850 , and fin 874 protrudes above and from between neighboring isolation regions 872 .
- a gate dielectric layer 818 is along sidewalls and over a top surface of fin 874 , and a gate electrode 820 is over gate dielectric layer 818 .
- Source/drain regions 802 are disposed in opposite sides of fin 874 with respect to gate dielectric layer 818 and gate electrode 820 .
- FIG. 17 illustrates a substrate 850 according to some embodiments.
- the substrate 850 has a first region 850 B and a second region 850 C.
- the first region 850 B can be for forming n-type devices, such as NMOS transistors, e.g., n-type FinFETs.
- Second region 850 C can be for forming p-type devices, such as PMOS transistors, e.g., p-type FinFETs.
- both first region 850 B and second region 850 C are used to form the same type of devices, such as both regions being for n-type devices or p-type devices.
- First region 850 B and second region 850 C may be physically separated from each other, and any number of structures (e.g., isolation regions, active devices, etc.) may be disposed between first region 850 B and second region 850 C.
- Substrate 850 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped.
- Substrate 850 may be a wafer, such as a silicon wafer.
- SOI substrate is a layer of a semiconductor material formed on an insulator layer.
- the insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like.
- the insulator layer is provided on a substrate, typically a silicon or glass substrate.
- Other substrates, such as a multi-layered or gradient substrate may also be used.
- the semiconductor material of substrate 850 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof.
- a film stack is formed over substrate 850 .
- the film stack is used during processing to form features in substrate 850 that may be a fraction of the minimum photolithographic pitch.
- the process is a self-aligned double patterning (SADP) process, where the features formed are one half the minimum photolithographic pitch.
- the process may be a self-aligned quadruple patterning (SAQP) process, where the features formed are one quarter of the minimum photolithographic pitch.
- the film stack includes an anti-reflective coating (ARC) 852 , a mask layer 854 , and a mandrel layer 856 .
- the film stack may include more or fewer layers.
- ARC 852 is formed over substrate 850 , and aids in the exposure and focus of overlying photoresist layers (discussed below) during patterning of the photoresist layers.
- ARC 852 may be formed from SiON, SiC, materials doped with oxygen (O) and nitrogen (N), or the like.
- ARC 852 is substantially free from nitrogen, and may be formed from an oxide.
- Mask layer 854 is formed over ARC 852 .
- the mask layer 854 is an LTD film, which may be similar to LTD film 116 , LTD film 516 , LTD film 616 , or LTD material 736 described previously with respect to FIGS. 1A-4 , FIGS. 5A-5C , FIGS. 6A-6E , and FIGS. 7A-15B .
- using an LTD film for the mask layer 854 may improve adhesion of an overlying layer or overlying features.
- using an LTD film for the mask layer 854 instead of another material for the mask layer 854 may reduce the chance of peeling of patterned features formed on the mask layer 854 .
- mask layer 854 may be formed of a hard masking material, and may include a metal and/or a dielectric.
- mask layer 854 may be formed of titanium nitride, titanium, tantalum nitride, tantalum, or the like.
- mask layer 854 includes a dielectric, it may be formed of an oxide, a nitride, or the like.
- Mask layer 854 may be formed by PVD, Radio Frequency PVD (RFPVD), Atomic Layer Deposition (ALD), or the like.
- RFPVD Radio Frequency PVD
- ALD Atomic Layer Deposition
- Mandrel layer 856 is a sacrificial layer formed over mask layer 854 .
- mandrel layer 856 is a photoresist or polymer material, and may be similar to underlayer 114 , underlayer 514 , underlayer 614 , or masking layer 728 described previously with respect to FIGS. 1A-1G , FIGS. 5A-5C , FIGS. 6A-6F , or FIGS. 7A-14B .
- mandrel layer 856 may formed of a material that has a high etching selectivity with the underlying layer, e.g., with mask layer 854 .
- mandrel layer 856 may be formed of a material such as amorphous silicon, polysilicon, silicon nitride, silicon oxide, the like, or a combination thereof, and may be formed using a process such as a chemical vapor deposition (CVD), PECVD, or the like. In an embodiment, mandrel layer 856 is formed of polysilicon.
- CVD chemical vapor deposition
- PECVD PECVD
- mandrel layer 856 is patterned to form mandrels 858 .
- Mandrel layer 856 may be patterned using any suitable photolithography technique.
- a tri-layer photoresist (not shown) may be formed over the film stack.
- the tri-layer photoresist may include a bottom layer, a middle layer, and an upper layer.
- the upper layer may be formed of a photosensitive material, such as a photoresist, which may comprise organic materials.
- the bottom layer may be a bottom anti-reflective coating (BARC).
- the middle layer may be formed of or include an inorganic material, which may be a nitride (such as silicon nitride), an oxynitride (such as silicon oxynitride), an oxide (such as silicon oxide), or the like.
- the middle layer has a high etching selectivity relative to the upper layer and the bottom layer. As a result, the upper layer is used as an etching mask for the patterning of the middle layer, and the middle layer is used as an etching mask for the patterning of the bottom layer.
- an etching process is performed to transfer the pattern of the bottom layer to mandrel layer 856 .
- the etching process may remove the portions of mandrel layer 856 exposed by the middle and bottom layers.
- the etching process may be a dry etch where mandrel layer 856 is exposed to a plasma source and one or more etchant gases.
- the etch may be an inductively coupled plasma (ICR) etch, a transformer coupled plasma (TCP) etch, an electron cyclotron resonance (ECR) etch, a reactive ion etch (RIE), or the like. Remaining portions of mandrel layer 856 form mandrels 858 .
- the etching process used to transfer the pattern to mandrel layer 856 may remove the middle layer and partially remove portions of the bottom layer.
- An ashing process may be performed to remove remaining residue of the middle and/or bottom layers.
- a LTD layer 862 is formed over mask layer 854 and mandrels 858 .
- LTD layer 862 may extend along top surfaces of mask layer 854 and mandrels 858 , and along sidewalls of mandrels 858 .
- LTD layer 862 may be similar to LTD film 116 , LTD film 516 , LTD film 616 , or LTD material 736 described previously with respect to FIGS. 1A-4 , FIGS. 5A-5C , FIGS. 6A-6E , and FIGS. 7A-14B .
- LTD layer 862 may be deposited by a PEALD process without using O 2 as a precursor material in order to reduce possible damage to mandrels 858 . Reducing damage to mandrels 858 may improve process uniformity during formation of fins 874 , described below.
- a suitable etching process is performed to remove the horizontal portions of LTD layer 862 .
- the etchant used to etch the horizontal portions of the LTD layer 862 is Cl 2 , CH 4 , N 2 , Ar, the like, or a combination thereof.
- the vertical portions of LTD layer 862 may remain along the sides of mandrels 858 , and are referred to as spacers 864 hereinafter.
- the etching process may be anisotropic, so that the width of spacers 864 does not significantly decrease.
- mandrels 858 are removed.
- Mandrels 858 may be removed by a suitable etching processes, such as an etching process including etchants such as CF 4 , CH 3 F, H 2 , N 2 , Ar, the like, or a combination thereof, an ashing process, or any other suitable etching process that can remove mandrels 858 without substantially damaging spacers 864 .
- a wet clean process may also be applied to substrate 850 to remove residual spacer and mandrel material.
- the spacer etch and the mandrel removal processes are performed in a same process chamber.
- spacers 864 are used as an etching mask to pattern mask layer 854 .
- a suitable etching process such as an anisotropic etch, may be performed with any suitable chemical, such as CF 4 , HBr, Cl 2 , O 2 , Ar, the like, or a combination thereof.
- the pattern of spacers 864 is therefore transferred to the mask layer 854 to form openings in mask layer 854 .
- fins 868 are formed in the substrate 850 . Fins 868 are formed by using the patterned mask layer 854 as an etching mask to etch ARC 852 and substrate 850 , thereby forming trenches in substrate 850 . The resulting semiconductor strips between the trenches form fins 868 .
- the etching may be any acceptable etch process, and may use etchants such as Cl 2 , N 2 , CH 4 , the like, or a combination thereof.
- the etch may be anisotropic.
- the spacers 864 , patterned mask layer 854 , and patterned ARC 852 may be consumed in this process. In some embodiments, a cleaning process may be performed to remove any residual material of spacers 864 , patterned mask layer 854 , or patterned ARC 852 .
- an insulation material is formed over substrate 850 and between neighboring fins 868 .
- the insulation material may be an oxide, such as silicon oxide, a nitride, the like, or a combination thereof.
- the insulation material is then recessed to form Shallow Trench Isolation (STI) regions 872 .
- the insulation material is recessed such that fins 874 in the first region 850 B and in the second region 850 C protrude from between neighboring STI regions 872 .
- the insulation material may be recessed to form STI regions 872 using an acceptable etching process, such as one that is selective to the material of the insulation material.
- the fins 874 may be similar to fin 874 shown in FIG. 16 , above.
- fins 874 After forming fins 874 , other processing steps may be performed to form FinFETs such as that shown in FIG. 16 .
- a gate dielectric layer 818 and a gate electrode 820 may be formed over each fin 874 , and source/drain regions 802 may be formed on opposite sides of each fin 874 .
- FIGS. 17 through 25 Although the process illustrated in FIGS. 17 through 25 is used to form the fins 874 , it should be appreciated that the fabrication steps shown in FIGS. 17 through 25 may be used in other processes. For example, spacers formed from an LTD layer could be formed over and used to pattern other semiconductor device elements such as polysilicon gates, metal gates, dummy gates, isolation regions, interconnect structures, gate spacers, a contact etch stop layer (CESL), and the like.
- CEL contact etch stop layer
- the LTD film described may be deposited over a photoresist or polymer layer with little or no damage to the photoresist or polymer layer.
- the LTD film described may be used as an etching mask for photoresist, polymer, or other material.
- the LTD film described can be used as a pad layer for as an adhesion improvement layer.
- a layer e.g., a photoresist, dielectric, or other type of layer
- the use of an LTD film may improve width variation or edge roughness of some features, such as metal lines or other features.
- the LTD film described may be used as part of a FEOL process or as part of a BEOL process.
- a method of manufacturing a semiconductor device includes depositing a layer over a semiconductor substrate placing the substrate in a deposition chamber, and depositing an oxide layer over and contacting the layer.
- Depositing the oxide layer includes flowing first precursor materials into the deposition chamber, within the deposition chamber, forming a portion of the oxide layer from the first precursor materials, igniting second precursor materials into a plasma, the second precursor materials being free of allotropes of oxygen, and within the deposition chamber, forming a portion of the oxide layer from the plasma.
- the method further includes patterning an opening in the layer.
- depositing the oxide layer includes depositing the oxide layer within the opening in the layer.
- the method further includes patterning the oxide layer to extend the opening into the oxide layer.
- the oxide layer includes a process temperature of less than about 200° C.
- the second precursor materials are free of gaseous oxygen.
- the second precursor materials include CO 2 .
- the oxide layer includes SiOC.
- a method of manufacturing a semiconductor device includes a dielectric layer over a substrate, performing a first patterning to form a recess in the dielectric layer, and depositing an oxide film over and contacting the dielectric layer and within the recess in the dielectric layer, wherein the oxide film is formed from multiple precursors, wherein the precursors of the multiple precursors are free of O 2 , and wherein depositing the oxide film includes forming a plasma of a first precursor of the multiple precursors.
- the oxide film is deposited to fill the recess in the dielectric layer.
- the recess has a first interior width, and depositing the oxide film within the recess forms a trench within the recess having a second interior width that is smaller than the first interior width.
- the oxide film is deposited conformally within the recess.
- the dielectric layer is a photoresist material or a polymer material.
- the oxide film is SiOC.
- the first precursor of the multiple precursors is CO 2 .
- a method in another embodiment, includes forming a dielectric layer over a semiconductor substrate, patterning a photoresist over the dielectric layer, placing the semiconductor substrate and the photoresist into a process chamber, transferring the pattern of the photoresist to the dielectric layer using an etching process, providing precursors of multiple precursors to the process chamber, wherein the precursors of the multiple precursors are free of allotropes of oxygen, and forming an oxide layer over and contacting the dielectric layer within the process chamber, including igniting at least one precursor of the multiple precursors into a plasma.
- the method further includes etching the oxide layer using an etching process performed within the process chamber.
- the multiple precursors include CO 2 , N 2 O, or ethanol.
- the oxide layer includes SiON.
- forming an oxide layer includes using a Plasma-Enhanced Atomic Layer Deposition (PEALD) process.
- PEALD Plasma-Enhanced Atomic Layer Deposition
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Abstract
Description
- This is a divisional of U.S. patent application Ser. No. 15/967,480, filed on Apr. 30, 2018, which claims the benefit of U.S. patent application Ser. No. 62/566,044, filed on Sep. 29, 2017 and entitled “Method of Manufacturing a Semiconductor Device,” which applications are incorporated herein by reference.
- Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a semiconductor substrate, and patterning the various material layers using lithography and etching processes to form circuit components and elements thereon.
- The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. However, as the minimum features sizes are reduced, additional problems arise within each of the processes that are used, and these additional problems should be addressed.
- Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
-
FIGS. 1A-1H illustrate cross-sectional views of various intermediary stages of manufacturing conductive lines in a semiconductor device using a low-temperature dielectric film in accordance with some embodiments. -
FIG. 2 illustrates a deposition system for depositing a low-temperature dielectric film in accordance with some embodiments. -
FIG. 3 illustrates a control unit for a deposition system in accordance with some embodiments. -
FIG. 4 illustrates experimental results reflecting the relationship between underlayer damage and low-temperature dielectric film thicknesses in accordance with some embodiments. -
FIGS. 5A-5C illustrate cross-sectional views of various intermediary stages of manufacturing a semiconductor device using a low-temperature dielectric film in accordance with some embodiments. -
FIGS. 6A-6J illustrate cross-sectional views or plan views of various intermediary stages of manufacturing conductive lines in a semiconductor device using a low-temperature dielectric film in accordance with some embodiments. -
FIGS. 7A-15B illustrate cross-sectional views, plan views, or perspective views of various intermediary stages of manufacturing conductive lines in a semiconductor device using a low-temperature dielectric film in accordance with some embodiments. -
FIGS. 16-25 illustrate cross-sectional views of various intermediary stages of manufacturing a FinFET semiconductor device using a low-temperature dielectric film in accordance with some embodiments. - The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- Various embodiments are described in respect to the formation of a low-temperature dielectric (LTD) film used during processing semiconductor devices. The LTD film described herein and the process, method, or materials described herein can be used in many applications, including fin-type field effect transistors (FinFETs). For example, the fins may be patterned to produce a relatively close spacing between features, for which this disclosure is well-suited. In addition, spacers used in forming fins of FinFETs, also referred to as mandrels, can be formed using techniques or materials described herein. As another example, the LTD film may be used as part of a multi-layer photoresist, in a multi-patterning process, or as a film to decrease feature size during patterning. However, the embodiments are not intended to be limited to such uses. As used herein, the term “LTD” refers to a dielectric deposited using a relatively low process temperature (e.g., 200° C. or less). In some cases, depositing a dielectric material at lower process temperatures can reduce the possibility of damage to layers beneath the dielectric material during the deposition.
- The low-temperature dielectric (LTD) film described herein may be used in different processes that form different types of semiconductor devices. In accordance with a first exemplary embodiment,
FIGS. 1A-1H illustrate cross-sectional views of intermediate stages of formingconductive lines 120 in an inter-layer dielectric (ILD)layer 112 on asemiconductor substrate 102. - In the embodiment of
FIGS. 1A-1H , anLTD film 116 is used as an etching mask for patterning of anILD layer 112 during formation ofconductive lines 120. The embodiment shown inFIGS. 1A-1H may, for example, be part of forming conductive lines in a Back End of Line (BEOL) process. InFIG. 1A , theILD layer 112 and anunderlayer 114 are formed insemiconductor device 100. In some embodiments, ILDlayer 112 may be formed over asemiconductor substrate 102. Thesemiconductor substrate 102 may be formed of a semiconductor material such as silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. Thesemiconductor substrate 102 may include other semiconductor materials, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. Other substrates, such as multi-layered or gradient substrates, may also be used. Devices (not illustrated), such as transistors, diodes, capacitors, resistors, etc., may be formed in and/or on an active surface ofsemiconductor substrate 102. The devices may include a variety of active devices such as transistors and the like and passive devices such as capacitors, resistors, inductors and the like. The active devices and passive devices may be formed using any suitable methods either within or else on thesubstrate 102. In some cases, thesemiconductor substrate 102 may be omitted. - The
ILD layer 112 may include a dielectric material formed using, for example, spin-on coating, CVD, flowable CVD, plasma-enhanced CVD (PECVD), or other deposition methods. TheILD layer 112 may be formed of Phospho-Silicate glass (PSG), Boro-Silicate Glass (BSG), Boron-Doped Phospho-Silicate Glass (BPSG), undoped Silicate Glass (USG), Tetra Ethyl Ortho Silicate (TEOS) oxide, or the like. -
FIG. 1A also illustrates the formation of anunderlayer 114 overILD layer 112. In some cases, other layers may be formed betweenILD layer 112 and theunderlayer 114. In some embodiments,underlayer 114 may be a photoresist layer or a polymer layer.Underlayer 114 may be formed by a spin-on process or another suitable process. As shown inFIG. 1A ,underlayer 114 may be formed to an initial thickness T1, which in some cases is between about 10 nm and about 600 nm. However, these thicknesses are meant to be illustrative only, and are not intended to limit the scope of the embodiments, as the precise thickness of the as-deposited layer may be any suitable desired thickness. - Although
FIGS. 1A-1G illustrateILD layer 112 being in physical contact withsemiconductor substrate 102 orunderlayer 114 being in physical contact withILD layer 112, any number of intervening layers may be disposed betweenILD layer 112 andsemiconductor substrate 102. Such intervening layers may include another ILD layer comprising a low-k dielectric and having contact plugs formed therein, IMD layers having conductive lines and/or vias formed therein, one or more intermediary layers (e.g., etch stop layers, adhesion layers, anti-reflective coating (ARC) layers, etc.), combinations thereof, and the like. For example, an optional etch stop layer (not illustrated) may be disposed directly underILD layer 112. An etch stop layer may act as a stop for an etching process subsequently performed on theILD layer 112. The material and process used to form the etch stop layer may depend on the material ofILD layer 112. - As illustrated in
FIG. 1B , a low-temperature dielectric (LTD)film 116 is formed overunderlayer 114. In some embodiments,LTD film 116 may be part of a multi-layer photoresist. For example,LTD film 116 may be a middle layer of a multi-layer photoresist stack, andunderlayer 114 may be the bottom layer of a multi-layer photoresist stack. In some embodiments,LTD film 116 may be formed of SiN, SiON, SiCON, SiC, SiOC, SiO, TiO, an oxide, other dielectrics, combinations thereof, or the like.LTD film 116 may be formed by a deposition process such as plasma enhanced chemical vapor deposition (PECVD), low pressure CVD (LPCVD), plasma vapor deposition (PVD), plasma-enhanced atomic layer deposition (PEALD), or the like. In some embodiments,LTD film 116 may be formed to a thickness between about 10 Å and about 50 nm. However, these thicknesses are meant to be illustrative only, and are not intended to limit the scope of the embodiments, as the precise thickness of the as-deposited layer may be any suitable desired thickness. -
FIGS. 2-3 illustrate adeposition system 200 that may be used to form a low-temperature dielectric (LTD) film such asLTD film 116. In some embodiments,deposition system 200 forms the LTD film using a PEALD process. In some embodiments,deposition system 200 receives a first precursor material from a firstprecursor delivery system 205 and a second precursor material from a secondprecursor delivery system 206 to form layers of materials ontosubstrate 102. In an embodiment, firstprecursor delivery system 205 and secondprecursor delivery system 206 may work in conjunction with one another to supply the various different precursor materials to adeposition chamber 203 in whichsubstrate 102 is placed. In some cases, firstprecursor delivery system 205 and secondprecursor delivery system 206 may have physical components that are similar with each other. In some embodiments, other precursor delivery systems may be part ofdeposition system 200, and may be similar to firstprecursor delivery system 205 or secondprecursor delivery system 206. - In some embodiments, first
precursor delivery system 205 and secondprecursor delivery system 206 may each include agas supply 207 and a flow controller 209 (labeled inFIG. 2 with regards to firstprecursor delivery system 205 but not labeled for clarity with respect to second precursor delivery system 206). In an embodiment in which the first precursor material is stored in a gaseous state,gas supply 207 may supply the first precursor material todeposition chamber 203.Gas supply 207 may be a vessel, such as a gas storage tank, that is located either locally todeposition chamber 203 or else may be located remotely fromdeposition chamber 203. Alternatively,gas supply 207 may be a facility that independently prepares and delivers the first precursor material to flowcontroller 209. Any suitable source for the first precursor material may be utilized asgas supply 207, and all such sources are fully intended to be included within the scope of the embodiments. -
Gas supply 207 may supply the desired first precursor material to flowcontroller 209.Flow controller 209 may be utilized to control the flow of the first precursor material toprecursor gas controller 213 and, eventually, todeposition chamber 203, thereby also helping to control the pressure withindeposition chamber 203.Flow controller 209 may be, e.g., a proportional valve, a modulating valve, a needle valve, a pressure regulator, a mass flow controller, combinations of these, or the like. However, any suitable method for controlling and regulating the flow of the carrier gas to precursor canister 211 may be utilized, and all such components and methods are fully intended to be included within the scope of the embodiments. - However, as one of ordinary skill in the art will recognize, while first
precursor delivery system 205 and secondprecursor delivery system 206 have been described herein as having identical components, this is merely an illustrative example and is not intended to limit the embodiments in any fashion. Any type of suitable precursor delivery system, with any type and number of individual components identical to or different from any of the other precursor delivery systems withindeposition system 200, may alternatively be utilized. All such precursor systems are fully intended to be included within the scope of the embodiments. - Additionally, in an embodiment in which the first precursor material is stored in a solid or liquid state,
gas supply 207 may store a carrier gas and the carrier gas may be introduced into a precursor canister (not separately illustrated), which stores the first precursor material in the solid or liquid state. The carrier gas is then used to push and carry the first precursor material as the first precursor material either evaporates or sublimates into a gaseous section of the precursor canister before being sent toprecursor gas controller 213. In some embodiments, a carrier gas may be an inert gas such as Ar, He, or another gas. Any suitable method and combination of units may be utilized to provide the first precursor material, and all such combination of units are fully intended to be included within the scope of the embodiments. - First
precursor delivery system 205 and secondprecursor delivery system 206 may supply their individual precursor materials into aprecursor gas controller 213.Precursor gas controller 213 connects and isolates firstprecursor delivery system 205 and secondprecursor delivery system 206 fromdeposition chamber 203 in order to deliver the desired precursor materials todeposition chamber 203.Precursor gas controller 213 may include such devices as valves, flow meters, sensors, and the like to control the delivery rates of each of the precursors, and may be controlled by instructions received from a control unit 215 (described further below with respect toFIG. 3 ). -
Precursor gas controller 213, upon receiving instructions fromcontrol unit 215, may open and close valves so as to connect one or more of firstprecursor delivery system 205 and secondprecursor delivery system 206 todeposition chamber 203 and direct a desired precursor material through a manifold 216, intodeposition chamber 203, and to ashowerhead 217.Showerhead 217 may be utilized to disperse the chosen precursor material(s) intodeposition chamber 203 and may be designed to evenly disperse the precursor material in order to minimize undesired process conditions that may arise from uneven dispersal. In some embodiments,showerhead 217 may have a circular design with openings dispersed evenly aroundshowerhead 217 to allow for the dispersal of the desired precursor material intodeposition chamber 203. - However, as one of ordinary skill in the art will recognize, the introduction of precursor materials to
deposition chamber 203 through asingle showerhead 217 or through a single point of introduction as described above is intended to be illustrative only and is not intended to be limiting to the embodiments. Any number of separate andindependent showerheads 217 or other openings to introduce precursor materials intodeposition chamber 203 may alternatively be utilized. All such combinations of showerheads and other points of introduction are fully intended to be included within the scope of the embodiments. -
Deposition chamber 203 may receive the desired precursor materials and expose the precursor materials tounderlayer 114, anddeposition chamber 203 may be any desired shape that may be suitable for dispersing the precursor materials and contacting the precursor materials withunderlayer 114. In the embodiment illustrated inFIG. 2 ,deposition chamber 203 has a cylindrical sidewall and a bottom. However,deposition chamber 203 is not limited to a cylindrical shape, and any other suitable shape, such as a hollow square tube, an octagonal shape, or the like, may be utilized. Furthermore,deposition chamber 203 may be surrounded by ahousing 219 made of material that is inert to the various process materials. As such, whilehousing 219 may be any suitable material that can withstand the chemistries and pressures involved in the deposition process, in anembodiment housing 219 may be steel, stainless steel, nickel, aluminum, alloys of these, combinations of these, and like. - Within
deposition chamber 203,substrate 102 may be placed on a mountingplatform 221 in order to position andcontrol substrate 102 andunderlayer 114 during the deposition processes. Mountingplatform 221 may be disposed on the bottom ofdeposition chamber 203, and may include heating mechanisms in order to heatsubstrate 102 during the deposition processes. Furthermore, while asingle mounting platform 221 is illustrated inFIG. 2 , any number of mountingplatforms 221 may additionally be included withindeposition chamber 203. - In some embodiments, mounting
platform 221 may also include afirst electrode 230 coupled to afirst RF generator 232. First electrode 220 may be electrically biased by first RF generator 232 (under control of control unit 215) at a RF voltage during a deposition process such as a PEALD process. By being electrically biased,first electrode 230 is used to provide a bias to the incoming gases (e.g., precursor materials and/or carrier gases) and assist to ignite them into a plasma. In some embodiments, a carrier gas may be ignited into a plasma along with a precursor material. Additionally,first electrode 230 is also used to maintain a plasma during a deposition by maintaining the bias. -
Deposition chamber 203 also includes anupper electrode 231, for use as a plasma generator. In an embodiment the plasma generator may be a transformer coupled plasma generator and may be, e.g., a coil. The coil may be attached to aRF generator 233 that is used to provide power to the upper electrode 231 (under control of control unit 215) in order to ignite gases into a plasma. - However, while the
upper electrode 231 is described above as a transformer coupled plasma generator, embodiments are not intended to be limited to a transformer coupled plasma generator. Rather, any suitable method of generating the plasma, such as inductively coupled plasma systems, magnetically enhanced reactive ion etching, electron cyclotron resonance, a remote plasma generator, or the like, may alternatively be utilized. For example, in some embodiments, incoming gases may be ignited into a plasma by a plasma generator located in a separate chamber that is connected todeposition chamber 203, or incoming gases may be ignited into a plasma indeposition chamber 203 by a plasma generator that is not coupled to mountingplatform 221. All such methods are fully intended to be included within the scope of the embodiments. - Additionally,
deposition chamber 203 and mountingplatform 221 may be part of a cluster tool system (not shown). The cluster tool system may be used in conjunction with an automated handling system in order to position andplace substrate 102 intodeposition chamber 203 prior to the deposition processes, position, holdsubstrate 102 during deposition processes, and removesubstrate 102 fromdeposition chamber 203 after the deposition processes. -
Deposition chamber 203 may also have anexhaust outlet 225 for exhaust gases to exitdeposition chamber 203. Avacuum pump 223 may be connected toexhaust outlet 225 ofdeposition chamber 203 in order to help evacuate the exhaust gases.Vacuum pump 223, under control ofcontrol unit 215, may also be utilized to reduce and control the pressure withindeposition chamber 203 to a desired pressure and may also be utilized to evacuate precursor materials fromdeposition chamber 203 in preparation for the introduction of the next precursor material. -
FIG. 3 illustrates an embodiment ofcontrol unit 215 that may be utilized to controlprecursor gas controller 213,vacuum pump 223, orRF generators Control unit 215 may be any form of computer processor that can be used in an industrial setting for controlling process machines. In an embodiment,control unit 215 may include aprocessing unit 301, such as a desktop computer, a workstation, a laptop computer, the like, or a dedicated unit customized for a particular application.Control unit 215 may be equipped with adisplay 303 and one or more input/output components 305, such as instruction outputs, sensor inputs, a mouse, a keyboard, printer, combinations of these, or the like.Processing unit 301 may include a central processing unit (CPU) 306,memory 308, amass storage device 310, avideo adapter 314, and an I/O interface 316 connected to abus 312. -
Bus 312 may be one or more of any type of several bus architectures including a memory bus or memory controller, a peripheral bus, or video bus.CPU 306 may include any type of electronic data processor, andmemory 308 may include any type of system memory, such as static random access memory (SRAM), dynamic random access memory (DRAM), or read-only memory (ROM).Mass storage device 310 may include any type of storage device configured to store data, programs, or other information and configured to make the data, programs, or other information accessible viabus 312.Mass storage device 310 may include, for example, one or more of a hard disk drive, a magnetic disk drive, or an optical disc drive. - The
video adapter 314 and the I/O interface 316 provide interfaces to couple external input and output devices to theprocessing unit 301. As illustrated inFIG. 3 , examples of input and output devices include thedisplay 303 coupled to thevideo adapter 314 and the I/O component 305, such as a mouse, keyboard, printer, and the like, coupled to the I/O interface 316. Other devices may be coupled to theprocessing unit 301, and additional or fewer interface cards may be utilized. For example, a serial interface card (not shown) may be used to provide a serial interface for a printer. Theprocessing unit 301 also may include anetwork interface 318 that may be a wired link to a local area network (LAN) or a wide area network (WAN) 320 and/or a wireless link. It should be noted thatcontrol unit 215 may include other components. For example,control unit 215 may include power supplies, cables, a motherboard, removable storage media, cases, and the like. These other components, although not shown inFIG. 3 , are considered part ofcontrol unit 215. - In some cases, an oxygen plasma presenuring deposition of a material over a photoresist or polymer underlayer can damage the underlayer surface. In some cases, the underlayer is damaged or consumed as oxygen radicals (O*) formed in the plasma break carbon-carbon bonds (C—C, C═C) or carbon-hydrogen bonds (C—H) within the underlayer. For example, the oxygen plasma may react with the underlayer according to:
-
C=C+O*→CO2 or CO -
C—H+O*→CO2+H2O, - though other reactions may be possible.
- In a PEALD process, the use of oxygen-containing precursor materials for the deposition of an oxygen-containing film can form an oxygen plasma during deposition that damages the underlayer. In some cases, the oxygen plasma consumes or etches part of the underlayer, which can result in a reduction of the thickness of the underlayer with respect to the as-deposited thickness. For example, oxygen plasma damage to
underlayer 114 due to the deposition ofLTD film 116 may reduce the thickness ofunderlayer 114 from its initial as-deposited thickness T1 to a smaller thickness T2. Thisunderlayer 114 thickness change is shown representatively inFIG. 1B by thickness change DT1. In some cases, the amount of thickness change DT1 is determined by the material ofunderlayer 114 and the characteristics of the oxygen plasma and the PEALD process. This damage can result in reduced process uniformity or reproducibility, and in some cases may affect the dimensions of patterned structures or other features. - In some embodiments, the use of an oxygen-containing precursor other than an allotrope of oxygen (e.g., gaseous oxygen O2, ozone O3, etc.) for the deposition of
LTD film 116 allows for the formation ofLTD film 116 with a reduction of oxygen plasma present during deposition. In some embodiments, instead of or in addition to an oxygen allotrope precursor, precursors such as CO2, N2O, or N2O2 may be used. In some embodiments, one or more alcohols may be used as a precursor, such as ethanol or other alcohols or combinations of alcohols. In some embodiments, more than one precursor may be used, and in some embodiments more than one precursor may be used in combination with or without the use of an oxygen allotrope precursor as another precursor material. The use of precursors with less oxygen content (e.g., precursors without gaseous oxygen O2, ozone O3, etc.) can form an oxygen-containingLTD film 116 overunderlayer 114 with less damage tounderlayer 114. -
FIG. 4 illustrates agraph 400 showing example results of experiments of depositing an LTD film on an underlayer, producing a multilayer structure similar to the structure shown inFIG. 1B .Graph 400 showscurves graph 400, three different LTD films are deposited, represented bycurves Curves curves curves curve 410. Thus,graph 400 shows an example of how the techniques described by some embodiments herein may reduce damage to a photoresist or polymer underlayer when an oxygen-containing dielectric film is deposited directly on the underlayer. - Returning now to
FIG. 1B , a deposition system such asdeposition system 200 may be utilized to depositLTD film 116 ontounderlayer 114. In some embodiments, the formation ofLTD film 116 may be initiated by introducing precursor materials into the firstprecursor delivery system 205 or the secondprecursor delivery system 206. In some embodiments, first precursor materials include CO2, N2O, N2O2, one or more alcohols, other materials, or a combination. In some embodiments, second precursor materials include tris(dimethylamino)silane (3DMAS), tetrakis(dimethylamino)titanium (TDMAT), bis(tertiary-butyl-amino) silane (BTBAS), bis(diethylamino)silane (BDEAS), other materials, or a combination. In some embodiments, an oxygen allotrope precursor may be used as a third precursor material in combination with another first precursor material. - Once a first precursor material and a second precursor material have been placed into first
precursor delivery system 205 and secondprecursor delivery system 206, the formation ofLTD film 116 may be initiated bycontrol unit 215 sending an instruction toprecursor gas controller 213 to sequentially or alternately connect firstprecursor delivery system 205 and secondprecursor delivery system 206 todeposition chamber 203. Once connected, firstprecursor delivery system 205 and secondprecursor delivery system 206 can deliver the first precursor material and the second precursor material to showerhead 217 throughprecursor gas controller 213 andmanifold 216.Showerhead 217 can then disperse the first precursor material and the second precursor material intodeposition chamber 203, in which the first precursor material and the second precursor material can formLTD film 116 onunderlayer 114.Control unit 215 can also ignite a precursor material into a plasma withindeposition chamber 203, for example, usingRF generators LTD film 116. In some cases,LTD film 116 may be deposited in thesame deposition chamber 203 as other processing steps such as deposition processes or etching processes. For example, a plasma etching process or another plasma-enhanced deposition process may also be performed onsemiconductor device 100 withindeposition chamber 203. - In some embodiments, for the formation of
LTD film 116, first precursor material may be flowed intodeposition chamber 203 at a flow rate of between about 10 sccm and about 5000 sccm, and second precursor material may be flowed intodeposition chamber 203 at a flow rate of between about 10 sccm and about 5000 sccm. For example, CO2 as a first precursor material may be flowed intodeposition chamber 203 at a flow rate of between about 10 sccm and about 5000 sccm. Additionally,deposition chamber 203 may be held at a pressure of between about 0.1 Torr and about 10 Torr and a temperature of between about 0° C. and about 200° C., such as about 90° C. In some embodiments,LTD film 116 is formed using an RF power of between about 1 Watt and about 2000 Watts. In some embodiments,LTD film 116 is formed using a DC power of between about 1 Watt and about 2000 Watts. However, as one of ordinary skill in the art will recognize, these process conditions are only intended to be illustrative, as any suitable process conditions may be utilized while remaining within the scope of the embodiments. - Turning to
FIG. 1C , anupper layer 118 is formed overLTD film 116. In some embodiments,upper layer 118 may be a photoresist. In some cases,upper layer 118 may be part of a multi-layer photoresist stack. For example,upper layer 118 may be the uppermost layer of a multi-layer photoresist stack andLTD film 116 may be a middle layer of the multi-layer photoresist stack.Upper layer 118 may be formed by a spin-on process or another suitable process. In some embodiments, an additional layer such as an adhesion layer may be formed overLTD film 116 prior to formingupper layer 118. InFIG. 1D ,upper layer 118 is patterned using a photolithographic process to form openings withinupper layer 118. - As shown in
FIG. 1E , the patternedupper layer 118 is used as an etching mask for patterning ofLTD film 116. The pattern ofupper layer 118 may be transferred toLTD film 116 via an etching process. In some cases, the etching process is anisotropic, so that the openings inupper layer 118 are extended throughLTD film 116 and have about the same sizes inLTD film 116 as they do inupper layer 118. In some embodiments, one or more etching processes are performed in the same chamber (e.g., deposition chamber 203) as the deposition ofLTD film 116. - As shown in
FIG. 1F , patternedLTD film 116 is used as an etching mask for patterning ofunderlayer 114. The pattern ofLTD film 116 may be transferred tounderlayer 114 via an etching process. In some cases, the etching process is anisotropic, so that the openings inLTD film 116 are extended throughunderlayer 114 and have about the same sizes inunderlayer 114 as they do inLTD film 116. In some cases, as part ofetching underlayer 114, some of or all ofupper layer 118 may be consumed. As shown inFIG. 1G , patternedunderlayer 114 is then used as an etching mask for patterning ofILD layer 112. The pattern ofunderlayer 114 may be transferred toILD layer 112 via an etching process. In some cases, as part ofetching ILD layer 112, some of or all ofLTD film 116 orunderlayer 114 may be consumed. In embodiments whenunderlayer 114 is not completely consumed while etchingILD layer 112, an ashing process may be performed to remove remaining residue of theunderlayer 114. - In
FIG. 1H , etched portions ofILD layer 112 are filled with a conductive material. Any suitable conductive material may be used, such as copper, aluminum, or another metal, and the conductive material may be formed using a plating process or another suitable process. In some embodiments, one or more additional layers may be deposited over the etched portions ofILD layer 112 before forming the conductive material, such as barrier layers, adhesion layers, seed layers, or other layers. After filling the etched portions, a planarization process, such as a chemical mechanical polish (CMP), may be performed to remove excess portions of the conductive material over theILD layer 112 to formconductive lines 120. - While the example embodiment of
FIGS. 1A-1H shows anLTD film 116 used to pattern anILD layer 112, in other embodiments, theILD layer 112 may be another type of layer. For example,ILD layer 112 may be a semiconductor substrate used to form devices such as FinFETs rather than an ILD layer. In some cases,ILD layer 112 includes one or more layers, such as additional inter-layer dielectric layers, other types of dielectric layers, semiconductor layers, conductive layers, etc. As such,ILD layer 112 is an example layer representative of one or more different kinds of layers that may be present during the formation of asemiconductor device 100. - In some cases, the presence of
LTD film 116 may improve adhesion of an overlying layer such asupper layer 118. In some cases, the presence ofLTD film 116 may reduce the chance of peeling of patterned features formed inupper layer 118. For example, usingLTD film 116 may improve adhesion of patternedupper layer 118, shown inFIG. 1D . - By using a deposition process having lower temperatures and reduced oxygen plasma, the techniques described herein allow for the deposition of an oxide LTD film on an underlayer with less damage to the underlayer. In particular, oxygen plasma damage to a photoresist or polymer underlayer may be reduced. In some cases, the use of an LTD film as described may allow for critical dimension shrinkage for patterned structures to enable smaller feature sizes. The deposition of an LTD film as described can enable finely patterned features to be formed with greater process control, decreased feature size, and increased yield.
- In other embodiments, LTD film as described herein may be used as a gap-fill material deposited within gaps or openings during processing of a semiconductor device. For example, in accordance with an exemplary embodiment,
FIGS. 5A-5C illustrate cross-sectional views of intermediate stages of forming asemiconductor device 500 using anLTD film 516 as a gap-fill material. InFIG. 5A , an optionalbottom layer 512 is formed over asubstrate 502. In some embodiments,substrate 502 may be similar tosubstrate 102 andbottom layer 512 may be similar toILD layer 112, described above with respect toFIGS. 1A-1G . -
FIG. 5A also illustrates anunderlayer 514 formed overbottom layer 512. In some embodiments,underlayer 514 is a photoresist or polymer material, andunderlayer 514 may be similar tounderlayer 114 described previously with respect toFIGS. 1A-1G . In some embodiments,underlayer 514 is formed to have an as-deposited thickness T3 between about 5 nm and about 1000 nm.Underlayer 514 may be formed by a spin-on process or another suitable process. -
FIG. 5A also illustrates anupper layer 518 formed overunderlayer 514. As shown inFIG. 5A ,upper layer 518 has been patterned using a photolithographic process to form openings withinupper layer 518. In some embodiments,upper layer 518 is an oxygen-containing dielectric material similar toLTD film 116, butupper layer 518 may be another dielectric material in other embodiments. As shown inFIG. 5B , patternedupper layer 518 is used as an etching mask for a patterning ofunderlayer 514. The pattern ofupper layer 518 may be transferred tounderlayer 514 via an etching process, formingopenings 522 withinunderlayer 514. In some cases, the etching process is anisotropic, so that openings inupper layer 518 are extended throughunderlayer 514 asopenings 522 and have about the same sizes inunderlayer 514 as they do inupper layer 518. In some cases, as part ofetching underlayer 514, some of or all ofupper layer 518 may be consumed, as shown inFIG. 5B .FIG. 5B also illustrates thatopenings 522 patterned intounderlayer 514 may have an initial width W1. In some embodiments, the initial width W1 may be between about 5 nm and about 100 nm. In some embodiments,openings 522 may be considered recesses inunderlayer 514. - In
FIG. 5C , anLTD film 516 is deposited over theunderlayer 514 and into theopenings 522 as a gap-fill material. In some embodiments,LTD film 516 is also deposited over remaining portions ofupper layer 518. In some embodiments,LTD film 516 may be used as a gap-fill material, sacrificial material, or a reverse material. In some embodiments,LTD film 516 may be deposited conformally to form on sidewalls and a bottom surface ofopenings 522, but inother embodiments film 516 is not deposited conformally. As deposition continues, portions ofLTD film 516 on opposing sidewalls of theopenings 522 may merge, which fills theopenings 522. In some embodiments, a top surface ofLTD film 516 may not be planar, as shown inFIG. 5C . - In some embodiments,
LTD film 516 may be similar toLTD film 116 described previously with respect toFIG. 1A through 4 . For example,LTD film 516 may be deposited by a PEALD process without using O2 as a precursor material in order to reduce possible damage tounderlayer 514. By formingLTD film 516 using one or more precursors that reduce oxygen plasma during deposition as described herein, damage to theunderlayer 514 can be reduced during formation ofLTD film 516. For example, the formation ofLTD film 516 overunderlayer 514 may reduce the thickness ofunderlayer 514 from a thickness T3 to a smaller thickness T4, shown representatively inFIG. 5C as thickness change DT3. By depositingLTD film 516 using the techniques described herein, the thickness change DT3 may be less than using other techniques in which more oxygen plasma is present during deposition. In some cases, deposition ofLTD film 516 may also consume portions of theunderlayer 514 sidewalls ofopenings 522. For example, as shown inFIG. 5C , the initial width W1 ofopenings 522 may increase to W2 after deposition ofLTD film 516. In some embodiments, the increase in width from W1 to W2 during formation ofLTD film 516 may be less than about 5 nm, such as about 3 nm. In some cases, the change in width after depositing an LTD film as described herein may be as much as about 5 nm less than the change in width after depositing a dielectric film using an O2 precursor. - In some embodiments, the
device 500 shown inFIGS. 5A-5C may be processed further. For example,LTD film 516 may be subsequently planarized using a CMP process. The remaining portions ofunderlayer 514 may then be removed, leaving portions ofLTD film 516 remaining on thebottom layer 512. The remaining portions ofLTD film 516 may then be used as an etch mask for the patterning of thebottom layer 512. A conductive material may be deposited over the patternedbottom layer 512 to form conductive lines, contacts, vias, or the like. This is an example process, and other processes using an LTD film as a gap-fill material are within the scope of this disclosure. - An LTD film as described herein may also be used for reducing feature sizes in a BEOL process of a semiconductor device. In accordance with another exemplary embodiment,
FIGS. 6A-6J illustrate cross-sectional views of intermediate stages of forming conductive lines in asemiconductor device 600. In particular,FIGS. 6A-6J illustrate an embodiment in which aLTD film 616 is used as a conformal material to decrease patterned feature size during processing ofsemiconductor device 600. InFIG. 6A ,ILD layer 612 is formed over asubstrate 602. In some embodiments,substrate 602 may be similar tosubstrate 102 orsubstrate 502 andILD layer 612 may be similar toILD layer 112 orbottom layer 512, described above with respect toFIGS. 1A-1H andFIGS. 5A-5C . In some cases,substrate 602 may be a partially processed semiconductor device. The embodiment shown inFIGS. 6A through 6J may, for example, be part of a BEOL process or part of another process. -
FIG. 6A also illustrates anunderlayer 614 formed overILD layer 612. In some embodiments,underlayer 614 is a photoresist material, andunderlayer 614 may be similar tounderlayer 114 orunderlayer 514 described previously with respect toFIGS. 1A-1H andFIG. 5A-5C . In some embodiments,underlayer 614 is formed to have an as-deposited thickness T5 between about 5 nm and about 1000 nm.Underlayer 614 may be formed by a spin-on process or another suitable process. -
FIG. 6A also illustrates anupper layer 618 formed overunderlayer 614. As shown inFIG. 6A ,upper layer 618 has been patterned using a photolithographic process to form openings withinupper layer 618. In some embodiments,upper layer 618 is an oxygen-containing dielectric material similar toLTD film 116, butupper layer 618 may be another dielectric material in other embodiments. As shown inFIG. 6B , patternedupper layer 618 is used as an etching mask for patterning ofunderlayer 614. The pattern ofupper layer 618 may be transferred tounderlayer 614 via an etching process, formingfirst openings 622 withinunderlayer 614. In some cases, the etching process is anisotropic, so that openings inupper layer 618 are extended throughunderlayer 614 asopenings 622 and have about the same sizes inunderlayer 614 as they do inupper layer 618. In some cases, as part ofetching underlayer 614, some of or all ofupper layer 618 may be consumed, as shown inFIG. 6B .FIG. 6B also illustrates thatopenings 622 patterned intounderlayer 614 may have an initial width W3. In some embodiments,openings 622 may be considered recesses inunderlayer 614. - In some cases, the sidewalls of
openings 622 may have rough surfaces after patterning. As an illustrated example,FIG. 6C shows a cross-sectional view of anexample opening 622, similar toopenings 622 shown inFIG. 6B .FIG. 6D shows theopening 622 ofFIG. 6C in a plan view, and the cross-sectional view ofFIG. 6C is alongline 6C-6C′ shown in the plan view ofFIG. 6D . As shown inFIG. 6D , theopening 622 sidewalls also exhibit roughness in a plan view. In some cases, the roughness may be characterized from one or more measurements of the deviation of theopening 622 sidewall edge from a fixed position, shown as Edge Roughness ER1 inFIG. 6D . In some cases, the roughness may be characterized from one or more measurements of the distance across theopening 622, shown as Width Roughness WR1 inFIG. 6D . In some cases, the use ofLTD film 616 may allow for improved width roughness or improved edge roughness of openings, patterned layers, or subsequently formed features. An example is described below inFIGS. 6F-6J . - Turning to
FIG. 6E , anLTD film 616 is deposited over theunderlayer 614 and intofirst openings 622. In some embodiments,LTD film 616 is also deposited over remaining portions of upper layer 618 (when present). As shown inFIG. 6C ,LTD film 616 may be deposited conformally to form on sidewalls and a bottom surface ofopenings 622. In some embodiments,LTD film 616 may have a thickness between about 0.1 nm and about 100 nm. In some embodiments,LTD film 516 may be similar toLTD film 116 orLTD film 516 described previously with respect toFIGS. 1A-4 andFIGS. 5A-5C . For example,LTD film 616 may be deposited by a PEALD process without using O2 as a precursor material in order to reduce possible damage tounderlayer 614. - Depositing
LTD film 616 conformally withinfirst openings 622 formssecond openings 624. Due to theLTD film 616,second openings 624 have a width W5 that is smaller than the initial width W3 offirst openings 622. The use ofLTD 616 in this manner may allow for smaller feature sizes to be patterned intotarget layer 612, described below in greater detail with respect toFIG. 6D . - Additionally, by forming
LTD film 616 using one or more precursors that reduce oxygen plasma during deposition as described herein, damage to theunderlayer 614 can be reduced during formation ofLTD film 616. For example, the formation ofLTD film 616 overunderlayer 614 may reduce the thickness ofunderlayer 614 from a thickness T5 to a smaller thickness T6, similar tounderlayer 514 as described above with respect toFIGS. 5A-5C . In some cases, deposition ofLTD film 616 may also consume portions of theunderlayer 614 sidewalls ofopenings 622. For example, as shown inFIG. 6C , the initial width W3 ofopenings 622 may increase to W4 after deposition ofLTD film 616. In some embodiments, during formation of aLTD film 616 that is about 3 nm thick, the increase in width from W3 to W4 may be less than about 50 nm, such as about 3 nm. In some embodiments, the thickness of anLTD film 616 deposited on a surface of theunderlayer 614 may be less than, greater than, or about the same as the thickness ofunderlayer 614 at that surface that is consumed during the deposition of theLTD film 616. By reducing the possible damage to the sidewalls ofopenings 622,openings 624 may be formed having smaller widths W5, which can reduce subsequently patterned feature sizes and allow for improved process control. - In some cases, forming
LTD film 616 over theunderlayer 614 and withinopenings 622 may improve sidewall roughness. As an illustrated example,FIGS. 6F-6G show a cross-sectional view and a plan view of theexample opening 622 shown inFIGS. 6C-6D after forming anLTD film 616 within theopening 622, formingopening 624. Theopening 624 shown inFIGS. 6F-6G is similar toopenings 624 shown inFIG. 6E . The cross-sectional view ofFIG. 6F is alongline 6F-6F′ shown in the plan view ofFIG. 6G . TheLTD film 616 may fill small recesses in the rough sidewalls of theunderlayer 614 and may have a smoother surface as deposited than the rough sidewalls of theunderlayer 614. Thus, as shown inFIG. 6F , theLTD film 616 of the sidewalls ofopenings 624 may be less rough than the sidewalls of theunderlayer 614. In some cases, an Edge Roughness ER2 of a sidewall of anopening 624 may be less than an Edge Roughness ER1 of a sidewall of anopening 622. In some cases, a Width Roughness WR2 of a sidewall of anopening 624 may be less than a Width Roughness WR1 of a sidewall of anopening 622. The use of an LTD film to reduce sidewall roughness in this manner may allow subsequently formed features to have less roughness or more uniformity. - Turning to
FIG. 6H ,openings 624 may be transferred to targetlayer 612 via an etching process. In some cases, the etching process is anisotropic, so that theopenings 624 are extended throughtarget layer 612 and have about the same sizes intarget layer 612 as they do inopenings 624. The etching process may also etch top surfaces ofLTD film 616 overunderlayer 614, as shown inFIG. 6H . In some cases, the use of an LTD film deposition process as described herein can allow for smaller feature sizes when used to decrease the size of openings formed in a previous patterning step. A planarization process (e.g., a chemical mechanical polish (CMP), dry etching, combinations thereof, or the like) may optionally be performed to remove portions ofLTD film 616 coveringunderlayer 614. In some cases, upper portions ofunderlayer 614 may also be removed by the planarization process. - In some embodiments, further processing may be performed. For example, in some embodiments, the
openings 624 intarget layer 612 may subsequently be filled with a conductive material to form vias, conductive lines, or other conductive features. As shown inFIGS. 6I-6J , theopenings 624 intarget layer 612 are filled with aconductive material 630 to formconductive lines 632. The cross-sectional view ofFIG. 61 is along line 61-61′ shown in the plan view ofFIG. 6J . After theconductive material 630 is formed, theLTD film 616,underlayer 614, and excess portions ofconductive material 630 may be removed by a planarization process such as CMP or by an etching process. In some embodiments, theLTD film 616 is removed before forming theconductive material 630. In this manner, theLTD film 616 may be used to form features having smaller dimensions, such asconductive lines 632. The embodiment shown inFIGS. 6A-6J is for illustrative purposes, and other embodiments may include additional layers, features, or process steps. - Using
LTD film 616 to improve the roughness ofopenings 622 may then also reduce roughness of features patterned from theopenings 622. For example, usingLTD film 616 to reduce sidewall roughness ofopenings 622 may reduce a Line Edge Roughness LER or a Line Width Roughness LWR ofconductive lines 632, shown inFIG. 6J . In this manner, the use of an LTD film to reduce the roughness of patterned features may allow subsequently formed features to have less roughness or more uniformity. - An LTD film as described herein may be used may also be used as a gap-fill material deposited within gaps or openings in a BEOL process of a semiconductor device. In accordance with an exemplary embodiment,
FIGS. 7A through 15B illustrate cross-sectional views and/or plan views of intermediate stages in the formation of conductive features in anILD layer 702 of asemiconductor device 700. The process shown inFIGS. 7A through 15B illustrate an embodiment in which anLTD film 736 may be used as a gap-fill material, andLTD film 736 may be used as a gap-fill material similar toLTD film 516 described above with respect toFIGS. 5A-5C . Thesemiconductor device 700 is shown inFIG. 7A (in cross-sectional view) andFIG. 7B (in plan view). The cross-sectional view ofFIG. 7A is along line A-A′ shown in the plan view ofFIG. 7B . InFIGS. 7A-7B ,ILD layer 702 is formed over asubstrate 704. In some embodiments,substrate 704 may be similar to other substrates described above, orILD layer 702 may be similar to other layers described above, such asILD layer 112 as described with respect toFIG. 1A , or may be another type of layer. The embodiment shown inFIGS. 7A through 15B may, for example, be part of a BEOL process or part of another process. -
FIGS. 7A-7B illustratemask regions 724 formed overILD layer 702. Themask regions 724 may be formed, for example, by patterning a blanket dielectric layer using a photolithographic process. In a plan view, gaps betweenmask regions 724 define regions in which conductive features may be formed inILD layer 702. InFIG. 8 , maskinglayer 728 is formed overmask regions 724 andILD layer 702. In some embodiments, maskinglayer 728 is a photoresist or polymer material, and may be similar tounderlayer 114,underlayer 514, orunderlayer 614 described previously with respect toFIGS. 1A-1G ,FIGS. 5A-5C , orFIGS. 6A-6J . In some embodiments, maskinglayer 728 includes multiple layers and multiple materials. - In
FIGS. 9A-9C , maskinglayer 728 is patterned using a photolithographic process to formopenings 734. The cross-sectional view ofFIG. 9A is along line A-A′ shown in the plan view ofFIG. 9B , which is also shown in the perspective view ofFIG. 9C . In the perspective view ofFIG. 9C , portions of maskinglayer 728 have been shown as transparent so that anopening 734 may be more clearly displayed. - In
FIGS. 10A-10C ,LTD material 736 is formed inopenings 734 and overmasking layer 728. The cross-sectional view ofFIG. 10A is along line A-A′ shown in the plan view ofFIG. 10B , which is also shown in the perspective view ofFIG. 10C . In the perspective view ofFIG. 10C , portions of maskinglayer 728 have been shown as transparent so that theLTD material 736 formed within anopening 734 may be more clearly displayed. In some embodiments,LTD material 736 may be used as a gap-fill material or as a sacrificial material. In some embodiments,LTD material 736 may be similar toLTD film 116,LTD film 516, orLTD film 616 described previously with respect toFIGS. 1A-4 ,FIGS. 5A-5C , andFIGS. 6A-6J . For example,LTD material 736 may be deposited by a PEALD process without using O2 as a precursor material in order to reduce possible damage tounderlayer 728. In some embodiments,LTD material 736 may be deposited conformally to fillopening 734. - As will be described in greater detail below, in subsequent processing the
LTD material 736 will be further patterned, and thepatterned LTD material 736 may be used to define a line cut between two adjacent conductive lines that will be formed in theILD layer 702. AlthoughFIG. 10 depicts the forming ofLTD material 736 in asingle opening 734, in some embodiments only one or more than twoopenings 734 may be present andLTD material 736 may be formed in the one or more than two openings 734 (for example, to form less line cuts or additional line cuts). - Next, in
FIG. 11 , a planarization process (e.g., CMP, dry etching, combinations thereof, or the like) may be performed to remove excess portions ofLTD material 736 outside ofopenings 734. Next, inFIGS. 12A-12B , remaining portions of maskinglayer 728 are removed. The cross-sectional view ofFIG. 12A is along line A-A′ shown in the plan view ofFIG. 12B . In some embodiments, themasking layer 728 may be removed using an ashing process. After themasking layer 728 is removed,LTD material 736 remains and covers a portion of themask regions 724 andILD layer 702. - Next, referring to
FIGS. 13A-13C , a planarization process is performed to remove excess portions ofLTD material 736 and planarize a top surface ofLTD material 736 to be level with top surfaces of themask regions 724. The cross-sectional view ofFIG. 13A is along line A-A′ shown in the plan view ofFIG. 13B , which is also shown in the perspective view ofFIG. 13C . In some embodiments, the planarization process includes one or more etching processes. For example, a dry etching process or a wet etching process may be used. In other embodiments, a grinding process such as CMP may be used. The resulting structure is depicted inFIGS. 13A and 13B . As can be seen inFIGS. 13A-13B , the planarization ofLTD material 736 has created discrete portions of theLTD material 736, where each discrete portion overlies a gap between twoadjacent mask regions 724. In some embodiments, each discrete portion overlies a region in which a line cut between two adjacent portions of conductive line will be formed. - Subsequently, in
FIGS. 14A and 14B ,LTD material 736 andmask regions 724 are used as an etching mask to formopenings 750 into theILD layer 702. Etching theILD layer 702 may include an anisotropic dry etch process or a wet etch process. Remaining portions of theILD layer 702 may have a same pattern as themask regions 724 and theLTD material 736 ofFIGS. 14A-14B . - Next, as shown in
FIGS. 15A and 15B , remaining portions of theopenings 750 may be filled with aconductive material 764.Conductive material 764 may be used, such as copper, aluminum, or another metal, andconductive material 764 may be formed using a plating process or another suitable process. In some cases,conductive material 764 may be initially deposited to overfillopenings 750. After filling theopenings 750, a planarization process, such as a chemical mechanical polish (CMP), may be performed to remove excess portions ofconductive material 764. In some embodiments, a liner material may be formed withinopenings 750 before forming theconductive material 764. - As shown in
FIGS. 15A-15B , a planarization process may be performed to remove excess portions of theconductive material 764 over theILD layer 702. Thus, conductive features may be formed in theILD layer 702. In some embodiments where the conductive features in theILD layer 702 are conductive lines, areas that are underneath the portions ofLTD material 736 whenILD layer 702 is patterned are areas where the conductive lines have gaps, or “line cuts.” For example, usingLTD material 736, line cut 770 separates firstconductive line 772 from secondconductive line 774. The use ofLTD material 736 as described may allow for improved line width variation or improved line edge roughness, which may allow for smaller conductive features and smaller line cuts between conductive features. - An LTD film as described herein may be used for forming features in a Front End of Line (FEOL) process of a semiconductor device. In accordance with an exemplary embodiment,
FIGS. 16-25 illustrate intermediate stages in a FEOL process using anLTD layer 862 to formfins 868 of a FinFET device.FIG. 16 illustrates an example of a FinFET in a three-dimensional view, according to some embodiments.FIGS. 17 through 25 illustrate cross-sectional views of intermediate stages of forming fins of FinFETs according to some embodiments. The cross-sectional views ofFIGS. 17 through 25 are taken along the line B-B′ shown in the three-dimensional view ofFIG. 16 . The example FinFET shown inFIG. 16 includes afin 874 on asubstrate 850.Isolation regions 872 are onsubstrate 850, andfin 874 protrudes above and from between neighboringisolation regions 872. Agate dielectric layer 818 is along sidewalls and over a top surface offin 874, and agate electrode 820 is overgate dielectric layer 818. Source/drain regions 802 are disposed in opposite sides offin 874 with respect togate dielectric layer 818 andgate electrode 820. Some embodiments discussed herein are discussed in the context of FinFETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Also, some embodiments contemplate aspects used in planar devices, such as planar FETs. The embodiment shown inFIGS. 16 through 25 may, for example, be part of a Front End of Line (FEOL) process or part of another process. -
FIG. 17 illustrates asubstrate 850 according to some embodiments. Thesubstrate 850 has afirst region 850B and asecond region 850C. Thefirst region 850B can be for forming n-type devices, such as NMOS transistors, e.g., n-type FinFETs.Second region 850C can be for forming p-type devices, such as PMOS transistors, e.g., p-type FinFETs. In some embodiments, bothfirst region 850B andsecond region 850C are used to form the same type of devices, such as both regions being for n-type devices or p-type devices.First region 850B andsecond region 850C may be physically separated from each other, and any number of structures (e.g., isolation regions, active devices, etc.) may be disposed betweenfirst region 850B andsecond region 850C.Substrate 850 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped.Substrate 850 may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multi-layered or gradient substrate may also be used. In some embodiments, the semiconductor material ofsubstrate 850 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. - In
FIG. 18 , a film stack is formed oversubstrate 850. The film stack is used during processing to form features insubstrate 850 that may be a fraction of the minimum photolithographic pitch. In some embodiments, the process is a self-aligned double patterning (SADP) process, where the features formed are one half the minimum photolithographic pitch. In other embodiments, the process may be a self-aligned quadruple patterning (SAQP) process, where the features formed are one quarter of the minimum photolithographic pitch. The film stack includes an anti-reflective coating (ARC) 852, amask layer 854, and amandrel layer 856. In other embodiments, the film stack may include more or fewer layers. -
ARC 852 is formed oversubstrate 850, and aids in the exposure and focus of overlying photoresist layers (discussed below) during patterning of the photoresist layers. In some embodiments,ARC 852 may be formed from SiON, SiC, materials doped with oxygen (O) and nitrogen (N), or the like. In some embodiments,ARC 852 is substantially free from nitrogen, and may be formed from an oxide. -
Mask layer 854 is formed overARC 852. In some embodiments, themask layer 854 is an LTD film, which may be similar toLTD film 116,LTD film 516,LTD film 616, orLTD material 736 described previously with respect toFIGS. 1A-4 ,FIGS. 5A-5C ,FIGS. 6A-6E , andFIGS. 7A-15B . In some cases, using an LTD film for themask layer 854 may improve adhesion of an overlying layer or overlying features. In some cases, using an LTD film for themask layer 854 instead of another material for themask layer 854 may reduce the chance of peeling of patterned features formed on themask layer 854. For example, using an LTD film for themask layer 854 may improve adhesion of amandrel layer 856 ormandrels 858, described below. In other embodiments,mask layer 854 may be formed of a hard masking material, and may include a metal and/or a dielectric. In embodiments wheremask layer 854 includes a metal, it may be formed of titanium nitride, titanium, tantalum nitride, tantalum, or the like. In embodiments wheremask layer 854 includes a dielectric, it may be formed of an oxide, a nitride, or the like.Mask layer 854 may be formed by PVD, Radio Frequency PVD (RFPVD), Atomic Layer Deposition (ALD), or the like. In subsequent processing steps, a pattern is formed in themask layer 854 as part of the SADP process.Mask layer 854 is then used as an etching mask, where the pattern ofmask layer 854 is transferred tosubstrate 850. -
Mandrel layer 856 is a sacrificial layer formed overmask layer 854. In some embodiments,mandrel layer 856 is a photoresist or polymer material, and may be similar tounderlayer 114,underlayer 514,underlayer 614, or maskinglayer 728 described previously with respect toFIGS. 1A-1G ,FIGS. 5A-5C ,FIGS. 6A-6F , orFIGS. 7A-14B . In some embodiments,mandrel layer 856 may formed of a material that has a high etching selectivity with the underlying layer, e.g., withmask layer 854. In some embodiments,mandrel layer 856 may be formed of a material such as amorphous silicon, polysilicon, silicon nitride, silicon oxide, the like, or a combination thereof, and may be formed using a process such as a chemical vapor deposition (CVD), PECVD, or the like. In an embodiment,mandrel layer 856 is formed of polysilicon. - In
FIG. 19 ,mandrel layer 856 is patterned to formmandrels 858.Mandrel layer 856 may be patterned using any suitable photolithography technique. As an example ofpatterning mandrel layer 856, a tri-layer photoresist (not shown) may be formed over the film stack. The tri-layer photoresist may include a bottom layer, a middle layer, and an upper layer. The upper layer may be formed of a photosensitive material, such as a photoresist, which may comprise organic materials. The bottom layer may be a bottom anti-reflective coating (BARC). The middle layer may be formed of or include an inorganic material, which may be a nitride (such as silicon nitride), an oxynitride (such as silicon oxynitride), an oxide (such as silicon oxide), or the like. The middle layer has a high etching selectivity relative to the upper layer and the bottom layer. As a result, the upper layer is used as an etching mask for the patterning of the middle layer, and the middle layer is used as an etching mask for the patterning of the bottom layer. - After the pattern is transferred to the bottom layer, an etching process is performed to transfer the pattern of the bottom layer to
mandrel layer 856. The etching process may remove the portions ofmandrel layer 856 exposed by the middle and bottom layers. In an embodiment, the etching process may be a dry etch wheremandrel layer 856 is exposed to a plasma source and one or more etchant gases. The etch may be an inductively coupled plasma (ICR) etch, a transformer coupled plasma (TCP) etch, an electron cyclotron resonance (ECR) etch, a reactive ion etch (RIE), or the like. Remaining portions ofmandrel layer 856form mandrels 858. In some embodiments, the etching process used to transfer the pattern tomandrel layer 856 may remove the middle layer and partially remove portions of the bottom layer. An ashing process may be performed to remove remaining residue of the middle and/or bottom layers. - In
FIG. 20 , aLTD layer 862 is formed overmask layer 854 andmandrels 858. After formation,LTD layer 862 may extend along top surfaces ofmask layer 854 andmandrels 858, and along sidewalls ofmandrels 858. In some embodiments,LTD layer 862 may be similar toLTD film 116,LTD film 516,LTD film 616, orLTD material 736 described previously with respect toFIGS. 1A-4 ,FIGS. 5A-5C ,FIGS. 6A-6E , andFIGS. 7A-14B . For example,LTD layer 862 may be deposited by a PEALD process without using O2 as a precursor material in order to reduce possible damage to mandrels 858. Reducing damage tomandrels 858 may improve process uniformity during formation offins 874, described below. - In
FIG. 21 , a suitable etching process is performed to remove the horizontal portions ofLTD layer 862. In some embodiments, the etchant used to etch the horizontal portions of theLTD layer 862 is Cl2, CH4, N2, Ar, the like, or a combination thereof. After the etching process, the vertical portions ofLTD layer 862 may remain along the sides ofmandrels 858, and are referred to asspacers 864 hereinafter. The etching process may be anisotropic, so that the width ofspacers 864 does not significantly decrease. - In
FIG. 22 ,mandrels 858 are removed.Mandrels 858 may be removed by a suitable etching processes, such as an etching process including etchants such as CF4, CH3F, H2, N2, Ar, the like, or a combination thereof, an ashing process, or any other suitable etching process that can removemandrels 858 without substantiallydamaging spacers 864. Further, a wet clean process may also be applied tosubstrate 850 to remove residual spacer and mandrel material. In some embodiments, the spacer etch and the mandrel removal processes are performed in a same process chamber. - In
FIG. 23 ,spacers 864 are used as an etching mask topattern mask layer 854. A suitable etching process, such as an anisotropic etch, may be performed with any suitable chemical, such as CF4, HBr, Cl2, O2, Ar, the like, or a combination thereof. The pattern ofspacers 864 is therefore transferred to themask layer 854 to form openings inmask layer 854. - In
FIG. 24 ,fins 868 are formed in thesubstrate 850.Fins 868 are formed by using the patternedmask layer 854 as an etching mask to etchARC 852 andsubstrate 850, thereby forming trenches insubstrate 850. The resulting semiconductor strips between the trenches formfins 868. The etching may be any acceptable etch process, and may use etchants such as Cl2, N2, CH4, the like, or a combination thereof. The etch may be anisotropic. Thespacers 864, patternedmask layer 854, and patternedARC 852 may be consumed in this process. In some embodiments, a cleaning process may be performed to remove any residual material ofspacers 864, patternedmask layer 854, or patternedARC 852. - In
FIG. 25 , an insulation material is formed oversubstrate 850 and between neighboringfins 868. The insulation material may be an oxide, such as silicon oxide, a nitride, the like, or a combination thereof. The insulation material is then recessed to form Shallow Trench Isolation (STI)regions 872. The insulation material is recessed such thatfins 874 in thefirst region 850B and in thesecond region 850C protrude from between neighboringSTI regions 872. The insulation material may be recessed to formSTI regions 872 using an acceptable etching process, such as one that is selective to the material of the insulation material. Thefins 874 may be similar tofin 874 shown inFIG. 16 , above. After formingfins 874, other processing steps may be performed to form FinFETs such as that shown inFIG. 16 . For example, agate dielectric layer 818 and agate electrode 820 may be formed over eachfin 874, and source/drain regions 802 may be formed on opposite sides of eachfin 874. This is an illustrative example, and other embodiments of forming a FinFET, including those using additional or other processing steps, are within the scope of this disclosure. - Although the process illustrated in
FIGS. 17 through 25 is used to form thefins 874, it should be appreciated that the fabrication steps shown inFIGS. 17 through 25 may be used in other processes. For example, spacers formed from an LTD layer could be formed over and used to pattern other semiconductor device elements such as polysilicon gates, metal gates, dummy gates, isolation regions, interconnect structures, gate spacers, a contact etch stop layer (CESL), and the like. - Various embodiments described above provide the use of a process for depositing a low-temperature dielectric (LTD) film. The LTD film described may be deposited over a photoresist or polymer layer with little or no damage to the photoresist or polymer layer. In some embodiments, the LTD film described may be used as an etching mask for photoresist, polymer, or other material. In some embodiments, the LTD film described can be used as a pad layer for as an adhesion improvement layer. For example, a layer (e.g., a photoresist, dielectric, or other type of layer) deposited on an LTD film may have better adhesion than if the layer is deposited on a different material. The use of an LTD film may improve width variation or edge roughness of some features, such as metal lines or other features. The LTD film described may be used as part of a FEOL process or as part of a BEOL process.
- In an embodiment, a method of manufacturing a semiconductor device includes depositing a layer over a semiconductor substrate placing the substrate in a deposition chamber, and depositing an oxide layer over and contacting the layer. Depositing the oxide layer includes flowing first precursor materials into the deposition chamber, within the deposition chamber, forming a portion of the oxide layer from the first precursor materials, igniting second precursor materials into a plasma, the second precursor materials being free of allotropes of oxygen, and within the deposition chamber, forming a portion of the oxide layer from the plasma. In an embodiment, the method further includes patterning an opening in the layer. In an embodiment, depositing the oxide layer includes depositing the oxide layer within the opening in the layer. In an embodiment, the method further includes patterning the oxide layer to extend the opening into the oxide layer. In an embodiment, the oxide layer includes a process temperature of less than about 200° C. In an embodiment, the second precursor materials are free of gaseous oxygen. In an embodiment, the second precursor materials include CO2. In an embodiment, the oxide layer includes SiOC.
- In another embodiment, a method of manufacturing a semiconductor device includes a dielectric layer over a substrate, performing a first patterning to form a recess in the dielectric layer, and depositing an oxide film over and contacting the dielectric layer and within the recess in the dielectric layer, wherein the oxide film is formed from multiple precursors, wherein the precursors of the multiple precursors are free of O2, and wherein depositing the oxide film includes forming a plasma of a first precursor of the multiple precursors. In an embodiment, the oxide film is deposited to fill the recess in the dielectric layer. In an embodiment, the recess has a first interior width, and depositing the oxide film within the recess forms a trench within the recess having a second interior width that is smaller than the first interior width. In an embodiment, the oxide film is deposited conformally within the recess. In an embodiment, the dielectric layer is a photoresist material or a polymer material. In an embodiment, the oxide film is SiOC. In an embodiment, the first precursor of the multiple precursors is CO2.
- In another embodiment, a method includes forming a dielectric layer over a semiconductor substrate, patterning a photoresist over the dielectric layer, placing the semiconductor substrate and the photoresist into a process chamber, transferring the pattern of the photoresist to the dielectric layer using an etching process, providing precursors of multiple precursors to the process chamber, wherein the precursors of the multiple precursors are free of allotropes of oxygen, and forming an oxide layer over and contacting the dielectric layer within the process chamber, including igniting at least one precursor of the multiple precursors into a plasma. In an embodiment, the method further includes etching the oxide layer using an etching process performed within the process chamber. In an embodiment, the multiple precursors include CO2, N2O, or ethanol. In an embodiment, the oxide layer includes SiON. In an embodiment, forming an oxide layer includes using a Plasma-Enhanced Atomic Layer Deposition (PEALD) process.
- The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims (20)
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US10727045B2 (en) | 2020-07-28 |
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