US20190349330A1

US20190349330A1 - Response status management in a social networking environment

Info

Publication number: US20190349330A1
Application number: US16/520,410
Authority: US
Inventors: Rajesh Patil; Prasad P. Purandare
Original assignee: International Business Machines Corp
Current assignee: International Business Machines Corp
Priority date: 2017-04-07
Filing date: 2019-07-24
Publication date: 2019-11-14
Also published as: US11038832B2; US10367776B2; US20180295089A1; US20190349329A1

Abstract

An embodiment of the invention may include a semiconductor structure for ensuring semiconductor design integrity. The semiconductor structure may include an electrical circuit necessary for the operation of the semiconductor circuit and white space having no electrical circuit. The semiconductor structure may include an optical pattern used for validating the semiconductor circuit design formed in the white space of the electrical circuit. In an embodiment of the invention, the optical pattern may include one or more deposition layers. In an embodiment of the invention, the optical pattern may include covershapes. In an embodiment of the invention, the optical pattern may be physically isolated from the electrical circuit. The optical pattern may include a Moiré pattern.

Description

BACKGROUND

The present invention generally relates to semiconductor mask manufacture, and particularly to optical validation of semiconductor masks.
Semiconductor photomasks are designed to define circuit patterns for the transitions and interconnect layers. The photomask design also contains white space in between and around the circuit patterns for the transitions and interconnect layers. The greater the available white space on a photomask, the greater the possibility of additional circuit elements being added to the design by a third party.

BRIEF SUMMARY

An embodiment of the invention may include a semiconductor structure. The semiconductor structure may include an electrical circuit necessary for the operation of the semiconductor circuit. The semiconductor structure may include white space, which may have no electrical circuit. The semiconductor structure may include an optical pattern formed in the white space of the electrical circuit for validating the semiconductor circuit design. In an embodiment of the invention, the optical pattern may include one or more deposition layers. In an embodiment of the invention, the optical pattern may include covershapes. In an embodiment of the invention, the optical pattern may be physically isolated from the electrical circuit. The optical pattern may include a Moiré pattern.

BRIEF DESCRIPTION OF THE DRAWINGS

The following detailed description, given by way of example and not intended to limit the invention solely thereto, will best be appreciated in conjunction with the accompanying drawings, in which:

FIG. 1 is a flow chart of a method for optically validating the correct mask was used during semiconductor manufacture, according to an embodiment of the present invention;

FIG. 2a is a plan view of a photomask for a semiconductor, according to an embodiment of the present invention;

FIG. 2b illustrates an example optical fingerprint design, according to an embodiment of the present invention;

FIG. 2c illustrates an example optical fingerprint design, according to an embodiment of the present invention;

FIG. 2d is plan view of a semiconductor design for a first deposition layer with an optical fingerprint, according to an embodiment of the present invention;

FIG. 2e is plan view of a semiconductor design for a second deposition layer with an optical fingerprint, according to an embodiment of the present invention; and

FIG. 2f is plan view of a semiconductor design for a first and second deposition layer with an optical fingerprint, according to an embodiment of the present invention.

Elements of the figures are not necessarily to scale and are not intended to portray specific parameters of the invention. For clarity and ease of illustration, scale of elements may be exaggerated. The detailed description should be consulted for accurate dimensions. The drawings are intended to depict only typical embodiments of the invention, and therefore should not be considered as limiting the scope of the invention. In the drawings, like numbering represents like elements.

DETAILED DESCRIPTION

The following description with reference to the accompanying drawings is provided to assist in a comprehensive understanding of exemplary embodiments of the invention as defined by the claims and their equivalents. It includes various specific details to assist in that understanding but these are to be regarded as merely exemplary. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the invention. In addition, descriptions of well-known functions and constructions may be omitted for clarity and conciseness.
The terms and words used in the following description and claims are not limited to the bibliographical meanings, but, are merely used to enable a clear and consistent understanding of the invention. Accordingly, it should be apparent to those skilled in the art that the following description of exemplary embodiments of the present invention is provided for illustration purpose only and not for the purpose of limiting the invention as defined by the appended claims and their equivalents.
It is to be understood that the singular forms “a,” “an,” and “the” include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to “a component surface” includes reference to one or more of such surfaces unless the context clearly dictates otherwise.
In the interest of not obscuring the presentation of embodiments of the present invention, in the following detailed description, some processing steps or operations that are known in the art may have been combined together for presentation and for illustration purposes and in some instances may have not been described in detail. In other instances, some processing steps or operations that are known in the art may not be described at all. It should be understood that the following description is rather focused on the distinctive features or elements of various embodiments of the present invention.
Embodiments of the invention generally relate to methods of optically validating the usage of a photomask in semiconductor manufacture. Semiconductor photomasks define the circuit patterns for the transitions and interconnect layers. Photomasks also contain white space in between and around the circuit patterns for the transitions and interconnect layers which allow for the possibility of unwanted additional circuit elements being added by a third party. The present invention uses an algorithm to analyze the available white space on a photomask and designs an optical pattern to be inserted on the photomask to consume the white space. The optical pattern may be viewed under a microscope and/or using a light source. Thus, the present invention prevents the addition of unwanted circuit elements into the design for a semiconductor by providing an optically viewable pattern to occupy the white space in a photomask design.
Embodiments of the present invention will now be described in detail with reference to the accompanying Figures.
FIG. 1 is a flow chart of a method for optically validating the correct mask was used during semiconductor manufacture, according to an embodiment of the present invention. Referring to FIG. 1, the method 100 includes a step 110, designing a photomask; a step 112, running a fingerprint algorithm; a step 114, inserting an optical fingerprint in the white space of the photomask; a step 116, enhancing the photomask using optical proximity correction; a step 118, building a mask; a step 120, building a wafer; a step 122, testing the optical patterns of the wafer; a step 124, comparing the optical patterns of the wafer to known optical patterns of the optical fingerprint design; a step 126, validating the wafer when the optical patterns match; and a step 128, discarding the wafer when the optical patterns do not match. Steps of the method 100 embodied in FIG. 1 are depicted in FIGS. 2a -f.
Referring to step S110, described in conjunction with FIG. 2a , a photomask 210 is designed, photomask 210, defining a design for deposition layer 212 for interconnect layers in a semiconductor chip 214. Photomask 210 design may contain white space 216, i.e. areas of no design, in between and around the circuit designs for the transitions and interconnect layers for semiconductor each chip 214. Photomask 210 may also contain a kerf 218, i.e., white space in between the one or more semiconductor chip 214 designs where the semiconductor chips 214 of a single wafer are cut apart. It may be appreciated that each semiconductor chip 214 is designed using multiple different photomasks 210, each photomask 210 defining circuit structures in a deposition layer 212, which are layered on top of one another.
Referring to step S112, described in conjunction with FIGS. 2b-c , a fingerprint algorithm is run to design an optical fingerprint 220 to fit within the available white space 216 of the design for semiconductor chips 214 on photomask 210. For example, the fingerprint algorithm may analyze the white space 216 of the design of objects to be printed, the sizes of the designed objects to be printed and the critical aspects of the designed objects to be printed for semiconductor chips 214 on photomask 210 and calculate an optical design to fit within white space 216. The fingerprint algorithm may analyze all photomasks 210 that will be used to manufacture semiconductor chip 214 to create optical fingerprint 220. The fingerprint algorithm may account for the overlay and placement of the generated fill structures of the design of optical fingerprint 220 between layers of optical fingerprint 220 to ensure that they are able to be tested and/or visually assessed during and post-manufacturing for validity against the inserted fill. For example, optical fingerprint 220 as illustrated in FIGS. 2b-c shows an optical fingerprint design for multiple photomasks 210 layered on top of one another, i.e. designs for subsequent deposition layers 212. In an embodiment of the invention, the fingerprint algorithm may intentionally omit certain overlay/contact points between layers in optical fingerprint 220. For example, the fingerprint algorithm may use, but is not limited to, a covershape approach to determine the regularity and placement of intentionally omitted shapes within the circuit design of optical fingerprint 220. The covershape definitions may be restricted to the fill definition and fingerprint algorithm and may not be shared with the subsequent manufacturing steps, and thus remain protected which may allow the unique covershape designs to be optically recognized.
Optical fingerprint 220 may be a design for trenches to be etched into the deposition layer 212 of semiconductor chip 214. In another embodiment of the invention, the optical fingerprint 220 may also be designed to fit within kerf 218 on photomask 210 between the designs for semiconductor chips 214.
Referring to step S114, described in conjunction with FIGS. 2d-f , the optical fingerprint 220 is inserted in the white space 216 of the photomask 210 design. FIG. 2d illustrates a first photomask 210 a corresponding to a first deposition layer of semiconductor chip 214 with a first optical fingerprint 220 a. FIG. 2e illustrates a second photomask 210 b corresponding to a second deposition layer of semiconductor chip 214 with a second optical fingerprint 220 b. FIG. 2f illustrates semiconductor chip 214 with the designs for first deposition layer with optical fingerprint 220 a and second deposition layer with optical fingerprint 220 b with overlap area 222. It can be appreciated that semiconductor chip 214 may consist of many deposition layers 212, with each deposition layer 212 having a unique design and optical fingerprint 220. Further, it can be appreciated that semiconductor chip 214 with deposition layers 212 with optical fingerprint 220 may have multiple overlap areas 222 Overlap areas 222 may have unique pattern that can be viewed using a light source or a microscope such as, but not limited to a Moiré pattern.
Referring to step S116, the photomask design containing the semiconductor circuit design and the design for optical fingerprint 220 may be optionally enhanced using optical proximity correction. Optical proximity correction is a photolithography enhancement technique used to compensate for image errors due to diffraction or process effects.
Referring to step S118, a photomask is built according to the photomask design to include optical fingerprint 220, and a wafer is fabricated using the photomask at step S120. The trenches to be etched into the deposition layer 212 of semiconductor chip 214 may contain metal and/or silicon depending on deposition layer 212. For example, semiconductor fabrication consists of several stages including, Front-End-Of-The-Line (FEOL), Middle-Of-The-Line (MOL), and Back-End-Of-The-Line (BEOL) processes. For deposition layers 212 created in FEOL processes, the trenches may be filled with a either silicon, such as, but not limited to Poly Silicon, or Amorphous Silicon, or a metal, such as, but not limited to, copper, aluminum, or tungsten. For deposition layers 212 created in MOL or BEOL processes, the trenches may be filled with a metal, such as, but not limited to, copper, aluminum, or tungsten. In an embodiment of the invention, steps S110-S120 may be repeated until all deposition layers 212 of semiconductor chip 214 are completed.
Referring to step S122, the wafer is optically analyzed to confirm the correct photomask design was used. For example, the trenches of the different deposition layers 212 of optical fingerprint 220 design may have a unique overlap pattern. For example, overlap areas 222 x may form Moiré patterns. The wafer may be analyzed using a light source, such as, but not limited to, an ultraviolet (UV) light source to illuminate semiconductor chip 214. In an embodiment of the invention, the wafer may be analyzed using a microscope. The wafer may be optically analyzed after each deposition layer 212 has been deposited. In an embodiment of the invention, the wafer may be analyzed after two or more deposition layers 212 of semiconductor chip 214 have been deposited.
Referring to step S124, the optical patterns of the wafer are compared to the known optical patterns of optical fingerprint 220. When the optical patterns of the wafer match the known optical patterns of optical fingerprint 220, the wafer is validated at step S126. When the optical patterns of the wafer do not match the known optical patterns of optical fingerprint 220, the wafer is discarded at step S128. In an embodiment of the invention, the wafer may be compared to known covershape designs.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiment, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein. It is therefore intended that the present invention not be limited to the exact forms and details described and illustrated but fall within the scope of the appended claims.

Claims

What is claimed is:

1. A semiconductor structure comprising:

an electrical circuit necessary for the operation of the semiconductor circuit, and white space, wherein the white space has no electrical circuit; and

an optical pattern formed in the white space of the electrical circuit, wherein the optical pattern is used for validating the semiconductor circuit design.

2. The structure of claim 1, wherein the optical pattern comprises one or more deposition layers.

3. The structure of claim 1, wherein the optical pattern comprises covershapes.

4. The structure of claim 1, wherein the optical pattern is physically isolated from the electrical circuit.

5. The structure of claim 1, wherein the optical pattern comprises a Moiré pattern.