US20180299835A1

US20180299835A1 - Time to digital converter with increased range and sensitivity

Info

Publication number: US20180299835A1
Application number: US15/488,278
Authority: US
Inventors: Nicolo Testi
Original assignee: Innophase Inc
Current assignee: Innophase Inc
Priority date: 2017-04-14
Filing date: 2017-04-14
Publication date: 2018-10-18
Anticipated expiration: 2037-04-14
Also published as: WO2018191448A1; CN110573970B; CN110573970A; KR102309359B1; EP3610334A4; KR20190139950A; US10108148B1; EP3610334A1

Abstract

Systems and methods are provided for converting time measurements to digital value representing phase. Such systems and methods use a ring oscillator to create a coarse measurement of the time difference between first and second rising edges of a modulated signal. A two-dimensional Vernier structure is used to create a fine resolution measurement of the error in the coarse measurement. The coarse and fine measurements are combined to calculate a digital time measurement. A digital time output is calculated as the difference in successive digital time measurements. An offset digital time output is calculated as a difference in a digital time output in relation to a carrier period offset. The offset digital time output is scaled and accumulated to calculate the integrated time signal. The integrated time signals are synchronized to the carrier frequency to output a series of final phase measurements.

Description

BACKGROUND

Time to Digital Converters (TDC) are generally used to provide a digital output representing a timing value. A typical TDC circuit measures a time difference between two events: a start and a stop event. In its simplest form, a counter updates based on a high frequency oscillator running at a frequency f₀. The counter updates once every period
$(\frac{1}{f_{0}}) .$
The TDC circuit initiates the counter when the start event occurs. The TDC reads the state of the counter when the stop event occurs and stores the value as the stop counter value. The count value, in conjunction with the counter update rate (or the period
$(\frac{1}{f_{0}}))$
may be used to determine the time difference between the start and stop events.

SUMMARY

In one example embodiment, a TDC uses a combination of coarse and fine measurements to obtain a time measurement. In a further embodiment, the TDC is used within a demodulator of a low power receiver. In some applications, the receiver is a low power, high performance RF system on-chip (SoC) using nanometer technology that features a low, core supply voltage. Taking advantage of nanometer process technology, the receiver's integrated circuit (IC) implements various levels of digital tuning to optimize the analog/RF performance. This specification describes an example receiver's Time to Digital Converter (TDC) to demodulate a received signal, where the demodulation may include removal of the carrier period, scaling and accumulation of the result, and a resampler, which in some embodiments uses a First In, First Out (FIFO) memory in conjunction with a sampling timer circuit.
A receiver time signal is converted to a digital word using coarse and fine TDC components. The coarse TDC portion uses a ring oscillator to calculate a coarse estimate of the length of time delay. The fine TDC portion uses a two-dimensional Vernier structure to calculate a fine resolution estimate of coarse measurement error. The system combines the coarse measurement with the fine measurement to calculate the digital time measurement. The system further processes the output word to handle counter rollover, to prepare a result at the proper sampling times for the baseband read circuit, to remove the carrier period offset, and to scale the resulting signal. For an example receiver, the resulting signal is stored in a FIFO and read from the FIFO when needed by a baseband circuit.
In one example embodiment, a coarse measurement circuit measures a coarse measurement of the time period between a first rising edge and a second rising edge of the modulated signal. In one non-limiting example, it operates for input periods between 2.5 ns and 5 ns. Those periods correspond to input frequencies between 200 MHz and 400 MHz. The Rx TDC comprises a coarse TDC, a fine TDC, and some digital reconstruction circuits. A coarse and fine structure is used in order to meet the desired range and resolution requirements. In the receiver, the coarse TDC generally takes care of the range, while the fine TDC generally takes care of the resolution.
The coarse TDC provides a first coarse measurement of the input period. For one example embodiment, a coarse TDC resolution is 160 ps, and it is based on a ring oscillator-type TDC. At every input rising edge, the system probes the state of the ring oscillator and generates the signals to be passed to the fine TDC circuit. The coarse measurement of the input period is achieved by analyzing the state of the ring oscillator chain and the counters connected to it. Because the ring oscillator in one embodiment avoids resetting during operation, its output corresponds to the accumulation of the sequence of input periods.
The fine TDC provides a finer measurement of the input period and serves as an error measurement of the coarse measurement. In one embodiment, it comprises a two-dimensional Vernier structure. The coarse TDC generates the input signals to be injected into the fine TDC's slow and fast delay lines. The input signals to the fine TDC are (i) the rising edge of the received modulated signal (suitably delayed) and the corresponding output of a coarse TDC ring oscillator element. The fine measurement happens after the coarse measurement has finished. The fine TDC operates on an edge injected into the slow line, which will take longer to propagate than an edge injected into the fast line. Based on where in the corresponding arbiter's grid the edge injected in the fast delay line catches up to the edge injected in the slow delay line, the system calculates the fine TDC value. The system combines the coarse measurement and the fine measurement to obtain the final measurement. In one example embodiment, a receiver's fine measurement circuit uses twelve 50 ps delays in the slow line and nine 45 ps delays in the fast line. The arbiter matrix uses five Vernier lines to provide a range of 240 ps and a resolution of 5 ps. The topology of the Rx TDC allows a wide input range (2.5 ns to 5 ns) with a small resolution size (5 ps). Each consecutive measurement corresponds to the accumulation of all the input periods up to that moment.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a polar receiver.

FIG. 2 is a flowchart of a detailed Time-to-Digital Conversion (TDC) method and post-processing actions.

FIG. 3 is a block diagram of a coarse estimate for a TDC.

FIG. 4 is a block diagram of a two-dimensional Vernier time to digital converter.

FIG. 5 is a block diagram of an arbiter circuit.

FIG. 6 is a block diagram of the combining of a coarse measurement and fine measurement

FIG. 7 is a digital component block diagram of signal processing performed on a digital time measurement.

FIG. 8 is a flowchart of a TDC method.

DETAILED DESCRIPTION

In one example embodiment, an Rx TDC covers a large range (several nanoseconds) with a small resolution (5×10⁻¹²seconds or 5 ps). Various embodiments use a sequence of coarse and fine time measurements to meet the range and resolution usage. Starting with a signal previously processed by other elements of a receive circuit (which will be labeled as the modulated signal), various circuits described herein make a coarse estimate of the period. The circuit makes a fine resolution estimate of the error. The system combines these coarse and fine measurements to arrive at an estimate of the input signal's period. Further processing occurs to convert the time measurement to a phase measurement.
FIG. 1 is a block diagram of an example polar receiver. A radio frequency signal 102 is received by a polar receiver 100 and may be amplified by an amplifier 104. The polar receiver 100 operates to receive and decode modulated radio-frequency signals, such as signals modulated using phase shift keying (PSK) or quadrature amplitude modulation (QAM). The amplifier's output signal connects to separate paths for amplitude and phase.
The amplitude path starts with an amplitude detector 106 such as an envelope detector or a power detector, which operates to provide a signal representing the amplitude of the modulated radio-frequency signal. The amplitude detector 106 may operate using various techniques such as, for example, signal rectification followed by low-pass filtering. The amplitude signal goes through an analog-to-digital converter (ADC) 108. The ADC operates to generate a series of digital amplitude signals representing the amplitude of the sampled radio-frequency signal. In some embodiments, ADC 108 samples the amplitude of the modulated radio-frequency signal at 160 Msps. The ADC's output is stored in a circular buffer 110. Samples stored in the circular buffer are read and delayed via a fractional delay filter 112 and outputted as amplitude sample A _i 130.
The polar receiver 100 is provided with frequency division circuitry 114. In addition, a limiter circuit (not shown) may be used to remove any amplitude information from the signal but which preserves the phase information. In some embodiments, and ILO may be used to remove the amplitude information. The frequency division circuitry has an input for receiving the sampled radio-frequency input signal from the buffer 104 and a frequency-divided output for providing a frequency-divided output signal to a trigger input of a time-to-digital converter (TDC) 116. The frequency division circuitry operates to divide the frequency of the input signal by a frequency divisor. In some embodiments, the frequency division circuitry can be implemented using a harmonic injection-locked oscillator, a digital frequency divider, or a combination thereof, among other possibilities. The frequency division circuitry 114 also acts as an amplitude normalization circuit.
For the phase path, the amplifier's output connects to frequency division circuitry 114 that divides the frequency (by 4 in one embodiment). The frequency division output signal goes into the time-to-digital (TDC) 116 to calculate a digital time output. The time-to-digital converter 116 operates to measure a characteristic time of the frequency-divided signal, such as the period of the frequency-divided signal. The time-to-digital converter 116 may operate to measure the period of the frequency-divided signal by measuring an elapsed time between successive corresponding features of the frequency-divided signal. For example, the time-to-digital converter may measure the period of the frequency-divided signal by measuring a time between successive rising edges of the frequency-divided signal or the time between successive falling edges of the frequency-divided signal. In alternative embodiments, the time-to-digital converter may measure a characteristic time other than a complete period, such as an elapsed time between a rising edge and a falling edge of the frequency-divided signal.
In some embodiments, the time-to-digital converter 116 operates without the use of an external trigger such as a clock signal. That is, the time-to-digital converter 116 measures the time between two features (e.g., two rising edges) of the frequency-divided signal rather than the time between an external trigger signal and a rising edge of the frequency-divided signal. Because the start and end of the time period measured by the time-to-digital converter 116 are both triggered by the frequency-divided signal, rather than an external clock signal, the time-to-digital converter 116, is referred to as a self-triggered time-to-digital converter. In the example of FIG. 7, the self-triggered time-to-digital converter 116 provides a digital time output that represents the period of the frequency-divided output signal.
The carrier period offset (T) is subtracted from the digital time output by adder 118. The offset digital time output is thus at or near zero when no shift is occurring in the phase of the frequency-divided signal. When a phase shift does occur in the sampled radio-frequency signal (a phase-modulated or frequency modulated carrier signal), this results in a temporary change in the period of the sampled radio-frequency signal, which in turn causes a temporary change in the period of the frequency-divided signal. This temporary change in the period of the frequency-divided signal is measured as a temporary change in the digital time output (and in the offset digital time output). In some embodiments, the offset digital time output is at or near zero during periods when the phase of the modulated radio-frequency signal remains steady, while a shift in the phase of the modulated radio-frequency signal results in the offset digital time output signal briefly taking on a positive or negative value, depending on the direction of the phase shift.
The offset digital time output may be scaled by a scaling factor via a multiplier 120. The scaled digital time signal (or offset digital time output in some embodiments) is accumulated by adder 122 and register 124. The digital integrator generates an integrated time signal. The register 124 may be clocked using the frequency-divided signal, resulting in an addition per cycle of the frequency-divided signal. In embodiments in which the offset digital time output signal represents a change in the phase of the sampled radio-frequency signal, the integrated time signal provides a value that represents the current phase of the sampled radio-frequency signal.
The accumulated value goes through another register 126 to be read at the appropriate time based on the input pulse 128. In some embodiments, the register 126 operates to sample the integrated time signal at 160 Msps, although other sampling rates may alternatively be used. The output is a phase sample ψ _i 132. In the embodiment of FIG. 7, frequency division circuitry 114, TDC 116, subtractor 118, multiplier 120, adder 122, and registers 124 and 126 operate as a phase detection circuit operative to generate a series of digital phase signals representing the phase of the sampled signal.
FIG. 2 is a block diagram of the processes executed to convert a time to a digital value and further calculate a phase of the original modulated signal. The frequency division output signal 201 corresponds to the input signal into the TDC block 116 shown on FIG. 1. In other embodiments, a frequency division operation is not used. The frequency division output signal is the input to the coarse TDC measurement block 202. The circuit calculates a coarse estimate of the elapsed time between a coarse measurement start signal and a coarse measurement stop signal. This coarse estimate may include an error amount due to the quantization size of the coarse measurement. The fine TDC measurement block 203 calculates an estimate of the error, and this error value is subtracted from the coarse measurement value with the coarse+fine measurement calculation 204. The digital time output goes into the digital time output calculation block 205 to check for wrapping of the value based on the maximum counter values used in the coarse measurement calculations. The system uses the output of this check to perform the 160 MHz baseband synchronization calculation 206. The polar receiver 100 uses phase calculations at certain times, and the 160 MHz baseband synchronization calculation compares the digital time output to a reference value corresponding to the 160 MHz baseband period. The output of the 160 MHz baseband synchronization calculation (integrated time output enable) is used to determine the appropriate time to read the integrated time signal 210. The offset digital time output calculation 207 subtracts the carrier period offset from the digital time output. The offset digital time output is scaled by the scaling calculation 208. The scaled digital time signal is accumulated by the accumulator circuitry 209. The integrated time signal 210 is read at the appropriate time based on the integrated time output enable.
FIG. 3 is the block diagram of an example coarse measurement circuit. The coarse estimate starts with a ring oscillator. FIG. 3 is an example embodiment where the ring oscillator contains nine inverting elements. Noting the inverse relationship between frequency and time, the ring oscillator's oscillation frequency is:
$f_{RO} = \frac{1}{2 * 9 * t_{delay, element}},$
where t_{delay element}is the delay of one of the nine elements of the ring oscillator.
A modulated signal with a first and second rising edge is received at the input node 335. The first and second rising edge signals are elements of the modulated signal. At each rising edge, the TDC circuit latches the output values of each element forming a ring oscillator. Each element in the ring oscillator outputs an inverted version of its input signal. When the input changes state, it takes time for the output to reflect that change. The location of the propagation edge in the ring oscillator is the inverter stage where the input and output are in the process of moving to opposite states. The system counts the number of complete oscillations of the ring and combines it with the present state of the ring oscillator to calculate a coarse estimate of the period of the modulated signal. One example method to determine generally complete oscillations of the ring is to increment a counter each time a particular inverter changes state. This specification discusses in later sections both determination of complete oscillations of the ring and calculation of a coarse estimate. The resolution of the coarse estimate for one example embodiment is the length of delay of an inverter stage because the coarse estimate circuit does not probe into the internal circuit of the inverter.
Choosing the delay for each element of the ring oscillator to be a power of 2 times the fine TDC resolution may reduce the number of digital logic components used to combine the coarse and fine measurements. Minimizing the fine TDC's range may decrease power consumption. The delay of each element of the ring oscillator also sets the minimum range of the fine TDC. The fine TDC typically consumes more power than the coarse TDC, though for some embodiments, the fine TDC may consume less power than the coarse TDC. Picking a larger delay for each element in the ring oscillator may reduce the number of ring oscillator stages. Using a lower oscillation frequency may reduce power consumption. Also, picking a lower oscillation frequency allows the coarse TDC control logic to settle earlier in the ring oscillator cycle. Limiting the number of elements may reduce logic complexity and save circuit board layout space.
For one example receiver, these constraints and other factors (for example, cost and availability) led to a choice of T_{delay element}equal to 2⁵*5 ps, which equals 32*5 ps or 160 ps. Hence, the frequency of the ring oscillator (f_RO) became 347.222 MHz.
FIG. 3's example embodiment connects the output of each ring oscillator inverter 336 to 344 into a D-flip-flop 320 to 328. The circuit uses the D-flip-flop outputs to store the state of each stage of the ring oscillator when the modulated signal has a rising edge. The circuit uses as the pulse-propagating inverter the inverter having a non-inverted latched output value. Depending on whether the ring oscillator is in the first half of an oscillation or the second half, the inverter of the ring's propagation stage may have its input and output both low or both high.
The example receiver circuit uses three counters 313 to 315 to record complete oscillations of the ring. Each of these counters connects to the output of a different stage in the ring. Because the rising edge of the modulated signal is asynchronous to the ring oscillator, the rising edge may arrive at any moment. Such an edge may occur at the same moment a ring oscillator stage counter updates. Using three counters makes sure a counter not in the process of updating will have enough settle time before probing it. One example embodiment uses the counter of a desired stage within the ring and two back-up counters two stages before and two stages after the desired measurement stage. Using counters positioned two delays apart allows the system to use stage outputs that will be in the same state after the propagation edge passes through both stages. Such a configuration ensures that at least two of the counters will be in the same state. The logic circuit for an example receiver picks which counter to use based on the location of the ring oscillator's propagation edge signal. If the propagation edge of the ring oscillator is currently at the same position as the desired counter, the logic uses one of the other two counters. Another example method may use a counter's value as the number of complete oscillations of the ring oscillator if it matches at least one other counter. Yet another example method may use a desired counter unless the propagation edge of the ring oscillator is at the same location of the desired counter or one position prior, in which case the system may use the back-up counter.
One embodiment may use two counters to count the number of complete oscillations of the ring oscillator. For this embodiment, a first counter is incremented when an output of a first inverter of the ring oscillator changes state. Likewise, a second counter is incremented when an output of a second inverter of the ring oscillator changes state. The circuit selects a count value from either the first or second counter based on the location of the pulse-propagating inverter in relation to the first and second inverters.
Using the position of the edge inside the ring oscillator, the system decides which of the three counters to use. For an example receiver, the counter at O1 (oscillator 1) has a count one more than the other two because its count is incremented as soon as the ring oscillator is enabled. If the edge is in the second half of the oscillation ring, the system may use the O1 counter 315 because the O1 counter has settled correctly. If the edge is in the first half of the oscillation ring, the system may use the O6 counter because the O6 counter has settled correctly. An exception occurs when the edge starts another oscillation and its position is 0. That position may be considered the first half of the oscillation, but sometimes the advanced counter (O6) 313 lacks enough time to settle. In those situations, the system selects the delayed counter (O1), but the +1 count may not be removed. Other embodiments may use different stage counters without changing the general principles.
Using ongoing counters avoids resetting the circuit after each coarse measurement. Each time a measurement is made, there is an error. Embodiments that accumulate the results in subsequent signal processing may accumulate those errors over a long time may become a large error and too big for the system to handle. Using a ring oscillator with ongoing counters allows the errors to cancel each other over a long period of time. The measurement error connects back directly into the system, and each new measurement remains within the resolution boundaries.
Generating input signals for the fine measurement takes time for the control logic to read and process the state of the ring oscillator. When the modulated signal arrives with a rising edge, an example receiver changes the D-flip-flop outputs to match the output signal for each stage of the ring oscillator. A signal corresponding to a received modulated signal also goes through delay elements 329 to 334 corresponding to the circuit's processing time for determining the location of the propagating edge in the ring oscillator circuit. The signal corresponding to the modulated signal goes through six inverters 329 to 334 that correspond to the delay of six stages in the ring oscillator. The fine measurement circuit uses as its fine measurement start signal the modulated signal delayed through six inverters (329 to 334), a multiplexer 318, and associated signaling components (304, 306, and 308). For the fine measurement stop signal, the receiver uses the ring oscillator inverter output signal for six stages past the location of the propagation edge. The fine measurement circuit uses a multiplexer 319 to pick the appropriate ring oscillator inverter stage output signal for the fine measurement stop signal. The fine measurement stop signal propagates through a set of signaling components (305, 307, and 309) similar to the fine measurement start signal. The fine resolution measurement calculates the difference between the fine measurement start and stop signals.
In one embodiment, the fine measurement start signal for a Vernier comparator circuit is the rising edge of the modulated signal. The fine measurement stop signal is selected to provide a delayed coarse measurement signal to a Vernier comparator circuit using a control logic circuit and a multiplexer. In one embodiment, the control logic circuit controls the multiplexer to select a comparator located a predetermined number of delay elements past the pulse-propagating inverter. In one embodiment, initiating the Vernier comparator circuit using the rising edge of the delayed coarse measurement signal comprises delaying the rising edge signal by using a multiplexer and a predetermined number of delay elements.
For example, if the ring oscillator state corresponds to the propagation edge being inside stage one, using control logic 303, a delay 316, a NAND gate 317, and a multiplexer 319, the circuit selects the ring oscillator element corresponding to stage seven (six stages later). The output signal of multiplexer 319 is the fine measurement stop signal 302. The circuit also delays the coarse measurement start signal six stages to create the fine measurement start signal 301. An example receiver delays the modulated signal six delay stages to put the fine measurement start signal 301 in the proper time frame for use with the fine measurement stop signal 302. Both signals go through matched components prior to propagating through the fine measurement circuit. For one example receiver, those components are a multiplexer (318 and 319), an XOR gate (306 and 307), a delay element (304 and 305), and a D-flip-flop (308 and 309), as shown in FIG. 3. The delayed coarse measurement signal is processed by a delay element and an XOR gate to generate a trigger upon either a rising edge or a falling edge of the delayed coarse measurement signal. The delay element (304 and 305) and the XOR gate (306 and 307) create short pulses for the fine measurement start and stop signals. The short pulses connect into the clock signals of D-flip-flops (308 and 309). The D-flip-flops output high signals as long as the associated enable signal is high and reset signal is low. Hence, the fine measurement start and stop signals 301 and 302 are edge signals.
FIG. 4 is a graphical example of how the fine measurement two-dimensional Vernier works. The system uses the two-dimensional Vernier circuit to estimate the error of the coarse measurement. It uses two sets of delay lines: one fast delay line and one slow delay line. One embodiment uses a set of one or more inverters 401 to 424 for each of these delay lines. The fine measurement start signal progresses through the slow line, while the fine measurement stop signal travels through the fast line. For an example receiver, a matrix of SR latches compares the delay line intersections of interest. For one embodiment, the matrix's size is equal to the number of inverters in the fast delay line times the number of inverters in the slow delay line. Using an SR latch as the arbiter, each fast line inverter output is connected to the S input for a row of SR latches in the matrix. Each slow line inverter output is connected to the R input for a column of SR latches in the matrix. Each SR latch outputs a high signal if the S input goes high while the R input stays low. When no edge is propagating through the delay lines, all delay cell outputs stay low, and all arbiter outputs remain high. This configuration means that the output of the arbiter goes high when the associated fast line pulse arrives at the arbiter before the associated slow line pulse. The fine TDC circuit detects this condition where the fast line pulse arrives first. When the second rising edge reaches the arbiter, its output is on hold and the result is not affected. Resetting the delay lines also resets the arbiters.
In one embodiment, calculation of the fine resolution measurement of the coarse measurement error comprises propagating a rising edge of the modulated signal (fine measurement start signal) through a first line of delay elements. The delayed coarse measurement signal (fine measurement stop signal) propagates through a second line of delay elements, where the first line of delay elements is slower than the second line of delay elements. A matrix of arbiters form a two-dimensional Vernier structure. Using the matrix of arbiters, a fine measurement point is determined to be a smallest arbiter location at which the fine measurement stop signal arrives at the arbiter location before the fine measurement start signal. An arbiter location identifier is calculated as the time difference for a signal to propagate through the corresponding portion of the first line of delay elements and the corresponding portion of the second line of delay elements. A first arbiter location is determined to be smaller than a second arbiter location if the first arbiter's time difference is smaller than the second arbiter's time difference. One embodiment outputs the fine resolution measurement as the fine measurement point.
One example receiver uses a two-dimensional Vernier structure 400 as shown in FIG. 4. The receiver's two-dimensional Vernier structure uses twelve slow delay elements 402, 404, 406, 408, 410, 412, 414, 416, 418, 420, 422 and 424 (each with 50 ps of delay), nine fast delay elements 401, 403, 405, 407, 409, 411, 413, 415, and 417 (each with 45 ps of delay), five Vernier lines, and forty-nine arbiters.
The fast delay line uses inverters with a shorter delay than the inverters used in the slow delay line. For one example receiver, the fast delay line uses inverters 401, 403, 405, 407, 409, 411, 413, 415, and 417 with a delay of 45 ps. The slow delay line uses inverters 402, 404, 406, 408, 410, 412, 414, 416, 418, 420, 422 and 424 with a delay of 50 ps. At each intersection of interest in FIG. 4, there is a value written as a multiple of R. The letter “R” represents the difference in delay for one delay element from the fast delay line and one delay element from the slow delay line. For one example receiver, the difference between these values is 5 ps (50 ps minus 45 ps). Hence, for the receiver, R is 5 ps. The values shown at the intersections of interest range from zero to 48 R. Replacing the R with a value of 5 ps, FIG. 5's two-dimensional Vernier structure may resolve measurement errors from zero (OR) to 240 ps (48 R).
Consider the intersection near the center of FIG. 4 that says “24 R.” The inputs to the SR latch that correlates to this intersection travel through six elements of delay on the slow delay line and four elements of delay on the fast delay line. For one example receiver embodiment, the slow delay line input experiences a delay of 6*50 ps=300 ps. The fast delay line input experiences a delay of 4*45 ps=180 ps. The difference between these values is 120 ps. Dividing this value by 5 ps (the value for R), produces a value of 24 R. One calculates the values shown at the intersections of interest in FIG. 4 using calculations similar to the ones shown in this example.
At each intersection shown with an “R” label on FIG. 4, there is an arbiter circuit to determine if the signal from the slow delay or the signal from the fast delay line propagated through the location first. FIG. 5 is one embodiment of such an arbiter circuit. The fast delay line at an arbiter location connects to an S input, which connects to NAND gate 501. The slow delay line at an arbiter location connects to an R input, which connects to NAND gate 502. The output of NAND gate 501 connects as an input to NAND gate 502 and as input to amplifier 503. Likewise, the output of NAND gate 502 is an input to NAND gate 501. The output of the amplifier is a signal Q.
When S is the low state (“0”) and R is in the high state (“1”), Q is in the high state (“1”). When both S and R are in the high state, Q retains the same value it had previously. If S is high and R is low, Q is in the low state. With no rising edge propagating through either the fast or slow delay lines, both S and R equal 0, so Q starts as a 1. If the rising edge of the slow delay line arrives first at the arbiter location, the arbiter output Q stays as a 1. If the rising edge of the fast delay arrives first at the arbiter location, the arbiter output Q changes to a 0.
To further explain how the two-dimensional Vernier structure works, consider an example where the edges for the fine measurement start and stop signals differ by 194 ps. For the 38 R intersection, the fine measurement start signal going through the slow delay line travels through eleven slow delay elements, which corresponds to a delay of 550 ps (11*50 ps). The fine measurement stop signal going through the fast delay line travels through eight fast delay elements, which corresponds to a delay of 360 ps (8*45 ps). The difference in these two lines corresponds to 190 ps (550 ps minus 360 ps). The slow delay line propagation edge beats the fast delay line propagation edge to the input of the arbiter (an SR latch for an example receiver), and the arbiter's output for 38 R remains high.
For the 39 R intersection, the fine measurement start signal going through the slow delay line travels through eleven slow delay elements, which corresponds to a delay of 600 ps (12*50 ps). The fine measurement stop signal going through the fast delay line travels through nine fast delay elements, which corresponds to a delay of 405 ps (9*45 ps). The difference in these two lines corresponds to 195 ps (600 ps minus 405 ps). The fast delay line propagation edge arrives prior to the slow delay line propagation edge at the input of the arbiter, and the arbiter's output for 39 R goes low. For the 40 R and higher intersections, the fast delay line propagation edge arrives prior to the slow delay line propagation edge at the input of the arbiter, and each of those arbiter outputs also goes low.
An example arbiter circuit (shown in FIG. 5) is used at each arbiter location. A Vernier two-dimensional structure circuit compares each arbiter location output with a low state and stores the lowest difference location (lowest multiple of R) where the fast delay line propagation edge signal arrived at the corresponding arbiter input before the slow delay line propagation edge signal. The system uses this lowest difference amount as the fine measurement.
The fine TDC resets after each measurement. When the edge propagating into the slow delay line reaches the end of the line, a reset pulse is generated. The reset pulse brings the fine measurement start and stop signals low, which propagates along the slow and fast lines. At the same time, this operation resets the arbiters.
FIG. 6 is a block diagram of one embodiment of digital logic used to reconstruct the period of the TDC input from the coarse and fine measurements. The example coarse TDC circuit uses three counter outputs (345, 346, and 347) that connect as three counter signals 612 to three D-flip-flops 601. The output of each D-flip-flop connects to the counter value logic block 604. The counter value logic block outputs a coarse measurement and connects it to a D-flip-flop 605. The D-flip-flop's output connects to the coarse measurement logic block 607. The D-flip-flops create pipelined stages to provide for additional processing time, in other embodiments, pipeline stages are not used.
Nine D-flip flop outputs, stored as a nine-bit ring oscillator register value 613, hold the state of each stage in the ring oscillator. The nine-bit ring oscillator outputs register 613 connects to a D-flip-flop 602. The output of the D-flip-flop 602 connects to the edge position logic block 603. The edge position logic block calculates the location of the propagating edge in the ring oscillator circuit. The output of the edge position logic block connects to the counter value logic block 604 and to a D-flip-flop 606. The output of the D-flip-flop connects to the logic block 607.
The coarse measurement logic block 607 calculates the coarse measurement of the input period 614 and uses this value as the input to D-flip-flop 608. The output of the D-flip-flop is used as an input to the overall measurement logic block 610. The fine TDC measurement 615 is the input to D-flip-flop 609. The output of the D-flip-flop is an input to the overall measurement logic block 610 that calculates the overall measurement of the input period. The overall measurement of the input period is used as an input to a D-flip-flop 611. The output of the D-flip-flop is the digital time measurement 616.
Using the position of the edge and the correct counter output, the coarse measurement is obtained. For one example receiver, the ring oscillator contains 9 stages and 18 delay elements in a full oscillation cycle. Hence, the coarse TDC measurement is calculated as:
T _coarse=18*C _final +D _final.
The coarse TDC measurement is calculated as the time of a measured amount of complete oscillations of the ring (18*C_final) plus a current propagation time (D_final).
The resolution of the coarse TDC is 160 ps, which is 32 times the fine TDC resolution. Hence, the digital time measurement is:
TDC _OUTPUT=32*T _coarse −T _fine+Corr.
A digital time measurement (TDC_OUTPUT) is calculated as a coarse measurement count ratio (32) times the coarse measurement time (T_coarse) minus the fine resolution measurement (T_fine) plus a calibration correction factor (Corr). The calibration correction factor depends on which edge the coarse TDC used to compute its value. Rising and falling edges have slightly different delays within the several gates, so a correction is applied to obtain an accurate result.
The predetermined number of delay elements equals the maximum coarse measurement logic processing time divided by a unit delay time of a ring oscillator delay element. For one example receiver, the predetermined number of delay elements is six. The multiplexer input select value equals the pulse-propagating inverter's stage position plus the predetermined number of delay elements. The multiplexer input select value is decremented by the total number of ring oscillator elements if the multiplexer input select value exceeds the total number of ring oscillator inverters. The coarse measurement count ratio is the unit delay time divided by the difference of a Vernier slow delay element and a Vernier fast delay element. For one example receiver, the coarse to fine measurement count ratio is
$\frac{160 ps}{(50 ps - 45 ps)} = 32.$
FIG. 7 is a functional block diagram that shows the circuit blocks for calculation of the phase of the modulated signal based on the digital time measurement. The output of FIG. 6 for one example receiver is a 13-bit digital time measurement. This value serves as the input for FIG. 7. The first circuit block 701, 702, 703, 704, 705, 706, and 707 (digital time difference circuit) subtracts the previous digital time measurement from the present digital time measurement to calculate a period difference value. Circuit block 703 shows this calculation. If the previous digital time measurement exceeds the present digital time measurement, the digital time measurement wrapped past the maximum value. In such a situation, the circuit adds a counter wrapping value to the present digital time measurement and subtracts the previous digital time measurement. Circuit blocks 702, 704, and 705 show these calculations. The circuit in FIG. 7 delays one stage period the output of this difference calculation via, for example, a D-Flip-flop 707. For one example circuit, logic components 701 to 707 perform these comparisons and delay functions. For one example receiver, the wrap-over value is 4608. To calculate this limit, take the coarse counters' 8 possible values (2³) times the 18 ring-oscillator stages times the coarse to fine measurement resolution ratio, 32. The result of this first circuit block is a period difference signal that is a difference in successive digital time measurements.
The second circuit block 708, 709, 710, 711, 712, 713, and 714 (baseband output time circuit) handles the baseband signal's 160 MHz read rate. The circuit block uses a feedback loop to add successive outputs of the first circuit block. If the successive additions exceed the output time threshold (1250), the output time threshold is subtracted from the feedback value and an output write signal goes high two stage periods later. The receiver uses the digital time output to reconstruct a 160 MHz timeline. The output time threshold (1250) corresponds to a 160 MHz read period with a 5 ps digital time output resolution value
$(\frac{1}{160 MHz * 5 ps}) .$
Every time the sum of consecutive periods exceeds 1250 (output time threshold), the baseband circuit samples the value. When such a condition occurs, the integrated time output enable 722 goes high two stages later, indicating an output time to write the phase of the modulated signal, the integrated time signal 723.
The third circuit block 715, 716, 717, 718, 719, 720, and 721 of FIG. 7 (offset digital time output circuit) handles subtracting a carrier period offset T from the first circuit block's output (digital time output) and scaling the result. The carrier period offset circuit subtracts off the carrier period offset for the offset digital time output calculation. The carrier period offset, T, is calculated as (f_cis the carrier frequency):
$T = \frac{8}{f_{c} * T D C_{resolution}}$
The scaling circuit scales the offset digital time output to the desired level. The coarse TDC circuit accumulates the scaled digital time signal so that its error stays within the fine TDC measurement resolution. The scaling factor is calculated as:
Scaling factor=1024*f _c *TDC _resolution.
The factor 1024 is because the phase 2π is mapped to 10 bits. An accumulating circuit accumulates a value as the final output of the phase demodulator circuit. The offset digital time output calculation and post-processing delay may be performed by circuit components 715 and 716. Scaling and post-processing delay may be performed by circuit components 717, 718, and 719. Accumulation of the scaled digital time signal and post-processing delay may be performed by circuit components 720 and 721 to output the integrated time signal 723.
One example receiver embodiment uses a FIFO to handle the baseband signal's 160 MHz read clock being asynchronous with the TDC circuit's output write clock of up to 400 MHz. The TDC circuit writes successive output values to a FIFO using a clock (TDC input signal) of up to 400 MHz at a rate set by the integrated time output enable signal 722, while the baseband circuit reads values at a rate of 160 MHz.
FIG. 8 is a method for calculating the phase of a modulated signal. The TDC method 800 via a reception process 802 receives a signal, which in some embodiments is a frequency division output signal. A course measurement process 804 uses the modulated signal to calculate a coarse measurement for the time to digital value conversion. The coarse measurement process 804 uses a ring oscillator of the TDC circuit to obtain a coarse measurement for the period between a first and a second rising edge of the modulated signal. A fine measurement process 806 calculates a fine measurement of the error in the coarse measurement. The fine measurement process 806 uses a Vernier comparator circuit of the TDC circuit to obtain a fine resolution measurement of a coarse measurement error. A combination process 808 combines the coarse and fine measurements to obtain a digital time measurement. A phase determination process 810 uses the digital time measurement to obtain the phase of the modulated signal.

Claims

1. A method comprising:

receiving at a receive time-to-digital conversion (TDC) circuit a modulated signal; using a ring oscillator of the TDC circuit to obtain a coarse measurement of a rising edge of the modulated signal;

using a 2D Vernier comparator circuit of the TDC circuit to obtain a fine resolution measurement of a coarse measurement error representing a difference between a delayed rising edge signal and a delayed coarse measurement signal;

using the coarse measurement and the fine resolution measurement to obtain a digital time measurement; and,

determining a phase of the modulated signal based on the digital time measurement.

2. The method of claim 1 wherein obtaining the coarse measurement comprises using the rising edge of the modulated signal to latch output values of each of a plurality of inverters in the ring oscillator.

3. The method of claim 2 wherein obtaining the coarse measurement further comprises identifying a pulse-propagating inverter as an inverter having a non-inverted latched output value.

4. The method of claim 3 further comprising counting a number of complete oscillations of the ring oscillator.

5. The method of claim 4 wherein counting the number of complete oscillations of the ring oscillator comprises:

incrementing a first counter when an output of a first inverter of the ring oscillator changes state;

incrementing a second counter when an output of a second inverter of the ring oscillator changes state; and

selecting a count value from either the first counter or the second counter based upon a location of the pulse-propagating inverter in relation to the first inverter and the second inverter.

6. The method of claim 1 further comprising:

initiating the Vernier comparator circuit using the rising edge of the modulated signal; and

selecting a stop input for providing a delayed coarse measurement signal to the Vernier comparator circuit using a control logic circuit and a first multiplexer.

7. The method of claim 6 wherein the control logic circuit controls the multiplexer to select a comparator located a predetermined number of delay elements past a pulse-propagating inverter.

8. The method of claim 6 wherein the delayed coarse measurement signal is processed by a delay element and an exclusive OR gate to generate a trigger signal upon a rising edge of the delayed coarse measurement signal.

9. The method of claim 7 wherein initiating the Vernier comparator circuit using the rising edge of the modulated signal comprises delaying the rising edge of the modulated signal using a second multiplexer and a number of delay elements equal to the predetermined number of delay elements.

10. The method of claim 1 wherein calculating the fine resolution measurement of the coarse measurement error comprises:

propagating the rising edge of the modulated signal through a first line of delay elements;

propagating the delayed coarse measurement signal through a second line of delay elements, wherein the first line of delay elements is slower than the second line of delay elements;

determining a fine measurement point using a matrix of arbiters that is a smallest arbiter location in which the delayed coarse measurement signal propagating through the second line of delay elements arrives at the fine measurement point before the rising edge of the modulated signal propagating through the first line of delay elements; and

outputting the fine resolution measurement.

11. The method of claim 10 wherein calculating a digital time measurement comprises:

calculating a coarse measurement time as the time of a measured amount of complete oscillations of the ring plus a current propagation time; and

calculating a digital time measurement as a coarse measurement count ratio times the coarse measurement time minus the fine resolution measurement plus a calibration correction factor.

12. The method of claim 11 wherein calculating the phase of the modulated signal based on the digital time measurement comprises:

calculating a digital time output as a difference in successive digital time measurements;

determining an output time to write the phase of the modulated signal; calculating a offset digital time output;

scaling the offset digital time output to calculate a scaled digital time signal; and accumulating the scaled digital time signal.

13. The method of claim 12 wherein calculating the digital time output comprises:

subtracting a first digital time measurement from a second digital time measurement to calculate a period difference value; and

adding a counter wrapping value to the period difference value when the first digital time measurement is greater than the second digital time measurement.

14. The method of claim 12 wherein determining the output time to write the phase of the modulated signal comprises enabling an output write signal when the digital time output exceeds an output time threshold.

15. The method of claim 12 wherein calculating an offset digital time output comprises subtracting a carrier period offset from the digital time output.

16. An apparatus comprising:

a coarse measurement circuit configured to calculate a coarse measurement of a period of a modulated signal represented by a first rising edge signal and a second rising edge signal, wherein the first rising edge signal and the second rising edge signal are elements of the modulated signal;

a fine measurement circuit configured to calculate a fine resolution measurement of a coarse measurement error representing a difference between the second rising edge signal and a subsequent coarse measurement signal; and

a phase calculation circuit configured to calculate the phase of the modulated signal, wherein the phase calculation circuit includes:

an offset digital time output circuit to subtract a carrier period offset from the digital time output;

a scaling circuit to scale a offset digital time output; and

an accumulating circuit to accumulate an output signal from the scaling circuit.

17. The apparatus of claim 16 wherein the coarse measurement circuit comprises: a first set of one or more inverters connected to form a ring of inverters;

one or more flip-flops connected to each inverter output in the ring of inverters;

one or more counters connected to one or more of inverter outputs from the first set of inverters;

a first multiplexer which has inputs connected to the inverter outputs from the first set of one or more inverters;

a first exclusive-OR logic gate input connected to the first multiplexer output;

a second set of one or more inverters connected in succession in which the output of the last inverter in the second set of one or more inverters is connected to all inputs of a second multiplexer; and

a second exclusive-OR logic gate connected to the second multiplexer output.

18. The apparatus of claim 16 wherein the fine measurement circuit comprises: a set of one or more inverters forming a first line of delay elements;

a set of one or more inverters forming a second line of delay elements, wherein the first line of delay elements is slower than the second line of delay elements;

a matrix of latches equal to the number of inverters in the first line of delay elements times the number of inverters in the second line of delay elements;

a set of connections that connect each inverter output in the first line of delay elements to each first latch input in a column of the matrix of latches; and

a set of connections that connect each inverter output in the second line of delay elements to each second latch input in a row of the matrix of latches.

19. The apparatus of claim 16 wherein the phase calculation circuit further comprises:

a digital time difference circuit to calculate a difference in successive period measurements; and

a baseband output time circuit to calculate when to write output data.