US20180019337A1 - Method and structure of forming self-aligned rmg gate for vfet - Google Patents
Method and structure of forming self-aligned rmg gate for vfet Download PDFInfo
- Publication number
- US20180019337A1 US20180019337A1 US15/683,228 US201715683228A US2018019337A1 US 20180019337 A1 US20180019337 A1 US 20180019337A1 US 201715683228 A US201715683228 A US 201715683228A US 2018019337 A1 US2018019337 A1 US 2018019337A1
- Authority
- US
- United States
- Prior art keywords
- fin
- semiconductor structure
- intermediate semiconductor
- spacer
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000000034 method Methods 0.000 title description 39
- 125000006850 spacer group Chemical group 0.000 claims abstract description 55
- 239000004065 semiconductor Substances 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 7
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 7
- 239000010703 silicon Substances 0.000 claims abstract description 7
- 239000000463 material Substances 0.000 claims description 122
- 229910052751 metal Inorganic materials 0.000 claims description 28
- 239000002184 metal Substances 0.000 claims description 28
- 150000004767 nitrides Chemical class 0.000 claims description 12
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 8
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 4
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 4
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 4
- 229910001233 yttria-stabilized zirconia Inorganic materials 0.000 claims description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 2
- 229910010038 TiAl Inorganic materials 0.000 claims description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 2
- 239000010941 cobalt Substances 0.000 claims description 2
- 229910017052 cobalt Inorganic materials 0.000 claims description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 2
- 229910052593 corundum Inorganic materials 0.000 claims description 2
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 2
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 claims description 2
- 229910000311 lanthanide oxide Inorganic materials 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims description 2
- 229910052698 phosphorus Inorganic materials 0.000 claims description 2
- 239000011574 phosphorus Substances 0.000 claims description 2
- 150000004760 silicates Chemical class 0.000 claims description 2
- 239000002210 silicon-based material Substances 0.000 claims description 2
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 claims description 2
- 229910052718 tin Inorganic materials 0.000 claims description 2
- 239000010936 titanium Substances 0.000 claims description 2
- 229910052719 titanium Inorganic materials 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 2
- 229910004166 TaN Inorganic materials 0.000 claims 1
- 229910034327 TiC Inorganic materials 0.000 claims 1
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 7
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 1
- 229920005591 polysilicon Polymers 0.000 abstract 1
- 238000000151 deposition Methods 0.000 description 23
- 230000008021 deposition Effects 0.000 description 11
- 230000005669 field effect Effects 0.000 description 10
- 230000006870 function Effects 0.000 description 10
- 238000005229 chemical vapour deposition Methods 0.000 description 9
- 238000000231 atomic layer deposition Methods 0.000 description 8
- 238000005530 etching Methods 0.000 description 8
- 230000008569 process Effects 0.000 description 7
- 238000005240 physical vapour deposition Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 4
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910021529 ammonia Inorganic materials 0.000 description 2
- 238000005234 chemical deposition Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 description 2
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000000313 electron-beam-induced deposition Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- 238000007737 ion beam deposition Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- -1 silicon nitride Chemical class 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 125000003698 tetramethyl group Chemical group [H]C([H])([H])* 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823885—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
Definitions
- This invention relates to vertical field effect transistors (VFET) and more particularly to forming self-aligned replacement metal gates therefor.
- VFET vertical field effect transistors
- Gate first fabrication techniques refer to a situation where the gate is patterned prior to the annealing step used to activate the source and drain.
- gate last techniques a dummy gate is used to occupy the gate space during the annealing process and a replacement metal gate is inserted into the dummy gate area after the anneal.
- the gate last technique and the use of replacement metal gates avoids the difficult thermal issues normally encountered with use of the gate first technique.
- a method of providing a fin structure includes a fin with sacrificial material above and adjacent the fin, with the fin structure being above a substrate adjacent a source or drain.
- the method includes removing a first portion of the sacrificial material above the fin to form an opening within the sacrificial material on top of the fin, forming a top source or drain within the opening on top of the fin, removing a second portion of the sacrificial material adjacent the top source or drain, depositing a spacer above and adjacent the top source or drain, depositing a gate material above the spacer and below the spacer to the sides of the fin, and removing the gate material above the bottom portion of the spacer to form a self aligned gate around the fin and a vertical field effect transistor.
- the sacrificial material includes a first sacrificial material.
- a top portion of the first sacrificial material located above and adjacent said fin structure is removed to allow a remaining portion of the first sacrificial material to remain adjacent said fin.
- a second sacrificial material may be deposited above the remaining first sacrificial material so that the sacrificial material includes a first sacrificial material, the second sacrificial material, and a hard mask on the top of the fin.
- the first sacrificial material may be a thin oxide surrounding the fin structure and an amorphous silicon deposited on top of the thin oxide.
- the second sacrificial material may be an oxide.
- the removing of a first portion of the sacrificial material above the fin to form an opening within the sacrificial material on top of the fin may include removing the hard mask above or on top of said fin.
- the self-aligned contact (SAC) cap may be deposited above the top source or drain within the oxide.
- the method may also include removing the oxide prior to depositing a spacer above and adjacent the top source or drain. Also, removing a third portion of the sacrificial material adjacent the fin may include removing the amorphous silicon.
- the method may further include removing the thin oxide, which may be a silicon oxide.
- the method may also include providing a bottom spacer above the source or drain and substrate adjacent the fin. And, may include depositing a high K dielectric material on the bottom spacer, where the spacer and the fin form an intermediate structure, and annealing the intermediate structure.
- the method may also include depositing a work function metal as part of the gate material and a metal over the work function metal as part of the gate material.
- Removing the gate material above the bottom portion of the spacer may include removing the work function metal and the metal.
- the method may further include removing annealed high K material above the spacer above and adjacent the top source or drain, depositing a second lithography stack over the barrier stack, performing a second lithography to pattern the at least one via opening, and etching to form at least one via opening.
- the method may also include providing multiple fin structures, multiple top sources or drains to form multiple vertical field effect transistors.
- the fin structures may be parallel spaced with at least two vertical field effect transistors spaced apart and aligned along lengths thereof and forming at least one additional gate connecting aligned on parallel spaced vertical field effect transistors.
- the method includes providing a fin structure having a fin with a hard mask on top of the fin.
- the fin structure is above a substrate adjacent a source or drain.
- the method includes depositing one or more sacrificial materials above and along sides of the fin structure, removing a top portion of the one or more sacrificial materials above a top of the fin to form an opening within the one or more sacrificial materials, forming a top source or drain within the opening on the top of said fin, removing a portion of the one or more sacrificial materials above and adjacent the top source or drain, depositing a spacer above the top source or drain, removing additional portions of the one or more sacrificial materials surrounding sides of the fin, depositing gate material above the spacer and below the spacer to the sides of the fin, and removing the gate material above the bottom portion of the spacer to form a self aligned gate around the fin and vertical field effort transistor.
- the invention in another aspect of the invention, includes an intermediate semiconductor structure having a fin structure.
- the fin structure includes a fin above a substrate adjacent a bottom source or drain, a top source or drain located on the top of the fin, a spacer located above and surrounding the top source or drain and adjacent a top portion of the fin, a self-aligned gate structure located below the top spacer and above a bottom spacer located above said substrate and source or drain, and one or more work function layers located between the bottom spacer and side walls of the fin and top spacer.
- FIG. 1A depicts a cross sectional view of a fin of negative channel field-effect transistor device (nFET) including hardmask material which may be situated above and or included adjacent as a bottom spacer to the fin and can include a bottom source drain region and insulator region;
- nFET negative channel field-effect transistor device
- FIG. 1B depicts a cross sectional view of a fin of a positive channel field-effect transistor device (pFET) including hardmask material which may be situated above and or included adjacent as a bottom to the fin and can include a bottom source drain region and insulator region;
- pFET positive channel field-effect transistor device
- FIG. 2A depicts a cross sectional view of the structure of FIG. 1A after application of a first sacrificial material which may be in the form of a thin oxide surrounding said fin structure, and a second sacrificial material which may be in the form of an amorphous silicon layer deposed upon the first sacrificial material;
- FIG. 2B depicts a cross sectional view of the structure of FIG. 1B after application of a first sacrificial material which may be in the form of a thin oxide surrounding said fin structure, and a second sacrificial material which may be in the form of an amorphous silicon layer deposed upon the first sacrificial material;
- FIG. 3A depicts a cross sectional view of the structure of FIG. 2A after removing of a first portion of the first sacrificial material a first portion of the second sacrificial material thereby exposing the hardmask material located above the fin;
- FIG. 3B depicts a cross sectional view of the structure of FIG. 2B after removing of a first portion of the first sacrificial material a first portion of the second sacrificial material thereby exposing the hardmask material located above the fin;
- FIG. 4A depicts a cross sectional view of the structure of FIG. 3A after the recessing of a second portion of the first sacrificial further exposing the second sacrificial material;
- FIG. 4B depicts a cross sectional view of the structure of FIG. 3B after the recessing of a second portion of the first sacrificial further exposing the second sacrificial material;
- FIG. 5A depicts a cross sectional view of the structure of FIG. 4A after application of a third sacrificial material which may include an oxide;
- FIG. 5B depicts a cross sectional view of the structure of FIG. 4B after application of a third sacrificial material which may include an oxide;
- FIG. 6A depicts a cross sectional view of the structure of FIG. 5A after removal of the exposed hardmask material, and formation of an upper source drain junction;
- FIG. 6B depicts a cross sectional view of the structure of FIG. 5B after removal of the exposed hardmask material, and deposition of an upper source drain junction;
- FIG. 7A depicts a cross sectional view of the structure of FIG. 6A after application of a cap, which may be composed of a self aligned contact nitride above the upper source drain junction;
- FIG. 7B depicts a cross sectional view of the structure of FIG. 6B after application of a cap, which may be composed of a self aligned contact nitride above the upper source drain junction;
- FIG. 8A depicts a cross sectional view of the structure of FIG. 7A after removal of the third sacrificial material
- FIG. 8B depicts a cross sectional view of the structure of FIG. 7B after removal of the third sacrificial material
- FIG. 9A depicts a cross sectional view of the structure of FIG. 8A after adding a top spacer by means which may include deposition consisting of a material that may include SiN;
- FIG. 9B depicts a cross sectional view of the structure of FIG. 8B after adding a top spacer by means which may include deposition consisting of a material that may include SiN;
- FIG. 10A depicts a cross sectional view of the structure of FIG. 9A after removal of the second sacrificial material
- FIG. 10B depicts a cross sectional view of the structure of FIG. 9B after removal of the second sacrificial material
- FIG. 11A depicts a cross sectional view of the structure of FIG. 10A after removal of the first sacrificial material
- FIG. 11B depicts a cross sectional view of the structure of FIG. 10B after removal of the first sacrificial material
- FIG. 12A depicts a cross sectional view of the structure of FIG. 11A after application of a material layer through means such as chemical deposition wherein the material contains the property of having a high dielectric constant;
- FIG. 12B depicts a cross sectional view of the structure of FIG. 11B after application of a material layer through means such as chemical deposition wherein the material contains the property of having a high dielectric constant;
- FIG. 13A depicts a cross sectional view of the structure of FIG. 12A after deposition of a work function metal layer
- FIG. 13B depicts a cross sectional view of the structure of FIG. 12B after deposition of a work function metal layer
- FIG. 14A depicts a cross sectional view of the structure of FIG. 13A after deposition of a gate metal
- FIG. 14B depicts a cross sectional view of the structure of FIG. 13B after deposition of a gate metal
- FIG. 15A depicts a cross sectional view of the structure of FIG. 14A after removal of the gate metal except for the portions located under the top spacer and above the bottom spacer;
- FIG. 15B depicts a cross sectional view of the structure of FIG. 14B after removal of the gate metal except for the portions located under the top spacer and above the bottom spacer;
- FIG. 16A depicts a cross sectional view of the structure of FIG. 15A after the high K dielectric layer is removed except for the portions located under the top spacer and above the bottom spacer;
- FIG. 16B depicts a cross sectional view of the structure of FIG. 15B after the high K dielectric layer is removed except for the portions located under the top spacer and above the bottom spacer.
- Approximating language may be applied to modify any quantitative representation that could permissibly vary without resulting in a change in the basic function to which it is related. Accordingly, a value modified by a term or terms, such as “about,” is not limited to the precise value specified. In some instances, the approximating language may correspond to the precision of an instrument for measuring the value.
- a method or device that “comprises,” “has,” “includes” or “contains” one or more steps or elements possesses those one or more steps or elements, but is not limited to possessing only those one or more steps or elements.
- a step of a method or an element of a device that “comprises,” “has,” “includes” or “contains” one or more features possesses those one or more features, but is not limited to possessing only those one or more features.
- a device or structure that is configured in a certain way is configured in at least that way, but may also be configured in ways that are not listed.
- the terms “may” and “may be” indicate a possibility of an occurrence within a set of circumstances; a possession of a specified property, characteristic or function; and/or qualify another verb by expressing one or more of an ability, capability, or possibility associated with the qualified verb. Accordingly, usage of “may” and “may be” indicates that a modified term is apparently appropriate, capable, or suitable for an indicated capacity, function, or usage, while taking into account that in some circumstances the modified term may sometimes not be appropriate, capable or suitable. For example, in some circumstances, an event or capacity can be expected, while in other circumstances the event or capacity cannot occur—this distinction is captured by the terms “may” and “may be.”
- depositing may include any now known or later developed techniques appropriate for the material to be deposited including but not limited to, for example: chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), semi-atmosphere CVD (SACVD) and high density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited reaction processing CVD (LRPCVD), metal-organic CVD (MOCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser assisted deposition, thermal oxidation, thermal nitridation, spin-on methods, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating, evaporation.
- CVD chemical vapor deposition
- LPCVD low-pressure CVD
- PECVD plasma-enhanced CVD
- SACVD semi-
- the following describes a method for manufacturing a fin structure, wherein this fin structure includes a fin with a sacrificial material above and/or adjacent to the fin.
- the fin structure also being above a substrate while being adjacent to a source or drain.
- the figures referenced are numbered and are labeled (A) and (B) to show the corresponding method for a negative channel field-effect transistor on the figures labeled with (A) and the corresponding method for a positive channel field-effect transistor on the figures labeled with (B).
- a n-type vertical FIN field-effect-transistor (n-VFINFET) is initially fabricated in a conventional manner.
- the structure includes hardmask material 12 which is situated above the vertical FIN channel, and a bottom spacer 16 , to a fin 14 and can include a bottom source/drain region 18 and a substrate 20 . There may also be an isolation region (not shown) between adjacent devices 10 if more than one device is fabricated.
- FIG. 1B a structure of a p-type VFINFET is fabricated in a conventional manner.
- the structure includes a hardmask material 12 , including but not limited to a nitride such as silicon nitride, which may be situated above and/or included adjacent a bottom spacer 16 (typically a nitride material) to a fin 14 and can include a bottom source/drain region 18 and an insulator region 20 .
- the n-VFINFET and p-VFINFET regions may be located on the same semiconductor wafer, for example in different, yet adjacent areas of a wafer separated by any distance that will not interfere with the operation of a VFET device.
- the fin 14 may include semiconductor materials, including but not limited to silicon, silicon germanium, and any III-V type materials.
- the bottom source/drain region 18 may include silicon, silicon germanium, or any other semiconductor material, and may be doped, often at high concentrations. The doping will vary for the device, but for an NFET it may be phosphorous doped and for a PFET it may be boron doped. Additionally, the source/drain region 18 in FIG. 1A may be different from the source/drain region 18 of FIG. 1B , and both may be doped differently.
- the substrate region 20 can include silicon, silicon germanium, and any type materials
- a first sacrificial material 34 and a second sacrificial material 36 are deposited onto the structure shown in FIG. 1A .
- the first sacrificial material 34 may be in the form of a thin oxide deposed on and surrounding the hardmask material 12 above the bottom spacer 16 , the fin 14 and the bottom spacer 16 itself.
- the second sacrificial material 36 may be an amorphous silicon layer and may be deposited over and surrounding the first sacrificial material 34 .
- the first sacrificial material 34 and second sacrificial material 36 are deposited onto the structure shown in FIG. 1A .
- the first sacrificial material 34 may be a thin oxide deposed on and surrounding the hardmask material 12 above the bottom spacer 16 , the fin 14 and the bottom spacer 16 itself.
- the second sacrificial material 36 which may be an amorphous silicon layer may be deposited over and surrounding said first sacrificial material 34 .
- First and Second sacrificial material 34 and 36 may be deposited, for instance, by atomic layer deposition (ALD), physical vapor deposition (PVD), or any other chemical vapor depositions (CVD) capable of applying thin films consistently.
- ALD atomic layer deposition
- PVD physical vapor deposition
- CVD chemical vapor depositions
- the structure of FIG. 2A is planarized by, for example, a chemical mechanical polishing (CMP) technique.
- CMP chemical mechanical polishing
- the first sacrificial material 34 and the second sacrificial material 36 is removed from a first portion 42 , i.e., the top of device 10 , exposing the top section of the hardmask material 12 .
- a portion of the second sacrificial material 36 , adjacent to hardmask 12 and a top portion of fin 14 is removed by, for example, etching using any wet or dry etch techniques to recess the second sacrificial material 36 below a top surface of device 10 .
- FIG. 3B illustrates the planarization of the structure of FIG. 2B by, for example, CMP.
- the first and second sacrificial material 34 and 36 is removed from a first portion 42 .
- a portion of the second sacrificial material 36 is removed by, for example, etching using any wet or dry etch techniques to recess the second sacrificial material 36 below a top surface of device 10 .
- a third sacrificial material 54 which may include an oxide material, is deposited by ALD, CVD, or PVD in some embodiments, in the region shown in FIG. 4A which has been etched to recess the second sacrificial material 36 .
- third sacrificial material 54 is similarly deposited on the positive channel.
- the remaining hardmask material 12 is removed by selective etching processes to expose the fin 14 .
- This can include any etch that is selective for a nitride material, and may include plasma etching.
- an upper source-drain 58 can be formed by selective epitaxy process, including but not limited to silicon and silicon germanium.
- the material and doping of upper source-drain 58 may be a different material for the n-VFINFET and p-VFINFET of FIGS. 6A and 6B .
- the n-VFINFET FIG. 6A
- the p-VFINFET FIG.
- a cap 62 is placed above the upper source-drain junction 58 .
- the cap 62 may be composed of a nitride, which will assist in subsequent self-aligned contact (SAC) etching to mask the upper source/drain junction 58 below.
- SAC self-aligned contact
- the hardmask material 12 is removed on the p-VFINFET area by selective etching, to expose the fin 14 . In its place an upper source-drain junction 58 can be formed.
- the nitride SAC cap 62 is also deposited above the upper source-drain junction 58 of the pFET region.
- a spacer 66 may be deposited adjacent the nitride cap 62 and around exposed source/drain region 58 . Spacer 66 can be of the same material as nitride cap 62 , and thus is shown as a single feature. Deposition can include any of CVD, PVD, and ALD.
- the Spacer 66 may then be etched back, if necessary, so as not to cover the entirety of the second sacrificial material 36 .
- the spacer 66 is deposited over and surrounding the upper source-drain junction 58 .
- the third sacrificial material 54 may be removed from the pFET regions as well as described above. Thereafter, as shown in FIG. 9B , spacer 66 is deposited adjacent the pFET nitride cap 62 and upper source-drain region 58 , creating a single spacer 66 merging with the nitride cap 62 .
- the second sacrificial material 36 may then be removed by wet etching, such as hot ammonia or tetra methyl ammonia hydroxide (TMAH). Then, as shown in FIG. 11A and 11B , the first sacrificial material 34 may then be removed by, for example, selective oxide etching or any other suitable techniques such as wet dilute hydrofluoric (DHF) etching, or dry chemical oxide removal (COR) process.
- wet etching such as hot ammonia or tetra methyl ammonia hydroxide (TMAH).
- TMAH tetra methyl ammonia hydroxide
- the first sacrificial material 34 may then be removed by, for example, selective oxide etching or any other suitable techniques such as wet dilute hydrofluoric (DHF) etching, or dry chemical oxide removal (COR) process.
- DHF wet dilute hydrofluoric
- COR dry chemical oxide removal
- a high K dielectric material is conformally deposited over the spacers 66 , the fin 14 and the bottom spacer 16 on both the n-VFINFET and p-VFINFET regions.
- the high K dielectric can include HfO 2 , ZrO 2 , Al 2 O 3 , TiO 2 , Ta 2 O 5 , lanthanide oxides and mixtures thereof, silicates and materials such as YSZ (yttria-stabilized zirconia), BST, BT, ST, and SBT.
- a work function metal (WFM) layer 74 is conformally deposited over the high K layer and remaining structure.
- the WFM layer 74 can include a single-element metal, for instance cobalt, titanium, aluminum, or other metals alloys that will allow proper workfunction to give desired threshold voltage (Vt), such as TiN, TaN, TiC, TiAl, etc, and may be deposited, for instance, using ALD.
- Vt threshold voltage
- the WFM layer 74 for n-VFINFET and p-VFINFET may be different, and can be formed by, e.g, depositing first WFM for both p-VFINFET and n-VFINFET first, followed by a lithography process to block the p-VFINVET region, and remove the first WFM layer from the n-VFINFET, followed by resist strip, and followed by second WFM deposition over both n-VFINFET and p-VFINFET.
- the WFM layer 74 for n and p-VFINFET could be different materials which also may have different thickness.
- a gate metal 78 for example tungsten or any other suitable metal typically used in a replacement metal gate (RMG) process, may be deposited on and surrounding the WFM layer 74 using ALD or other deposition techniques.
- the gate metal 78 and WFM layer 74 may be selectively removed from the sides of the structure, but remaining between the upper source/drain junction 58 and adjacent the fin 14 and in the recess between spacer 66 .
- the selective removal includes RIE, wherein the high K dielectric 70 layer, in some embodiments hafnium oxide (HfO 2 ), acts like a mask and protects the rest of the structure, essentially a gate that has been formed self-aligned to the top S/D region to the VFINFET device, from erosion.
- the exposed portions of the high K dielectric layer 70 are then removed, leaving only a lining in the recesses adjacent the fins 14 , forming a self-aligned RMG gate in device 10 for both the n-VINFETside ( FIG. 16A ) and the p-VFINFET side ( FIG. 16B ).
- device 10 may be further processed following a known set of steps for conventional VFINFET device flow to form a connecting wire to bottom S/D, gate, and top S/D, followed by a back-end-of build.
- methods according to certain embodiments allow for an RMG gate that has been self-aligned to a vertical fin using the above patterning techniques.
- the whole high-k/metal gate formation is after bottom and top S/D formation, thus, the high-k and WFM won't see any thermal impact due to the thermal budget during S/D formation.
- different metal gate 78 materials can be used to vary the threshold voltage (Vt) without concern for how to recess the different metals in order to define the gate length, since the unique shape of the high K dielectric layer 70 allows for self-patterning. Additionally, in recessing the gate, this also allows for protection from any plasma damage to the gate during the recessing.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Materials Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
- This application is a continuation application of U.S. patent application Ser. No. 15/212,755, filed Jul. 18, 2016, and entitled “METHOD AND STRUCTURE OF FORMING SELF-ALIGNED RMG GATE FOR VFET,” the entirety of which is hereby incorporated herein by reference.
- This invention relates to vertical field effect transistors (VFET) and more particularly to forming self-aligned replacement metal gates therefor.
- Currently, the fabrication of VFETs utilize a gate first fabrication technique. Gate first fabrication techniques refer to a situation where the gate is patterned prior to the annealing step used to activate the source and drain. However, in gate last techniques, a dummy gate is used to occupy the gate space during the annealing process and a replacement metal gate is inserted into the dummy gate area after the anneal. The gate last technique and the use of replacement metal gates avoids the difficult thermal issues normally encountered with use of the gate first technique.
- Accordingly, it is desirable to provide a self-aligned replacement metal gate method and structure for forming self-aligned replacement metal gates for vertical field effect transistors to provide desired thermal characteristics and effective area scaling.
- In accordance with one aspect of the invention, a method of providing a fin structure is disclosed. The fin structure includes a fin with sacrificial material above and adjacent the fin, with the fin structure being above a substrate adjacent a source or drain. The method includes removing a first portion of the sacrificial material above the fin to form an opening within the sacrificial material on top of the fin, forming a top source or drain within the opening on top of the fin, removing a second portion of the sacrificial material adjacent the top source or drain, depositing a spacer above and adjacent the top source or drain, depositing a gate material above the spacer and below the spacer to the sides of the fin, and removing the gate material above the bottom portion of the spacer to form a self aligned gate around the fin and a vertical field effect transistor.
- The sacrificial material includes a first sacrificial material. A top portion of the first sacrificial material located above and adjacent said fin structure is removed to allow a remaining portion of the first sacrificial material to remain adjacent said fin. A second sacrificial material may be deposited above the remaining first sacrificial material so that the sacrificial material includes a first sacrificial material, the second sacrificial material, and a hard mask on the top of the fin.
- The first sacrificial material may be a thin oxide surrounding the fin structure and an amorphous silicon deposited on top of the thin oxide. The second sacrificial material may be an oxide. The removing of a first portion of the sacrificial material above the fin to form an opening within the sacrificial material on top of the fin may include removing the hard mask above or on top of said fin. The self-aligned contact (SAC) cap may be deposited above the top source or drain within the oxide. The method may also include removing the oxide prior to depositing a spacer above and adjacent the top source or drain. Also, removing a third portion of the sacrificial material adjacent the fin may include removing the amorphous silicon.
- The method may further include removing the thin oxide, which may be a silicon oxide. The method may also include providing a bottom spacer above the source or drain and substrate adjacent the fin. And, may include depositing a high K dielectric material on the bottom spacer, where the spacer and the fin form an intermediate structure, and annealing the intermediate structure.
- The method may also include depositing a work function metal as part of the gate material and a metal over the work function metal as part of the gate material.
- Removing the gate material above the bottom portion of the spacer may include removing the work function metal and the metal.
- The method may further include removing annealed high K material above the spacer above and adjacent the top source or drain, depositing a second lithography stack over the barrier stack, performing a second lithography to pattern the at least one via opening, and etching to form at least one via opening.
- The method may also include providing multiple fin structures, multiple top sources or drains to form multiple vertical field effect transistors. The fin structures may be parallel spaced with at least two vertical field effect transistors spaced apart and aligned along lengths thereof and forming at least one additional gate connecting aligned on parallel spaced vertical field effect transistors.
- In another aspect of the invention, the method includes providing a fin structure having a fin with a hard mask on top of the fin. The fin structure is above a substrate adjacent a source or drain. The method includes depositing one or more sacrificial materials above and along sides of the fin structure, removing a top portion of the one or more sacrificial materials above a top of the fin to form an opening within the one or more sacrificial materials, forming a top source or drain within the opening on the top of said fin, removing a portion of the one or more sacrificial materials above and adjacent the top source or drain, depositing a spacer above the top source or drain, removing additional portions of the one or more sacrificial materials surrounding sides of the fin, depositing gate material above the spacer and below the spacer to the sides of the fin, and removing the gate material above the bottom portion of the spacer to form a self aligned gate around the fin and vertical field effort transistor.
- In another aspect of the invention, the invention includes an intermediate semiconductor structure having a fin structure. The fin structure includes a fin above a substrate adjacent a bottom source or drain, a top source or drain located on the top of the fin, a spacer located above and surrounding the top source or drain and adjacent a top portion of the fin, a self-aligned gate structure located below the top spacer and above a bottom spacer located above said substrate and source or drain, and one or more work function layers located between the bottom spacer and side walls of the fin and top spacer.
- One or more aspects of the present invention are particularly pointed out and distinctly claimed as examples in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:
-
FIG. 1A depicts a cross sectional view of a fin of negative channel field-effect transistor device (nFET) including hardmask material which may be situated above and or included adjacent as a bottom spacer to the fin and can include a bottom source drain region and insulator region; -
FIG. 1B depicts a cross sectional view of a fin of a positive channel field-effect transistor device (pFET) including hardmask material which may be situated above and or included adjacent as a bottom to the fin and can include a bottom source drain region and insulator region; -
FIG. 2A depicts a cross sectional view of the structure ofFIG. 1A after application of a first sacrificial material which may be in the form of a thin oxide surrounding said fin structure, and a second sacrificial material which may be in the form of an amorphous silicon layer deposed upon the first sacrificial material; -
FIG. 2B depicts a cross sectional view of the structure ofFIG. 1B after application of a first sacrificial material which may be in the form of a thin oxide surrounding said fin structure, and a second sacrificial material which may be in the form of an amorphous silicon layer deposed upon the first sacrificial material; -
FIG. 3A depicts a cross sectional view of the structure ofFIG. 2A after removing of a first portion of the first sacrificial material a first portion of the second sacrificial material thereby exposing the hardmask material located above the fin; -
FIG. 3B depicts a cross sectional view of the structure ofFIG. 2B after removing of a first portion of the first sacrificial material a first portion of the second sacrificial material thereby exposing the hardmask material located above the fin; -
FIG. 4A depicts a cross sectional view of the structure ofFIG. 3A after the recessing of a second portion of the first sacrificial further exposing the second sacrificial material; -
FIG. 4B depicts a cross sectional view of the structure ofFIG. 3B after the recessing of a second portion of the first sacrificial further exposing the second sacrificial material; -
FIG. 5A depicts a cross sectional view of the structure ofFIG. 4A after application of a third sacrificial material which may include an oxide; -
FIG. 5B depicts a cross sectional view of the structure ofFIG. 4B after application of a third sacrificial material which may include an oxide; -
FIG. 6A depicts a cross sectional view of the structure ofFIG. 5A after removal of the exposed hardmask material, and formation of an upper source drain junction; -
FIG. 6B depicts a cross sectional view of the structure ofFIG. 5B after removal of the exposed hardmask material, and deposition of an upper source drain junction; -
FIG. 7A depicts a cross sectional view of the structure ofFIG. 6A after application of a cap, which may be composed of a self aligned contact nitride above the upper source drain junction; -
FIG. 7B depicts a cross sectional view of the structure ofFIG. 6B after application of a cap, which may be composed of a self aligned contact nitride above the upper source drain junction; -
FIG. 8A depicts a cross sectional view of the structure ofFIG. 7A after removal of the third sacrificial material; -
FIG. 8B depicts a cross sectional view of the structure ofFIG. 7B after removal of the third sacrificial material; -
FIG. 9A depicts a cross sectional view of the structure ofFIG. 8A after adding a top spacer by means which may include deposition consisting of a material that may include SiN; -
FIG. 9B depicts a cross sectional view of the structure ofFIG. 8B after adding a top spacer by means which may include deposition consisting of a material that may include SiN; -
FIG. 10A depicts a cross sectional view of the structure ofFIG. 9A after removal of the second sacrificial material; -
FIG. 10B depicts a cross sectional view of the structure ofFIG. 9B after removal of the second sacrificial material; -
FIG. 11A depicts a cross sectional view of the structure ofFIG. 10A after removal of the first sacrificial material; -
FIG. 11B depicts a cross sectional view of the structure ofFIG. 10B after removal of the first sacrificial material; -
FIG. 12A depicts a cross sectional view of the structure ofFIG. 11A after application of a material layer through means such as chemical deposition wherein the material contains the property of having a high dielectric constant; -
FIG. 12B depicts a cross sectional view of the structure ofFIG. 11B after application of a material layer through means such as chemical deposition wherein the material contains the property of having a high dielectric constant; -
FIG. 13A depicts a cross sectional view of the structure ofFIG. 12A after deposition of a work function metal layer; -
FIG. 13B depicts a cross sectional view of the structure ofFIG. 12B after deposition of a work function metal layer; -
FIG. 14A depicts a cross sectional view of the structure ofFIG. 13A after deposition of a gate metal; -
FIG. 14B depicts a cross sectional view of the structure ofFIG. 13B after deposition of a gate metal; -
FIG. 15A depicts a cross sectional view of the structure ofFIG. 14A after removal of the gate metal except for the portions located under the top spacer and above the bottom spacer; -
FIG. 15B depicts a cross sectional view of the structure ofFIG. 14B after removal of the gate metal except for the portions located under the top spacer and above the bottom spacer; -
FIG. 16A depicts a cross sectional view of the structure ofFIG. 15A after the high K dielectric layer is removed except for the portions located under the top spacer and above the bottom spacer; -
FIG. 16B depicts a cross sectional view of the structure ofFIG. 15B after the high K dielectric layer is removed except for the portions located under the top spacer and above the bottom spacer. - Aspects of the present invention and certain features, advantages, and details thereof, are explained more fully below with reference to the non-limiting examples illustrated in the accompanying drawings. Descriptions of well-known materials, fabrication tools, processing techniques, etc., are omitted so as not to unnecessarily obscure the invention in detail. It should be understood, however, that the detailed description and the specific examples, while indicating aspects of the invention, are given by way of illustration only, and are not by way of limitation. Various substitutions, modifications, additions, and/or arrangements, within the spirit and/or scope of the underlying inventive concepts will be apparent to those skilled in the art from this disclosure.
- Approximating language, as used herein throughout the specification and claims, may be applied to modify any quantitative representation that could permissibly vary without resulting in a change in the basic function to which it is related. Accordingly, a value modified by a term or terms, such as “about,” is not limited to the precise value specified. In some instances, the approximating language may correspond to the precision of an instrument for measuring the value.
- The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprise” (and any form of comprise, such as “comprises” and “comprising”), “have” (and any form of have, such as “has” and “having”), “include (and any form of include, such as “includes” and “including”)”, and “contain” (and any form of contain, such as “contains” and “containing”) are open-ended linking verbs. As a result, a method or device that “comprises,” “has,” “includes” or “contains” one or more steps or elements possesses those one or more steps or elements, but is not limited to possessing only those one or more steps or elements. Likewise, a step of a method or an element of a device that “comprises,” “has,” “includes” or “contains” one or more features possesses those one or more features, but is not limited to possessing only those one or more features. Furthermore, a device or structure that is configured in a certain way is configured in at least that way, but may also be configured in ways that are not listed.
- As used herein, the terms “may” and “may be” indicate a possibility of an occurrence within a set of circumstances; a possession of a specified property, characteristic or function; and/or qualify another verb by expressing one or more of an ability, capability, or possibility associated with the qualified verb. Accordingly, usage of “may” and “may be” indicates that a modified term is apparently appropriate, capable, or suitable for an indicated capacity, function, or usage, while taking into account that in some circumstances the modified term may sometimes not be appropriate, capable or suitable. For example, in some circumstances, an event or capacity can be expected, while in other circumstances the event or capacity cannot occur—this distinction is captured by the terms “may” and “may be.”
- As used herein, “depositing” may include any now known or later developed techniques appropriate for the material to be deposited including but not limited to, for example: chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), semi-atmosphere CVD (SACVD) and high density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited reaction processing CVD (LRPCVD), metal-organic CVD (MOCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser assisted deposition, thermal oxidation, thermal nitridation, spin-on methods, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating, evaporation.
- Reference is made below to the drawings, which are not drawn to scale for ease of understanding, wherein the same reference numbers are used throughout different figures designate the same or similar components.
- In accordance with one aspect of this invention, the following describes a method for manufacturing a fin structure, wherein this fin structure includes a fin with a sacrificial material above and/or adjacent to the fin. The fin structure also being above a substrate while being adjacent to a source or drain. The figures referenced are numbered and are labeled (A) and (B) to show the corresponding method for a negative channel field-effect transistor on the figures labeled with (A) and the corresponding method for a positive channel field-effect transistor on the figures labeled with (B).
- Referring to
FIG. 1A , a n-type vertical FIN field-effect-transistor (n-VFINFET) is initially fabricated in a conventional manner. The structure includeshardmask material 12 which is situated above the vertical FIN channel, and abottom spacer 16, to afin 14 and can include a bottom source/drain region 18 and asubstrate 20. There may also be an isolation region (not shown) betweenadjacent devices 10 if more than one device is fabricated. Referring toFIG. 1B a structure of a p-type VFINFET is fabricated in a conventional manner. The structure includes ahardmask material 12, including but not limited to a nitride such as silicon nitride, which may be situated above and/or included adjacent a bottom spacer 16 (typically a nitride material) to afin 14 and can include a bottom source/drain region 18 and aninsulator region 20. The n-VFINFET and p-VFINFET regions may be located on the same semiconductor wafer, for example in different, yet adjacent areas of a wafer separated by any distance that will not interfere with the operation of a VFET device. Thefin 14 may include semiconductor materials, including but not limited to silicon, silicon germanium, and any III-V type materials. The bottom source/drain region 18 may include silicon, silicon germanium, or any other semiconductor material, and may be doped, often at high concentrations. The doping will vary for the device, but for an NFET it may be phosphorous doped and for a PFET it may be boron doped. Additionally, the source/drain region 18 inFIG. 1A may be different from the source/drain region 18 ofFIG. 1B , and both may be doped differently. Thesubstrate region 20 can include silicon, silicon germanium, and any type materials - Referring to
FIG. 2A , a firstsacrificial material 34 and a secondsacrificial material 36 are deposited onto the structure shown inFIG. 1A . The firstsacrificial material 34 may be in the form of a thin oxide deposed on and surrounding thehardmask material 12 above thebottom spacer 16, thefin 14 and thebottom spacer 16 itself. The secondsacrificial material 36 may be an amorphous silicon layer and may be deposited over and surrounding the firstsacrificial material 34. Referring toFIG. 2B , the firstsacrificial material 34 and secondsacrificial material 36 are deposited onto the structure shown inFIG. 1A . The firstsacrificial material 34 may be a thin oxide deposed on and surrounding thehardmask material 12 above thebottom spacer 16, thefin 14 and thebottom spacer 16 itself. The secondsacrificial material 36 which may be an amorphous silicon layer may be deposited over and surrounding said firstsacrificial material 34. First and Secondsacrificial material - Referring to
FIG. 3A , the structure ofFIG. 2A is planarized by, for example, a chemical mechanical polishing (CMP) technique. During planarization, the firstsacrificial material 34 and the secondsacrificial material 36 is removed from afirst portion 42, i.e., the top ofdevice 10, exposing the top section of thehardmask material 12. Then, as shown inFIG. 4A , a portion of the secondsacrificial material 36, adjacent to hardmask 12 and a top portion offin 14, is removed by, for example, etching using any wet or dry etch techniques to recess the secondsacrificial material 36 below a top surface ofdevice 10. -
FIG. 3B illustrates the planarization of the structure ofFIG. 2B by, for example, CMP. During planarization, as described in reference toFIG. 3A , the first and secondsacrificial material first portion 42. Then as shown inFIG. 4B , a portion of the secondsacrificial material 36, adjacent to hardmask 12 and a top portion offin 14, is removed by, for example, etching using any wet or dry etch techniques to recess the secondsacrificial material 36 below a top surface ofdevice 10. - Referring to
FIG. 5A , a thirdsacrificial material 54, which may include an oxide material, is deposited by ALD, CVD, or PVD in some embodiments, in the region shown inFIG. 4A which has been etched to recess the secondsacrificial material 36. Referring toFIG. 5B , thirdsacrificial material 54 is similarly deposited on the positive channel. - Referring to
FIG. 6A , the remaininghardmask material 12 is removed by selective etching processes to expose thefin 14. This can include any etch that is selective for a nitride material, and may include plasma etching. In its place, an upper source-drain 58 can be formed by selective epitaxy process, including but not limited to silicon and silicon germanium. The material and doping of upper source-drain 58 may be a different material for the n-VFINFET and p-VFINFET ofFIGS. 6A and 6B . For instance, the n-VFINFET (FIG. 6A ) may include a heavily phosphorus doped silicon material, and the p-VFINFET (FIG. 6B ) may be a heavily boron doped SiGe material. The patterning processes to form separate top S/D materials are not shown in detail here, because it is not the main focus of this disclosure. As shown inFIG. 7A , acap 62 is placed above the upper source-drain junction 58. Thecap 62 may be composed of a nitride, which will assist in subsequent self-aligned contact (SAC) etching to mask the upper source/drain junction 58 below. Similarly, referring toFIG. 6B , thehardmask material 12 is removed on the p-VFINFET area by selective etching, to expose thefin 14. In its place an upper source-drain junction 58 can be formed. As shown inFIG. 7B , thenitride SAC cap 62 is also deposited above the upper source-drain junction 58 of the pFET region. - Referring to
FIG. 8A , what remains of the thirdsacrificial material 54 is removed, for instance, by buffered hydrofluoric acid (BHF) oxide etch, from the structure ofFIG. 7A . This may also remove the exposed portion of the firstsacrificial material 34 below upper source/drain junction 58 and above the secondsacrificial material 36. Then, depicted inFIG. 9A , aspacer 66 may be deposited adjacent thenitride cap 62 and around exposed source/drain region 58.Spacer 66 can be of the same material asnitride cap 62, and thus is shown as a single feature. Deposition can include any of CVD, PVD, and ALD. TheSpacer 66 may then be etched back, if necessary, so as not to cover the entirety of the secondsacrificial material 36. Thespacer 66 is deposited over and surrounding the upper source-drain junction 58. Similarly, referring toFIG. 8B , the thirdsacrificial material 54 may be removed from the pFET regions as well as described above. Thereafter, as shown inFIG. 9B ,spacer 66 is deposited adjacent thepFET nitride cap 62 and upper source-drain region 58, creating asingle spacer 66 merging with thenitride cap 62. - Referring to
FIG. 10A and 10B , the secondsacrificial material 36 may then be removed by wet etching, such as hot ammonia or tetra methyl ammonia hydroxide (TMAH). Then, as shown inFIG. 11A and 11B , the firstsacrificial material 34 may then be removed by, for example, selective oxide etching or any other suitable techniques such as wet dilute hydrofluoric (DHF) etching, or dry chemical oxide removal (COR) process. - Referring to
FIG. 12A and 12B , a high K dielectric material is conformally deposited over thespacers 66, thefin 14 and thebottom spacer 16 on both the n-VFINFET and p-VFINFET regions. The high K dielectric can include HfO2, ZrO2, Al2O3, TiO2, Ta2O5, lanthanide oxides and mixtures thereof, silicates and materials such as YSZ (yttria-stabilized zirconia), BST, BT, ST, and SBT. Then, as shown inFIG. 13A and 13B , a work function metal (WFM)layer 74 is conformally deposited over the high K layer and remaining structure. TheWFM layer 74 can include a single-element metal, for instance cobalt, titanium, aluminum, or other metals alloys that will allow proper workfunction to give desired threshold voltage (Vt), such as TiN, TaN, TiC, TiAl, etc, and may be deposited, for instance, using ALD. Additionally, theWFM layer 74 for n-VFINFET and p-VFINFET may be different, and can be formed by, e.g, depositing first WFM for both p-VFINFET and n-VFINFET first, followed by a lithography process to block the p-VFINVET region, and remove the first WFM layer from the n-VFINFET, followed by resist strip, and followed by second WFM deposition over both n-VFINFET and p-VFINFET. Thus, theWFM layer 74 for n and p-VFINFET could be different materials which also may have different thickness. Then, as depicted inFIG. 14A and 14B , agate metal 78, for example tungsten or any other suitable metal typically used in a replacement metal gate (RMG) process, may be deposited on and surrounding theWFM layer 74 using ALD or other deposition techniques. - Referring to
FIG. 15A and 15B , thegate metal 78 andWFM layer 74 may be selectively removed from the sides of the structure, but remaining between the upper source/drain junction 58 and adjacent thefin 14 and in the recess betweenspacer 66. In some embodiments, the selective removal includes RIE, wherein the high K dielectric 70 layer, in some embodiments hafnium oxide (HfO2), acts like a mask and protects the rest of the structure, essentially a gate that has been formed self-aligned to the top S/D region to the VFINFET device, from erosion. Finally, as shown inFIG. 16A and 16B , the exposed portions of the high Kdielectric layer 70 are then removed, leaving only a lining in the recesses adjacent thefins 14, forming a self-aligned RMG gate indevice 10 for both the n-VINFETside (FIG. 16A ) and the p-VFINFET side (FIG. 16B ). - Following these steps,
device 10 may be further processed following a known set of steps for conventional VFINFET device flow to form a connecting wire to bottom S/D, gate, and top S/D, followed by a back-end-of build. - Thus, as described above, methods according to certain embodiments allow for an RMG gate that has been self-aligned to a vertical fin using the above patterning techniques. The whole high-k/metal gate formation is after bottom and top S/D formation, thus, the high-k and WFM won't see any thermal impact due to the thermal budget during S/D formation. Also, due to the unique shape of the structure,
different metal gate 78 materials can be used to vary the threshold voltage (Vt) without concern for how to recess the different metals in order to define the gate length, since the unique shape of the high Kdielectric layer 70 allows for self-patterning. Additionally, in recessing the gate, this also allows for protection from any plasma damage to the gate during the recessing.
Claims (13)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/683,228 US20180019337A1 (en) | 2016-07-18 | 2017-08-22 | Method and structure of forming self-aligned rmg gate for vfet |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/212,755 US9780208B1 (en) | 2016-07-18 | 2016-07-18 | Method and structure of forming self-aligned RMG gate for VFET |
US15/683,228 US20180019337A1 (en) | 2016-07-18 | 2017-08-22 | Method and structure of forming self-aligned rmg gate for vfet |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/212,755 Continuation US9780208B1 (en) | 2016-07-18 | 2016-07-18 | Method and structure of forming self-aligned RMG gate for VFET |
Publications (1)
Publication Number | Publication Date |
---|---|
US20180019337A1 true US20180019337A1 (en) | 2018-01-18 |
Family
ID=59929344
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/212,755 Active US9780208B1 (en) | 2016-07-18 | 2016-07-18 | Method and structure of forming self-aligned RMG gate for VFET |
US15/683,228 Abandoned US20180019337A1 (en) | 2016-07-18 | 2017-08-22 | Method and structure of forming self-aligned rmg gate for vfet |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/212,755 Active US9780208B1 (en) | 2016-07-18 | 2016-07-18 | Method and structure of forming self-aligned RMG gate for VFET |
Country Status (1)
Country | Link |
---|---|
US (2) | US9780208B1 (en) |
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10373912B2 (en) | 2018-01-05 | 2019-08-06 | International Business Machines Corporation | Replacement metal gate processes for vertical transport field-effect transistor |
US10453844B2 (en) * | 2017-12-06 | 2019-10-22 | International Business Machines Corporation | Techniques for enhancing vertical gate-all-around FET performance |
US10535754B2 (en) | 2018-06-05 | 2020-01-14 | International Business Machines Corporation | Method and structure for forming a vertical field-effect transistor |
US10658243B2 (en) | 2018-06-07 | 2020-05-19 | Globalfoundries Inc. | Method for forming replacement metal gate and related structures |
US10672670B2 (en) | 2018-08-21 | 2020-06-02 | International Business Machines Corporation | Replacement metal gate process for vertical transport field-effect transistors with multiple threshold voltages |
US10672905B2 (en) | 2018-08-21 | 2020-06-02 | International Business Machines Corporation | Replacement metal gate process for vertical transport field-effect transistor with self-aligned shared contacts |
US10714399B2 (en) | 2018-08-21 | 2020-07-14 | International Business Machines Corporation | Gate-last process for vertical transport field-effect transistor |
US10804391B2 (en) | 2018-06-15 | 2020-10-13 | Samsung Electronics Co., Ltd. | Vertical field-effect transistor (VFET) devices and methods of forming the same |
US10818756B2 (en) | 2018-11-02 | 2020-10-27 | International Business Machines Corporation | Vertical transport FET having multiple threshold voltages with zero-thickness variation of work function metal |
US10985073B2 (en) | 2019-07-08 | 2021-04-20 | International Business Machines Corporation | Vertical field effect transistor replacement metal gate fabrication |
US11177367B2 (en) | 2020-01-15 | 2021-11-16 | International Business Machines Corporation | Self-aligned bottom spacer EPI last flow for VTFET |
US11239342B2 (en) | 2018-06-28 | 2022-02-01 | International Business Machines Corporation | Vertical transistors having improved control of top source or drain junctions |
US11437489B2 (en) * | 2019-09-27 | 2022-09-06 | International Business Machines Corporation | Techniques for forming replacement metal gate for VFET |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9935195B1 (en) | 2017-01-12 | 2018-04-03 | International Business Machines Corporation | Reduced resistance source and drain extensions in vertical field effect transistors |
US10622458B2 (en) * | 2017-05-19 | 2020-04-14 | International Business Machines Corporation | Self-aligned contact for vertical field effect transistor |
KR102337408B1 (en) * | 2017-09-13 | 2021-12-10 | 삼성전자주식회사 | Semiconductor devices having a vertical channel and method of manufacturing the same |
US10211288B1 (en) * | 2017-10-20 | 2019-02-19 | International Business Machines Corporation | Vertical transistors with multiple gate lengths |
US10170588B1 (en) * | 2017-10-30 | 2019-01-01 | International Business Machines Corporation | Method of forming vertical transport fin field effect transistor with high-K dielectric feature uniformity |
US10566444B2 (en) * | 2017-12-21 | 2020-02-18 | International Business Machines Corporation | Vertical fin field effect transistor with a reduced gate-to-bottom source/drain parasitic capacitance |
US10361200B1 (en) | 2018-03-07 | 2019-07-23 | International Business Machines Corporation | Vertical fin field effect transistor with integral U-shaped electrical gate connection |
US10529850B2 (en) * | 2018-04-18 | 2020-01-07 | International Business Machines Corporation | Vertical field-effect transistor including a fin having sidewalls with a tapered bottom profile |
US10559676B2 (en) | 2018-04-23 | 2020-02-11 | International Business Machines Corporation | Vertical FET with differential top spacer |
US10629499B2 (en) | 2018-06-13 | 2020-04-21 | International Business Machines Corporation | Method and structure for forming a vertical field-effect transistor using a replacement metal gate process |
US10396151B1 (en) * | 2018-06-14 | 2019-08-27 | International Business Machines Corporation | Vertical field effect transistor with reduced gate to source/drain capacitance |
US10916638B2 (en) * | 2018-09-18 | 2021-02-09 | International Business Machines Corporation | Vertical fin field effect transistor devices with reduced top source/drain variability and lower resistance |
US10700062B2 (en) | 2018-10-12 | 2020-06-30 | International Business Machines Corporation | Vertical transport field-effect transistors with uniform threshold voltage |
US10679993B2 (en) | 2018-11-06 | 2020-06-09 | International Business Machines Corporation | Vertical fin field effect transistor devices with a replacement metal gate |
US11245025B2 (en) | 2019-05-07 | 2022-02-08 | International Business Machines Corporation | Gate last vertical transport field effect transistor |
US11538939B2 (en) | 2020-01-14 | 2022-12-27 | International Business Machines Corporation | Controlled bottom junctions |
US11164907B2 (en) | 2020-03-11 | 2021-11-02 | International Business Machines Corporation | Resistive random access memory integrated with stacked vertical transistors |
US11482617B2 (en) | 2020-03-17 | 2022-10-25 | International Business Machines Corporation | Vertical transport field-effect transistor including replacement gate |
US11251287B2 (en) | 2020-04-14 | 2022-02-15 | International Business Machines Corporation | Self-aligned uniform bottom spacers for VTFETS |
US11640987B2 (en) * | 2021-02-04 | 2023-05-02 | Applied Materials, Inc. | Implant to form vertical FETs with self-aligned drain spacer and junction |
US11757036B2 (en) | 2021-07-29 | 2023-09-12 | International Business Machines Corporation | Moon-shaped bottom spacer for vertical transport field effect transistor (VTFET) devices |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040191971A1 (en) * | 2000-06-19 | 2004-09-30 | International Rectifier Corporation | Method for fabrication of MOSFET with buried gate |
US20090104742A1 (en) * | 2007-10-23 | 2009-04-23 | Texas Instruments Incorporated | Methods for forming gate electrodes for integrated circuits |
US20090159964A1 (en) * | 2007-12-24 | 2009-06-25 | Hynix Semiconductor Inc. | Vertical channel transistor and method of fabricating the same |
US20100127332A1 (en) * | 2008-11-26 | 2010-05-27 | Jun Liu | Integrated circuit transistors |
US20110070702A1 (en) * | 2009-09-21 | 2011-03-24 | United Microelectronics Corp. | Method for fabricating semiconductor device |
US9530866B1 (en) * | 2016-04-13 | 2016-12-27 | Globalfoundries Inc. | Methods of forming vertical transistor devices with self-aligned top source/drain conductive contacts |
US9761726B1 (en) * | 2016-04-27 | 2017-09-12 | International Business Machines Corporation | Vertical field effect transistor with undercut buried insulating layer to improve contact resistance |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW461096B (en) * | 1999-05-13 | 2001-10-21 | Hitachi Ltd | Semiconductor memory |
KR100653711B1 (en) * | 2005-11-14 | 2006-12-05 | 삼성전자주식회사 | Schottky barrier finfet device and fabrication method thereof |
US8148222B2 (en) * | 2009-12-10 | 2012-04-03 | Micron Technology, Inc. | Cross-point diode arrays and methods of manufacturing cross-point diode arrays |
US8207032B2 (en) * | 2010-08-31 | 2012-06-26 | Micron Technology, Inc. | Methods of forming pluralities of vertical transistors, and methods of forming memory arrays |
-
2016
- 2016-07-18 US US15/212,755 patent/US9780208B1/en active Active
-
2017
- 2017-08-22 US US15/683,228 patent/US20180019337A1/en not_active Abandoned
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040191971A1 (en) * | 2000-06-19 | 2004-09-30 | International Rectifier Corporation | Method for fabrication of MOSFET with buried gate |
US20090104742A1 (en) * | 2007-10-23 | 2009-04-23 | Texas Instruments Incorporated | Methods for forming gate electrodes for integrated circuits |
US20090159964A1 (en) * | 2007-12-24 | 2009-06-25 | Hynix Semiconductor Inc. | Vertical channel transistor and method of fabricating the same |
US20100127332A1 (en) * | 2008-11-26 | 2010-05-27 | Jun Liu | Integrated circuit transistors |
US20110070702A1 (en) * | 2009-09-21 | 2011-03-24 | United Microelectronics Corp. | Method for fabricating semiconductor device |
US9530866B1 (en) * | 2016-04-13 | 2016-12-27 | Globalfoundries Inc. | Methods of forming vertical transistor devices with self-aligned top source/drain conductive contacts |
US9761726B1 (en) * | 2016-04-27 | 2017-09-12 | International Business Machines Corporation | Vertical field effect transistor with undercut buried insulating layer to improve contact resistance |
Cited By (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11069686B2 (en) | 2017-12-06 | 2021-07-20 | International Business Machines Corporation | Techniques for enhancing vertical gate-all-around FET performance |
US10453844B2 (en) * | 2017-12-06 | 2019-10-22 | International Business Machines Corporation | Techniques for enhancing vertical gate-all-around FET performance |
US10658299B2 (en) | 2018-01-05 | 2020-05-19 | International Business Machines Corporation | Replacement metal gate processes for vertical transport field-effect transistor |
US10373912B2 (en) | 2018-01-05 | 2019-08-06 | International Business Machines Corporation | Replacement metal gate processes for vertical transport field-effect transistor |
US10535754B2 (en) | 2018-06-05 | 2020-01-14 | International Business Machines Corporation | Method and structure for forming a vertical field-effect transistor |
US11302799B2 (en) | 2018-06-05 | 2022-04-12 | International Business Machines Corporation | Method and structure for forming a vertical field-effect transistor |
US10658243B2 (en) | 2018-06-07 | 2020-05-19 | Globalfoundries Inc. | Method for forming replacement metal gate and related structures |
US10804391B2 (en) | 2018-06-15 | 2020-10-13 | Samsung Electronics Co., Ltd. | Vertical field-effect transistor (VFET) devices and methods of forming the same |
US11239342B2 (en) | 2018-06-28 | 2022-02-01 | International Business Machines Corporation | Vertical transistors having improved control of top source or drain junctions |
US11257721B2 (en) | 2018-08-21 | 2022-02-22 | International Business Machines Corporation | Replacement metal gate process for vertical transport field-effect transistors with multiple threshold voltages |
US11145555B2 (en) | 2018-08-21 | 2021-10-12 | International Business Machines Corporation | Gate-last process for vertical transport field-effect transistor |
US10714399B2 (en) | 2018-08-21 | 2020-07-14 | International Business Machines Corporation | Gate-last process for vertical transport field-effect transistor |
US10672905B2 (en) | 2018-08-21 | 2020-06-02 | International Business Machines Corporation | Replacement metal gate process for vertical transport field-effect transistor with self-aligned shared contacts |
US11271106B2 (en) | 2018-08-21 | 2022-03-08 | International Business Machines Corporation | Replacement metal gate process for vertical transport field-effect transistor with self-aligned shared contacts |
US10672670B2 (en) | 2018-08-21 | 2020-06-02 | International Business Machines Corporation | Replacement metal gate process for vertical transport field-effect transistors with multiple threshold voltages |
US10818756B2 (en) | 2018-11-02 | 2020-10-27 | International Business Machines Corporation | Vertical transport FET having multiple threshold voltages with zero-thickness variation of work function metal |
US10985073B2 (en) | 2019-07-08 | 2021-04-20 | International Business Machines Corporation | Vertical field effect transistor replacement metal gate fabrication |
US11437489B2 (en) * | 2019-09-27 | 2022-09-06 | International Business Machines Corporation | Techniques for forming replacement metal gate for VFET |
US11177367B2 (en) | 2020-01-15 | 2021-11-16 | International Business Machines Corporation | Self-aligned bottom spacer EPI last flow for VTFET |
US11923434B2 (en) | 2020-01-15 | 2024-03-05 | International Business Machines Corporation | Self-aligned bottom spacer epi last flow for VTFET |
Also Published As
Publication number | Publication date |
---|---|
US9780208B1 (en) | 2017-10-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9780208B1 (en) | Method and structure of forming self-aligned RMG gate for VFET | |
US9368502B2 (en) | Replacement gate multigate transistor for embedded DRAM | |
US10121786B2 (en) | FinFET with U-shaped channel and S/D epitaxial cladding extending under gate spacers | |
US8846491B1 (en) | Forming a diffusion break during a RMG process | |
US9627262B2 (en) | Method of patterning features of a semiconductor device | |
US9236479B2 (en) | Methods of forming replacement gate structures and fins on FinFET devices and the resulting devices | |
US9412822B2 (en) | Methods of forming stressed channel regions for a FinFET semiconductor device and the resulting device | |
US9054213B2 (en) | FinFET with metal gate stressor | |
US6512266B1 (en) | Method of fabricating SiO2 spacers and annealing caps | |
US8895434B2 (en) | Replacement metal gate structure for CMOS device | |
US10141263B2 (en) | Method for fabricating semiconductor device | |
TW201913817A (en) | Semiconductor structure and method of forming same | |
US9373690B2 (en) | Variable length multi-channel replacement metal gate including silicon hard mask | |
US11315922B2 (en) | Fin cut to prevent replacement gate collapse on STI | |
CN101714507A (en) | Semiconductor device having metal gate stacks and making method thereof | |
CN102272906B (en) | Comprise the semiconductor device of double-grid structure and form the method for this type of semiconductor device | |
US8883623B2 (en) | Facilitating gate height uniformity and inter-layer dielectric protection | |
US9502408B2 (en) | FinFET device including fins having a smaller thickness in a channel region, and a method of manufacturing same | |
US11437489B2 (en) | Techniques for forming replacement metal gate for VFET | |
US20160322468A1 (en) | Semiconductor device | |
US20160086952A1 (en) | Preventing epi damage for cap nitride strip scheme in a fin-shaped field effect transistor (finfet) device | |
US10170353B2 (en) | Devices and methods for dynamically tunable biasing to backplates and wells | |
JP2010098157A (en) | Process of fabricating semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:XIE, RUILONG;PARK, CHANRO;SUNG, MIN GYU;AND OTHERS;REEL/FRAME:043357/0836 Effective date: 20160715 |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: FINAL REJECTION MAILED |
|
AS | Assignment |
Owner name: WILMINGTON TRUST, NATIONAL ASSOCIATION, DELAWARE Free format text: SECURITY AGREEMENT;ASSIGNOR:GLOBALFOUNDRIES INC.;REEL/FRAME:049490/0001 Effective date: 20181127 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WILMINGTON TRUST, NATIONAL ASSOCIATION;REEL/FRAME:054636/0001 Effective date: 20201117 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. INC., NEW YORK Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WILMINGTON TRUST, NATIONAL ASSOCIATION;REEL/FRAME:056987/0001 Effective date: 20201117 |