US20160293711A1 - Substrate For Molecular Beam Epitaxy (MBE) HGCDTE Growth - Google Patents
Substrate For Molecular Beam Epitaxy (MBE) HGCDTE Growth Download PDFInfo
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- US20160293711A1 US20160293711A1 US15/185,561 US201615185561A US2016293711A1 US 20160293711 A1 US20160293711 A1 US 20160293711A1 US 201615185561 A US201615185561 A US 201615185561A US 2016293711 A1 US2016293711 A1 US 2016293711A1
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- 239000000758 substrate Substances 0.000 title description 12
- 238000001451 molecular beam epitaxy Methods 0.000 title description 11
- 239000004065 semiconductor Substances 0.000 claims abstract description 65
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 22
- 239000010703 silicon Substances 0.000 claims abstract description 22
- 229910004613 CdTe Inorganic materials 0.000 claims abstract description 4
- 239000000463 material Substances 0.000 claims description 3
- 235000012431 wafers Nutrition 0.000 description 78
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 18
- 229910000661 Mercury cadmium telluride Inorganic materials 0.000 description 14
- 239000012535 impurity Substances 0.000 description 8
- 238000000034 method Methods 0.000 description 7
- 238000005247 gettering Methods 0.000 description 6
- 230000005855 radiation Effects 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 238000003491 array Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- MCMSPRNYOJJPIZ-UHFFFAOYSA-N cadmium;mercury;tellurium Chemical compound [Cd]=[Te]=[Hg] MCMSPRNYOJJPIZ-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003908 quality control method Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
- H01L29/32—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being within the semiconductor body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/02433—Crystal orientation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02551—Group 12/16 materials
- H01L21/02562—Tellurides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
- H01L21/3223—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering using cavities formed by hydrogen or noble gas ion implantation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
- H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
Definitions
- This disclosure relates generally to semiconductor substrates and more particularly to semiconductor substrates for MBE growth of mercury cadmium telluride (HgCdTe) devices.
- HgCdTe mercury cadmium telluride
- cryogenic infrared detectors are typically made of small band gap (about 0.1-0.2 eV) semiconductors such as HgCdTe (mercury cadmium telluride) grown on a semiconductor substrate, such as a silicon substrate, using molecular beam epitaxy (MBE).
- HgCdTe compoundcury cadmium telluride
- MBE molecular beam epitaxy
- the silicon surface upon which the HgCdTe is MBE grown should have a ⁇ 211> crystallographic orientation.
- the wafers should have sufficient support thicknesses, typically, at least in the order of 100 microns.
- Float Zone (FZ) silicon wafers are readily available, these wafers have surfaces with a ⁇ 100> crystallographic orientation and are therefore not suitable for MBE formation. of the HgCdTe detectors.
- silicon wafers produced by the Czochralski (CZ) process produces silicon wafers (CZ silicon wafers) having a surface with a ⁇ 211> orientation
- the CZ silicon wafers having thickness in the order of 100 microns are undesirable in many application because oxygen impurities therein absorb light in many frequency bands where radiation detection is required as in LWIR applications.
- eight inch diameter CZ silicon wafers with surfaces having a ⁇ 211> orientation are not readily available.
- a semiconductor structure comprising: a first semiconductor body having an upper surface with a non ⁇ 211> crystallographic orientation; a second semiconductor body having a surface with a ⁇ 211> crystallographic orientation, the surface of the second semiconductor body being bonded to a bottom surface of the first semiconductor body.
- the structure includes a layer comprising CdTe epitaxially disposed on the upper surface of the second semiconductor body.
- the second semiconductor body is CZ silicon.
- the second semiconductor body has a thickness less than 10 microns.
- the second semiconductor body has a diameter of at least eight inches.
- the first semiconductor body and the second semiconductor body are of the same semiconductor material.
- the second semiconductor body has a thickness at least an order of magnitude thinner than the thickness of the first semiconductor body.
- a semiconductor structure comprising; a first semiconductor body; a getter layer; and a second semiconductor body.
- the getter layer has a bottom surface formed on an upper surface of the first semiconductor body and has an upper surface bonded to a bottom surface of the second semiconductor body.
- the getter layer has nanocavities.
- the first semiconductor body is FZ silicon.
- wafer bonding is used to bond a readily available ⁇ 211> CZ wafer to an ordinary orientation Float Zone silicon wafer.
- the ⁇ 211> CZ wafer is then thinned so that it does not appreciably absorb LWIR radiation, and the FZ wafer serves only as an LWIR transparent handle wafer.
- This arrangement an LWIR compatible 8-in diameter substrate for MBE growth and focal plane arrays is obtained without having to obtain an 8-in diameter ⁇ 211> FZ silicon wafer; enables placing an impurity getter layer in the benign location between the two substrates in close proximity to the HgCdTe; and eases supply chain issues associated with ⁇ 211> silicon (Si) substrates.
- the use of wafer bonding of two more readily available wafers to replace a difficult to obtain wafer will enable the engineered silicon substrate to be a manufactured product with more predictable lead times and better quality control.
- FIGS. 1A-1E are diagrammatical cross sectional Sketches of a process used to form an array of photo-detectors at various stages in the fabrication thereof in accordance with the disclosure.
- FIGS. 2A-2E are diagrammatical cross sectional sketches of a process used to form an array of photo-detectors at various stages in the fabrication thereof in accordance with another embodiment of the disclosure;
- a semiconductor wafer 10 here an FZ silicon wafer
- the wafer 10 is an eight inch diameter wafer have an upper surface with a ⁇ 100> crystallographic orientation, it should be understood that the wafer 10 here has ⁇ 100 >crystallographic orientation, other crystallographic orientations may be used.
- the thickness of the wafer 10 is here, for example, 100 microns.
- a semiconductor wafer 12 here an eight inch diameter CZ silicon wafer, disposed above the upper surface of wafer 10 ; the wafer 12 having a top and bottom surfaces each with a ⁇ 211> crystallographic orientation.
- the thickness of wafer 12 is here, for example, 100 microns,
- the top surface of wafer 12 and bottom surface of wafer 12 are cleaned and polished and then bonded together in an oxide free environment to form an atomic bond between the two wafers 10 , 12 , to form structure 14 , as indicated. Because the wafer bond interface will be silicon-to-silicon, the bonding is likely to be a combination of atomic bonding and Van der Waal's attraction.
- the upper surface of the wafer 12 is polished, for example using standard silicon semiconductor polishing methods to achieve a smooth, particle free surface, to reduce the thickness of the wafer 12 to a wafer 12 ′ having a thickness thick enough for handling until it can he wafer bonded to the handle wafer, for example, as thin as 100 ⁇ m.
- the ⁇ 211> wafer can be thinned to its final thickness ⁇ 5 ⁇ m so as not to appreciably absorb MR IR radiation.
- the wafer 10 serves as a handle for the thinned wafer 12 ′ and that the upper surface of the thinned wafer 12 ; has a ⁇ 211> crystallographic orientation.
- a layer 16 of HgCdTe is formed using MBE on the upper surface of the thinned wafer 12 ′.
- an array of HgCdTe detectors 18 is formed in the layer 16 using conventional photolithographic—etching processing.
- an array of HgCdTe photo-detectors has been formed on an eight inch diameter substrate, here the structure 14 , using MBE on a surface (the upper surface of the thinned, and hence low oxygen impurity, CZ wafer 12 ′) having a ⁇ 211> crystallographic orientation.
- a semiconductor wafer 20 here an FL silicon wafer, is shown.
- the wafer 20 is an eight inch diameter wafer have an upper surface with a ⁇ 100> crystallographic orientation. It should be understood that other semiconductor materials may be used as well as other crystallographic orientations for the surface.
- the thickness of the wafer 20 is here, for example, 100 microns.
- the upper surface of wafer 20 has a getter layer 21 , here a layer formed with nanocavities by, for example, implanting ion of helium into the surface of either wafer at the bonding interface between layers 12 and 20 , as shown in FIG. 2A .
- the formation of the gettering layer 21 must occur before wafer bonding (thereby putting the gettering layer buried in the bondline between, protecting it from both the MBE growth process and the wafer fabrication process), followed by the application of heat to form bubbles in the upper surface of wafer 20 .
- the getter layer 21 to be used to trap impurities in the environment, such as, for example, copper. More particularly, the internal surfaces of the bubbles formed by the nanocavities trap the impurities.
- the top surface of wafer 12 and bottom surface of wafer 22 are cleaned and polished and cleaned to form oxide free surfaces and then bonded together in a clean environment to form an atomic bond between the two wafers 20 , 12 , to form structure 14 , as indicated.
- the gettering layer 21 will attract undesired metallic impurities such as copper so that the impurities will not affect the HgCdTe to be grown onto the wafer.
- the upper surface of the wafer 12 is polished, as described in connection with FIG. 1C to reduce the thickness of the wafer 12 to the wafer 12 ′ having a thickness in the range between 540 ⁇ m although it may be possible to be as thin as 2 ⁇ m if a high degree of polishing is provided.
- the wafer 20 serves as a handle for the thinned wafer 12 ′ and that the upper surface of the thinned wafer 12 ; has a ⁇ 211> crystallographic orientation.
- the layer 16 of HgCdTe is formed using MBE on the upper surface of the thinned wafer 12 ,′ as described in connection with FIG. 1C .
- an array of HgCdTe detectors is formed in the layer 16 using conventional photolithographic—etching processing as described in connection with FIG. 1D .
- an array of HgCdTh photo-detectors 18 has been formed on an eight inch diameter substrate, here the structure 14 , using MBE on a surface (the upper surface of the thinned, and hence low oxygen impurity, CZ wafer 12 ′) having a ⁇ 211> crystallographic orientation having an internal, buried, getter layer 21 .
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Abstract
A semiconductor structure having a first semiconductor body having an upper surface with a non <211> crystallographic orientation and a second semiconductor body having a surface with a <211> crystallographic orientation, the surface of the second semiconductor body being bonded to a bottom surface of the first semiconductor body. A layer comprising CdTe is epitaxially disposed on the upper surface of the second semiconductor body. The second semiconductor body is CZ silicon, has a thickness less than 10 microns and has a diameter of at least eight inches. A getter having micro-cavities has a bottom surface formed on an upper surface of the first semiconductor body and has an upper surface bonded to a bottom surface of the second semiconductor body.
Description
- This is a Divisional Application of application Ser. No. 14/271,727 filed May 7, 2014 which application is hereby incorporated herein by reference in its entirety.
- This disclosure relates generally to semiconductor substrates and more particularly to semiconductor substrates for MBE growth of mercury cadmium telluride (HgCdTe) devices.
- As is known in the art, cryogenic infrared detectors are typically made of small band gap (about 0.1-0.2 eV) semiconductors such as HgCdTe (mercury cadmium telluride) grown on a semiconductor substrate, such as a silicon substrate, using molecular beam epitaxy (MBE). In order for proper crystallographic epitaxial growth, the silicon surface upon which the HgCdTe is MBE grown should have a<211> crystallographic orientation. Also, the wafers should have sufficient support thicknesses, typically, at least in the order of 100 microns.
- As is also known in the art, many imaging application require large arrays of the detectors on a single substrate, or wafer; preferably at least eight inches in diameter. While, eight inch diameter Float Zone (FZ) silicon wafers are readily available, these wafers have surfaces with a <100> crystallographic orientation and are therefore not suitable for MBE formation. of the HgCdTe detectors. While silicon wafers produced by the Czochralski (CZ) process produces silicon wafers (CZ silicon wafers) having a surface with a <211> orientation, the CZ silicon wafers having thickness in the order of 100 microns are undesirable in many application because oxygen impurities therein absorb light in many frequency bands where radiation detection is required as in LWIR applications. Further, eight inch diameter CZ silicon wafers with surfaces having a <211> orientation are not readily available.
- In accordance with the present disclosure, a semiconductor structure is provided, comprising: a first semiconductor body having an upper surface with a non <211> crystallographic orientation; a second semiconductor body having a surface with a <211> crystallographic orientation, the surface of the second semiconductor body being bonded to a bottom surface of the first semiconductor body.
- In one embodiment, the structure includes a layer comprising CdTe epitaxially disposed on the upper surface of the second semiconductor body.
- In one embodiment, the second semiconductor body is CZ silicon.
- In one embodiment, the second semiconductor body has a thickness less than 10 microns.
- In one embodiment, the second semiconductor body has a diameter of at least eight inches.
- In one embodiment, the first semiconductor body and the second semiconductor body are of the same semiconductor material.
- In one embodiment, the second semiconductor body has a thickness at least an order of magnitude thinner than the thickness of the first semiconductor body.
- In one embodiment, a semiconductor structure is provided, comprising; a first semiconductor body; a getter layer; and a second semiconductor body. The getter layer has a bottom surface formed on an upper surface of the first semiconductor body and has an upper surface bonded to a bottom surface of the second semiconductor body.
- In one embodiment, the getter layer has nanocavities.
- In one embodiment, the first semiconductor body is FZ silicon.
- With such an arrangement, wafer bonding is used to bond a readily available <211> CZ wafer to an ordinary orientation Float Zone silicon wafer. After wafer bonding, the <211> CZ wafer is then thinned so that it does not appreciably absorb LWIR radiation, and the FZ wafer serves only as an LWIR transparent handle wafer. This arrangement: an LWIR compatible 8-in diameter substrate for MBE growth and focal plane arrays is obtained without having to obtain an 8-in diameter <211> FZ silicon wafer; enables placing an impurity getter layer in the benign location between the two substrates in close proximity to the HgCdTe; and eases supply chain issues associated with <211> silicon (Si) substrates. The use of wafer bonding of two more readily available wafers to replace a difficult to obtain wafer will enable the engineered silicon substrate to be a manufactured product with more predictable lead times and better quality control.
-
FIGS. 1A-1E are diagrammatical cross sectional Sketches of a process used to form an array of photo-detectors at various stages in the fabrication thereof in accordance with the disclosure; and, -
FIGS. 2A-2E are diagrammatical cross sectional sketches of a process used to form an array of photo-detectors at various stages in the fabrication thereof in accordance with another embodiment of the disclosure; - Like reference symbols in the various drawings indicate like elements.
- Referring now to
FIG. 1A , asemiconductor wafer 10, here an FZ silicon wafer, is shown. Here, thewafer 10 is an eight inch diameter wafer have an upper surface with a <100> crystallographic orientation, it should be understood that thewafer 10 here has <100>crystallographic orientation, other crystallographic orientations may be used. The thickness of thewafer 10 is here, for example, 100 microns. Also shown inFIG. 1A is asemiconductor wafer 12, here an eight inch diameter CZ silicon wafer, disposed above the upper surface ofwafer 10; thewafer 12 having a top and bottom surfaces each with a <211> crystallographic orientation. The thickness ofwafer 12 is here, for example, 100 microns, - Referring now to
FIG. 1B , the top surface ofwafer 12 and bottom surface ofwafer 12 are cleaned and polished and then bonded together in an oxide free environment to form an atomic bond between the twowafers structure 14, as indicated. Because the wafer bond interface will be silicon-to-silicon, the bonding is likely to be a combination of atomic bonding and Van der Waal's attraction. - Next, referring to
FIG. 1C , the upper surface of thewafer 12 is polished, for example using standard silicon semiconductor polishing methods to achieve a smooth, particle free surface, to reduce the thickness of thewafer 12 to awafer 12′ having a thickness thick enough for handling until it can he wafer bonded to the handle wafer, for example, as thin as 100 μm. After wafer bonding is complete, the <211> wafer can be thinned to its final thickness ˜5 μm so as not to appreciably absorb MR IR radiation. It is noted that thewafer 10 serves as a handle for thethinned wafer 12′ and that the upper surface of thethinned wafer 12; has a <211> crystallographic orientation. - Next, referring to
FIG. 1D , alayer 16 of HgCdTe is formed using MBE on the upper surface of thethinned wafer 12′. - Here, referring to
FIG. 1E , an array ofHgCdTe detectors 18 is formed in thelayer 16 using conventional photolithographic—etching processing. Thus, an array of HgCdTe photo-detectors has been formed on an eight inch diameter substrate, here thestructure 14, using MBE on a surface (the upper surface of the thinned, and hence low oxygen impurity,CZ wafer 12′) having a <211> crystallographic orientation. - Referring now to
FIG. 2A , asemiconductor wafer 20, here an FL silicon wafer, is shown. Here, thewafer 20 is an eight inch diameter wafer have an upper surface with a <100> crystallographic orientation. It should be understood that other semiconductor materials may be used as well as other crystallographic orientations for the surface. The thickness of thewafer 20 is here, for example, 100 microns. Here, the upper surface ofwafer 20 has agetter layer 21, here a layer formed with nanocavities by, for example, implanting ion of helium into the surface of either wafer at the bonding interface betweenlayers FIG. 2A . In either case, the formation of the getteringlayer 21 must occur before wafer bonding (thereby putting the gettering layer buried in the bondline between, protecting it from both the MBE growth process and the wafer fabrication process), followed by the application of heat to form bubbles in the upper surface ofwafer 20. Thegetter layer 21 to be used to trap impurities in the environment, such as, for example, copper. More particularly, the internal surfaces of the bubbles formed by the nanocavities trap the impurities. - Referring now to
FIG. 2B , the top surface ofwafer 12 and bottom surface of wafer 22 are cleaned and polished and cleaned to form oxide free surfaces and then bonded together in a clean environment to form an atomic bond between the twowafers structure 14, as indicated. Thegettering layer 21 will attract undesired metallic impurities such as copper so that the impurities will not affect the HgCdTe to be grown onto the wafer. - Next, referring to
FIG. 2C , the upper surface of thewafer 12 is polished, as described in connection withFIG. 1C to reduce the thickness of thewafer 12 to thewafer 12′ having a thickness in the range between 540 μm although it may be possible to be as thin as 2 μm if a high degree of polishing is provided. It is noted that thewafer 20 serves as a handle for the thinnedwafer 12′ and that the upper surface of the thinnedwafer 12; has a <211> crystallographic orientation. - Next, referring to
FIG. 2D , thelayer 16 of HgCdTe is formed using MBE on the upper surface of the thinnedwafer 12,′ as described in connection withFIG. 1C . - Here, referring to
FIG. 2E , an array of HgCdTe detectors is formed in thelayer 16 using conventional photolithographic—etching processing as described in connection withFIG. 1D . Thus, an array of HgCdTh photo-detectors 18 has been formed on an eight inch diameter substrate, here thestructure 14, using MBE on a surface (the upper surface of the thinned, and hence low oxygen impurity,CZ wafer 12′) having a <211> crystallographic orientation having an internal, buried,getter layer 21. - A summary of the process is as follows:
-
- 1. Obtain a growth wafer having <211> crystallographic orientation a handle wafer having a Non <211> crystallographic orientation
- 2. If not pre-thinned, then thin the <211> crystallographic orientation growth wafer to ˜100 μm.
- 3. Create a gettering layer on either one or both wafers
- 4. Bond the wafers together with gettering layer(s) at the interface
- 5. If required, thermally activate gettering layer.
- 6. Thin the <211> crystallographic orientation wafer to ˜5 μm or less to minimize LWIR loss. The surface of the thinned <211> crystallographic orientation side needs to be smooth and substantially particle free so that it is capable of supporting the epitaxial growth of HgCdTe. The backside of the handle wafer also needs to be polished to enable the transmission of IR radiation through it.
- A number of embodiments of the disclosure have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the disclosure. For example, smaller wafer diameters, variations in the growth to handle wafer such as CA to CZ or FZ to FZ. Accordingly, other embodiments are within the scope of the following claims.
Claims (11)
1. A semiconductor structure, comprising:
a first semiconductor body;
a getter layer;
a second semiconductor body;
wherein the getter layer has a bottom surface formed on an upper surface of the first semiconductor body and has an upper surface bonded to a bottom surface of the second semiconductor body.
2. The semiconductor structure recited in claim 1 wherein the second semiconductor body has a surface with a <211>.
3. The semiconductor structure recited in claim 2 including a layer comprising CdTe epitaxially disposed on the upper surface of the second semiconductor body.
4. The semiconductor structure recited in claim 3 wherein the second semiconductor body has a thickness at least an order of magnitude thinner than the thickness of the first semiconductor body.
5. The semiconductor body recited in claim 1 wherein the second semiconductor body is CZ silicon.
6. The semiconductor structure recited in claim 5 wherein the second semiconductor body has a thickness less than 10 microns.
7. The semiconductor structure recited in claim 1 wherein the first semiconductor body and the second semiconductor body are of the same semiconductor material.
8. The semiconductor structure recited in claim 1 wherein the getter layer has nanocavities.
9. The semiconductor structure recited in claim 8 wherein the second semiconductor body has a surface with a <211>.
10. The semiconductor structure recited in claim 9 including a layer comprising CdTe epitaxially disposed on the upper surface of the second semiconductor body.
11. The semiconductor structure recited in claim 1 wherein the first semiconductor body is FZ silicon.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/185,561 US20160293711A1 (en) | 2014-05-07 | 2016-06-17 | Substrate For Molecular Beam Epitaxy (MBE) HGCDTE Growth |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/271,727 US9443923B2 (en) | 2014-05-07 | 2014-05-07 | Substrate for molecular beam epitaxy (MBE) HgCdTe growth |
US15/185,561 US20160293711A1 (en) | 2014-05-07 | 2016-06-17 | Substrate For Molecular Beam Epitaxy (MBE) HGCDTE Growth |
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US14/271,727 Division US9443923B2 (en) | 2014-05-07 | 2014-05-07 | Substrate for molecular beam epitaxy (MBE) HgCdTe growth |
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US7518207B1 (en) * | 2004-03-19 | 2009-04-14 | The United States Of America As Represented By The Secretary Of The Navy | Molecular beam epitaxy growth of ternary and quaternary metal chalcogenide films |
US20100244100A1 (en) * | 2009-03-26 | 2010-09-30 | Covalent Materials Corporation | Compound semiconductor substrate |
US20130119401A1 (en) * | 2010-06-18 | 2013-05-16 | Soraa, Inc. | Large area nitride crystal and method for making it |
US20130199440A1 (en) * | 2010-04-13 | 2013-08-08 | Schmid Silicon Technology Gmbh | Monocrystalline semiconductor materials |
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US7670928B2 (en) * | 2006-06-14 | 2010-03-02 | Intel Corporation | Ultra-thin oxide bonding for S1 to S1 dual orientation bonding |
US8608894B2 (en) | 2010-11-23 | 2013-12-17 | Raytheon Company | Wafer level packaged focal plane array |
-
2014
- 2014-05-07 US US14/271,727 patent/US9443923B2/en not_active Expired - Fee Related
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2016
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US7518207B1 (en) * | 2004-03-19 | 2009-04-14 | The United States Of America As Represented By The Secretary Of The Navy | Molecular beam epitaxy growth of ternary and quaternary metal chalcogenide films |
US20100244100A1 (en) * | 2009-03-26 | 2010-09-30 | Covalent Materials Corporation | Compound semiconductor substrate |
US20130199440A1 (en) * | 2010-04-13 | 2013-08-08 | Schmid Silicon Technology Gmbh | Monocrystalline semiconductor materials |
US20130119401A1 (en) * | 2010-06-18 | 2013-05-16 | Soraa, Inc. | Large area nitride crystal and method for making it |
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US20150325661A1 (en) | 2015-11-12 |
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