US20160181180A1 - Packaged semiconductor device having attached chips overhanging the assembly pad - Google Patents

Packaged semiconductor device having attached chips overhanging the assembly pad Download PDF

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Publication number
US20160181180A1
US20160181180A1 US14/580,836 US201414580836A US2016181180A1 US 20160181180 A1 US20160181180 A1 US 20160181180A1 US 201414580836 A US201414580836 A US 201414580836A US 2016181180 A1 US2016181180 A1 US 2016181180A1
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length
chip
edge
inactive
smaller
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US14/580,836
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Alok Kumar Lohia
Reynaldo Corpuz Javier
Andy Quang Tran
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Texas Instruments Inc
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Texas Instruments Inc
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Priority to US14/580,836 priority Critical patent/US20160181180A1/en
Assigned to TEXAS INSTRUMENTS INCORPORATED reassignment TEXAS INSTRUMENTS INCORPORATED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: JAVIER, REYNALDO CORPUZ, LOHIA, ALOK KUMAR, TRAN, ANDY QUANG
Priority to US15/099,864 priority patent/US9768098B2/en
Publication of US20160181180A1 publication Critical patent/US20160181180A1/en
Abandoned legal-status Critical Current

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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10157—Shape being other than a cuboid at the active surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/183—Connection portion, e.g. seal
    • H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part

Definitions

  • Embodiments of the invention are related in general to the field of semiconductor devices and processes, and more specifically to the structure and fabrication method of packaged semiconductor devices with single or stacked chips overhanging the assembly pad.
  • chip areas have to be at least slightly smaller than assembly pad areas to allow enough space for the bulges of adhesive material.
  • a new generation of assembly pads has to be provided with a pad area larger than the one required before. In order to satisfy this need, time and money have to be expended.
  • the singulation of chips from a semiconductor wafer is performed in two steps.
  • the inactive side of the wafer receives a grid of linear grooves of a first width and a depth smaller than the wafer thickness.
  • the active side of the wafer receives a matching grid of linear slits of a second width smaller than the first width and a depth merging the slits with the respective grooves, thereby singulating chips from the wafer.
  • each chip has a large-area active side while exhibiting an overhang over the smaller-area passive side.
  • the chip maintains the active side required by the circuitry while obtaining a passive area acceptable to the available assembly pad.
  • FIG. 1 shows a cross section of a packaged semiconductor device having a chip attached to a substrate pad, wherein the active chip side is greater than the inactive chip side, forming an overhang, and at least as large as the pad.
  • FIG. 2 illustrates a cross section of another packaged semiconductor device having a chip attached to a substrate pad, wherein the active chip side is greater than the inactive chip side, forming an overhang, and greater than the pad, forming an overhang over the pad.
  • FIG. 3 depicts a cross section of yet another packaged semiconductor device having two chips vertically assembled and the stack attached to a substrate pad, wherein the active chip sides are greater than the inactive chip sides, forming overhangs, and also greater than the pad, forming also overhangs over the pad.
  • FIG. 1 illustrates an exemplary embodiment of the invention, a packaged semiconductor device generally designated 100 .
  • the device has an overall length of 4.0 mm and a thickness 141 of 0.6 mm.
  • the device includes a semiconductor chip 101 , which has an electrically active side 101 a and an opposite electrically inactive side 101 b (which may, however, include ground potential).
  • the chip thickness 120 may be about 0.20 mm.
  • active side 101 a may be characterized as the patterned side
  • inactive side 101 b may be characterized as the un-patterned side.
  • the semiconductor material may be silicon, silicon germanium, gallium arsenide, gallium nitride, or any other III-V or II-VI compound used for electronic devices.
  • Both the active side and the inactive side of the chip have rectangular or square peripheries but are not of identical size; active side 101 a has a larger circumference than inactive side 101 b.
  • active side 101 a has a larger circumference than inactive side 101 b.
  • the smaller size of the inactive side relative to the active side is indicated in the cross section of FIG. 1 by the shorter length 102 b compared to the greater length 102 a of the active side.
  • the active side 101 a is bordered by an edge with a first length, which, for brevity, is also designated 102 a.
  • the inactive side 101 b is bordered by a parallel edge having a second length 102 b smaller than the first length.
  • the inactive or un-patterned side may be smaller than the active or patterned side not along all four edges, but only along one, two, or three edges.
  • the shorter lengths may not be parallel to the greater lengths, but form an angle relative to the greater lengths.
  • FIG. 1 indicates that the surface 130 of the transition from the larger active chip side to the smaller inactive chip side may be curved in a concave sense.
  • the chips may have a linear transition surface, or a surface which starts at the edge parallel to the active chip side and then gradually changes into a concave shape.
  • the chip material close to the active surface forms an overhang over the inactive chip side.
  • the overhanging semiconductor material may have a thickness 121 of about 0.17 mm; in other devices, thickness 121 is 0.10 mm.
  • the semiconductor chip may have triangular sides or any other geometric configuration.
  • the electrically active side has a larger area than the electrically inactive or passive area, and the analogous side edges are greater for the active side than for the inactive side.
  • FIG. 1 indicates that chip 101 is attached to suitable site of a substrate.
  • the substrate may be the chip pad 110 of a metal leadframe, as shown by the example of FIG. 1 .
  • the site may be an attachment pad of a laminated substrate, or it may be the metallized pad of a board.
  • the substrate provides an assembly pad bordered by a linear edge having a third length.
  • the third length is shown as length 110 a; in this example, length 110 a is 2.5 mm.
  • the third length is equal to parallel first length shown as 102 a, allowing the chip to use the full lateral dimension of the pad. In other embodiments (see FIG. 2 ), the third length is smaller than the parallel first length.
  • the inactive chip side 101 b is attached to the pad so that the chip edge of first length is parallel to the pad edge of third length.
  • a layer of a conductive adhesive polymer is preferred as attachment material; other devices use a solder layer.
  • the layer preferably has a thickness of about 25 ⁇ m.
  • chip 101 is connected by bonding wires 160 to terminals of device 100 , which are exemplified by leadframe leads 150 .
  • leads 150 are replaced by metallic terminal pads.
  • Chip 101 , bonding wires 160 and portions of pad 110 and leads 150 are encapsulated in a packaging compound 170 , preferably an epoxy-based molding compound.
  • FIG. 2 shows an exemplary embodiment 200 , wherein a significant overhang is formed between the active chip side 201 a and the attachment pad 210 .
  • the active chip side with the edge of first length, represented by 202 a, is between about 3.05 mm and 3.55 mm, while third length 210 a of the pad is 2.5 mm.
  • the inactive chip side has an edge of second length 202 b of about 2.25 mm allowing attachment to pad 210 .
  • the overhang of the chip over the attachment pad may be formed by an undercut with a surface 230 configured to transit gently from the greater active chip side to the narrower inactive side; in the example of FIG.
  • the overhang may be along one edge of the attached chip; in other devices, the overhang may be along more than one edges, for instance along all four edges.
  • FIG. 2 indicates that in device 200 the substrate for attaching chip 201 may be a metal leadframe with pad 210 and leads 250 as terminals of packaged device 200 .
  • FIG. 1 indicates that chip 101 is attached to suitable site of a substrate.
  • attachment site 210 may be a metallized pad of a laminated substrate, or it may be the metallized pad of a board.
  • the substrate provides an assembly pad bordered by a linear edge having a third length. As FIG. 2 shows, the third length is parallel to first length.
  • the inactive chip side 102 b is attached to the pad by an adhesive layer, which may be a conductive polymer or a solder layer.
  • the layer preferably has a thickness of about 25 ⁇ m.
  • chip 201 is connected by bonding wires 260 to leads 250 as terminals of device 200 .
  • Chip 201 , bonding wires 260 and portions of pad 210 and leads 250 are encapsulated in a packaging compound 270 , preferably an epoxy-based molding compound.
  • the device thickness 241 may, for instance, be 0.6 mm; other devices may be thicker or even thinner.
  • Device 300 has a first semiconductor chip 301 with an electrically active side 301 a and an opposite electrically inactive side 301 b .
  • the active side is bordered by an edge having a first length 302 a
  • the inactive side is bordered by a parallel edge having a second length 302 b smaller than the first length 302 a.
  • the first length may be about 3.05 mm
  • the second length may be about 2.25 mm. In other devices, the lengths may be greater or smaller.
  • the active side forms an overhang over the inactive side, which may be shaped as a concave undercut.
  • the thickness 320 of first chip 301 may be about 0.2 mm; greater or smaller thicknesses are being employed.
  • Device 300 further has a second semiconductor chip 305 with an electrically active side 305 a and an opposite electrically inactive side 305 b .
  • the active side is bordered by an edge having a third length 306 a, which may be equal to, smaller than, or greater than the first length 302 a; in the example of FIG. 3 , third length 306 a is equal to first length 302 a.
  • the inactive side of second chip 305 is bordered by a parallel edge having a fourth length 306 b smaller than the third length 306 a.
  • the inactive chip side 301 b of the first chip 301 is attached to the active side 305 a of the second chip 305 .
  • the attachment is performed so that the edge of the first length 302 a is parallel to the edge of the third length 305 a.
  • a layer of a conductive adhesive polymer is preferred as attachment material; other devices use a solder layer.
  • the layer preferably has a thickness of about 25 ⁇ m.
  • First chip 301 and second chip 305 form a stack of chips.
  • the distance 307 i.e. the separation between the chips, is the sum of the thicknesses of the attachment layer and the undercut of the first chip.
  • Distance 307 may be about 0.10 mm high; at any rate, distance 307 has to be large enough to accommodate the wire arch resulting from the wire bonding operation.
  • the second chip 305 is attached to suitable site of a substrate.
  • the substrate may be the chip pad 310 of a metal leadframe, as shown for the exemplary device 300 .
  • the site may be an attachment pad of a laminated substrate, or it may be the metallized pad of a board.
  • the substrate provides an assembly pad bordered by a linear edge having a fifth length.
  • the fifth length is shown as length 310 a ; in this example, length 310 a is 2.50 mm.
  • the fifth length is smaller than parallel first length 301 a and third length 306 a, allowing the chip stack to use the space beyond the lateral dimension of pad 310 .
  • the overhang of one or both chips may be longer and even extend over a portion of the leads 350 .
  • fifth length 310 a may be equal to third length 306 a.
  • Embodiments include devices wherein the third length is equal to or smaller than the first length and the active side of the attached first chip forms an overhang over the active side of the second chip. Further, embodiments include devices wherein the fifth length is smaller than the third length and the active side of the attached second chip forms an overhang over the top pad side.
  • the inactive chip side 306 b is attached to pad 310 so that the chip edge of third length 306 a is parallel to the pad edge of fifth length 310 a. Consequently, chips 301 and 305 are assembled as a stack on pad 310 .
  • a layer of a conductive adhesive polymer is preferred as attachment material; other devices use a solder layer.
  • the layer preferably has a thickness of about 25 ⁇ m.
  • chips 301 and 305 are connected by bonding wires 360 to terminals of device 300 , which are exemplified by leadframe leads 350 .
  • leads 350 are replaced by metallic terminal pads.
  • Chips 301 and 305 , bonding wires 360 and portions of pad 310 and leads 350 are encapsulated in a packaging compound 370 , preferably an epoxy-based molding compound.
  • the height 341 of the packaged device 300 may be about 0.90 mm; however, devices may have a greater or smaller height.
  • Length 340 of the packaged device 300 may be about 4.0 mm; however, devices may have a greater or smaller length.
  • Another embodiment of the invention is a method for fabricating a semiconductor chip with an overhang of the chip side containing the active elements over the opposite side free of active elements.
  • the method starts by providing a semiconductor wafer of a first thickness, which has an electrically active side and an opposite electrically inactive side.
  • the active side includes a plurality of sites, which will become chips, containing elements such as transistors, diodes, and integrated circuitry; the fabrication of the active elements is completed.
  • the sites have linear borders between adjacent chips. As an example, the sites may have rectangular configuration with linear borders between the each adjacent site.
  • the inactive wafer side is subjected to a backgrinding technique in order to reduce the first thickness of the wafer to a second thickness smaller than the first thickness.
  • first width may be between 0.2 mm and 1.0 mm or more.
  • the grooves have a rounded bottom; alternatively, the bottom may be more triangular or cornered.
  • a matching grid of linear slits is formed on the active wafer side.
  • the slits are arrayed in parallel rows intersecting with parallel columns.
  • the preferred technique to form the slits is a mechanical saw with thin blade.
  • the slits have edges spaced by a second width smaller than the first width and a depth deep enough so that the slits can merge with the respective grooves.
  • each slit is administered about in the middle of the respective groove penetrating the wafer from the opposite side.
  • the merged slits and grooves represent effective cuts for singulating discrete rectangular chips from the wafer.
  • Each singulated chip has an electrically active side bordered by an edge having a first length, and an opposite electrically inactive side bordered by a parallel edge having a second length smaller than the first length.
  • Another embodiment of the invention is a method for fabricating a semiconductor device with a single chip with an overhang attached to a substrate.
  • the method starts by providing a semiconductor chip with an electrically active side and an opposite electrically inactive side.
  • the active side is bordered by an edge having a first length
  • the opposite inactive side is bordered by a parallel edge having a second length smaller than the first length. Consequently, the active side forms an overhang over the inactive side.
  • the second length may be 2.25 mm and the first length 3.55 mm, creating a relatively long overhang of 0.65 mm on each chip end.
  • a substrate which has an assembly pad bordered by a linear edge having a third length equal to or smaller than the first length.
  • a preferred substrate is a metal leadframe.
  • the substrate may made by laminating metal and insulating layers into a multilayer composite.
  • the substrate has a plurality of leads, which serve a terminals of the completed device; the leads are in the proximity of the pad and may surround the pad.
  • the inactive chip side is attached to the pad so that the edge of the first length is parallel to the edge of the third length. Thereafter, the chip is connected to respective substrate terminals by bonding wires. Then, the chip and the bonding wires are encapsulated in a packaging compound, for instance in an epoxy-based molding compound.
  • Another embodiment of the invention is a method for fabricating a semiconductor device having a set of vertically stacked chips with overhangs attached to a substrate.
  • the method starts by providing a first semiconductor chip with an electrically active side and an opposite electrically inactive side.
  • the active side is bordered by an edge with a first length
  • the inactive side is bordered by a parallel edge having a second length smaller than the first length.
  • the active side forms an overhang over the inactive side.
  • the second length may be 2.25 mm and the first length 3.55 mm, creating a relatively long overhang of 0.65 mm on each chip end.
  • a second semiconductor chip which has an electrically active side and an opposite electrically inactive side, the active side bordered by an edge having a third length equal to, smaller, or greater than the first length, the inactive side bordered by a parallel edge having a fourth length smaller than the third length.
  • the inactive chip side of the first chip is attached to the active side of the second chip so that the edge of the first length is parallel to the edge of the third length. Consequently, the first chip is vertically stacked on the second chip, forming a vertical chip set.
  • the active side of the attached first chip forms an overhang over the active side of the second chip.
  • a substrate which has an assembly pad bordered by a linear edge with a fifth length equal to or smaller than the third length.
  • the substrate may be a metal leadframe or a laminated board.
  • the substrate includes a plurality of leads or terminals in the proximity of the assembly pad.
  • the inactive chip side of the second chip is attached to the pad so that the edge of the third length is parallel to the edge of the fifth length.
  • the active side of the attached second chip forms an overhang over the pad.
  • the adhesive layer is preferably formed by a conductive polymer, but may also be formed by solder; in both cases, the preferred thickness of the adhesive layer is about 0.025 mm.
  • the first chip and the second chip are connected to respective substrate terminals by bonding wires. Thereafter, the chips and the bonding wires are encapsulated in a packaging compound, preferably by an epoxy-based molding compound.
  • the invention applies to two, three or more chips.
  • the invention applies to products with chips of equal thickness and to products, wherein the chips have different thicknesses.
  • the invention applies to products with chips of equal overhangs, and to products, wherein the chips have different overhangs.
  • the invention applies to any semiconductor device family which uses QFN/SON leadframes, or a leadframe with pins.
  • the invention further applies to any amount of overhang over to the attachment pads/

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Abstract

A semiconductor device (200) comprising a semiconductor chip (201) has an electrically active side (201 a) and an opposite electrically inactive side (201 b); the active side bordered by an edge having a first length (202 a), and the inactive side bordered by a parallel edge having a second length (202 b) smaller than the first length; a substrate has an assembly pad (210) bordered by a linear edge having a third length (210 a) equal to or smaller than the first length; the inactive chip side attached to the pad so that the edge of the first length is parallel to the edge of the third length; the active side of the attached chip forms an overhang over the pad, when the third length is smaller than the first length.

Description

    FIELD
  • Embodiments of the invention are related in general to the field of semiconductor devices and processes, and more specifically to the structure and fabrication method of packaged semiconductor devices with single or stacked chips overhanging the assembly pad.
    • DESCRIPTION OF RELATED ART
  • It is common practice in fabricating semiconductor devices that semiconductor chips are attached to substrate pads with an adhesive material such as a solder or a polymeric compound. In this attachment process, first a controlled amount of adhesive material is deposited on the pad, and then the chip is placed on top of the material while enough pressure is applied to distribute the material uniformly and allow a small amount of material to bulge from the chip edges. For the visual process quality control by inspectors, this bulge is indispensable as a signal of defect-free assembly.
  • As a consequence of this generally accepted quality control practice, chip areas have to be at least slightly smaller than assembly pad areas to allow enough space for the bulges of adhesive material. Whenever a new product requires a larger chip area than the preceding product, a new generation of assembly pads has to be provided with a pad area larger than the one required before. In order to satisfy this need, time and money have to be expended.
    • SUMMARY
  • Applicants realized that the ongoing market pressures for greater flexibility in satisfying customer needs and for faster product turn-around time need a quantum jump in assembling semiconductor chips on substrate pads. Applicant saw that until now a semiconductor chip has been considered an inseparable unit, wherein the active side and the passive side (which is to be attached) form an immutable hexahedron with straight sidewalls.
  • By considering the passive chip side independent from the active side, applicants solved the problem of requiring an enlarged assembly pad every time the chip size is increased, when they discovered a methodology of diminishing the area of the passive side for the attachment process while retaining the area of the active side for the circuitry.
  • In the methodology, the singulation of chips from a semiconductor wafer is performed in two steps. The inactive side of the wafer receives a grid of linear grooves of a first width and a depth smaller than the wafer thickness. Then, the active side of the wafer receives a matching grid of linear slits of a second width smaller than the first width and a depth merging the slits with the respective grooves, thereby singulating chips from the wafer.
  • As a result of the two-step singulation process, each chip has a large-area active side while exhibiting an overhang over the smaller-area passive side. As a hexahedron with concave curved sidewalls, the chip maintains the active side required by the circuitry while obtaining a passive area acceptable to the available assembly pad.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 shows a cross section of a packaged semiconductor device having a chip attached to a substrate pad, wherein the active chip side is greater than the inactive chip side, forming an overhang, and at least as large as the pad.
  • FIG. 2 illustrates a cross section of another packaged semiconductor device having a chip attached to a substrate pad, wherein the active chip side is greater than the inactive chip side, forming an overhang, and greater than the pad, forming an overhang over the pad.
  • FIG. 3 depicts a cross section of yet another packaged semiconductor device having two chips vertically assembled and the stack attached to a substrate pad, wherein the active chip sides are greater than the inactive chip sides, forming overhangs, and also greater than the pad, forming also overhangs over the pad.
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • FIG. 1 illustrates an exemplary embodiment of the invention, a packaged semiconductor device generally designated 100. The device has an overall length of 4.0 mm and a thickness 141 of 0.6 mm. The device includes a semiconductor chip 101, which has an electrically active side 101 a and an opposite electrically inactive side 101 b (which may, however, include ground potential). As an example, the chip thickness 120 may be about 0.20 mm. More generally, active side 101 a may be characterized as the patterned side, and inactive side 101 b may be characterized as the un-patterned side. The semiconductor material may be silicon, silicon germanium, gallium arsenide, gallium nitride, or any other III-V or II-VI compound used for electronic devices. Both the active side and the inactive side of the chip have rectangular or square peripheries but are not of identical size; active side 101 a has a larger circumference than inactive side 101 b. Considering analogous parallel lengths, the smaller size of the inactive side relative to the active side is indicated in the cross section of FIG. 1 by the shorter length 102 b compared to the greater length 102 a of the active side. The active side 101 a is bordered by an edge with a first length, which, for brevity, is also designated 102 a. The inactive side 101 b is bordered by a parallel edge having a second length 102 b smaller than the first length.
  • In some devices, the inactive or un-patterned side may be smaller than the active or patterned side not along all four edges, but only along one, two, or three edges. In still other devices, the shorter lengths may not be parallel to the greater lengths, but form an angle relative to the greater lengths.
  • FIG. 1 indicates that the surface 130 of the transition from the larger active chip side to the smaller inactive chip side may be curved in a concave sense. In other devices, the chips may have a linear transition surface, or a surface which starts at the edge parallel to the active chip side and then gradually changes into a concave shape. In all cases, the chip material close to the active surface forms an overhang over the inactive chip side. In the example of FIG. 1, the overhanging semiconductor material may have a thickness 121 of about 0.17 mm; in other devices, thickness 121 is 0.10 mm.
  • In other embodiments, the semiconductor chip may have triangular sides or any other geometric configuration. In all cases, though, the electrically active side has a larger area than the electrically inactive or passive area, and the analogous side edges are greater for the active side than for the inactive side.
  • FIG. 1 indicates that chip 101 is attached to suitable site of a substrate. The substrate may be the chip pad 110 of a metal leadframe, as shown by the example of FIG. 1. Alternatively the site may be an attachment pad of a laminated substrate, or it may be the metallized pad of a board. In these and other examples, the substrate provides an assembly pad bordered by a linear edge having a third length. In FIG. 1, the third length is shown as length 110 a; in this example, length 110 a is 2.5 mm. As FIG. 1 shows, the third length is equal to parallel first length shown as 102 a, allowing the chip to use the full lateral dimension of the pad. In other embodiments (see FIG. 2), the third length is smaller than the parallel first length.
  • As FIG. 1 indicates, the inactive chip side 101 b is attached to the pad so that the chip edge of first length is parallel to the pad edge of third length. For many devices, a layer of a conductive adhesive polymer is preferred as attachment material; other devices use a solder layer. The layer preferably has a thickness of about 25 μm.
  • In the device example of FIG. 1, chip 101 is connected by bonding wires 160 to terminals of device 100, which are exemplified by leadframe leads 150. In laminated substrates, leads 150 are replaced by metallic terminal pads. Chip 101, bonding wires 160 and portions of pad 110 and leads 150 are encapsulated in a packaging compound 170, preferably an epoxy-based molding compound.
  • In contrast, FIG. 2 shows an exemplary embodiment 200, wherein a significant overhang is formed between the active chip side 201 a and the attachment pad 210. The active chip side with the edge of first length, represented by 202 a, is between about 3.05 mm and 3.55 mm, while third length 210 a of the pad is 2.5 mm. The inactive chip side has an edge of second length 202 b of about 2.25 mm allowing attachment to pad 210. As FIG. 2 illustrates, the overhang of the chip over the attachment pad may be formed by an undercut with a surface 230 configured to transit gently from the greater active chip side to the narrower inactive side; in the example of FIG. 2, a portion of linear surface approximately parallel to surface 201 a morphs into a concave portion extending to surface 201 b. The methods for forming these and other surface contours see below. In some devices, the overhang may be along one edge of the attached chip; in other devices, the overhang may be along more than one edges, for instance along all four edges.
  • Similar to exemplary device 100, FIG. 2 indicates that in device 200 the substrate for attaching chip 201 may be a metal leadframe with pad 210 and leads 250 as terminals of packaged device 200. FIG. 1 indicates that chip 101 is attached to suitable site of a substrate. Alternatively, attachment site 210 may be a metallized pad of a laminated substrate, or it may be the metallized pad of a board. In these and other examples, the substrate provides an assembly pad bordered by a linear edge having a third length. As FIG. 2 shows, the third length is parallel to first length.
  • As FIG. 2 displays, the inactive chip side 102 b is attached to the pad by an adhesive layer, which may be a conductive polymer or a solder layer. The layer preferably has a thickness of about 25 μm. In exemplary device 200, chip 201 is connected by bonding wires 260 to leads 250 as terminals of device 200. Chip 201, bonding wires 260 and portions of pad 210 and leads 250 are encapsulated in a packaging compound 270, preferably an epoxy-based molding compound. The device thickness 241 may, for instance, be 0.6 mm; other devices may be thicker or even thinner.
  • Another embodiment of the invention, generally designated 300, is illustrated in FIG. 3. Device 300 has a first semiconductor chip 301 with an electrically active side 301 a and an opposite electrically inactive side 301 b. The active side is bordered by an edge having a first length 302 a, the inactive side is bordered by a parallel edge having a second length 302 b smaller than the first length 302 a. In the example of FIG. 3, the first length may be about 3.05 mm, and the second length may be about 2.25 mm. In other devices, the lengths may be greater or smaller. The active side forms an overhang over the inactive side, which may be shaped as a concave undercut. The thickness 320 of first chip 301 may be about 0.2 mm; greater or smaller thicknesses are being employed.
  • Device 300 further has a second semiconductor chip 305 with an electrically active side 305 a and an opposite electrically inactive side 305 b. The active side is bordered by an edge having a third length 306 a, which may be equal to, smaller than, or greater than the first length 302 a; in the example of FIG. 3, third length 306 a is equal to first length 302 a. The inactive side of second chip 305 is bordered by a parallel edge having a fourth length 306 b smaller than the third length 306 a.
  • As FIG. 3 shows, the inactive chip side 301 b of the first chip 301 is attached to the active side 305 a of the second chip 305. The attachment is performed so that the edge of the first length 302 a is parallel to the edge of the third length 305 a. For many devices, a layer of a conductive adhesive polymer is preferred as attachment material; other devices use a solder layer. The layer preferably has a thickness of about 25 μm. First chip 301 and second chip 305 form a stack of chips. As FIG. 3 illustrates, the distance 307, i.e. the separation between the chips, is the sum of the thicknesses of the attachment layer and the undercut of the first chip. Distance 307 may be about 0.10 mm high; at any rate, distance 307 has to be large enough to accommodate the wire arch resulting from the wire bonding operation.
  • The second chip 305 is attached to suitable site of a substrate. The substrate may be the chip pad 310 of a metal leadframe, as shown for the exemplary device 300. Alternatively, the site may be an attachment pad of a laminated substrate, or it may be the metallized pad of a board. In these and other examples, the substrate provides an assembly pad bordered by a linear edge having a fifth length. In FIG. 3, the fifth length is shown as length 310 a; in this example, length 310 a is 2.50 mm. For the exemplary device 300 in FIG. 3, the fifth length is smaller than parallel first length 301 a and third length 306 a, allowing the chip stack to use the space beyond the lateral dimension of pad 310. In other embodiments, the overhang of one or both chips may be longer and even extend over a portion of the leads 350. In yet other embodiments, fifth length 310 a may be equal to third length 306 a.
  • Embodiments include devices wherein the third length is equal to or smaller than the first length and the active side of the attached first chip forms an overhang over the active side of the second chip. Further, embodiments include devices wherein the fifth length is smaller than the third length and the active side of the attached second chip forms an overhang over the top pad side.
  • As FIG. 3 indicates, the inactive chip side 306 b is attached to pad 310 so that the chip edge of third length 306 a is parallel to the pad edge of fifth length 310 a. Consequently, chips 301 and 305 are assembled as a stack on pad 310. For many devices, a layer of a conductive adhesive polymer is preferred as attachment material; other devices use a solder layer. The layer preferably has a thickness of about 25 μm.
  • In the device example of FIG. 3, chips 301 and 305 are connected by bonding wires 360 to terminals of device 300, which are exemplified by leadframe leads 350. In laminated substrates, leads 350 are replaced by metallic terminal pads. Chips 301 and 305, bonding wires 360 and portions of pad 310 and leads 350 are encapsulated in a packaging compound 370, preferably an epoxy-based molding compound. The height 341 of the packaged device 300 may be about 0.90 mm; however, devices may have a greater or smaller height. Length 340 of the packaged device 300 may be about 4.0 mm; however, devices may have a greater or smaller length.
  • Another embodiment of the invention is a method for fabricating a semiconductor chip with an overhang of the chip side containing the active elements over the opposite side free of active elements. The method starts by providing a semiconductor wafer of a first thickness, which has an electrically active side and an opposite electrically inactive side. The active side includes a plurality of sites, which will become chips, containing elements such as transistors, diodes, and integrated circuitry; the fabrication of the active elements is completed. The sites have linear borders between adjacent chips. As an example, the sites may have rectangular configuration with linear borders between the each adjacent site.
  • In the next process, the inactive wafer side is subjected to a backgrinding technique in order to reduce the first thickness of the wafer to a second thickness smaller than the first thickness.
  • Next, a grid of linear grooves is formed in the semiconductor material of the inactive wafer side. The grooves are arrayed in parallel rows intersecting with parallel columns so that the rows and columns are at right angles to each other. The technique to form the grooves is selected from a group including laser sawing, mechanical sawing with a relatively wide blade, chemical etching, and hitting with liquid jets. The grooves such generated have edges spaced by a first width and a depth smaller than the second thickness. Dependent on device type, first width may be between 0.2 mm and 1.0 mm or more. Preferably, the grooves have a rounded bottom; alternatively, the bottom may be more triangular or cornered.
  • In the next process, a matching grid of linear slits is formed on the active wafer side. The slits are arrayed in parallel rows intersecting with parallel columns. The preferred technique to form the slits is a mechanical saw with thin blade. The slits have edges spaced by a second width smaller than the first width and a depth deep enough so that the slits can merge with the respective grooves. Preferably, each slit is administered about in the middle of the respective groove penetrating the wafer from the opposite side. After the merger of slit and grooves, the merged slits and grooves represent effective cuts for singulating discrete rectangular chips from the wafer.
  • The resulting chips have overhangs of the active side over the inactive side. Each singulated chip has an electrically active side bordered by an edge having a first length, and an opposite electrically inactive side bordered by a parallel edge having a second length smaller than the first length.
  • Another embodiment of the invention is a method for fabricating a semiconductor device with a single chip with an overhang attached to a substrate. The method starts by providing a semiconductor chip with an electrically active side and an opposite electrically inactive side. The active side is bordered by an edge having a first length, the opposite inactive side is bordered by a parallel edge having a second length smaller than the first length. Consequently, the active side forms an overhang over the inactive side. For some exemplary chips, the second length may be 2.25 mm and the first length 3.55 mm, creating a relatively long overhang of 0.65 mm on each chip end.
  • Next, a substrate is provided, which has an assembly pad bordered by a linear edge having a third length equal to or smaller than the first length. A preferred substrate is a metal leadframe. Alternatively, the substrate may made by laminating metal and insulating layers into a multilayer composite. In addition to the assembly pad, the substrate has a plurality of leads, which serve a terminals of the completed device; the leads are in the proximity of the pad and may surround the pad.
  • In the next process, the inactive chip side is attached to the pad so that the edge of the first length is parallel to the edge of the third length. Thereafter, the chip is connected to respective substrate terminals by bonding wires. Then, the chip and the bonding wires are encapsulated in a packaging compound, for instance in an epoxy-based molding compound.
  • Another embodiment of the invention is a method for fabricating a semiconductor device having a set of vertically stacked chips with overhangs attached to a substrate. The method starts by providing a first semiconductor chip with an electrically active side and an opposite electrically inactive side. The active side is bordered by an edge with a first length, the inactive side is bordered by a parallel edge having a second length smaller than the first length. As a consequence, the active side forms an overhang over the inactive side. For some exemplary chips, the second length may be 2.25 mm and the first length 3.55 mm, creating a relatively long overhang of 0.65 mm on each chip end.
  • Next, a second semiconductor chip is provided, which has an electrically active side and an opposite electrically inactive side, the active side bordered by an edge having a third length equal to, smaller, or greater than the first length, the inactive side bordered by a parallel edge having a fourth length smaller than the third length.
  • In the next process, the inactive chip side of the first chip is attached to the active side of the second chip so that the edge of the first length is parallel to the edge of the third length. Consequently, the first chip is vertically stacked on the second chip, forming a vertical chip set. For devices wherein the third length is equal to or smaller than the first length, the active side of the attached first chip forms an overhang over the active side of the second chip. After the stack set has been assembled, there has to be enough space between the overhang of the first chip and the active side of the second chip to span bonding wires from the second chip to substrate leads without contact between the wires and the underside surface of the overhang.
  • Next, a substrate is provided, which has an assembly pad bordered by a linear edge with a fifth length equal to or smaller than the third length. The substrate may be a metal leadframe or a laminated board. The substrate includes a plurality of leads or terminals in the proximity of the assembly pad. The inactive chip side of the second chip is attached to the pad so that the edge of the third length is parallel to the edge of the fifth length. For devices wherein the fifth length is smaller than the third length, the active side of the attached second chip forms an overhang over the pad. As mentioned, the adhesive layer is preferably formed by a conductive polymer, but may also be formed by solder; in both cases, the preferred thickness of the adhesive layer is about 0.025 mm.
  • In the next process, the first chip and the second chip are connected to respective substrate terminals by bonding wires. Thereafter, the chips and the bonding wires are encapsulated in a packaging compound, preferably by an epoxy-based molding compound.
  • While this invention has been described in reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. As an example, the invention applies to products using any type of semiconductor chip, discrete or integrated circuit, and the material of the semiconductor chip may comprise silicon, silicon germanium, gallium arsenide, or any other semiconductor or compound material used in integrated circuit manufacturing.
  • For products with more than one chip, the invention applies to two, three or more chips. The invention applies to products with chips of equal thickness and to products, wherein the chips have different thicknesses. The invention applies to products with chips of equal overhangs, and to products, wherein the chips have different overhangs.
  • As another example, the invention applies to any semiconductor device family which uses QFN/SON leadframes, or a leadframe with pins. The invention further applies to any amount of overhang over to the attachment pads/
  • It is therefore intended that the appended claims encompass any such modifications or embodiment.

Claims (28)

1. A semiconductor device comprising:
a semiconductor chip having an electrically active side and an opposite electrically inactive side, the active side bordered by an edge having a first length, the inactive side bordered by a parallel edge having a second length smaller than the first length;
a substrate having an assembly pad bordered by a linear edge having a third length smaller than the first length; and
the electrically inactive side attached to the pad, wherein the electrically active side of the attached chip forms an overhang over pad.
2. (canceled)
3. The device of claim 1 wherein the overhang is along one edge of the attached chip.
4. The device of claim 1 wherein the overhang is along all four edges of the attached chip.
5. The device of claim 1 further including terminals surrounding the assembly pad, wherein the attached chip is connected to respective terminals by bonding wires.
6. The device of claim 5 wherein the assembly pad and the terminals are parts of a metal leadframe.
7. The device of claim 5 wherein the assembly pad and the terminals are metal layers and are integral to a laminated substrate.
8. The device of claim 5 further including a package encapsulating the chip, the bonding wires, and at least portions of the assembly pad and terminals.
9. A semiconductor device comprising:
a first semiconductor chip having an electrically active side and an opposite electrically inactive side, the active side bordered by an edge having a first length, the inactive side bordered by a parallel edge having a second length smaller than the first length;
a second semiconductor chip having an electrically active side and an opposite electrically inactive side, the active side bordered by an edge having a third length equal to, smaller than, or greater than the first length, the inactive side bordered by a parallel edge having a fourth length smaller than the third length;
the inactive chip side of the first chip attached to the active side of the second chip so that the edge of the first length is parallel to the edge of the third length;
an assembly pad having a top side bordered by an edge with a fifth length equal to or smaller than the third length; and
the inactive chip side of the second chip attached to the top pad side so that the edge of the third length is parallel to the edge of the fifth length, wherein the chips are assembled as a stack on the pad.
10. The device of claim 9 wherein the third length is equal to or smaller than the first length and the active side of the attached first chip forms an overhang over the active side of the second chip.
11. The device of claim 9 wherein the fifth length is smaller than the third length and the active side of the attached second chip forms an overhang over the top pad side.
12. The device of claim 9 further including terminals surrounding the assembly pad, wherein the attached chips are connected to respective terminals by bonding wires.
13. The device of claim 12 wherein the assembly pad and the terminals are parts of a metal leadframe.
14. The device of claim 12 wherein the assembly pad and the terminals are metal layers and are integral to a laminated substrate.
15. The device of claim 12 further including a package encapsulating the chips, the bonding wires, and at least portions of the assembly pad and terminals.
16. A method for fabricating a semiconductor chip comprising:
providing a semiconductor wafer of a first thickness having an electrically active side and an opposite electrically inactive side, the wafer including a plurality of device chips having linear borders between adjacent chips;
backgrinding the inactive wafer side to reduce the first wafer thickness to a smaller second thickness;
forming on the inactive wafer side a grid of linear grooves arrayed in parallel rows intersecting with parallel columns, the rows and columns at right angle to each other, the grooves having edges spaced by a first width and a depth smaller than the second thickness; and
forming on the active wafer side a matching grid of linear slits arrayed in parallel rows intersecting with parallel columns, the slits having edges spaced by a second width smaller than the first width and a depth merging with respective grooves, wherein merged slits and grooves form cuts singulating discrete rectangular chips from the wafer.
17. The method of claim 16, wherein each singulated chip has an electrically active side bordered by an edge having a first length, and an opposite electrically inactive side bordered by a parallel edge having a second length smaller than the first length.
18. The method of claim 17 wherein the active side forms an overhang over the inactive side.
19. The method of claim 16 wherein the technique to form the grooves is selected from a group including laser saw, mechanical saw with wide blade, chemical etchant, and liquid jet.
20. The method of claim 16 wherein the technique to form the slits is a mechanical saw with thin blade.
21. A method for fabricating a semiconductor device comprising:
providing a semiconductor chip having an electrically active side and an opposite electrically inactive side, the active side bordered by an edge having a first length, the inactive side bordered by a parallel edge having a second length smaller than the first length;
providing a substrate having an assembly pad bordered by a linear edge having a third length smaller than the first length; and
attaching the inactive chip side to the pad.
22. The method of claim 21 wherein the substrate further includes terminals surrounding the assembly pad.
23. The method of claim 22 further including the processes of:
connecting the chip to respective substrate terminals by bonding wires; and
encapsulating the chip and bonding wires in a packaging compound.
24. A method for fabricating a semiconductor device comprising:
providing a first semiconductor chip having an electrically active side and an opposite electrically inactive side, the active side bordered by an edge having a first length, the inactive side bordered by a parallel edge having a second length smaller than the first length;
providing a second semiconductor chip having an electrically active side and an opposite electrically inactive side, the active side bordered by an edge having a third length equal to, smaller, or greater than the first length, the inactive side bordered by a parallel edge having a fourth length smaller than the third length;
attaching the inactive chip side of the first chip to the active side of the second chip so that the edge of the first length is parallel to the edge of the third length;
providing a substrate having an assembly pad bordered by a linear edge with a fifth length equal to or smaller than the third length; and
attaching the inactive chip side of the second chip to the pad so that the edge of the third length is parallel to the edge of the fifth length.
25. The method of claim 24 wherein the third length is equal to or smaller than the first length and the active side of the attached first chip forms an overhang over the active side of the second chip.
26. The method of claim 24 wherein the fifth length is smaller than the third length and the active side of the attached second chip forms an overhang over the pad.
27. The method of claim 24 wherein the substrate further includes terminals surrounding the assembly pad.
28. The method of claim 27 further including the processes of:
connecting the chips to respective substrate terminals by bonding wires; and
encapsulating the chips and bonding wires in a packaging compound.
US14/580,836 2014-12-23 2014-12-23 Packaged semiconductor device having attached chips overhanging the assembly pad Abandoned US20160181180A1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10199312B1 (en) * 2017-09-09 2019-02-05 Amkor Technology, Inc. Method of forming a packaged semiconductor device having enhanced wettable flank and structure
US20190074431A1 (en) * 2017-09-04 2019-03-07 Rohm Co., Ltd. Semiconductor device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9893058B2 (en) * 2015-09-17 2018-02-13 Semiconductor Components Industries, Llc Method of manufacturing a semiconductor device having reduced on-state resistance and structure

Family Cites Families (50)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5019943A (en) * 1990-02-14 1991-05-28 Unisys Corporation High density chip stack having a zigzag-shaped face which accommodates connections between chips
AU4242693A (en) * 1992-05-11 1993-12-13 Nchip, Inc. Stacked devices for multichip modules
US5952725A (en) * 1996-02-20 1999-09-14 Micron Technology, Inc. Stacked semiconductor devices
US6351028B1 (en) * 1999-02-08 2002-02-26 Micron Technology, Inc. Multiple die stack apparatus employing T-shaped interposer elements
KR20010056618A (en) * 1999-12-16 2001-07-04 프랑크 제이. 마르쿠치 Semiconductor package
KR100426494B1 (en) * 1999-12-20 2004-04-13 앰코 테크놀로지 코리아 주식회사 Semiconductor package and its manufacturing method
US6342730B1 (en) * 2000-01-28 2002-01-29 Advanced Semiconductor Engineering, Inc. Low-pin-count chip package and manufacturing method thereof
US20020096754A1 (en) * 2001-01-24 2002-07-25 Chen Wen Chuan Stacked structure of integrated circuits
KR100407472B1 (en) * 2001-06-29 2003-11-28 삼성전자주식회사 Chip-Stacked Package Device Having Upper Chip Provided With Corner Trenchs And Method For Manufacturing the Same
JP2003023239A (en) * 2001-07-05 2003-01-24 Sumitomo Electric Ind Ltd Circuit board and its manufacturing method and high output module
JP2003023134A (en) * 2001-07-09 2003-01-24 Hitachi Ltd Semiconductor device and its manufacturing method
US7084488B2 (en) * 2001-08-01 2006-08-01 Fairchild Semiconductor Corporation Packaged semiconductor device and method of manufacture using shaped die
US6759745B2 (en) * 2001-09-13 2004-07-06 Texas Instruments Incorporated Semiconductor device and manufacturing method thereof
US7332819B2 (en) * 2002-01-09 2008-02-19 Micron Technology, Inc. Stacked die in die BGA package
US20030111720A1 (en) * 2001-12-18 2003-06-19 Tan Lan Chu Stacked die semiconductor device
JP3507059B2 (en) * 2002-06-27 2004-03-15 沖電気工業株式会社 Stacked multi-chip package
US20040026768A1 (en) * 2002-08-08 2004-02-12 Taar Reginald T. Semiconductor dice with edge cavities
JP2004296897A (en) * 2003-03-27 2004-10-21 Seiko Epson Corp Semiconductor device, electron device, electronic equipment and method for manufacturing semiconductor device
US6894376B1 (en) * 2003-06-09 2005-05-17 National Semiconductor Corporation Leadless microelectronic package and a method to maximize the die size in the package
US6927479B2 (en) * 2003-06-25 2005-08-09 St Assembly Test Services Ltd Method of manufacturing a semiconductor package for a die larger than a die pad
SG153627A1 (en) * 2003-10-31 2009-07-29 Micron Technology Inc Reduced footprint packaged microelectronic components and methods for manufacturing such microelectronic components
US8324725B2 (en) * 2004-09-27 2012-12-04 Formfactor, Inc. Stacked die module
US7675153B2 (en) * 2005-02-02 2010-03-09 Kabushiki Kaisha Toshiba Semiconductor device having semiconductor chips stacked and mounted thereon and manufacturing method thereof
US7687919B2 (en) * 2005-08-10 2010-03-30 Stats Chippac Ltd. Integrated circuit package system with arched pedestal
US7365417B2 (en) * 2006-01-06 2008-04-29 Stats Chippac Ltd. Overhang integrated circuit package system
US7667333B2 (en) * 2006-01-27 2010-02-23 Infineon Technologies Ag Stack of semiconductor chips
US8492906B2 (en) * 2006-04-28 2013-07-23 Utac Thai Limited Lead frame ball grid array with traces under die
US8460970B1 (en) * 2006-04-28 2013-06-11 Utac Thai Limited Lead frame ball grid array with traces under die having interlocking features
US8461694B1 (en) * 2006-04-28 2013-06-11 Utac Thai Limited Lead frame ball grid array with traces under die having interlocking features
US8344487B2 (en) * 2006-06-29 2013-01-01 Analog Devices, Inc. Stress mitigation in packaged microchips
JP2008172123A (en) * 2007-01-15 2008-07-24 Renesas Technology Corp Semiconductor device
KR100846096B1 (en) * 2007-04-30 2008-07-14 삼성전자주식회사 Multi chip package and method of manufacturing the same
US7838974B2 (en) * 2007-09-13 2010-11-23 National Semiconductor Corporation Intergrated circuit packaging with improved die bonding
US8143102B2 (en) * 2007-10-04 2012-03-27 Stats Chippac Ltd. Integrated circuit package system including die having relieved active region
US7923846B2 (en) * 2007-11-16 2011-04-12 Stats Chippac Ltd. Integrated circuit package-in-package system with wire-in-film encapsulant
US8294251B2 (en) * 2008-06-30 2012-10-23 Sandisk Technologies Inc. Stacked semiconductor package with localized cavities for wire bonding
US8470640B2 (en) * 2008-06-30 2013-06-25 Sandisk Technologies Inc. Method of fabricating stacked semiconductor package with localized cavities for wire bonding
US8039311B2 (en) * 2008-09-05 2011-10-18 Stats Chippac Ltd. Leadless semiconductor chip carrier system
US7911067B2 (en) * 2008-09-22 2011-03-22 Stats Chippac Ltd. Semiconductor package system with die support pad
JP2011159942A (en) * 2010-01-06 2011-08-18 Renesas Electronics Corp Electronic device and method of manufacturing the electronic device
CN102208389B (en) * 2010-04-28 2014-02-26 先进封装技术私人有限公司 Semiconductor package, substrate and manufacturing method thereof
KR101855294B1 (en) * 2010-06-10 2018-05-08 삼성전자주식회사 Semiconductor package
US20130001761A1 (en) * 2011-07-03 2013-01-03 Rogren Philip E Lead carrier with thermally fused package components
US9171790B2 (en) * 2012-05-30 2015-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package devices and methods of packaging semiconductor dies
DE112014001686T5 (en) * 2013-03-26 2015-12-24 Ps4 Luxco S.A.R.L. Semiconductor device
US9318451B2 (en) * 2013-10-31 2016-04-19 Freescale Semiconductor, Inc. Wirebond recess for stacked die
EP2947692B1 (en) * 2013-12-20 2020-09-23 Analog Devices, Inc. Integrated device die and package with stress reduction features
KR102137063B1 (en) * 2014-03-20 2020-07-23 에스케이하이닉스 주식회사 Semiconductor chip and semiconductor package having the same
KR102163708B1 (en) * 2014-04-18 2020-10-12 에스케이하이닉스 주식회사 Semiconductor package and the method for fabricating of the same
US20160005679A1 (en) * 2014-07-02 2016-01-07 Nxp B.V. Exposed die quad flat no-leads (qfn) package

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190074431A1 (en) * 2017-09-04 2019-03-07 Rohm Co., Ltd. Semiconductor device
US10535812B2 (en) * 2017-09-04 2020-01-14 Rohm Co., Ltd. Semiconductor device
US10944046B2 (en) * 2017-09-04 2021-03-09 Rohm Co., Ltd. Semiconductor device
US10199312B1 (en) * 2017-09-09 2019-02-05 Amkor Technology, Inc. Method of forming a packaged semiconductor device having enhanced wettable flank and structure
US20190148270A1 (en) * 2017-09-09 2019-05-16 Amkor Technology, Inc. Method of forming a packaged semiconductor device having enhanced wettable flank and structure
US10529655B2 (en) * 2017-09-09 2020-01-07 Amkor Technology, Inc. Method of forming a packaged semiconductor device having enhanced wettable flank and structure
US10825755B2 (en) * 2017-09-09 2020-11-03 Amkor Technology Singapore Holding Pte. Ltd. Method of forming a packaged semiconductor device having enhanced wettable flank and structure
US11410916B2 (en) * 2017-09-09 2022-08-09 Amkor Technology Singapore Holding Pte. Ltd. Method of forming a packaged semiconductor device having enhanced wettable flank and structure
US20230026949A1 (en) * 2017-09-09 2023-01-26 Amkor Technology Singapore Holding Pte. Ltd. Method of forming a packaged semiconductor device having enhanced wettable flank and structure
US11862539B2 (en) * 2017-09-09 2024-01-02 Amkor Technology Singapore Holding Pte. Ltd. Method of forming a packaged semiconductor device having enhanced wettable flank and structure

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Owner name: TEXAS INSTRUMENTS INCORPORATED, TEXAS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LOHIA, ALOK KUMAR;JAVIER, REYNALDO CORPUZ;TRAN, ANDY QUANG;REEL/FRAME:034669/0969

Effective date: 20150105

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION