US20140312928A1

US20140312928A1 - High-Speed Current Steering Logic Output Buffer

Info

Publication number: US20140312928A1
Application number: US13/898,725
Authority: US
Inventors: Sharat Ippili
Original assignee: Kool Chip Inc
Current assignee: Soctronics Inc
Priority date: 2013-04-19
Filing date: 2013-05-21
Publication date: 2014-10-23
Also published as: US9948310B2; US20140314190A1; US20140312946A1; US20140312945A1; US9337846B2; US20160246325A1; US8952737B2; US9467149B2; US20140317434A1; US20140317432A1; US9564905B2

Abstract

A current steering logic buffer for generating an output clock signal, comprises: a buffer for receiving an input clock signal; a current source; switches controlled by the buffer, wherein the switches connect the current source to outputs for generating the output clock signal; and a feedback loop for controlling the current source as a function of the outputs and a reference voltage.

Description

CROSS REFERENCE

This application claims priority from a provisional patent application entitled “Apparatuses, Methods, and Systems Using Integrated Circuits” filed on Apr. 19, 2013 and having an Application No. 61/814,153. Said application is incorporated herein by reference.

FIELD OF INVENTION

This invention generally relates to a high-speed current steering logic (“HCSL”) output buffer, and, in particular, to a low jitter internally biased HCSL output buffer for peripheral component interconnect express.

BACKGROUND

Peripheral component interconnect express (“PCI-Express”) is a high performance, generic and scalable interconnect bus system for a wide variety of applications ranging from personal computers to embedded applications. PCI-Express implements a serial, full duplex, multi-lane, point-to-point interconnect, packet-based, and switch based technology.
In PCI-Express, a clock signal is distributed throughout the system to control the timing of the system operation. When data is transmitted to another portion of a circuit board or across wires to another part of the computer system, a clock signal can also be distributed throughout the computer system for sampling of that data. The clock signal will generally pass through several levels of buffering in a tree-like structure.
Conventional techniques for extending the strength of the distributed clock signal suffer from various shortcomings. For example, in an approach commonly referred to as inductive peaking, an on-chip spiral inductor is added in series with a resistive load device of a differential amplifier. The inductor is sized so that, at the specified operating frequency of the circuit, the reactance of the inductor partially cancels the reactance of the parasitic capacitance at the output of the differential pair. However, inductive peaking suffers from undesirable characteristics, including for example, a frequency dependent gain which may present a problem for low speed functionality. It also has a frequency dependent delay, particularly near the resonant frequency of the peaking. This can present a problem if the delay of the clock signal needs to be controlled with respect to other delays in the circuit. Also, the area of on-chip spiral inductors is generally quite large, on the order of a factor of ten times, as compared to the area of a typical logic gate. Finally, a circuit with inductive peaking is of limited use in buffering an arbitrary data signal with unknown frequency components.
PCI-Express applications require a very low jitter clock signal from a reference PLL of the computer system. This low jitter clock is driven by an HCSL buffer on the computer board system. Typically, the HCSL buffer uses an external resistor to control the output current of the HCSL buffer. However, this results in several drawbacks including having to use an extra pad.
Therefore, it is desirable to present methods and circuits for an HCSL buffer that is internally biased to generate differential output signals for the output clock and that has low jitter.

SUMMARY OF INVENTION

An object of this invention is to provide methods and circuits for a low jitter clock signal driven by an HCSL buffer.
Another object of this invention is to provide methods and circuits for an HCSL buffer using an internally referenced current source to generate an output clock signal.
Yet another object of this invention is to provide methods and circuits for an HCSL buffer that converts current mode level logic level inputs from an internal core supply to an output supply domain.
Briefly, the present invention discloses a current steering logic buffer for generating an output clock signal for PCI-Express applications, comprising: a buffer for receiving an input clock signal; a current source; switches controlled by the buffer, wherein the switches connect the current source to outputs for generating the output clock signal; and a feedback loop for controlling the current source as a function of the outputs and a reference voltage.
An advantage of this invention is that methods and circuits for a low jitter clock signal driven by an HCSL buffer are provided.
Another advantage of this invention is that methods and circuits for an HCSL buffer using an internally referenced current source to generate an output clock signal are provided.
Yet another advantage of this invention is that methods and circuits for an HCSL buffer that converts current mode level logic level inputs from an internal core supply, e.g., ranging from 1V to 1.8V, to an output supply domain are provided.

DESCRIPTION OF THE DRAWINGS

The foregoing and other objects, aspects, and advantages of the invention can be better understood from the following detailed description of the preferred embodiment of the invention when taken in conjunction with the accompanying drawings in which:

FIG. 1 illustrates a block diagram having phase locked loops and an HCSL buffer of the present invention interconnected for distributing a clock signal.

FIG. 2 illustrates a circuit diagram for an HCSL buffer of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following detailed description of the embodiments, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration of specific embodiments in which the present invention may be practiced.
FIG. 1 illustrates a block diagram having phase locked loops and an HCSL buffer of the present invention interconnected for distributing a clock signal. A computer system (not shown) can comprise various computer chips 2, 4, and 6 to perform various functions for the computer system. For PCI-Express, the computer system also comprises an HCSL buffer 100 of the present invention to retransmit a clock signal from one area of the computer system to another area of the computer system, e.g., from one computer chip to another computer chip. The clock signal can be transmitted to these computer chips 2, 4, and 6 either directly from the computer system, relayed by a PLL, or regenerated by the HCSL buffer 100.
The computer chip 2 can comprise PLLs 1, 2, and 3 and the HCSL buffer 100. The computer chip 2 can receive the clock signal as differential signals refclk_p and refclk_n from the computer system. The differential signals refclk_p and refclk_n are inputted to the PLL 1 from an external source, e.g., a crystal oscillator. The PLL 1 can relay the differential signals i_refclk_p and i_refclk_n to the PLLs 2 and 3 and to the HCSL buffer 100. The HCSL buffer 100 can receive the differential signals i_refclk_p and i_refclk_n in current mode logic (“CML”) levels, and then transmit strengthened differential signals o_refclk_p and o_refclk_n to the computer chips 4 and 6 for use by the PLLs 4-7 and/or to other areas on the computer system. Thus, the HCSL buffer 100 can drive multiple PLLs in other computer chips or other areas of the computer system.
FIG. 2 illustrates a circuit diagram for an HCSL buffer of the present invention. The HCSL buffer 100 of the present invention comprises a buffer 10, a current source 12, an operational amplifier 14, switches 16 and 18, a sampling circuit 20, and a capacitor 22. A termination circuit 24 can be connected to the output of the HCSL buffer 100.
The HCSL buffer 100 converts current mode logic level inputs from an internal core supply to HCSL levels at the output. Typically, HCSL levels are higher than the CML level inputs. The HCSL buffer 100 uses an internal reference in conjunction with a common mode feedback amplifier to bias the current source 12 to HCSL levels. In this manner, the output signals of the HCSL buffer 100 can be within a predefined tolerance of the HCSL levels (e.g., +/−10% of the HCSL levels) based upon the load conditions of the respective computer system for the HCSL buffer 100.
Differential signals i_refclk_p and i_refclk_n can be from the current mode logic from the computer system, which is inputted to the buffer 10. The differential signals i_refclk_p and i_refclk_n represent an input clock signal that is an internal reference clock for the computer system. The output of the HCSL buffer 100 can be forwarded off chip to other circuits, other computer chips, and other areas on the computer system.
The differential signals i_refclk_p and i_refclk_n are buffered by the buffer 10 to drive the switches 16 and 18. The switches 16 and 18 can be transistors, e.g., a PMOS or other types of transistors. The switches 16 and 18 serve to connect the current source 12 to the outputs of the HCSL buffer 100 for generating differential output signals o_refclk_p and o_refclk_n, which form an output clock signal that can be transmitted to other areas of the computer system. The outputs of the HCSL buffer 100 are sensed by the sampling circuit 20.
The sampling circuit 20 internally samples the HCSL buffer 100's output voltages. The sampling circuit 20 outputs a sampled voltage to the operational amplifier 14 for comparison to a reference voltage Vref. The operational amplifier 14 can also be a summing or subtractor circuit. The reference voltage Vref is internally generated by a band gap voltage generator (not shown). The band gap reference voltage can be internal to the buffer 100, such that external biasing, external resistors, and/or external pads are not necessary for the generation of the reference voltage. The reference voltage Vref can be set to the common mode voltage, e.g., an average voltage at the outputs of the HCSL buffer 100. Typical values for the reference voltage Vref can be 0.35 Volts +/−50 millivolts, or other voltage values as desired. Based upon this comparison, the operational amplifier 14 can equalize the differential output signals o_refclk_p and o_refclk_n of the HCSL buffer 100 to within a predefined tolerance of the HCSL levels.
The operational amplifier 14 provides a control signal to the current source 12 to control the current output of the current source 12. The current source 12 can be implemented by PMOS devices or by another implementation for a current source. For PCI-Express applications, the output of the current source 12 can be set to a predefined current amount for PCI-Express, e.g., about 14 mA. The current source 12 can be operated in an internal feedback loop to produce a current at the output of the HCSL buffer 100 within a predefined tolerance of the HCSL levels. For instance, if the current at the output of the HCSL buffer 100 is around 14 mA and assuming the termination circuit 24 is equivalent to 50 Ohms, then the output voltages of the HCSL buffer 100 are about 700 mV. In addition, an enable signal i_oe can be inputted to the current source 12 to enable and disable the current source as needed or desired.
The output of the sampling circuit 20 is connected to the capacitor 22 which is in a feedback loop to help stabilize the loop. The outputs of the HCSL buffer 100 can be connected to the termination circuit 24. Additionally, the differential output signals o_refclk_p and o_refclk_n can be outputted to other phase locked loops. Generally, the voltage level of the input differential signals i_refclk_p and i_refclk_p are internal to the chip and is set to a predefined level. However, if the differential signals i_refclk_p and i_refclk_p are outputted to somewhere else on the computer system, then the HCSL buffer 100 can strengthen the differential signals i_refclk_p and i_refclk_p for transmission.
While the present invention has been described with reference to certain preferred embodiments or methods, it is to be understood that the present invention is not limited to such specific embodiments or methods. Rather, it is the inventor's contention that the invention be understood and construed in its broadest meaning as reflected by the following claims. Thus, these claims are to be understood as incorporating not only the preferred apparatuses, methods, and systems described herein, but all those other and further alterations and modifications as would be apparent to those of ordinary skilled in the art.

Claims

We claim:

1. A current steering logic buffer for generating an output clock signal, comprising:

a buffer for receiving an input clock signal;

a current source;

switches controlled by the buffer, wherein the switches connect the current source to outputs for generating the output clock signal; and

a feedback loop for controlling the current source as a function of the outputs and a reference voltage.

2. The current steering logic buffer of claim 1 wherein the feedback loop comprises an operational amplifier, and wherein the operational amplifier compares the reference voltage and a sampled voltage from the outputs to control the current source.

3. The current steering logic buffer of claim 2 further comprising a sampling circuit for generating the sampled voltage.

4. The current steering logic buffer of claim 3 wherein the sampling circuit comprises serially-connected resistors connected across the outputs and serially-connected capacitors connected across the outputs, and wherein the serially-connected resistors and the serially-connected capacitors have a common node for determining the sampled voltage.

5. The current steering logic buffer of claim 4 wherein the common node is connected to a capacitor for stabilizing the sampled voltage.

6. The current steering logic buffer of claim 1 wherein the input clock signal is a differential signal in accordance with current mode logic levels.

7. The current steering logic buffer of claim 1 wherein the output clock signal is a differential signal in accordance with high-speed current steering logic (“HCSL”) levels.

8. The current steering logic buffer of claim 7 wherein the output clock signal supports multiple HCSL levels by setting the reference voltage to one or more predefined voltages.

9. The current steering logic buffer of claim 1 wherein the buffer has a first buffer output and a second buffer output, wherein the switches comprise a first switch and a second switch, wherein the first buffer output is connected to the first switch, and wherein the second buffer output is connected to the second switch.

10. The current steering logic buffer of claim 1 wherein the logic buffer further comprising a band gap voltage generator to generate the internally-generated reference voltage.

11. A current steering logic buffer for generating an output clock signal for PCI-Express applications, comprising:

a buffer for receiving an input clock signal, wherein the input clock signal is a differential signal in accordance with current mode logic levels;

a current source;

switches controlled by the buffer, wherein the switches connect the current source to outputs for generating the output clock signal and wherein the output clock signal is a differential signal in accordance with high-speed current steering logic (“HCSL”) levels; and

a feedback loop for controlling the current source as a function of the outputs and an internally generated reference voltage,

wherein the feedback loop comprises an operational amplifier, and

wherein the operational amplifier compares the reference voltage and a sampled voltage from the outputs to control the current source.

12. The current steering logic buffer of claim 11 further comprising a sampling circuit for generating the sampled voltage.

13. The current steering logic buffer of claim 12 wherein the sampling circuit comprises serially-connected resistors connected across the outputs and serially-connected capacitors connected across the outputs, and wherein the serially-connected resistors and the serially-connected capacitors have a common node for determining the sampled voltage.

14. The current steering logic buffer of claim 13 wherein the common node is connected to a capacitor for stabilizing the sampled voltage.

15. The current steering logic buffer of claim 11 wherein the output clock signal supports multiple HCSL levels by setting the reference voltage to one or more predefined voltages.

16. The current steering logic buffer of claim 11 wherein the buffer has a first buffer output and a second buffer output, wherein the switches comprise a first switch and a second switch, wherein the first buffer output is connected to the first switch, and wherein the second buffer output is connected to the second switch.

17. The current steering logic buffer of claim 11 wherein the logic buffer further comprising a band gap voltage generator to generate the internally-generated reference voltage.

18. A current steering logic buffer for generating an output clock signal for PCI-Express applications, comprising:

a current source;

switches controlled by the buffer, wherein the switches connect the current source to outputs for generating the output clock signal, wherein the output clock signal is a differential signal in accordance with high-speed current steering logic (“HCSL”) levels, and wherein the output clock signal supports multiple HCSL levels by setting the reference voltage to one or more predefined voltages;

a feedback loop for controlling the current source as a function of the outputs and an internally generated reference voltage; and

a sampling circuit for generating the sampled voltage, wherein the sampling circuit comprises serially-connected resistors connected across the outputs and serially-connected capacitors connected across the outputs, wherein the serially-connected resistors and the serially-connected capacitors have a common node for determining the sampled voltage, and wherein the common node is connected to a capacitor for stabilizing the sampled voltage,

wherein the feedback loop comprises an operational amplifier, and

wherein the operational amplifier compares the reference voltage and the sampled voltage from the outputs to control the current source.

19. The current steering logic buffer of claim 18 wherein the buffer has a first buffer output and a second buffer output, wherein the switches comprise a first switch and a second switch, wherein the first buffer output is connected to the first switch, and wherein the second buffer output is connected to the second switch.

20. The current steering logic buffer of claim 18 wherein the logic buffer further comprising a band gap voltage generator to generate the internally-generated reference voltage.