US20140273525A1 - Atomic Layer Deposition of Reduced-Leakage Post-Transition Metal Oxide Films - Google Patents
Atomic Layer Deposition of Reduced-Leakage Post-Transition Metal Oxide Films Download PDFInfo
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- US20140273525A1 US20140273525A1 US14/019,961 US201314019961A US2014273525A1 US 20140273525 A1 US20140273525 A1 US 20140273525A1 US 201314019961 A US201314019961 A US 201314019961A US 2014273525 A1 US2014273525 A1 US 2014273525A1
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- purge
- precursor
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- metal oxide
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- 238000000231 atomic layer deposition Methods 0.000 title abstract description 17
- 229910001848 post-transition metal Inorganic materials 0.000 title 1
- 238000010926 purge Methods 0.000 claims abstract description 43
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 30
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 30
- 238000000034 method Methods 0.000 claims description 50
- 239000002243 precursor Substances 0.000 claims description 35
- 230000008569 process Effects 0.000 claims description 25
- 239000000758 substrate Substances 0.000 claims description 25
- 239000001301 oxygen Substances 0.000 claims description 16
- 229910052760 oxygen Inorganic materials 0.000 claims description 16
- 229910052751 metal Inorganic materials 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 13
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 11
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 10
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 10
- 229910052782 aluminium Inorganic materials 0.000 claims description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 7
- 239000011261 inert gas Substances 0.000 claims description 7
- 229910052786 argon Inorganic materials 0.000 claims description 5
- 239000001307 helium Substances 0.000 claims description 5
- 229910052734 helium Inorganic materials 0.000 claims description 5
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 5
- 229910052757 nitrogen Inorganic materials 0.000 claims description 5
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 claims description 5
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims description 4
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 claims description 3
- 229910052735 hafnium Inorganic materials 0.000 claims description 3
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 claims description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 3
- 229910052726 zirconium Inorganic materials 0.000 claims description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 abstract description 8
- 230000002035 prolonged effect Effects 0.000 abstract description 4
- 238000007254 oxidation reaction Methods 0.000 abstract description 3
- 239000003989 dielectric material Substances 0.000 abstract description 2
- 238000001465 metallisation Methods 0.000 abstract description 2
- 230000003647 oxidation Effects 0.000 abstract description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract 1
- 229910052593 corundum Inorganic materials 0.000 abstract 1
- 229910001845 yogo sapphire Inorganic materials 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 38
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 19
- 239000010408 film Substances 0.000 description 14
- 238000012360 testing method Methods 0.000 description 10
- 239000000463 material Substances 0.000 description 9
- 239000004020 conductor Substances 0.000 description 8
- 239000007789 gas Substances 0.000 description 8
- 239000000377 silicon dioxide Substances 0.000 description 7
- 230000007423 decrease Effects 0.000 description 6
- 238000000151 deposition Methods 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 230000005641 tunneling Effects 0.000 description 5
- 230000008021 deposition Effects 0.000 description 4
- 229910000449 hafnium oxide Inorganic materials 0.000 description 4
- -1 Al2O3 Chemical class 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 229910001928 zirconium oxide Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 239000006227 byproduct Substances 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910004200 TaSiN Inorganic materials 0.000 description 1
- 229910008482 TiSiN Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910008807 WSiN Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000001351 cycling effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910000314 transition metal oxide Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
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- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
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- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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Definitions
- SiO 2 Silicon dioxide
- SiO 2 a gate dielectric used in larger scale devices, would need to be ⁇ 1.5 nm thick to be used in a sub-100 nm MOSFET device.
- SiO 2 is subject to high tunneling leakage in thicknesses ⁇ 2 nm. The tunneling leakage increases power consumption and reduces device reliability.
- Materials with dielectric constants, k, greater than the SiO 2 's value of 3.9 (“high-k materials”) have been studied as replacements for SiO 2 .
- EOT equivalent oxide thickness
- Tunneling is not the only source of unwanted leakage current that inhibits progress in fabricating reliable smaller-scale transistors (and other components, such as memory cells).
- Material properties such as mobile charge-carrying defects and metallic nanoclusters that can form in metal-oxide layers subjected to sufficiently strong electric fields, facilitate leakage by other mechanisms that cannot be mitigated by simply thickening the layer. These material properties are often highly dependent on process conditions and methods of forming the high-k layers, but the variables can be challenging to measure and correct.
- films of aluminum oxide (Al 2 O 3 ) and other metal oxides such as hafnium oxide (HfO x ) and zirconium oxide (ZrO x ) are prone to high or inconsistent leakage current at thicknesses of 2-10 ⁇ .
- Metal-oxide films made by atomic layer deposition are formed by alternating cycles of metal deposition and oxidation (“A-B cycling”). Each cycle deposits a monolayer of metal oxide. Each cycle includes exposing the substrate to a metal precursor; purging the chamber to remove unreacted precursors and by-products; exposing the substrate to an oxygen precursor; and purging the chamber a second time. A typical purge duration is 5-15 seconds. If the purge after the exposure to the oxygen precursor is prolonged to longer than 60 seconds, the leakage current in the resulting film is markedly reduced.
- a typical purge duration is 5-15 seconds. If the purge after the exposure to the oxygen precursor is prolonged to longer than 60 seconds, the leakage current in the resulting film is markedly reduced.
- the second purge has a duration longer than 60 seconds; for example, 60-120 seconds or 65-80 seconds.
- the first purge can be kept short, less than 15 seconds or 5-15 seconds.
- Each of the monolayers may have an effective thickness between about 0.6 ⁇ and about 1.2 ⁇ , and the A-B cycle may be repeated until the metal oxide film is between about 2 ⁇ and about 50 ⁇ thick.
- the resulting film may have a leakage current density less than about 0.1 microamps per square centimeter ( ⁇ A/cm 2 ); sometimes it may be less than about 0.05 ⁇ A/cm 2 or 0.01-0.05 ⁇ A/cm 2 .
- the metal precursor may include a precursor for aluminum, zirconium, or hafnium.
- An aluminum precursor may include trimethylaluminum (TMA).
- TMA trimethylaluminum
- the oxygen precursor may include water or ozone.
- Either the first (post-metal) or the second (post-oxygen) purge may include flooding the chamber with an inert gas such as argon, nitrogen, or helium.
- FIG. 1 illustrates an example of a metal-oxide semiconductor field effect transistor (MOSFET) device.
- MOSFET metal-oxide semiconductor field effect transistor
- FIG. 2 is an example flowchart for forming a high-k metal oxide layer by atomic layer deposition (ALD).
- ALD atomic layer deposition
- FIG. 3 is an example flowchart of a process for testing leakage current in candidate high-k metal oxide ALD films by forming a test stack.
- FIG. 4 is an example graph of leakage current results for candidate Al2O3 gate-dielectric films in a Si/SiOx/Al2O3/TiN test stack.
- FIG. 1 illustrates an example of a metal-oxide semiconductor field effect transistor (MOSFET) device.
- the MOSFET can be incorporated into integrated circuits, interconnected with other devices.
- the MOSFET may include a substrate 101 , which may include one or more underlying layers on a silicon, silicon-on-insulator, silicon-germanium, or germanium wafer or other base.
- Source region 102 and drain region 103 in substrate 101 may be doped with arsenic, phosphorous, boron or other suitable materials using a self-aligning ion implantation process or other suitable process.
- Other components, such as n-well or p-well regions, may be included in some devices.
- a gate stack fabricated on substrate 101 includes high-k gate dielectric layer 104 , gate electrode layer 105 , and gate conductor layer 106 . Spacers 107 are formed between the gate stack ⁇ 104 , 105 , 106 ⁇ and the surrounding interlayer dielectric (ILD) 108 .
- High-k dielectric layer 104 may include a metal oxide such as Al 2 O 3 , HfO x , or ZrO x .
- High-k dielectric layer 104 provides a sufficient equivalent oxide thickness (EOT) to prevent leakage current through the gate due to tunneling.
- Gate electrode layer 105 is formed on high-k dielectric layer 104 and may include aluminum, polysilicon, or other suitable conductive materials (e.g., TiN, TaN, HfN, RuN, WN, W, MoN, TaSiN, RuSiN, WSiN, HfSiN, TiSiN, etc.).
- Spacers 107 made of SiO 2 , Si 3 N 4 , tetraethyl Orthosilicate (TEOS) or other suitable dielectric materials isolate gate electrode 105 and high-k dielectric layer 104 from source region 102 and drain region 103 .
- high-k dielectric layer 104 , gate electrode layer 105 , and gate conductor layer 106 may be initially formed as blanket layers on substrate 101 . Then the layers may be patterned (e.g., by dry or wet etching or lithography) to remove everything except the gate stack. Afterward, the surrounding structures are fabricated; source 102 and drain 103 dopants are implanted, spacers 107 are formed, and the ILD 108 is added.
- high-k dielectric layer 104 is also initially formed as a blanket layer on substrate 101 .
- a sacrificial material e.g., polysilicon
- the surrounding structures are fabricated around the dummy gate stack.
- the sacrificial material is removed by etching or another suitable process, to be replaced by gate electrode layer 105 and gate conductor layer 106 .
- the dummy gate approach can be advantageous if the materials of gate electrode layer 105 and gate conductor layer 106 can be damaged by some of the processes for making the surrounding structure (e.g., high temperature).
- FIG. 2 is an example flowchart for forming a high-k metal oxide layer by atomic layer deposition (ALD).
- a substrate is positioned 201 in a process chamber.
- a metal precursor e.g., TMA, some other aluminum precursor, or a hafnium or zirconium precursor
- the exposure may include a “pulse” of precursor flowing into the chamber, followed by a time delay when no additional precursor flows but the precursor already present reacts with, or adheres to the substrate.
- the process chamber is purged 203 to remove any unreacted metal precursor or by-products from the reaction zone and other surfaces.
- the purge may include an evacuation of the chamber, a pulse of a purge gas, or a combination.
- the purge gas may flow continuously through the reaction zone throughout deposition.
- the purge gas may be an inert gas such as argon, nitrogen, or helium.
- Post-metal purge 203 may have a duration of less than 15 seconds, such as between 5 and 15 seconds.
- an oxygen precursor such as water (H 2 O) or ozone (O 3 ) is introduced 204 into the chamber, as a pulse or as a continuous flow, then the chamber is purged 205 a second time.
- the purge may include an evacuation of the chamber, a pulse of a purge gas, or a combination. Alternatively, the purge gas may flow continuously through the reaction zone throughout deposition.
- the purge gas may be an inert gas such as argon, nitrogen, or helium.
- Post-oxygen purge 205 has a duration longer than 60 seconds, which may be between 60 and 120 seconds or between 65 and 80 seconds. This completes one ALD cycle, depositing a layer of metal oxide about 0.6 ⁇ -1.2 ⁇ thick.
- ALD layer thickness is typically expressed as an average thickness.
- a contiguous monolayer is one molecule thick. However, a non-contiguous monolayer, where there are empty spaces left between the deposited atoms, can be less than 1 molecule thick on average.
- Thickness determination 206 can be made by monitoring the film thickness or, when the thickness per cycle is known, simply by counting cycles.
- the desired thickness may be in a range of 2-50 ⁇ , or 2-10 ⁇ , or 25-35 ⁇ .
- FIG. 3 is an example flowchart of a process for testing leakage current in candidate high-k metal oxide ALD films by forming a test stack.
- a silicon substrate with a silicon oxide layer is prepared 301 for ALD.
- a set of trial process parameters for the metal-oxide ALD is selected 302 .
- the metal oxide is deposited 303 on the silicon oxide according to the selected process parameters; for example, by a procedure like that of FIG. 2 .
- Process parameters may include precursor composition, purge gas composition, pulse and purge times, pulse and purge flow rates, chamber pressure, substrate or ambient temperature, and variations of any of those during the deposition. In some test cases, process parameters may also extend to temperature, duration, ambient gas composition, or pressure of a post-ALD anneal 304 or optionally to a post-anneal treatment 305 such as an ozone treatment.
- a conductive layer is then added 306 above the metal oxide.
- the conductive layer may operate as an electrode and may also cap the metal-oxide layer to protect it from the environment outside the process chamber.
- the conductive layer may have its process parameters kept constant for each variation of the metal oxide, or its process parameters may also be selected for variation.
- the conductive layer may also be annealed or otherwise treated after deposition.
- One or more capacitors are formed 307 from the resulting test stack of Si/SiOx/metal oxide/conductor.
- a test voltage is applied 308 and the leakage current is measured 309 .
- Other tests may also be performed.
- the results from different sets of process parameters are compared to select the best metal-oxide process.
- Each set of selected process parameters may be implemented and tested on a separate substrate, or, with equipment and methods such as the High Productivity Combinatorial system described in U.S. Pat. No. 7,947,531 (incorporated herein by reference for all purposes), multiple sets of process parameters may be implemented and tested on a single substrate.
- FIG. 4 is an example graph of leakage current results for candidate Al 2 O 3 gate-dielectric films in a Si/SiO x /Al 2 O 3 /TiN test stack.
- the Al precursor was TMA
- the oxygen precursor was H 2 O
- the film thickness was 30 ⁇ .
- the x-axis is the device number, an arbitrary way to separate the points within a data set.
- Data set 401 shows the leakage current distribution for a post-oxygen purge of the standard 5-15 sec duration.
- Data set 402 s shows the leakage current distribution for a post-oxygen purge of a prolonged 70 sec duration.
- the prolonged post-oxygen purge caused roughly an order-of-magnitude decrease in leakage current, to less than 0.1 ⁇ A/cm 2 ; most samples had leakage J g less than 0.05 ⁇ A/cm 2 , or between about 0.01 and about 0.05 ⁇ A/cm 2 .
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Abstract
Metal-oxide films (e.g., aluminum oxide) with low leakage current suitable for high-k gate dielectrics are deposited by atomic layer deposition (ALD). The purge time after the metal-deposition phase is 5-15 seconds, and the purge time after the oxidation phase is prolonged beyond 60 seconds. Prolonging the post-oxidation purge produced an order-of-magnitude reduction of leakage current in 30 Å-thick Al2O3 films.
Description
- This application claims priority to U.S. Prov. Pat. App. No. 61/779,740, filed 13 Mar. 2013, the entirety of which is incorporated herein by reference for all purposes.
- Related fields include thin-film semiconductor device manufacture, particularly atomic layer deposition of oxide films.
- As integrated circuit feature sizes decrease, other device dimensions also decrease to maintain the proper device operation. For example, as gate conductor widths decrease, the thickness of the gate dielectric needs to decrease to provide proper capacitance to control the transistor.
- Silicon dioxide (SiO2), a gate dielectric used in larger scale devices, would need to be <1.5 nm thick to be used in a sub-100 nm MOSFET device. Unfortunately, SiO2 is subject to high tunneling leakage in thicknesses <2 nm. The tunneling leakage increases power consumption and reduces device reliability. Materials with dielectric constants, k, greater than the SiO2 's value of 3.9 (“high-k materials”) have been studied as replacements for SiO2. For example, a ˜5 nm-thick layer of material with k=20 (e.g., a transition metal oxide such as hafnium oxide), has the same capacitance as a SiO2 layer that is only 1 nm thick; thus, its “equivalent oxide thickness” (EOT) would be 1 nm. Tunneling leakage current decreases rapidly with physical thickness, and is very low through a 5 nm gate.
- Tunneling, however, is not the only source of unwanted leakage current that inhibits progress in fabricating reliable smaller-scale transistors (and other components, such as memory cells). Material properties, such as mobile charge-carrying defects and metallic nanoclusters that can form in metal-oxide layers subjected to sufficiently strong electric fields, facilitate leakage by other mechanisms that cannot be mitigated by simply thickening the layer. These material properties are often highly dependent on process conditions and methods of forming the high-k layers, but the variables can be challenging to measure and correct. In particular, films of aluminum oxide (Al2O3) and other metal oxides such as hafnium oxide (HfOx) and zirconium oxide (ZrOx) are prone to high or inconsistent leakage current at thicknesses of 2-10 Å.
- Therefore, a need exists for a method of forming metal-oxide films with consistently low leakage current from all leakage mechanisms.
- The following summary presents some concepts in a simplified form as an introduction to the detailed description that follows. It does not necessarily identify key or critical elements and is not intended to reflect a scope of invention.
- Metal-oxide films made by atomic layer deposition (ALD) are formed by alternating cycles of metal deposition and oxidation (“A-B cycling”). Each cycle deposits a monolayer of metal oxide. Each cycle includes exposing the substrate to a metal precursor; purging the chamber to remove unreacted precursors and by-products; exposing the substrate to an oxygen precursor; and purging the chamber a second time. A typical purge duration is 5-15 seconds. If the purge after the exposure to the oxygen precursor is prolonged to longer than 60 seconds, the leakage current in the resulting film is markedly reduced.
- In some embodiments, the second purge has a duration longer than 60 seconds; for example, 60-120 seconds or 65-80 seconds. The first purge can be kept short, less than 15 seconds or 5-15 seconds. Each of the monolayers may have an effective thickness between about 0.6 Å and about 1.2 Å, and the A-B cycle may be repeated until the metal oxide film is between about 2 Å and about 50 Åthick. The resulting film may have a leakage current density less than about 0.1 microamps per square centimeter (μA/cm2); sometimes it may be less than about 0.05 μA/cm2 or 0.01-0.05 μA/cm2.
- The metal precursor may include a precursor for aluminum, zirconium, or hafnium. An aluminum precursor may include trimethylaluminum (TMA). The oxygen precursor may include water or ozone. Either the first (post-metal) or the second (post-oxygen) purge may include flooding the chamber with an inert gas such as argon, nitrogen, or helium.
-
FIG. 1 illustrates an example of a metal-oxide semiconductor field effect transistor (MOSFET) device. -
FIG. 2 is an example flowchart for forming a high-k metal oxide layer by atomic layer deposition (ALD). -
FIG. 3 is an example flowchart of a process for testing leakage current in candidate high-k metal oxide ALD films by forming a test stack. -
FIG. 4 is an example graph of leakage current results for candidate Al2O3 gate-dielectric films in a Si/SiOx/Al2O3/TiN test stack. -
FIG. 1 illustrates an example of a metal-oxide semiconductor field effect transistor (MOSFET) device. The MOSFET can be incorporated into integrated circuits, interconnected with other devices. The MOSFET may include asubstrate 101, which may include one or more underlying layers on a silicon, silicon-on-insulator, silicon-germanium, or germanium wafer or other base.Source region 102 anddrain region 103 insubstrate 101 may be doped with arsenic, phosphorous, boron or other suitable materials using a self-aligning ion implantation process or other suitable process. Other components, such as n-well or p-well regions, may be included in some devices. - A gate stack fabricated on
substrate 101 includes high-k gatedielectric layer 104,gate electrode layer 105, andgate conductor layer 106.Spacers 107 are formed between the gate stack {104, 105, 106} and the surrounding interlayer dielectric (ILD) 108. High-kdielectric layer 104 may include a metal oxide such as Al2O3, HfOx, or ZrOx. High-kdielectric layer 104 provides a sufficient equivalent oxide thickness (EOT) to prevent leakage current through the gate due to tunneling. -
Gate electrode layer 105 is formed on high-kdielectric layer 104 and may include aluminum, polysilicon, or other suitable conductive materials (e.g., TiN, TaN, HfN, RuN, WN, W, MoN, TaSiN, RuSiN, WSiN, HfSiN, TiSiN, etc.). Spacers 107 (made of SiO2, Si3N4, tetraethyl Orthosilicate (TEOS) or other suitable dielectric materials)isolate gate electrode 105 and high-kdielectric layer 104 fromsource region 102 anddrain region 103. - Various processes exist for creating the MOSFET structure. For example, in a “gate-first” process, high-k
dielectric layer 104,gate electrode layer 105, andgate conductor layer 106 may be initially formed as blanket layers onsubstrate 101. Then the layers may be patterned (e.g., by dry or wet etching or lithography) to remove everything except the gate stack. Afterward, the surrounding structures are fabricated;source 102 anddrain 103 dopants are implanted,spacers 107 are formed, and the ILD 108 is added. - In an alternative “gate-last,” “dummy gate,” or “replacement gate” process, high-k
dielectric layer 104 is also initially formed as a blanket layer onsubstrate 101. However, a sacrificial material (e.g., polysilicon) temporarily takes the place ofgate electrode layer 105 andgate conductor layer 106; it is deposited on top of high-kdielectric layer 104 and patterned along with it to form a dummy gate stack. The surrounding structures are fabricated around the dummy gate stack. Afterward, the sacrificial material is removed by etching or another suitable process, to be replaced bygate electrode layer 105 andgate conductor layer 106. The dummy gate approach can be advantageous if the materials ofgate electrode layer 105 andgate conductor layer 106 can be damaged by some of the processes for making the surrounding structure (e.g., high temperature). -
FIG. 2 is an example flowchart for forming a high-k metal oxide layer by atomic layer deposition (ALD). A substrate is positioned 201 in a process chamber. In part “A” of the cycle, a metal precursor (e.g., TMA, some other aluminum precursor, or a hafnium or zirconium precursor) is then introduced into the chamber so that the substrate is exposed to it 202. The exposure may include a “pulse” of precursor flowing into the chamber, followed by a time delay when no additional precursor flows but the precursor already present reacts with, or adheres to the substrate. Next, the process chamber is purged 203 to remove any unreacted metal precursor or by-products from the reaction zone and other surfaces. The purge may include an evacuation of the chamber, a pulse of a purge gas, or a combination. Alternatively, the purge gas may flow continuously through the reaction zone throughout deposition. The purge gas may be an inert gas such as argon, nitrogen, or helium.Post-metal purge 203 may have a duration of less than 15 seconds, such as between 5 and 15 seconds. - In part “B” of the cycle, an oxygen precursor such as water (H2O) or ozone (O3) is introduced 204 into the chamber, as a pulse or as a continuous flow, then the chamber is purged 205 a second time. The purge may include an evacuation of the chamber, a pulse of a purge gas, or a combination. Alternatively, the purge gas may flow continuously through the reaction zone throughout deposition. The purge gas may be an inert gas such as argon, nitrogen, or helium.
Post-oxygen purge 205 has a duration longer than 60 seconds, which may be between 60 and 120 seconds or between 65 and 80 seconds. This completes one ALD cycle, depositing a layer of metal oxide about 0.6 Å-1.2 Åthick. ALD layer thickness is typically expressed as an average thickness. A contiguous monolayer is one molecule thick. However, a non-contiguous monolayer, where there are empty spaces left between the deposited atoms, can be less than 1 molecule thick on average. - If the film is determined 206 to have reached a desired thickness after the most recent cycle, the process is complete; if not, another A-B cycle is performed.
Thickness determination 206 can be made by monitoring the film thickness or, when the thickness per cycle is known, simply by counting cycles. For example, the desired thickness may be in a range of 2-50 Å, or 2-10 Å, or 25-35 Å. -
FIG. 3 is an example flowchart of a process for testing leakage current in candidate high-k metal oxide ALD films by forming a test stack. A silicon substrate with a silicon oxide layer is prepared 301 for ALD. A set of trial process parameters for the metal-oxide ALD is selected 302. The metal oxide is deposited 303 on the silicon oxide according to the selected process parameters; for example, by a procedure like that ofFIG. 2 . Process parameters may include precursor composition, purge gas composition, pulse and purge times, pulse and purge flow rates, chamber pressure, substrate or ambient temperature, and variations of any of those during the deposition. In some test cases, process parameters may also extend to temperature, duration, ambient gas composition, or pressure of apost-ALD anneal 304 or optionally to apost-anneal treatment 305 such as an ozone treatment. - A conductive layer is then added 306 above the metal oxide. The conductive layer may operate as an electrode and may also cap the metal-oxide layer to protect it from the environment outside the process chamber. The conductive layer may have its process parameters kept constant for each variation of the metal oxide, or its process parameters may also be selected for variation. Optionally, the conductive layer may also be annealed or otherwise treated after deposition.
- One or more capacitors are formed 307 from the resulting test stack of Si/SiOx/metal oxide/conductor. A test voltage is applied 308 and the leakage current is measured 309. Other tests may also be performed. The results from different sets of process parameters are compared to select the best metal-oxide process. Each set of selected process parameters may be implemented and tested on a separate substrate, or, with equipment and methods such as the High Productivity Combinatorial system described in U.S. Pat. No. 7,947,531 (incorporated herein by reference for all purposes), multiple sets of process parameters may be implemented and tested on a single substrate.
-
FIG. 4 is an example graph of leakage current results for candidate Al2O3 gate-dielectric films in a Si/SiOx/Al2O3/TiN test stack. The Al precursor was TMA, the oxygen precursor was H2O, and the film thickness was 30 Å. The x-axis is the device number, an arbitrary way to separate the points within a data set. Data set 401 shows the leakage current distribution for a post-oxygen purge of the standard 5-15 sec duration. Data set 402 s shows the leakage current distribution for a post-oxygen purge of a prolonged 70 sec duration. The prolonged post-oxygen purge caused roughly an order-of-magnitude decrease in leakage current, to less than 0.1 μA/cm2; most samples had leakage Jg less than 0.05 μA/cm2, or between about 0.01 and about 0.05 μA/cm2. - Although the foregoing examples have been described in some detail to aid understanding, the invention is not limited to the details in the description and drawings. The examples are illustrative, not restrictive. There are many alternative ways of implementing the invention. Various aspects or components of the described embodiments may be used singly or in any combination. The scope is limited only by the claims, which encompass numerous alternatives, modifications, and equivalents.
Claims (20)
1. A method of forming a metal oxide film on a substrate in a process chamber, the method comprising:
exposing the substrate to a metal precursor;
performing a first purge of the chamber;
exposing the substrate to an oxygen precursor; and
performing a second purge of the chamber;
wherein the second purge has a duration longer than about 60 seconds.
2. The method of claim 1 , wherein the second purge has a duration between about 60 seconds and about 120 seconds.
3. The method of claim 1 , wherein the second purge has a duration between about 65 seconds and about 80 seconds.
4. The method of claim 1 , wherein the first purge has a duration shorter than about 15 seconds.
5. The method of claim 4 , wherein the first purge has a duration between about 5 seconds and about 15 seconds.
6. The method of claim 1 , wherein the metal oxide film formed by exposing the substrate to the metal precursor, performing the first purge, exposing the substrate to the oxygen precursor, and performing the second purge has an effective thickness between about 0.6 Å and about 1.2 Å.
7. The method of claim 1 , further comprising repeating the steps of exposing the substrate to the metal precursor, performing the first purge, exposing the substrate to the oxygen precursor, and performing the second purge until the metal oxide film is between about 2 Å and about 50 Åthick.
8. The method of claim 7 , wherein the metal oxide film has a leakage current density less than about 0.1 microamps per square centimeter.
9. The method of claim 7 , wherein the metal oxide film has a leakage current density less than about 0.05 microamps per square centimeter.
10. The method of claim 7 , wherein the metal oxide film has a leakage current density between about 0.01 and about 0.05 microamps per square centimeter.
11. The method of claim 1 , further comprising repeating the steps of exposing the substrate to the metal precursor, performing the first purge, exposing the substrate to the oxygen precursor, and performing the second purge until the metal oxide film is between about 2 Å and about 10 Åthick.
12. The method of claim 1 , further comprising repeating the steps of exposing the substrate to the metal precursor, performing the first purge, exposing the substrate to the oxygen precursor, and performing the second purge until the metal oxide film is between about 25 Å and about 35 Åthick.
13. The method of claim 1 , wherein the metal precursor comprises an aluminum, zirconium, or hafnium precursor.
14. The method of claim 13 , wherein the metal precursor comprises an aluminum precursor.
15. The method of claim 14 , wherein the aluminum precursor comprises trimethylaluminum.
16. The method of claim 1 , wherein the oxygen precursor comprises water or ozone.
17. The method of claim 1 , wherein the second purge comprises flooding the chamber with an inert gas.
18. The method of claim 16 , wherein the inert gas comprises argon, nitrogen, or helium.
19. The method of claim 1 , wherein the first purge comprises flooding the chamber with an inert gas.
20. The method of claim 19 , wherein the inert gas comprises argon, nitrogen, or helium.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/019,961 US20140273525A1 (en) | 2013-03-13 | 2013-09-06 | Atomic Layer Deposition of Reduced-Leakage Post-Transition Metal Oxide Films |
PCT/US2014/026690 WO2014160460A1 (en) | 2013-03-13 | 2014-03-13 | Atomic layer deposition of reduced-leakage post-transition metal oxide films |
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US201361779740P | 2013-03-13 | 2013-03-13 | |
US14/019,961 US20140273525A1 (en) | 2013-03-13 | 2013-09-06 | Atomic Layer Deposition of Reduced-Leakage Post-Transition Metal Oxide Films |
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US20140273525A1 true US20140273525A1 (en) | 2014-09-18 |
Family
ID=51523560
Family Applications (7)
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US14/019,961 Abandoned US20140273525A1 (en) | 2013-03-13 | 2013-09-06 | Atomic Layer Deposition of Reduced-Leakage Post-Transition Metal Oxide Films |
US14/031,975 Expired - Fee Related US8987143B2 (en) | 2013-03-13 | 2013-09-19 | Hydrogen plasma cleaning of germanium oxide surfaces |
US14/091,854 Abandoned US20140273404A1 (en) | 2013-03-13 | 2013-11-27 | Advanced Targeted Microwave Degas System |
US14/135,431 Expired - Fee Related US9076641B2 (en) | 2013-03-13 | 2013-12-19 | Ultra-low resistivity contacts |
US14/137,183 Abandoned US20140264281A1 (en) | 2013-03-13 | 2013-12-20 | Channel-Last Methods for Making FETS |
US14/137,866 Abandoned US20140264507A1 (en) | 2013-03-13 | 2013-12-20 | Fluorine Passivation in CMOS Image Sensors |
US14/721,248 Abandoned US20150255332A1 (en) | 2013-03-13 | 2015-05-26 | Ultra-Low Resistivity Contacts |
Family Applications After (6)
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US14/031,975 Expired - Fee Related US8987143B2 (en) | 2013-03-13 | 2013-09-19 | Hydrogen plasma cleaning of germanium oxide surfaces |
US14/091,854 Abandoned US20140273404A1 (en) | 2013-03-13 | 2013-11-27 | Advanced Targeted Microwave Degas System |
US14/135,431 Expired - Fee Related US9076641B2 (en) | 2013-03-13 | 2013-12-19 | Ultra-low resistivity contacts |
US14/137,183 Abandoned US20140264281A1 (en) | 2013-03-13 | 2013-12-20 | Channel-Last Methods for Making FETS |
US14/137,866 Abandoned US20140264507A1 (en) | 2013-03-13 | 2013-12-20 | Fluorine Passivation in CMOS Image Sensors |
US14/721,248 Abandoned US20150255332A1 (en) | 2013-03-13 | 2015-05-26 | Ultra-Low Resistivity Contacts |
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- 2013-09-19 US US14/031,975 patent/US8987143B2/en not_active Expired - Fee Related
- 2013-11-27 US US14/091,854 patent/US20140273404A1/en not_active Abandoned
- 2013-12-19 US US14/135,431 patent/US9076641B2/en not_active Expired - Fee Related
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-
2014
- 2014-03-13 WO PCT/US2014/026732 patent/WO2014160467A1/en active Application Filing
- 2014-03-13 WO PCT/US2014/026690 patent/WO2014160460A1/en active Application Filing
-
2015
- 2015-05-26 US US14/721,248 patent/US20150255332A1/en not_active Abandoned
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US10767259B2 (en) | 2013-07-19 | 2020-09-08 | Agilent Technologies, Inc. | Components with an atomic layer deposition coating and methods of producing the same |
US10895009B2 (en) | 2013-07-19 | 2021-01-19 | Agilent Technologies, Inc. | Metal components with inert vapor phase coating on internal surfaces |
WO2016114850A1 (en) * | 2015-01-14 | 2016-07-21 | Agilent Technologies, Inc. | Components with an atomic layer deposition coating and methods of producing the same |
CN108604635A (en) * | 2016-01-26 | 2018-09-28 | Arm有限公司 | The manufacture of associated electrical material devices |
Also Published As
Publication number | Publication date |
---|---|
US8987143B2 (en) | 2015-03-24 |
US20140273493A1 (en) | 2014-09-18 |
US20140273404A1 (en) | 2014-09-18 |
US20140264507A1 (en) | 2014-09-18 |
US20140264825A1 (en) | 2014-09-18 |
US9076641B2 (en) | 2015-07-07 |
US20150255332A1 (en) | 2015-09-10 |
WO2014160467A1 (en) | 2014-10-02 |
WO2014160460A1 (en) | 2014-10-02 |
US20140264281A1 (en) | 2014-09-18 |
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