US20140273525A1 - Atomic Layer Deposition of Reduced-Leakage Post-Transition Metal Oxide Films - Google Patents

Atomic Layer Deposition of Reduced-Leakage Post-Transition Metal Oxide Films Download PDF

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US20140273525A1
US20140273525A1 US14/019,961 US201314019961A US2014273525A1 US 20140273525 A1 US20140273525 A1 US 20140273525A1 US 201314019961 A US201314019961 A US 201314019961A US 2014273525 A1 US2014273525 A1 US 2014273525A1
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purge
precursor
substrate
metal oxide
seconds
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US14/019,961
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Kurt Pang
Sean Barstow
Chi-I Lang
Michael Miller
Sandip Niyogi
Prashant B. Phatak
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Intermolecular Inc
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Intermolecular Inc
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Priority to US14/019,961 priority Critical patent/US20140273525A1/en
Assigned to INTERMOLECULAR, INC. reassignment INTERMOLECULAR, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: PHATAK, PRASHANT, BARSTOW, SEAN, LANG, CHI-I, MILLER, MICHAEL, PANG, KURT, NIYOGI, SANDIP
Priority to PCT/US2014/026690 priority patent/WO2014160460A1/en
Publication of US20140273525A1 publication Critical patent/US20140273525A1/en
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Definitions

  • SiO 2 Silicon dioxide
  • SiO 2 a gate dielectric used in larger scale devices, would need to be ⁇ 1.5 nm thick to be used in a sub-100 nm MOSFET device.
  • SiO 2 is subject to high tunneling leakage in thicknesses ⁇ 2 nm. The tunneling leakage increases power consumption and reduces device reliability.
  • Materials with dielectric constants, k, greater than the SiO 2 's value of 3.9 (“high-k materials”) have been studied as replacements for SiO 2 .
  • EOT equivalent oxide thickness
  • Tunneling is not the only source of unwanted leakage current that inhibits progress in fabricating reliable smaller-scale transistors (and other components, such as memory cells).
  • Material properties such as mobile charge-carrying defects and metallic nanoclusters that can form in metal-oxide layers subjected to sufficiently strong electric fields, facilitate leakage by other mechanisms that cannot be mitigated by simply thickening the layer. These material properties are often highly dependent on process conditions and methods of forming the high-k layers, but the variables can be challenging to measure and correct.
  • films of aluminum oxide (Al 2 O 3 ) and other metal oxides such as hafnium oxide (HfO x ) and zirconium oxide (ZrO x ) are prone to high or inconsistent leakage current at thicknesses of 2-10 ⁇ .
  • Metal-oxide films made by atomic layer deposition are formed by alternating cycles of metal deposition and oxidation (“A-B cycling”). Each cycle deposits a monolayer of metal oxide. Each cycle includes exposing the substrate to a metal precursor; purging the chamber to remove unreacted precursors and by-products; exposing the substrate to an oxygen precursor; and purging the chamber a second time. A typical purge duration is 5-15 seconds. If the purge after the exposure to the oxygen precursor is prolonged to longer than 60 seconds, the leakage current in the resulting film is markedly reduced.
  • a typical purge duration is 5-15 seconds. If the purge after the exposure to the oxygen precursor is prolonged to longer than 60 seconds, the leakage current in the resulting film is markedly reduced.
  • the second purge has a duration longer than 60 seconds; for example, 60-120 seconds or 65-80 seconds.
  • the first purge can be kept short, less than 15 seconds or 5-15 seconds.
  • Each of the monolayers may have an effective thickness between about 0.6 ⁇ and about 1.2 ⁇ , and the A-B cycle may be repeated until the metal oxide film is between about 2 ⁇ and about 50 ⁇ thick.
  • the resulting film may have a leakage current density less than about 0.1 microamps per square centimeter ( ⁇ A/cm 2 ); sometimes it may be less than about 0.05 ⁇ A/cm 2 or 0.01-0.05 ⁇ A/cm 2 .
  • the metal precursor may include a precursor for aluminum, zirconium, or hafnium.
  • An aluminum precursor may include trimethylaluminum (TMA).
  • TMA trimethylaluminum
  • the oxygen precursor may include water or ozone.
  • Either the first (post-metal) or the second (post-oxygen) purge may include flooding the chamber with an inert gas such as argon, nitrogen, or helium.
  • FIG. 1 illustrates an example of a metal-oxide semiconductor field effect transistor (MOSFET) device.
  • MOSFET metal-oxide semiconductor field effect transistor
  • FIG. 2 is an example flowchart for forming a high-k metal oxide layer by atomic layer deposition (ALD).
  • ALD atomic layer deposition
  • FIG. 3 is an example flowchart of a process for testing leakage current in candidate high-k metal oxide ALD films by forming a test stack.
  • FIG. 4 is an example graph of leakage current results for candidate Al2O3 gate-dielectric films in a Si/SiOx/Al2O3/TiN test stack.
  • FIG. 1 illustrates an example of a metal-oxide semiconductor field effect transistor (MOSFET) device.
  • the MOSFET can be incorporated into integrated circuits, interconnected with other devices.
  • the MOSFET may include a substrate 101 , which may include one or more underlying layers on a silicon, silicon-on-insulator, silicon-germanium, or germanium wafer or other base.
  • Source region 102 and drain region 103 in substrate 101 may be doped with arsenic, phosphorous, boron or other suitable materials using a self-aligning ion implantation process or other suitable process.
  • Other components, such as n-well or p-well regions, may be included in some devices.
  • a gate stack fabricated on substrate 101 includes high-k gate dielectric layer 104 , gate electrode layer 105 , and gate conductor layer 106 . Spacers 107 are formed between the gate stack ⁇ 104 , 105 , 106 ⁇ and the surrounding interlayer dielectric (ILD) 108 .
  • High-k dielectric layer 104 may include a metal oxide such as Al 2 O 3 , HfO x , or ZrO x .
  • High-k dielectric layer 104 provides a sufficient equivalent oxide thickness (EOT) to prevent leakage current through the gate due to tunneling.
  • Gate electrode layer 105 is formed on high-k dielectric layer 104 and may include aluminum, polysilicon, or other suitable conductive materials (e.g., TiN, TaN, HfN, RuN, WN, W, MoN, TaSiN, RuSiN, WSiN, HfSiN, TiSiN, etc.).
  • Spacers 107 made of SiO 2 , Si 3 N 4 , tetraethyl Orthosilicate (TEOS) or other suitable dielectric materials isolate gate electrode 105 and high-k dielectric layer 104 from source region 102 and drain region 103 .
  • high-k dielectric layer 104 , gate electrode layer 105 , and gate conductor layer 106 may be initially formed as blanket layers on substrate 101 . Then the layers may be patterned (e.g., by dry or wet etching or lithography) to remove everything except the gate stack. Afterward, the surrounding structures are fabricated; source 102 and drain 103 dopants are implanted, spacers 107 are formed, and the ILD 108 is added.
  • high-k dielectric layer 104 is also initially formed as a blanket layer on substrate 101 .
  • a sacrificial material e.g., polysilicon
  • the surrounding structures are fabricated around the dummy gate stack.
  • the sacrificial material is removed by etching or another suitable process, to be replaced by gate electrode layer 105 and gate conductor layer 106 .
  • the dummy gate approach can be advantageous if the materials of gate electrode layer 105 and gate conductor layer 106 can be damaged by some of the processes for making the surrounding structure (e.g., high temperature).
  • FIG. 2 is an example flowchart for forming a high-k metal oxide layer by atomic layer deposition (ALD).
  • a substrate is positioned 201 in a process chamber.
  • a metal precursor e.g., TMA, some other aluminum precursor, or a hafnium or zirconium precursor
  • the exposure may include a “pulse” of precursor flowing into the chamber, followed by a time delay when no additional precursor flows but the precursor already present reacts with, or adheres to the substrate.
  • the process chamber is purged 203 to remove any unreacted metal precursor or by-products from the reaction zone and other surfaces.
  • the purge may include an evacuation of the chamber, a pulse of a purge gas, or a combination.
  • the purge gas may flow continuously through the reaction zone throughout deposition.
  • the purge gas may be an inert gas such as argon, nitrogen, or helium.
  • Post-metal purge 203 may have a duration of less than 15 seconds, such as between 5 and 15 seconds.
  • an oxygen precursor such as water (H 2 O) or ozone (O 3 ) is introduced 204 into the chamber, as a pulse or as a continuous flow, then the chamber is purged 205 a second time.
  • the purge may include an evacuation of the chamber, a pulse of a purge gas, or a combination. Alternatively, the purge gas may flow continuously through the reaction zone throughout deposition.
  • the purge gas may be an inert gas such as argon, nitrogen, or helium.
  • Post-oxygen purge 205 has a duration longer than 60 seconds, which may be between 60 and 120 seconds or between 65 and 80 seconds. This completes one ALD cycle, depositing a layer of metal oxide about 0.6 ⁇ -1.2 ⁇ thick.
  • ALD layer thickness is typically expressed as an average thickness.
  • a contiguous monolayer is one molecule thick. However, a non-contiguous monolayer, where there are empty spaces left between the deposited atoms, can be less than 1 molecule thick on average.
  • Thickness determination 206 can be made by monitoring the film thickness or, when the thickness per cycle is known, simply by counting cycles.
  • the desired thickness may be in a range of 2-50 ⁇ , or 2-10 ⁇ , or 25-35 ⁇ .
  • FIG. 3 is an example flowchart of a process for testing leakage current in candidate high-k metal oxide ALD films by forming a test stack.
  • a silicon substrate with a silicon oxide layer is prepared 301 for ALD.
  • a set of trial process parameters for the metal-oxide ALD is selected 302 .
  • the metal oxide is deposited 303 on the silicon oxide according to the selected process parameters; for example, by a procedure like that of FIG. 2 .
  • Process parameters may include precursor composition, purge gas composition, pulse and purge times, pulse and purge flow rates, chamber pressure, substrate or ambient temperature, and variations of any of those during the deposition. In some test cases, process parameters may also extend to temperature, duration, ambient gas composition, or pressure of a post-ALD anneal 304 or optionally to a post-anneal treatment 305 such as an ozone treatment.
  • a conductive layer is then added 306 above the metal oxide.
  • the conductive layer may operate as an electrode and may also cap the metal-oxide layer to protect it from the environment outside the process chamber.
  • the conductive layer may have its process parameters kept constant for each variation of the metal oxide, or its process parameters may also be selected for variation.
  • the conductive layer may also be annealed or otherwise treated after deposition.
  • One or more capacitors are formed 307 from the resulting test stack of Si/SiOx/metal oxide/conductor.
  • a test voltage is applied 308 and the leakage current is measured 309 .
  • Other tests may also be performed.
  • the results from different sets of process parameters are compared to select the best metal-oxide process.
  • Each set of selected process parameters may be implemented and tested on a separate substrate, or, with equipment and methods such as the High Productivity Combinatorial system described in U.S. Pat. No. 7,947,531 (incorporated herein by reference for all purposes), multiple sets of process parameters may be implemented and tested on a single substrate.
  • FIG. 4 is an example graph of leakage current results for candidate Al 2 O 3 gate-dielectric films in a Si/SiO x /Al 2 O 3 /TiN test stack.
  • the Al precursor was TMA
  • the oxygen precursor was H 2 O
  • the film thickness was 30 ⁇ .
  • the x-axis is the device number, an arbitrary way to separate the points within a data set.
  • Data set 401 shows the leakage current distribution for a post-oxygen purge of the standard 5-15 sec duration.
  • Data set 402 s shows the leakage current distribution for a post-oxygen purge of a prolonged 70 sec duration.
  • the prolonged post-oxygen purge caused roughly an order-of-magnitude decrease in leakage current, to less than 0.1 ⁇ A/cm 2 ; most samples had leakage J g less than 0.05 ⁇ A/cm 2 , or between about 0.01 and about 0.05 ⁇ A/cm 2 .

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Abstract

Metal-oxide films (e.g., aluminum oxide) with low leakage current suitable for high-k gate dielectrics are deposited by atomic layer deposition (ALD). The purge time after the metal-deposition phase is 5-15 seconds, and the purge time after the oxidation phase is prolonged beyond 60 seconds. Prolonging the post-oxidation purge produced an order-of-magnitude reduction of leakage current in 30 Å-thick Al2O3 films.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application claims priority to U.S. Prov. Pat. App. No. 61/779,740, filed 13 Mar. 2013, the entirety of which is incorporated herein by reference for all purposes.
  • BACKGROUND
  • Related fields include thin-film semiconductor device manufacture, particularly atomic layer deposition of oxide films.
  • As integrated circuit feature sizes decrease, other device dimensions also decrease to maintain the proper device operation. For example, as gate conductor widths decrease, the thickness of the gate dielectric needs to decrease to provide proper capacitance to control the transistor.
  • Silicon dioxide (SiO2), a gate dielectric used in larger scale devices, would need to be <1.5 nm thick to be used in a sub-100 nm MOSFET device. Unfortunately, SiO2 is subject to high tunneling leakage in thicknesses <2 nm. The tunneling leakage increases power consumption and reduces device reliability. Materials with dielectric constants, k, greater than the SiO2 's value of 3.9 (“high-k materials”) have been studied as replacements for SiO2. For example, a ˜5 nm-thick layer of material with k=20 (e.g., a transition metal oxide such as hafnium oxide), has the same capacitance as a SiO2 layer that is only 1 nm thick; thus, its “equivalent oxide thickness” (EOT) would be 1 nm. Tunneling leakage current decreases rapidly with physical thickness, and is very low through a 5 nm gate.
  • Tunneling, however, is not the only source of unwanted leakage current that inhibits progress in fabricating reliable smaller-scale transistors (and other components, such as memory cells). Material properties, such as mobile charge-carrying defects and metallic nanoclusters that can form in metal-oxide layers subjected to sufficiently strong electric fields, facilitate leakage by other mechanisms that cannot be mitigated by simply thickening the layer. These material properties are often highly dependent on process conditions and methods of forming the high-k layers, but the variables can be challenging to measure and correct. In particular, films of aluminum oxide (Al2O3) and other metal oxides such as hafnium oxide (HfOx) and zirconium oxide (ZrOx) are prone to high or inconsistent leakage current at thicknesses of 2-10 Å.
  • Therefore, a need exists for a method of forming metal-oxide films with consistently low leakage current from all leakage mechanisms.
  • SUMMARY
  • The following summary presents some concepts in a simplified form as an introduction to the detailed description that follows. It does not necessarily identify key or critical elements and is not intended to reflect a scope of invention.
  • Metal-oxide films made by atomic layer deposition (ALD) are formed by alternating cycles of metal deposition and oxidation (“A-B cycling”). Each cycle deposits a monolayer of metal oxide. Each cycle includes exposing the substrate to a metal precursor; purging the chamber to remove unreacted precursors and by-products; exposing the substrate to an oxygen precursor; and purging the chamber a second time. A typical purge duration is 5-15 seconds. If the purge after the exposure to the oxygen precursor is prolonged to longer than 60 seconds, the leakage current in the resulting film is markedly reduced.
  • In some embodiments, the second purge has a duration longer than 60 seconds; for example, 60-120 seconds or 65-80 seconds. The first purge can be kept short, less than 15 seconds or 5-15 seconds. Each of the monolayers may have an effective thickness between about 0.6 Å and about 1.2 Å, and the A-B cycle may be repeated until the metal oxide film is between about 2 Å and about 50 Åthick. The resulting film may have a leakage current density less than about 0.1 microamps per square centimeter (μA/cm2); sometimes it may be less than about 0.05 μA/cm2 or 0.01-0.05 μA/cm2.
  • The metal precursor may include a precursor for aluminum, zirconium, or hafnium. An aluminum precursor may include trimethylaluminum (TMA). The oxygen precursor may include water or ozone. Either the first (post-metal) or the second (post-oxygen) purge may include flooding the chamber with an inert gas such as argon, nitrogen, or helium.
  • BRIEF DESCRIPTION OF DRAWINGS
  • FIG. 1 illustrates an example of a metal-oxide semiconductor field effect transistor (MOSFET) device.
  • FIG. 2 is an example flowchart for forming a high-k metal oxide layer by atomic layer deposition (ALD).
  • FIG. 3 is an example flowchart of a process for testing leakage current in candidate high-k metal oxide ALD films by forming a test stack.
  • FIG. 4 is an example graph of leakage current results for candidate Al2O3 gate-dielectric films in a Si/SiOx/Al2O3/TiN test stack.
  • DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS
  • FIG. 1 illustrates an example of a metal-oxide semiconductor field effect transistor (MOSFET) device. The MOSFET can be incorporated into integrated circuits, interconnected with other devices. The MOSFET may include a substrate 101, which may include one or more underlying layers on a silicon, silicon-on-insulator, silicon-germanium, or germanium wafer or other base. Source region 102 and drain region 103 in substrate 101 may be doped with arsenic, phosphorous, boron or other suitable materials using a self-aligning ion implantation process or other suitable process. Other components, such as n-well or p-well regions, may be included in some devices.
  • A gate stack fabricated on substrate 101 includes high-k gate dielectric layer 104, gate electrode layer 105, and gate conductor layer 106. Spacers 107 are formed between the gate stack {104, 105, 106} and the surrounding interlayer dielectric (ILD) 108. High-k dielectric layer 104 may include a metal oxide such as Al2O3, HfOx, or ZrOx. High-k dielectric layer 104 provides a sufficient equivalent oxide thickness (EOT) to prevent leakage current through the gate due to tunneling.
  • Gate electrode layer 105 is formed on high-k dielectric layer 104 and may include aluminum, polysilicon, or other suitable conductive materials (e.g., TiN, TaN, HfN, RuN, WN, W, MoN, TaSiN, RuSiN, WSiN, HfSiN, TiSiN, etc.). Spacers 107 (made of SiO2, Si3N4, tetraethyl Orthosilicate (TEOS) or other suitable dielectric materials) isolate gate electrode 105 and high-k dielectric layer 104 from source region 102 and drain region 103.
  • Various processes exist for creating the MOSFET structure. For example, in a “gate-first” process, high-k dielectric layer 104, gate electrode layer 105, and gate conductor layer 106 may be initially formed as blanket layers on substrate 101. Then the layers may be patterned (e.g., by dry or wet etching or lithography) to remove everything except the gate stack. Afterward, the surrounding structures are fabricated; source 102 and drain 103 dopants are implanted, spacers 107 are formed, and the ILD 108 is added.
  • In an alternative “gate-last,” “dummy gate,” or “replacement gate” process, high-k dielectric layer 104 is also initially formed as a blanket layer on substrate 101. However, a sacrificial material (e.g., polysilicon) temporarily takes the place of gate electrode layer 105 and gate conductor layer 106; it is deposited on top of high-k dielectric layer 104 and patterned along with it to form a dummy gate stack. The surrounding structures are fabricated around the dummy gate stack. Afterward, the sacrificial material is removed by etching or another suitable process, to be replaced by gate electrode layer 105 and gate conductor layer 106. The dummy gate approach can be advantageous if the materials of gate electrode layer 105 and gate conductor layer 106 can be damaged by some of the processes for making the surrounding structure (e.g., high temperature).
  • FIG. 2 is an example flowchart for forming a high-k metal oxide layer by atomic layer deposition (ALD). A substrate is positioned 201 in a process chamber. In part “A” of the cycle, a metal precursor (e.g., TMA, some other aluminum precursor, or a hafnium or zirconium precursor) is then introduced into the chamber so that the substrate is exposed to it 202. The exposure may include a “pulse” of precursor flowing into the chamber, followed by a time delay when no additional precursor flows but the precursor already present reacts with, or adheres to the substrate. Next, the process chamber is purged 203 to remove any unreacted metal precursor or by-products from the reaction zone and other surfaces. The purge may include an evacuation of the chamber, a pulse of a purge gas, or a combination. Alternatively, the purge gas may flow continuously through the reaction zone throughout deposition. The purge gas may be an inert gas such as argon, nitrogen, or helium. Post-metal purge 203 may have a duration of less than 15 seconds, such as between 5 and 15 seconds.
  • In part “B” of the cycle, an oxygen precursor such as water (H2O) or ozone (O3) is introduced 204 into the chamber, as a pulse or as a continuous flow, then the chamber is purged 205 a second time. The purge may include an evacuation of the chamber, a pulse of a purge gas, or a combination. Alternatively, the purge gas may flow continuously through the reaction zone throughout deposition. The purge gas may be an inert gas such as argon, nitrogen, or helium. Post-oxygen purge 205 has a duration longer than 60 seconds, which may be between 60 and 120 seconds or between 65 and 80 seconds. This completes one ALD cycle, depositing a layer of metal oxide about 0.6 Å-1.2 Åthick. ALD layer thickness is typically expressed as an average thickness. A contiguous monolayer is one molecule thick. However, a non-contiguous monolayer, where there are empty spaces left between the deposited atoms, can be less than 1 molecule thick on average.
  • If the film is determined 206 to have reached a desired thickness after the most recent cycle, the process is complete; if not, another A-B cycle is performed. Thickness determination 206 can be made by monitoring the film thickness or, when the thickness per cycle is known, simply by counting cycles. For example, the desired thickness may be in a range of 2-50 Å, or 2-10 Å, or 25-35 Å.
  • FIG. 3 is an example flowchart of a process for testing leakage current in candidate high-k metal oxide ALD films by forming a test stack. A silicon substrate with a silicon oxide layer is prepared 301 for ALD. A set of trial process parameters for the metal-oxide ALD is selected 302. The metal oxide is deposited 303 on the silicon oxide according to the selected process parameters; for example, by a procedure like that of FIG. 2. Process parameters may include precursor composition, purge gas composition, pulse and purge times, pulse and purge flow rates, chamber pressure, substrate or ambient temperature, and variations of any of those during the deposition. In some test cases, process parameters may also extend to temperature, duration, ambient gas composition, or pressure of a post-ALD anneal 304 or optionally to a post-anneal treatment 305 such as an ozone treatment.
  • A conductive layer is then added 306 above the metal oxide. The conductive layer may operate as an electrode and may also cap the metal-oxide layer to protect it from the environment outside the process chamber. The conductive layer may have its process parameters kept constant for each variation of the metal oxide, or its process parameters may also be selected for variation. Optionally, the conductive layer may also be annealed or otherwise treated after deposition.
  • One or more capacitors are formed 307 from the resulting test stack of Si/SiOx/metal oxide/conductor. A test voltage is applied 308 and the leakage current is measured 309. Other tests may also be performed. The results from different sets of process parameters are compared to select the best metal-oxide process. Each set of selected process parameters may be implemented and tested on a separate substrate, or, with equipment and methods such as the High Productivity Combinatorial system described in U.S. Pat. No. 7,947,531 (incorporated herein by reference for all purposes), multiple sets of process parameters may be implemented and tested on a single substrate.
  • FIG. 4 is an example graph of leakage current results for candidate Al2O3 gate-dielectric films in a Si/SiOx/Al2O3/TiN test stack. The Al precursor was TMA, the oxygen precursor was H2O, and the film thickness was 30 Å. The x-axis is the device number, an arbitrary way to separate the points within a data set. Data set 401 shows the leakage current distribution for a post-oxygen purge of the standard 5-15 sec duration. Data set 402 s shows the leakage current distribution for a post-oxygen purge of a prolonged 70 sec duration. The prolonged post-oxygen purge caused roughly an order-of-magnitude decrease in leakage current, to less than 0.1 μA/cm2; most samples had leakage Jg less than 0.05 μA/cm2, or between about 0.01 and about 0.05 μA/cm2.
  • Although the foregoing examples have been described in some detail to aid understanding, the invention is not limited to the details in the description and drawings. The examples are illustrative, not restrictive. There are many alternative ways of implementing the invention. Various aspects or components of the described embodiments may be used singly or in any combination. The scope is limited only by the claims, which encompass numerous alternatives, modifications, and equivalents.

Claims (20)

What is claimed is:
1. A method of forming a metal oxide film on a substrate in a process chamber, the method comprising:
exposing the substrate to a metal precursor;
performing a first purge of the chamber;
exposing the substrate to an oxygen precursor; and
performing a second purge of the chamber;
wherein the second purge has a duration longer than about 60 seconds.
2. The method of claim 1, wherein the second purge has a duration between about 60 seconds and about 120 seconds.
3. The method of claim 1, wherein the second purge has a duration between about 65 seconds and about 80 seconds.
4. The method of claim 1, wherein the first purge has a duration shorter than about 15 seconds.
5. The method of claim 4, wherein the first purge has a duration between about 5 seconds and about 15 seconds.
6. The method of claim 1, wherein the metal oxide film formed by exposing the substrate to the metal precursor, performing the first purge, exposing the substrate to the oxygen precursor, and performing the second purge has an effective thickness between about 0.6 Å and about 1.2 Å.
7. The method of claim 1, further comprising repeating the steps of exposing the substrate to the metal precursor, performing the first purge, exposing the substrate to the oxygen precursor, and performing the second purge until the metal oxide film is between about 2 Å and about 50 Åthick.
8. The method of claim 7, wherein the metal oxide film has a leakage current density less than about 0.1 microamps per square centimeter.
9. The method of claim 7, wherein the metal oxide film has a leakage current density less than about 0.05 microamps per square centimeter.
10. The method of claim 7, wherein the metal oxide film has a leakage current density between about 0.01 and about 0.05 microamps per square centimeter.
11. The method of claim 1, further comprising repeating the steps of exposing the substrate to the metal precursor, performing the first purge, exposing the substrate to the oxygen precursor, and performing the second purge until the metal oxide film is between about 2 Å and about 10 Åthick.
12. The method of claim 1, further comprising repeating the steps of exposing the substrate to the metal precursor, performing the first purge, exposing the substrate to the oxygen precursor, and performing the second purge until the metal oxide film is between about 25 Å and about 35 Åthick.
13. The method of claim 1, wherein the metal precursor comprises an aluminum, zirconium, or hafnium precursor.
14. The method of claim 13, wherein the metal precursor comprises an aluminum precursor.
15. The method of claim 14, wherein the aluminum precursor comprises trimethylaluminum.
16. The method of claim 1, wherein the oxygen precursor comprises water or ozone.
17. The method of claim 1, wherein the second purge comprises flooding the chamber with an inert gas.
18. The method of claim 16, wherein the inert gas comprises argon, nitrogen, or helium.
19. The method of claim 1, wherein the first purge comprises flooding the chamber with an inert gas.
20. The method of claim 19, wherein the inert gas comprises argon, nitrogen, or helium.
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016114850A1 (en) * 2015-01-14 2016-07-21 Agilent Technologies, Inc. Components with an atomic layer deposition coating and methods of producing the same
CN108604635A (en) * 2016-01-26 2018-09-28 Arm有限公司 The manufacture of associated electrical material devices
US10767259B2 (en) 2013-07-19 2020-09-08 Agilent Technologies, Inc. Components with an atomic layer deposition coating and methods of producing the same
US10895009B2 (en) 2013-07-19 2021-01-19 Agilent Technologies, Inc. Metal components with inert vapor phase coating on internal surfaces

Families Citing this family (93)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140034632A1 (en) * 2012-08-01 2014-02-06 Heng Pan Apparatus and method for selective oxidation at lower temperature using remote plasma source
US9132436B2 (en) 2012-09-21 2015-09-15 Applied Materials, Inc. Chemical control features in wafer process equipment
US10256079B2 (en) 2013-02-08 2019-04-09 Applied Materials, Inc. Semiconductor processing systems having multiple plasma configurations
US9362130B2 (en) 2013-03-01 2016-06-07 Applied Materials, Inc. Enhanced etching processes using remote plasma sources
US20150093889A1 (en) * 2013-10-02 2015-04-02 Intermolecular Methods for removing a native oxide layer from germanium susbtrates in the fabrication of integrated circuits
US20150093887A1 (en) * 2013-10-02 2015-04-02 GlobalFoundries, Inc. Methods for removing a native oxide layer from germanium susbtrates in the fabrication of integrated circuitsi
US9224594B2 (en) * 2013-11-18 2015-12-29 Intermolecular, Inc. Surface preparation with remote plasma
US9299557B2 (en) 2014-03-19 2016-03-29 Asm Ip Holding B.V. Plasma pre-clean module and process
US20150270134A1 (en) * 2014-03-19 2015-09-24 Qualcomm Incorporated Methods of forming a metal-insulator-semiconductor (mis) structure and a dual contact device
US9324804B2 (en) * 2014-03-21 2016-04-26 Wisconsin Alumni Research Foundation Graphene-on-semiconductor substrates for analog electronics
US9309598B2 (en) 2014-05-28 2016-04-12 Applied Materials, Inc. Oxide and metal removal
US9287359B1 (en) 2014-09-15 2016-03-15 Wisconsin Alumni Research Foundation Oriented bottom-up growth of armchair graphene nanoribbons on germanium
US9966240B2 (en) 2014-10-14 2018-05-08 Applied Materials, Inc. Systems and methods for internal surface conditioning assessment in plasma processing equipment
US9355922B2 (en) 2014-10-14 2016-05-31 Applied Materials, Inc. Systems and methods for internal surface conditioning in plasma processing equipment
US11637002B2 (en) 2014-11-26 2023-04-25 Applied Materials, Inc. Methods and systems to enhance process uniformity
US10573496B2 (en) 2014-12-09 2020-02-25 Applied Materials, Inc. Direct outlet toroidal plasma source
US9934992B2 (en) 2014-12-11 2018-04-03 Evatec Ag Chamber for degassing substrates
US9474163B2 (en) * 2014-12-30 2016-10-18 Asm Ip Holding B.V. Germanium oxide pre-clean module and process
US11257693B2 (en) 2015-01-09 2022-02-22 Applied Materials, Inc. Methods and systems to improve pedestal temperature control
US20160225652A1 (en) 2015-02-03 2016-08-04 Applied Materials, Inc. Low temperature chuck for plasma processing systems
US9728437B2 (en) 2015-02-03 2017-08-08 Applied Materials, Inc. High temperature chuck for plasma processing systems
US10373850B2 (en) 2015-03-11 2019-08-06 Asm Ip Holding B.V. Pre-clean chamber and process with substrate tray for changing substrate temperature
US10644187B2 (en) * 2015-07-24 2020-05-05 Artilux, Inc. Multi-wafer based light absorption apparatus and applications thereof
EP3326203B1 (en) 2015-07-24 2024-03-06 Artilux, Inc. Multi-wafer based light absorption apparatus and applications thereof
US9741593B2 (en) 2015-08-06 2017-08-22 Applied Materials, Inc. Thermal management systems and methods for wafer processing systems
US9691645B2 (en) 2015-08-06 2017-06-27 Applied Materials, Inc. Bolted wafer chuck thermal management systems and methods for wafer processing systems
US9349605B1 (en) 2015-08-07 2016-05-24 Applied Materials, Inc. Oxide etch selectivity systems and methods
US10504700B2 (en) 2015-08-27 2019-12-10 Applied Materials, Inc. Plasma etching systems and methods with secondary plasma injection
US9484255B1 (en) 2015-11-03 2016-11-01 International Business Machines Corporation Hybrid source and drain contact formation using metal liner and metal insulator semiconductor contacts
US9595449B1 (en) * 2015-12-21 2017-03-14 International Business Machines Corporation Silicon-germanium semiconductor devices and method of making
WO2017151958A1 (en) * 2016-03-02 2017-09-08 Tokyo Electron Limited Isotropic silicon and silicon-germanium etching with tunable selectivity
CN108780766B (en) 2016-03-08 2022-03-04 瑞士艾发科技 Chamber for degassing a substrate
SG11201809811VA (en) * 2016-05-05 2018-12-28 Veloce Biopharma Llc Compositions and methods for treatment of inflammation or infection of the eye
US10522371B2 (en) 2016-05-19 2019-12-31 Applied Materials, Inc. Systems and methods for improved semiconductor etching and component protection
US10504754B2 (en) 2016-05-19 2019-12-10 Applied Materials, Inc. Systems and methods for improved semiconductor etching and component protection
US11222959B1 (en) * 2016-05-20 2022-01-11 Hrl Laboratories, Llc Metal oxide semiconductor field effect transistor and method of manufacturing same
US9761669B1 (en) 2016-07-18 2017-09-12 Wisconsin Alumni Research Foundation Seed-mediated growth of patterned graphene nanoribbon arrays
US10269714B2 (en) 2016-09-06 2019-04-23 International Business Machines Corporation Low resistance contacts including intermetallic alloy of nickel, platinum, titanium, aluminum and type IV semiconductor elements
US10629473B2 (en) 2016-09-09 2020-04-21 Applied Materials, Inc. Footing removal for nitride spacer
US10546729B2 (en) 2016-10-04 2020-01-28 Applied Materials, Inc. Dual-channel showerhead with improved profile
US9934942B1 (en) 2016-10-04 2018-04-03 Applied Materials, Inc. Chamber with flow-through source
US10062579B2 (en) 2016-10-07 2018-08-28 Applied Materials, Inc. Selective SiN lateral recess
US10163696B2 (en) 2016-11-11 2018-12-25 Applied Materials, Inc. Selective cobalt removal for bottom up gapfill
US10026621B2 (en) 2016-11-14 2018-07-17 Applied Materials, Inc. SiN spacer profile patterning
US10566206B2 (en) 2016-12-27 2020-02-18 Applied Materials, Inc. Systems and methods for anisotropic material breakthrough
US10431429B2 (en) 2017-02-03 2019-10-01 Applied Materials, Inc. Systems and methods for radial and azimuthal control of plasma uniformity
US10319739B2 (en) 2017-02-08 2019-06-11 Applied Materials, Inc. Accommodating imperfectly aligned memory holes
US10943834B2 (en) 2017-03-13 2021-03-09 Applied Materials, Inc. Replacement contact process
US10319649B2 (en) 2017-04-11 2019-06-11 Applied Materials, Inc. Optical emission spectroscopy (OES) for remote plasma monitoring
US11276590B2 (en) 2017-05-17 2022-03-15 Applied Materials, Inc. Multi-zone semiconductor substrate supports
US11276559B2 (en) 2017-05-17 2022-03-15 Applied Materials, Inc. Semiconductor processing chamber for multiple precursor flow
KR102398688B1 (en) 2017-05-26 2022-05-16 주식회사 디비하이텍 Image sensor and method of manufacturing the same
US10497579B2 (en) 2017-05-31 2019-12-03 Applied Materials, Inc. Water-free etching methods
CN107248496B (en) * 2017-06-07 2019-11-15 西安电子科技大学 The modification method of ohmic contact regions square resistance
US10920320B2 (en) 2017-06-16 2021-02-16 Applied Materials, Inc. Plasma health determination in semiconductor substrate processing reactors
US10541246B2 (en) 2017-06-26 2020-01-21 Applied Materials, Inc. 3D flash memory cells which discourage cross-cell electrical tunneling
US10727080B2 (en) 2017-07-07 2020-07-28 Applied Materials, Inc. Tantalum-containing material removal
US10541184B2 (en) 2017-07-11 2020-01-21 Applied Materials, Inc. Optical emission spectroscopic techniques for monitoring etching
US10043674B1 (en) 2017-08-04 2018-08-07 Applied Materials, Inc. Germanium etching systems and methods
US10297458B2 (en) 2017-08-07 2019-05-21 Applied Materials, Inc. Process window widening using coated parts in plasma etch processes
US10283324B1 (en) * 2017-10-24 2019-05-07 Applied Materials, Inc. Oxygen treatment for nitride etching
US10424487B2 (en) 2017-10-24 2019-09-24 Applied Materials, Inc. Atomic layer etching processes
KR102018075B1 (en) * 2017-11-30 2019-09-04 무진전자 주식회사 Dry clean apparatus and method for removing polysilicon seletively
US10903054B2 (en) 2017-12-19 2021-01-26 Applied Materials, Inc. Multi-zone gas distribution systems and methods
US11328909B2 (en) 2017-12-22 2022-05-10 Applied Materials, Inc. Chamber conditioning and removal processes
US10290719B1 (en) 2017-12-27 2019-05-14 International Business Machines Corporation Indium gallium arsenide metal oxide semiconductor field effect transistor having a low contact resistance to metal electrode
US10854426B2 (en) 2018-01-08 2020-12-01 Applied Materials, Inc. Metal recess for semiconductor structures
US10964512B2 (en) 2018-02-15 2021-03-30 Applied Materials, Inc. Semiconductor processing chamber multistage mixing apparatus and methods
US10679870B2 (en) 2018-02-15 2020-06-09 Applied Materials, Inc. Semiconductor processing chamber multistage mixing apparatus
TWI766433B (en) 2018-02-28 2022-06-01 美商應用材料股份有限公司 Systems and methods to form airgaps
US10593560B2 (en) 2018-03-01 2020-03-17 Applied Materials, Inc. Magnetic induction plasma source for semiconductor processes and equipment
US10319600B1 (en) 2018-03-12 2019-06-11 Applied Materials, Inc. Thermal silicon etch
US10497573B2 (en) 2018-03-13 2019-12-03 Applied Materials, Inc. Selective atomic layer etching of semiconductor materials
US10573527B2 (en) 2018-04-06 2020-02-25 Applied Materials, Inc. Gas-phase selective etching systems and methods
US10490406B2 (en) 2018-04-10 2019-11-26 Appled Materials, Inc. Systems and methods for material breakthrough
US10699879B2 (en) 2018-04-17 2020-06-30 Applied Materials, Inc. Two piece electrode assembly with gap for plasma control
US10886137B2 (en) 2018-04-30 2021-01-05 Applied Materials, Inc. Selective nitride removal
US10872778B2 (en) 2018-07-06 2020-12-22 Applied Materials, Inc. Systems and methods utilizing solid-phase etchants
US10755941B2 (en) 2018-07-06 2020-08-25 Applied Materials, Inc. Self-limiting selective etching systems and methods
US10672642B2 (en) 2018-07-24 2020-06-02 Applied Materials, Inc. Systems and methods for pedestal configuration
US11049755B2 (en) 2018-09-14 2021-06-29 Applied Materials, Inc. Semiconductor substrate supports with embedded RF shield
US10892198B2 (en) 2018-09-14 2021-01-12 Applied Materials, Inc. Systems and methods for improved performance in semiconductor processing
US11062887B2 (en) 2018-09-17 2021-07-13 Applied Materials, Inc. High temperature RF heater pedestals
US11417534B2 (en) 2018-09-21 2022-08-16 Applied Materials, Inc. Selective material removal
US11682560B2 (en) 2018-10-11 2023-06-20 Applied Materials, Inc. Systems and methods for hafnium-containing film removal
US11121002B2 (en) 2018-10-24 2021-09-14 Applied Materials, Inc. Systems and methods for etching metals and metal derivatives
US11437242B2 (en) 2018-11-27 2022-09-06 Applied Materials, Inc. Selective removal of silicon-containing materials
US11088028B2 (en) * 2018-11-30 2021-08-10 Taiwan Semiconductor Manufacturing Company, Ltd. Fin field-effect transistor device and method of forming the same
US11721527B2 (en) 2019-01-07 2023-08-08 Applied Materials, Inc. Processing chamber mixing systems
US10920319B2 (en) 2019-01-11 2021-02-16 Applied Materials, Inc. Ceramic showerheads with conductive electrodes
CN112986357A (en) * 2019-12-13 2021-06-18 成都今是科技有限公司 Microelectrode of gene sequencing chip, preparation method thereof and gene sequencing chip
WO2022098517A1 (en) * 2020-11-03 2022-05-12 Tokyo Electron Limited Method for filling recessed features in semiconductor devices with a low-resistivity metal
US11618681B2 (en) 2021-06-28 2023-04-04 Wisconsin Alumni Research Foundation Graphene nanoribbons grown from aromatic molecular seeds

Family Cites Families (85)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3676756A (en) * 1969-09-18 1972-07-11 Innotech Corp Insulated gate field effect device having glass gate insulator
GB1417085A (en) * 1973-05-17 1975-12-10 Standard Telephones Cables Ltd Plasma etching
US4361461A (en) 1981-03-13 1982-11-30 Bell Telephone Laboratories, Incorporated Hydrogen etching of semiconductors and oxides
US4675073A (en) * 1986-03-07 1987-06-23 Texas Instruments Incorporated Tin etch process
US5116679A (en) * 1988-07-29 1992-05-26 Alcan International Limited Process for producing fibres composed of or coated with carbides or nitrides
KR0144932B1 (en) * 1995-01-26 1998-07-01 김광호 Capacitor of semiconductor device and manufacturing method thereof
US6013553A (en) * 1997-07-24 2000-01-11 Texas Instruments Incorporated Zirconium and/or hafnium oxynitride gate dielectric
US6714300B1 (en) * 1998-09-28 2004-03-30 Therma-Wave, Inc. Optical inspection equipment for semiconductor wafers with precleaning
US7012292B1 (en) * 1998-11-25 2006-03-14 Advanced Technology Materials, Inc Oxidative top electrode deposition process, and microelectronic device structure
US7053002B2 (en) * 1998-12-04 2006-05-30 Applied Materials, Inc Plasma preclean with argon, helium, and hydrogen gases
JP2002016248A (en) * 2000-06-30 2002-01-18 Mitsubishi Electric Corp Manufacturing method of semiconductor device
US6613695B2 (en) * 2000-11-24 2003-09-02 Asm America, Inc. Surface preparation prior to deposition
US6900498B2 (en) * 2001-05-08 2005-05-31 Advanced Technology Materials, Inc. Barrier structures for integration of high K oxides with Cu and Al electrodes
CN100468638C (en) * 2001-12-18 2009-03-11 松下电器产业株式会社 Method for mfg. semiconductor elements
DE10221503A1 (en) * 2002-05-14 2003-11-27 Infineon Technologies Ag Metal object intended for at least partial coating with a substance
US20030232501A1 (en) * 2002-06-14 2003-12-18 Kher Shreyas S. Surface pre-treatment for enhancement of nucleation of high dielectric constant materials
US6804136B2 (en) * 2002-06-21 2004-10-12 Micron Technology, Inc. Write once read only memory employing charge trapping in insulators
JP2004186567A (en) * 2002-12-05 2004-07-02 Toshiba Corp Semiconductor device and manufacturing method of semiconductor device
US6756291B1 (en) * 2003-01-24 2004-06-29 Taiwan Semiconductor Manufacturing Co., Ltd Method for hardening gate oxides using gate etch process
CN1841675A (en) * 2003-02-12 2006-10-04 松下电器产业株式会社 Method for fabricating semiconductor device
US7604708B2 (en) 2003-02-14 2009-10-20 Applied Materials, Inc. Cleaning of native oxide with hydrogen-containing radicals
JP4315701B2 (en) * 2003-02-25 2009-08-19 シャープ株式会社 Nitride III-V compound semiconductor electrode and method for producing the same
KR100541678B1 (en) * 2003-06-30 2006-01-11 주식회사 하이닉스반도체 method for manufacturing metal line
US6811448B1 (en) 2003-07-15 2004-11-02 Advanced Micro Devices, Inc. Pre-cleaning for silicidation in an SMOS process
US20050056219A1 (en) * 2003-09-16 2005-03-17 Tokyo Electron Limited Formation of a metal-containing film by sequential gas exposure in a batch type processing system
JP3729826B2 (en) * 2004-01-09 2005-12-21 松下電器産業株式会社 Method for manufacturing solid-state imaging device
EP1722970A4 (en) * 2004-02-25 2012-10-03 Agc Flat Glass Na Inc Heat stabilized sub-stoichiometric dielectrics
JP2005268312A (en) 2004-03-16 2005-09-29 Semiconductor Leading Edge Technologies Inc Resist removing method and semiconductor device manufactured using same
US6946368B1 (en) * 2004-03-23 2005-09-20 Applied Materials, Inc. Reduction of native oxide at germanium interface using hydrogen-based plasma
US7279413B2 (en) * 2004-06-16 2007-10-09 International Business Machines Corporation High-temperature stable gate structure with metallic electrode
US8084400B2 (en) * 2005-10-11 2011-12-27 Intermolecular, Inc. Methods for discretized processing and process sequence integration of regions of a substrate
US7465674B2 (en) * 2005-05-31 2008-12-16 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of semiconductor device
US20100200863A1 (en) * 2005-07-08 2010-08-12 Nec Corporation Electrode structure, semiconductor device, and methods for manufacturing those
US7402534B2 (en) * 2005-08-26 2008-07-22 Applied Materials, Inc. Pretreatment processes within a batch ALD reactor
US20070107750A1 (en) 2005-11-14 2007-05-17 Sawin Herbert H Method of using NF3 for removing surface deposits from the interior of chemical vapor deposition chambers
US7892985B1 (en) * 2005-11-15 2011-02-22 Novellus Systems, Inc. Method for porogen removal and mechanical strength enhancement of low-k carbon doped silicon oxide using low thermal budget microwave curing
US8772772B2 (en) * 2006-05-18 2014-07-08 Intermolecular, Inc. System and method for increasing productivity of combinatorial screening
US20070202610A1 (en) * 2006-02-10 2007-08-30 Chiang Tony P Method and apparatus for combinatorially varying materials, unit process and process sequence
US20080087890A1 (en) * 2006-10-16 2008-04-17 Micron Technology, Inc. Methods to form dielectric structures in semiconductor devices and resulting devices
US8169078B2 (en) * 2006-12-28 2012-05-01 Renesas Electronics Corporation Electrode structure, semiconductor element, and methods of manufacturing the same
FR2913146B1 (en) * 2007-02-23 2009-05-01 Saint Gobain DISCONTINUOUS ELECTRODE, ORGANIC ELECTROLUMINESCENCE DEVICE INCORPORATING THE SAME, AND THEIR MANUFACTURING
US8344375B2 (en) * 2007-03-05 2013-01-01 Intermolecular, Inc. Nonvolatile memory elements with metal deficient resistive switching metal oxides
US8144498B2 (en) * 2007-05-09 2012-03-27 Intermolecular, Inc. Resistive-switching nonvolatile memory elements
KR100864932B1 (en) 2007-07-23 2008-10-22 주식회사 동부하이텍 Method for cleaning of a semiconductor substrate
TW200929526A (en) * 2007-12-24 2009-07-01 Powerchip Semiconductor Corp Non-volatile memory and fabricating method thereof
FR2925981B1 (en) * 2007-12-27 2010-02-19 Saint Gobain CARRIER SUBSTRATE OF AN ELECTRODE, ORGANIC ELECTROLUMINESCENT DEVICE INCORPORATING IT.
US8343813B2 (en) * 2009-04-10 2013-01-01 Intermolecular, Inc. Resistive-switching memory elements having improved switching characteristics
TWI450399B (en) * 2008-07-31 2014-08-21 Semiconductor Energy Lab Semiconductor device and method for manufacturing the same
US8124992B2 (en) * 2008-08-27 2012-02-28 Showa Denko K.K. Light-emitting device, manufacturing method thereof, and lamp
WO2010038423A1 (en) * 2008-10-01 2010-04-08 パナソニック株式会社 Nonvolatile storage element and nonvolatile storage device using same
KR20100101450A (en) * 2009-03-09 2010-09-17 삼성전자주식회사 Semiconductor device and associated methods of manufacture
EP2259267B1 (en) * 2009-06-02 2013-08-21 Imec Method for manufacturing a resistive switching memory cell comprising a nickel oxide layer operable at low-power and memory cells obtained thereof
WO2011007538A1 (en) * 2009-07-13 2011-01-20 パナソニック株式会社 Variably resistant element and variably resistant memory device
KR102443836B1 (en) * 2009-09-17 2022-09-15 사이오닉스, 엘엘씨 Photosensitive imaging devices and associated methods
US8476681B2 (en) * 2009-09-17 2013-07-02 Sionyx, Inc. Photosensitive imaging devices and associated methods
US8106469B2 (en) * 2010-01-14 2012-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of fluorine passivation
EP2348531B1 (en) * 2010-01-26 2021-05-26 Samsung Electronics Co., Ltd. Thin film transistor and method of manufacturing the same
US8435902B2 (en) 2010-03-17 2013-05-07 Applied Materials, Inc. Invertable pattern loading with dry etch
WO2011114725A1 (en) * 2010-03-19 2011-09-22 パナソニック株式会社 Nonvolatile memory element, production method therefor, design support method therefor, and nonvolatile memory device
US8629523B2 (en) * 2010-04-16 2014-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Inserted reflective shield to improve quantum efficiency of image sensors
JP5320601B2 (en) * 2010-04-23 2013-10-23 シャープ株式会社 Nonvolatile variable resistance element and nonvolatile semiconductor memory device
JP5186634B2 (en) * 2010-06-29 2013-04-17 シャープ株式会社 Nonvolatile semiconductor memory device
WO2012001993A1 (en) * 2010-07-02 2012-01-05 パナソニック株式会社 Variable resistance non-volatile storage element, variable resistance non-volatile storage device, and manufacturing method for variable resistance non-volatile storage element
US8374018B2 (en) * 2010-07-09 2013-02-12 Crossbar, Inc. Resistive memory using SiGe material
US8889478B2 (en) * 2010-11-19 2014-11-18 Panasonic Corporation Method for manufacturing nonvolatile semiconductor memory element, and nonvolatile semiconductor memory element
US8861257B2 (en) * 2010-11-24 2014-10-14 Panasonic Corporation Nonvolatile memory element, manufacturing method thereof, nonvolatile memory device, and design support method for nonvolatile memory element
WO2012081248A1 (en) * 2010-12-15 2012-06-21 パナソニック株式会社 Non-volatile memory device
US8349731B2 (en) * 2011-03-25 2013-01-08 GlobalFoundries, Inc. Methods for forming copper diffusion barriers for semiconductor interconnect structures
US8546781B2 (en) * 2011-05-31 2013-10-01 The Board Of Trustees Of The Leland Stanford Junior University Nitrogen doped aluminum oxide resistive random access memory
US20120313205A1 (en) * 2011-06-10 2012-12-13 Homayoon Haddad Photosensitive Imagers Having Defined Textures for Light Trapping and Associated Methods
US8846443B2 (en) * 2011-08-05 2014-09-30 Intermolecular, Inc. Atomic layer deposition of metal oxides for memory applications
US8288297B1 (en) * 2011-09-01 2012-10-16 Intermolecular, Inc. Atomic layer deposition of metal oxide materials for memory applications
US8659001B2 (en) * 2011-09-01 2014-02-25 Sandisk 3D Llc Defect gradient to boost nonvolatile memory performance
US9087581B2 (en) * 2011-09-09 2015-07-21 Panasonic Intellectual Property Management Co., Ltd. Cross point variable resistance nonvolatile memory device and method of writing thereby
JP5404977B2 (en) * 2011-09-27 2014-02-05 パナソニック株式会社 Nonvolatile memory element, nonvolatile memory device and manufacturing method thereof
US8822265B2 (en) * 2011-10-06 2014-09-02 Intermolecular, Inc. Method for reducing forming voltage in resistive random access memory
WO2013073187A1 (en) * 2011-11-17 2013-05-23 パナソニック株式会社 Variable resistance nonvolatile storage device and method for manufacturing same
JP5845866B2 (en) * 2011-12-07 2016-01-20 富士通セミコンダクター株式会社 Manufacturing method of semiconductor device
US8920618B2 (en) * 2011-12-29 2014-12-30 Intermolecular, Inc. Combinatorial processing using high deposition rate sputtering
US8779406B2 (en) * 2012-01-23 2014-07-15 Panasonic Corporation Nonvolatile memory element and method for manufacturing the same
JP2013157469A (en) * 2012-01-30 2013-08-15 Sharp Corp Variable resistive element, and nonvolatile semiconductor storage device
US8569104B2 (en) * 2012-02-07 2013-10-29 Intermolecular, Inc. Transition metal oxide bilayers
US20140011339A1 (en) 2012-07-06 2014-01-09 Applied Materials, Inc. Method for removing native oxide and residue from a germanium or iii-v group containing surface
US20140124817A1 (en) * 2012-11-05 2014-05-08 Intermolecular, Inc. Contact Layers
US9331293B2 (en) * 2013-03-14 2016-05-03 Nutech Ventures Floating-gate transistor photodetector with light absorbing layer

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10767259B2 (en) 2013-07-19 2020-09-08 Agilent Technologies, Inc. Components with an atomic layer deposition coating and methods of producing the same
US10895009B2 (en) 2013-07-19 2021-01-19 Agilent Technologies, Inc. Metal components with inert vapor phase coating on internal surfaces
WO2016114850A1 (en) * 2015-01-14 2016-07-21 Agilent Technologies, Inc. Components with an atomic layer deposition coating and methods of producing the same
CN108604635A (en) * 2016-01-26 2018-09-28 Arm有限公司 The manufacture of associated electrical material devices

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