US20140157001A1 - Secure testing of semiconductor device - Google Patents
Secure testing of semiconductor device Download PDFInfo
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- US20140157001A1 US20140157001A1 US13/846,718 US201313846718A US2014157001A1 US 20140157001 A1 US20140157001 A1 US 20140157001A1 US 201313846718 A US201313846718 A US 201313846718A US 2014157001 A1 US2014157001 A1 US 2014157001A1
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- processor
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/76—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/14—Protection against unauthorised use of memory or access to memory
- G06F12/1408—Protection against unauthorised use of memory or access to memory by using cryptography
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
- G06F21/57—Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
- G06F21/57—Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
- G06F21/572—Secure firmware programming, e.g. of basic input output system [BIOS]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/60—Protecting data
- G06F21/606—Protecting data by securing the transmission between two devices or processes
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/60—Protecting data
- G06F21/64—Protecting data integrity, e.g. using checksums, certificates or signatures
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2221/00—Indexing scheme relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F2221/21—Indexing scheme relating to G06F21/00 and subgroups addressing additional information or applications relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F2221/2107—File encryption
Definitions
- the technical field of the present disclosure relates to information security and, in particular to secure testing of semiconductor devices.
- Maintaining security in processors can be critical for various reasons. Such security may be desirable to maintain secrecy of certain aspects of proprietary code, prevent malicious code from interfering with processing and avoid unintended interaction with other processing code.
- FIG. 1 is an example schematic representation of a manufacturing flow
- FIG. 2 is an example schematic representation of another manufacturing flow
- FIG. 3 is a flow chart illustrating an example delivery of secure processing code in the manufacturing flows of FIGS. 1 and 2 ;
- FIG. 4 is an example schematic representation of a testing arrangement
- FIG. 5 is an example schematic representation of another testing arrangement.
- FIG. 6 is a flow chart of an example testing process.
- a semiconductor device such as a chip or chipset, that may be used in various communication devices.
- Semiconductor devices may include various components, such as circuitry, memory, etc.
- Some semiconductor devices may include an embedded flash memory which may be used to store various processing code, for example.
- a semiconductor device such as a chip or a chipset
- an external flash memory may be coupled to the semiconductor device subsequent to fabrication and testing of the semiconductor device.
- the embedded flash memory may be included in the semiconductor device prior to testing.
- a controlled or certified manufacturing flow arrangement 100 may be used to design, fabricate and test semiconductor devices.
- the flow arrangement 100 begins with the design of the physical circuitry, processing code and other components and/or functionality of a semiconductor device in a secure zone 110 .
- the secure zone 110 may be a physical or virtual location with access limited to certain individuals and/or entities.
- design information of a semiconductor device may be transmitted to a fabrication facility 140 .
- the design information may be transmitted via a stream of data in, for example, a graphic data system (GDS-II) format.
- the fabrication facility 140 may produce semiconductor devices that are then delivered to a testing facility 150 .
- the secure zone 110 , fabrication facility 140 and the testing facility 150 may be remotely located to each other, or two or more facilities may be co-located.
- a secure processing code also known as an image
- the encrypted image 130 may include, for example, operating system patches for customization of the destination semiconductor device.
- the encrypted image 130 may also include, without limitation, customized or pre-personalized applets or confidential customer data.
- the code is encrypted using the Triple Data Encryption Standard (3DES) algorithm.
- 3DES Triple Data Encryption Standard
- an identifier associated with a device or a set of devices may be used in the encryption process. For example, a serial number or a set of serial numbers may be used as the identifier.
- the fabricated semiconductor devices are delivered to testing facility 150 from the fabrication facility 140 for testing.
- a hardware security module (HSM) 120 containing certain encryption keys may be delivered to the testing facility.
- the HSM 120 may be a hardware component which includes encryption keys associated with the encrypted image 130 .
- the encryption keys may be used for testing of a secure portion of a semiconductor device using the HSM.
- the semiconductor devices s are tested by operators at the testing facility 150 through one or more tests 152 .
- the HSM places (e.g., writes, stores or injects) the encryption keys into the semiconductor device 154 .
- the keys may be injected into a secure portion of the semiconductor device.
- the semiconductor devices, such as the semiconductor device 190 may then be delivered to an original equipment manufacturer (OEM) 160 for implementing, for example, into a communication device.
- OEM original equipment manufacturer
- the encrypted image 130 is typically stored on a flash memory.
- the semiconductor device design may not include an embedded flash memory. Accordingly, in accordance with the illustrated example of FIG. 1 , the encrypted image 130 is transmitted to the OEM 160 for storage in a memory device, such as an external flash memory 170 .
- the semiconductor device 190 fabricated using the manufacturing flow 100 to the OEM 160 includes a non-secure portion 192 , also referred to herein as a peripheral processing system (PPS), and a secure portion 194 , also referred to herein as a secure processing system (SPS).
- the secure portion 194 may include functionality associated with secure processing by the semiconductor device 190 .
- the secure portion 194 may include the encryption keys injected into the semiconductor device 190 by the HSM 120 .
- the encrypted image 130 received by the OEM 160 may be written to the flash memory 170 through the non-secure portion 192 of the semiconductor device 190 (arrow 182 ).
- the encrypted image 130 in the flash memory 170 may be verified by decrypting the encrypted image in the secure portion 194 of the semiconductor device 190 using the encryption keys injected into the secure portion 194 (arrow 184 ).
- code may be provided in the secure portion 194 to perform the decryption using the encryption keys.
- the semiconductor device 190 may be securely customized, or pre-personalized, in the secure zone.
- the encrypted image 130 may be associated with a specific semiconductor device, and the encryption keys used to decrypt the encrypted image at the secure portion 194 of the semiconductor device 190 may also be accordingly associated with the specific semiconductor device.
- the encryption keys may be associated with, for example, a serial number of the target semiconductor device.
- the secure portion 194 may then re-encrypt the image for writing to the flash memory 170 (arrow 186 ).
- the re-encryption by the secure portion 194 may be accomplished using encryption keys that may be generated by the secure portion 194 and that may be unique to each semiconductor device.
- the encrypted image 130 may be securely delivered to an external flash memory 170 .
- the encrypted image 130 may be written to a flash memory 170 during, for example, manufacture of the flash memory 170 .
- the encrypted image 130 may be delivered to a manufacturer of the flash memory 170 or to a post-manufacturing entity of the flash memory 170 .
- the flash memory 170 with the encrypted image 130 may then be delivered to the OEM 160 for association with the semiconductor device 190 (e.g., installation on a user equipment having the semiconductor device 190 ).
- the semiconductor device 190 e.g., installation on a user equipment having the semiconductor device 190 .
- the secure portion 194 of the semiconductor device 190 may decrypt and verify the encrypted image 130 (arrow 184 ) and re-encrypt the decrypted image using encryption keys generated by the secure portion 194 for writing back onto the flash memory 170 (arrow 186 ).
- the image may be encrypted with an encryption key (block 10 ) at, for example, a secure zone 110 .
- an encryption key block 10
- the encrypted image is delivered to an OEM (block 12 ), where the encrypted image may be written on a flash memory that is embedded in a user equipment having a semiconductor device associated with the encrypted image (block 14 ).
- the flash memory may be external to a semiconductor device that is delivered to the OEM.
- the encrypted image is written to a flash memory (block 16 ) during, for example, manufacturing of the flash memory.
- the flash memory with the encrypted image may then be delivered to the OEM for coupling to a semiconductor device (block 18 ).
- the encrypted image may be decrypted in a secure portion of the semiconductor device (block 20 ) by, for example, code provided in the secure portion to perform decryption using the encryption key.
- the semiconductor device may be provided with the encryption key used to decrypt the image for verification, for example.
- the secure portion of the semiconductor device may then re-encrypt the decrypted image (block 22 ) for re-writing the re-encrypted image to the flash memory (block 24 ).
- the re-encryption of the decrypted image may be accomplished using any of a variety of encryption techniques.
- the encryption keys used for the re-encryption may be generated by the secure portion of the semiconductor device to provide additional security.
- the encryption keys since the encryption keys are generated by the secure portion and may be unique to each semiconductor device, the encryption keys may be unknown to any other entity and may thus be unbreakable.
- the semiconductor devices may be delivered from the fabrication facility 140 to a testing facility 150 .
- Such testing facilities may be used to test various devices, such as semiconductor devices. Further, such testing facilities may be used to test devices that may have secure and non-secure portions.
- Traditional testing may use a test key which may serve as an encryption key used during the testing.
- the test key may be embedded on the device, such as a semiconductor device, which may be referred to during testing as a device under test (DUT).
- DUT device under test
- sensitive information such as test keys or encryption keys to be injected into a secure portion
- test keys may include encryption keys that are used specifically for testing of the DUT and may not be injected into the DUT for any later use.
- other encryption keys that are injected into the secure portion may be used to decrypt and verify an encrypted image, as described above.
- all sensitive information is securely removed from the tester 210 .
- the tester 210 is shown connected to a load board 220 .
- the load board 220 may accommodate one or more DUTs, such as the semiconductor device 190 .
- the semiconductor device 190 includes a non-secure portion 192 and a secure portion 194 .
- the load board 220 may further accommodate one or more HSMs, such as HSM 120 .
- FIG. 4 illustrates a load board 220 having a single semiconductor device 190 and a single HSM 120
- various examples may include any desired number of semiconductor devices and any appropriate number of HSMs.
- the HSM 120 illustrated in FIG. 4 is provided with a first interface 124 for communication with the semiconductor device 190 and a second interface 126 for communication with the tester 210 .
- the HSM 120 may also include a processor, such as a secure testing processor 122 , configured to perform various functions such as, for example, perform testing of the secure portion 194 of the semiconductor device 190 , as described below. Further, the secure testing processor 122 may also be configured to control operation of the HSM 120 and control communication with the semiconductor device 190 and/or the tester 210 . The secure testing processor 122 may also be provided with a memory for storage, for example, of data such as encryption keys.
- the testing of the non-secure portion 192 may be performed by the tester 210
- testing of the secure portion 194 may be performed by the HSM 120 without providing access to the secure portion to the tester 210 .
- the HSM 120 may allow direct communication between the tester 210 and the non-secure portion 192 of the semiconductor device 190 .
- the tester 210 may send signals to and receive signals from the non-secure portion 192 of the semiconductor device 190 , as illustrated by the line 224 in FIG. 4 .
- the direct communication between the non-secure portion 192 and the tester 210 may be performed through the HSM 120 , through the interfaces 124 , 126 .
- the HSM 120 may server merely as a conduit for the communication between the non-secure portion 194 and the tester 210 .
- the communication between the non-secure portion 194 and the tester 210 may completely bypass the HSM 120 .
- the secure portion 194 may be isolated from the tester 210 . As illustrated in the example of FIG. 4 , the testing of the secure portion 194 may be performed by the secure testing processor 122 of the HSM 120 . In this regard, the HSM 120 or the secure testing processor 122 may be provided with secure testing keys which may be delivered (e.g., injected or installed) into the secure portion 194 for purposes of testing. Any necessary testing of the secure portion 194 may be performed by the secure testing processor 122 of the HSM 120 with communication through the first interface 124 , as illustrated by the line 222 in FIG. 4 .
- the results of the testing of the secure portion 194 may be communicated to the tester 210 by the HSM 120 through the second interface 126 as, for example, a simple pass or fail indication.
- the result may be communicated as a 1-bit signal where a “0” is indicative of a pass and a “1” is indicative of a fail (or vice versa).
- the tester 210 may test the non-secure portion 192 by commanding the HSM 120 to position a relay 230 to allow direct communication between the tester 210 and the non-secure portion 192 of the semiconductor device 190 .
- the HSM 120 may position the relay 230 to a tester input/output position 234 .
- the tester 210 may command the HSM 120 to switch the relay 230 to an interface 232 between the HSM 120 and the semiconductor device 190 .
- the HSM 120 may then establish a secure channel with the secure portion 194 using a test key.
- the secure portion 192 and the non-secure portion 194 may be tested in any order. For example, in some cases, the non-secure portion 194 may be tested first, while in other cases, the secure portion 192 may be tested first.
- the testing of the secure portion 194 may be performed under the control of the HSM 120 .
- the HSM may inject the secure testing keys into the secure portion 194 .
- the HSM 120 may communicate the results of the testing of the secure portion 194 to the tester 210 with a simple indication of “pass” or “fail”.
- the indication may be a 1-bit signal.
- the load board Upon completion of the testing, the load board is removed from the tester. Along with the load board, all secure information (e.g., the secure portion 194 of the semiconductor device 190 and the test keys for testing of the secure portion) are also removed. Thus, the tester 210 is never provided with access to any secure information. For example, the test keys and encryption keys provided in the HSM 120 are kept isolated from the tester 210 .
- a semiconductor device may be coupled to an HSM through a first interface (block 610 ).
- the semiconductor device 190 shown in FIGS. 4 and 5 may be coupled to the HSM 120 through the first interface 124 .
- a tester may be coupled to the HSM through a second interface (block 612 ).
- the tester 210 may be coupled to the load board 220 and the HSM 120 through the second interface 126 .
- the secure portion of the semiconductor device may then be tested by the HSM using a test key which may have been provided with the HSM (block 614 ).
- a test key which may have been provided with the HSM
- test keys and/or other secure information may be provided in the HSM 120 .
- all secure information is kept isolated from the tester.
- a simple “pass” or “fail” indication of the results of the testing of the secure portion may be communicated by the HSM 120 to the tester 210 through the second interface 126 .
- the HSM may inject encryption keys into the secure portion (block 616 ).
- the HSM may include secure information, such as encryption keys, that are injected into the secure portion. Again, this allows isolation of all secure information from the tester during testing.
- the encryption keys may be used to decrypt processing code, such as the encrypted image 130 , as illustrated by the arrow 184 in FIGS. 1 and 2 .
- the HSM may position a relay switch, such as relay switch 230 of FIG. 5 , to allow direct communication between the non-secure portion of the semiconductor device and the tester (block 618 ). As noted above, this allows the tester to test the non-secure portion of the semiconductor device (block 620 ).
- the positioning of the relay switch by the HSM may be in response to commands from the tester, for example. While FIG. 6 illustrates an example in which the secure portion is tested before the non-secure portion, those skilled in the art will appreciate that the order of testing may be reversed. For example, the non-secure portion may be tested and then the relay switch may be positioned to allow the processor of the HSM to test the secure portion.
- the secure portion of the semiconductor device may be tested and various keys (e.g., encryption keys) may be provided to the secure portion in a secure manner without the need for placing the tester in a secure location.
- the various diagrams may depict an example architectural or other configuration for the various embodiments, which is done to aid in understanding the features and functionality that can be included in embodiments.
- the present disclosure is not restricted to the illustrated example architectures or configurations, and the desired features can be implemented using a variety of alternative architectures and configurations. Indeed, it will be apparent to one of skill in the art how alternative functional, logical or physical partitioning and configurations can be implemented to implement various embodiments. Also, a multitude of different constituent module names other than those depicted herein can be applied to the various partitions. Additionally, with regard to flow diagrams, operational descriptions and method claims, the order in which the steps are presented herein shall not mandate that various embodiments be implemented to perform the recited functionality in the same order unless the context dictates otherwise.
- various embodiments described herein are described in the general context of method steps or processes, which may be implemented in one embodiment by a computer program product, embodied in, e.g., a non-transitory computer-readable memory, including computer-executable instructions, such as program code, executed by computers in networked environments.
- a computer-readable memory may include removable and non-removable storage devices including, but not limited to, Read Only Memory (ROM), Random Access Memory (RAM), compact discs (CDs), digital versatile discs (DVD), etc.
- program modules may include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types.
- Computer-executable instructions, associated data structures, and program modules represent examples of program code for executing steps of the methods disclosed herein. The particular sequence of such executable instructions or associated data structures represents examples of corresponding acts for implementing the functions described in such steps or processes.
- module can describe a given unit of functionality that can be performed in accordance with one or more embodiments.
- a module might be implemented utilizing any form of hardware, software, or a combination thereof.
- processors, controllers, application-specific integrated circuits (ASICs), programmable logic arrays (PLAs), programmable array logic (PALs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), logical components, software routines or other mechanisms might be implemented to make up a module.
- ASICs application-specific integrated circuits
- PLAs programmable logic arrays
- PALs programmable array logic
- CPLDs complex programmable logic devices
- FPGAs field-programmable gate arrays
- the various modules described herein might be implemented as discrete modules or the functions and features described can be shared in part or in total among one or more modules.
Abstract
Description
- The technical field of the present disclosure relates to information security and, in particular to secure testing of semiconductor devices.
- Maintaining security in processors can be critical for various reasons. Such security may be desirable to maintain secrecy of certain aspects of proprietary code, prevent malicious code from interfering with processing and avoid unintended interaction with other processing code.
- For a more complete understanding of various examples, reference is now made to the following descriptions taken in connection with the accompanying drawings in which:
-
FIG. 1 is an example schematic representation of a manufacturing flow; -
FIG. 2 is an example schematic representation of another manufacturing flow; -
FIG. 3 is a flow chart illustrating an example delivery of secure processing code in the manufacturing flows ofFIGS. 1 and 2 ; -
FIG. 4 is an example schematic representation of a testing arrangement; -
FIG. 5 is an example schematic representation of another testing arrangement; and -
FIG. 6 is a flow chart of an example testing process. - In various embodiments, a semiconductor device, such as a chip or chipset, that may be used in various communication devices is provided. Semiconductor devices may include various components, such as circuitry, memory, etc. Some semiconductor devices may include an embedded flash memory which may be used to store various processing code, for example.
- In various embodiments described herein, a semiconductor device, such as a chip or a chipset, may be manufactured without an embedded flash memory. Instead, an external flash memory may be coupled to the semiconductor device subsequent to fabrication and testing of the semiconductor device. In other examples, the embedded flash memory may be included in the semiconductor device prior to testing.
- Referring now to
FIG. 1 , an example schematic representation of a manufacturing flow is illustrated. In the example ofFIG. 1 , a controlled or certifiedmanufacturing flow arrangement 100 may be used to design, fabricate and test semiconductor devices. Theflow arrangement 100 begins with the design of the physical circuitry, processing code and other components and/or functionality of a semiconductor device in asecure zone 110. Thesecure zone 110 may be a physical or virtual location with access limited to certain individuals and/or entities. From thesecure zone 110, design information of a semiconductor device may be transmitted to afabrication facility 140. In some embodiments, the design information may be transmitted via a stream of data in, for example, a graphic data system (GDS-II) format. Thefabrication facility 140 may produce semiconductor devices that are then delivered to atesting facility 150. In various embodiments, thesecure zone 110,fabrication facility 140 and thetesting facility 150 may be remotely located to each other, or two or more facilities may be co-located. - Referring again to the
secure zone 110, a secure processing code, also known as an image, may be generated and encrypted to produce encrypted processing code, or anencrypted image 130. Theencrypted image 130 may include, for example, operating system patches for customization of the destination semiconductor device. In various embodiments, theencrypted image 130 may also include, without limitation, customized or pre-personalized applets or confidential customer data. - In encrypting the image, various encryption strategies may be used. For example, in one embodiment, the code is encrypted using the Triple Data Encryption Standard (3DES) algorithm. In one embodiment, in order to facilitate customization or pre-personalization of a destination device, an identifier associated with a device or a set of devices may be used in the encryption process. For example, a serial number or a set of serial numbers may be used as the identifier.
- Referring now to the
testing facility 150, as noted above, the fabricated semiconductor devices are delivered totesting facility 150 from thefabrication facility 140 for testing. Additionally, a hardware security module (HSM) 120 containing certain encryption keys may be delivered to the testing facility. In this regard, the HSM 120 may be a hardware component which includes encryption keys associated with theencrypted image 130. As described below, the encryption keys may be used for testing of a secure portion of a semiconductor device using the HSM. - The semiconductor devices s are tested by operators at the
testing facility 150 through one ormore tests 152. Upon successful completion of the testing, the HSM places (e.g., writes, stores or injects) the encryption keys into thesemiconductor device 154. As described below, the keys may be injected into a secure portion of the semiconductor device. The semiconductor devices, such as thesemiconductor device 190, may then be delivered to an original equipment manufacturer (OEM) 160 for implementing, for example, into a communication device. - The
encrypted image 130 is typically stored on a flash memory. As noted above, in various embodiments, the semiconductor device design may not include an embedded flash memory. Accordingly, in accordance with the illustrated example ofFIG. 1 , theencrypted image 130 is transmitted to theOEM 160 for storage in a memory device, such as anexternal flash memory 170. - The
semiconductor device 190 fabricated using themanufacturing flow 100 to the OEM 160 includes anon-secure portion 192, also referred to herein as a peripheral processing system (PPS), and asecure portion 194, also referred to herein as a secure processing system (SPS). Thesecure portion 194 may include functionality associated with secure processing by thesemiconductor device 190. For example, as illustrated inFIG. 1 , thesecure portion 194 may include the encryption keys injected into thesemiconductor device 190 by theHSM 120. - As illustrated in
FIG. 1 , theencrypted image 130 received by theOEM 160 may be written to theflash memory 170 through thenon-secure portion 192 of the semiconductor device 190 (arrow 182). Theencrypted image 130 in theflash memory 170 may be verified by decrypting the encrypted image in thesecure portion 194 of thesemiconductor device 190 using the encryption keys injected into the secure portion 194 (arrow 184). In this regard, code may be provided in thesecure portion 194 to perform the decryption using the encryption keys. - Thus, the
semiconductor device 190 may be securely customized, or pre-personalized, in the secure zone. For example, theencrypted image 130 may be associated with a specific semiconductor device, and the encryption keys used to decrypt the encrypted image at thesecure portion 194 of thesemiconductor device 190 may also be accordingly associated with the specific semiconductor device. In one example, the encryption keys may be associated with, for example, a serial number of the target semiconductor device. Thus, the verification may ensure that the pre-personalization of theencrypted image 130 corresponds to theproper semiconductor device 190. Thesecure portion 194 may then re-encrypt the image for writing to the flash memory 170 (arrow 186). In this regard, the re-encryption by thesecure portion 194 may be accomplished using encryption keys that may be generated by thesecure portion 194 and that may be unique to each semiconductor device. - Since the encryption keys are generated by the
secure portion 194 and may be unique to each semiconductor device, they may be unknown to any other entity and may thus be unbreakable. Therefore, theencrypted image 130 may be securely delivered to anexternal flash memory 170. - In other embodiments, as illustrated in
FIG. 2 , theencrypted image 130 may be written to aflash memory 170 during, for example, manufacture of theflash memory 170. In this regard, theencrypted image 130 may be delivered to a manufacturer of theflash memory 170 or to a post-manufacturing entity of theflash memory 170. Theflash memory 170 with theencrypted image 130 may then be delivered to theOEM 160 for association with the semiconductor device 190 (e.g., installation on a user equipment having the semiconductor device 190). As with the example ofFIG. 1 , thesecure portion 194 of thesemiconductor device 190 may decrypt and verify the encrypted image 130 (arrow 184) and re-encrypt the decrypted image using encryption keys generated by thesecure portion 194 for writing back onto the flash memory 170 (arrow 186). - Referring now to
FIG. 3 , a flow chart illustrates an example delivery of secure processing code in the manufacturing flows ofFIGS. 1 and 2 . The image may be encrypted with an encryption key (block 10) at, for example, asecure zone 110. As noted above, any of a variety of encryption techniques may be used to encrypt the image. In one embodiment, the encrypted image is delivered to an OEM (block 12), where the encrypted image may be written on a flash memory that is embedded in a user equipment having a semiconductor device associated with the encrypted image (block 14). As noted above, the flash memory may be external to a semiconductor device that is delivered to the OEM. - In another embodiment, the encrypted image is written to a flash memory (block 16) during, for example, manufacturing of the flash memory. The flash memory with the encrypted image may then be delivered to the OEM for coupling to a semiconductor device (block 18).
- At the OEM, the encrypted image may be decrypted in a secure portion of the semiconductor device (block 20) by, for example, code provided in the secure portion to perform decryption using the encryption key. As noted above with reference to
FIGS. 1 and 2 , the semiconductor device may be provided with the encryption key used to decrypt the image for verification, for example. The secure portion of the semiconductor device may then re-encrypt the decrypted image (block 22) for re-writing the re-encrypted image to the flash memory (block 24). As noted above, the re-encryption of the decrypted image may be accomplished using any of a variety of encryption techniques. Further, the encryption keys used for the re-encryption may be generated by the secure portion of the semiconductor device to provide additional security. As noted above, since the encryption keys are generated by the secure portion and may be unique to each semiconductor device, the encryption keys may be unknown to any other entity and may thus be unbreakable. - Referring now to
FIG. 4 , an example schematic representation of a testing arrangement is illustrated. As described above with reference toFIGS. 1 and 2 , the semiconductor devices may be delivered from thefabrication facility 140 to atesting facility 150. Such testing facilities may be used to test various devices, such as semiconductor devices. Further, such testing facilities may be used to test devices that may have secure and non-secure portions. Traditional testing may use a test key which may serve as an encryption key used during the testing. The test key may be embedded on the device, such as a semiconductor device, which may be referred to during testing as a device under test (DUT). - In various examples, sensitive information, such as test keys or encryption keys to be injected into a secure portion, may be provided in the
HSM 120. In this regard, test keys may include encryption keys that are used specifically for testing of the DUT and may not be injected into the DUT for any later use. Additionally, other encryption keys that are injected into the secure portion may be used to decrypt and verify an encrypted image, as described above. In various examples, when a load board having one or more DUTs and one ormore HSMs 120 is removed from thetester 210, all sensitive information is securely removed from thetester 210. - Referring again to
FIG. 4 , thetester 210 is shown connected to aload board 220. Theload board 220 may accommodate one or more DUTs, such as thesemiconductor device 190. As noted above, thesemiconductor device 190 includes anon-secure portion 192 and asecure portion 194. Theload board 220 may further accommodate one or more HSMs, such asHSM 120. WhileFIG. 4 illustrates aload board 220 having asingle semiconductor device 190 and asingle HSM 120, various examples may include any desired number of semiconductor devices and any appropriate number of HSMs. TheHSM 120 illustrated inFIG. 4 is provided with afirst interface 124 for communication with thesemiconductor device 190 and asecond interface 126 for communication with thetester 210. TheHSM 120 may also include a processor, such as asecure testing processor 122, configured to perform various functions such as, for example, perform testing of thesecure portion 194 of thesemiconductor device 190, as described below. Further, thesecure testing processor 122 may also be configured to control operation of theHSM 120 and control communication with thesemiconductor device 190 and/or thetester 210. Thesecure testing processor 122 may also be provided with a memory for storage, for example, of data such as encryption keys. - In various examples, the testing of the
non-secure portion 192 may be performed by thetester 210, while testing of thesecure portion 194 may be performed by theHSM 120 without providing access to the secure portion to thetester 210. Thus, as illustrated in the example ofFIG. 4 , theHSM 120 may allow direct communication between thetester 210 and thenon-secure portion 192 of thesemiconductor device 190. In this regard, thetester 210 may send signals to and receive signals from thenon-secure portion 192 of thesemiconductor device 190, as illustrated by theline 224 inFIG. 4 . As illustrated inFIG. 4 , the direct communication between thenon-secure portion 192 and thetester 210 may be performed through theHSM 120, through theinterfaces HSM 120 may server merely as a conduit for the communication between thenon-secure portion 194 and thetester 210. In other examples, the communication between thenon-secure portion 194 and thetester 210 may completely bypass theHSM 120. - For testing of the
secure portion 194, thesecure portion 194 may be isolated from thetester 210. As illustrated in the example ofFIG. 4 , the testing of thesecure portion 194 may be performed by thesecure testing processor 122 of theHSM 120. In this regard, theHSM 120 or thesecure testing processor 122 may be provided with secure testing keys which may be delivered (e.g., injected or installed) into thesecure portion 194 for purposes of testing. Any necessary testing of thesecure portion 194 may be performed by thesecure testing processor 122 of theHSM 120 with communication through thefirst interface 124, as illustrated by theline 222 inFIG. 4 . The results of the testing of thesecure portion 194 may be communicated to thetester 210 by theHSM 120 through thesecond interface 126 as, for example, a simple pass or fail indication. In one example, the result may be communicated as a 1-bit signal where a “0” is indicative of a pass and a “1” is indicative of a fail (or vice versa). - In one example, as illustrated in
FIG. 5 , thetester 210 may test thenon-secure portion 192 by commanding theHSM 120 to position arelay 230 to allow direct communication between thetester 210 and thenon-secure portion 192 of thesemiconductor device 190. In response, theHSM 120 may position therelay 230 to a tester input/output position 234. When thetester 210 wishes thesecure portion 194 to be tested, thetester 210 may command theHSM 120 to switch therelay 230 to aninterface 232 between theHSM 120 and thesemiconductor device 190. TheHSM 120 may then establish a secure channel with thesecure portion 194 using a test key. Thesecure portion 192 and thenon-secure portion 194 may be tested in any order. For example, in some cases, thenon-secure portion 194 may be tested first, while in other cases, thesecure portion 192 may be tested first. - Thus, in accordance with the examples of
FIGS. 4 and 5 , the testing of thesecure portion 194 may be performed under the control of theHSM 120. During or after successful testing of thesecure portion 194, the HSM may inject the secure testing keys into thesecure portion 194. TheHSM 120 may communicate the results of the testing of thesecure portion 194 to thetester 210 with a simple indication of “pass” or “fail”. As noted above, in some examples, the indication may be a 1-bit signal. Thus, the tester may be informed of the testing results without being given any information on the reasons for the results. - Upon completion of the testing, the load board is removed from the tester. Along with the load board, all secure information (e.g., the
secure portion 194 of thesemiconductor device 190 and the test keys for testing of the secure portion) are also removed. Thus, thetester 210 is never provided with access to any secure information. For example, the test keys and encryption keys provided in theHSM 120 are kept isolated from thetester 210. - Referring now to
FIG. 6 , a flowchart illustrating an example process for secure testing of semiconductor device is provided. As illustrated inFIG. 6 , a semiconductor device may be coupled to an HSM through a first interface (block 610). For example, thesemiconductor device 190 shown inFIGS. 4 and 5 may be coupled to theHSM 120 through thefirst interface 124. - Referring again to
FIG. 6 , a tester may be coupled to the HSM through a second interface (block 612). For example, as illustrated inFIGS. 4 and 5 , thetester 210 may be coupled to theload board 220 and theHSM 120 through thesecond interface 126. - The secure portion of the semiconductor device may then be tested by the HSM using a test key which may have been provided with the HSM (block 614). For example, as noted above, in various examples, test keys and/or other secure information may be provided in the
HSM 120. Thus, during the testing, all secure information is kept isolated from the tester. Further, as noted above, a simple “pass” or “fail” indication of the results of the testing of the secure portion may be communicated by theHSM 120 to thetester 210 through thesecond interface 126. - In various examples, the HSM may inject encryption keys into the secure portion (block 616). As noted above, the HSM may include secure information, such as encryption keys, that are injected into the secure portion. Again, this allows isolation of all secure information from the tester during testing. The encryption keys may be used to decrypt processing code, such as the
encrypted image 130, as illustrated by thearrow 184 inFIGS. 1 and 2 . - The HSM may position a relay switch, such as
relay switch 230 ofFIG. 5 , to allow direct communication between the non-secure portion of the semiconductor device and the tester (block 618). As noted above, this allows the tester to test the non-secure portion of the semiconductor device (block 620). The positioning of the relay switch by the HSM may be in response to commands from the tester, for example. WhileFIG. 6 illustrates an example in which the secure portion is tested before the non-secure portion, those skilled in the art will appreciate that the order of testing may be reversed. For example, the non-secure portion may be tested and then the relay switch may be positioned to allow the processor of the HSM to test the secure portion. Thus, the secure portion of the semiconductor device may be tested and various keys (e.g., encryption keys) may be provided to the secure portion in a secure manner without the need for placing the tester in a secure location. - The various diagrams may depict an example architectural or other configuration for the various embodiments, which is done to aid in understanding the features and functionality that can be included in embodiments. The present disclosure is not restricted to the illustrated example architectures or configurations, and the desired features can be implemented using a variety of alternative architectures and configurations. Indeed, it will be apparent to one of skill in the art how alternative functional, logical or physical partitioning and configurations can be implemented to implement various embodiments. Also, a multitude of different constituent module names other than those depicted herein can be applied to the various partitions. Additionally, with regard to flow diagrams, operational descriptions and method claims, the order in which the steps are presented herein shall not mandate that various embodiments be implemented to perform the recited functionality in the same order unless the context dictates otherwise.
- It should be understood that the various features, aspects and/or functionality described in one or more of the individual embodiments are not limited in their applicability to the particular embodiment with which they are described, but instead can be applied, alone or in various combinations, to one or more of the other embodiments, whether or not such embodiments are described and whether or not such features, aspects and/or functionality are presented as being a part of a described embodiment. Thus, the breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments.
- Terms and phrases used in this document, and variations thereof, unless otherwise expressly stated, should be construed as open ended as opposed to limiting. As examples of the foregoing: the term “including” should be read as meaning “including, without limitation” or the like; the term “example” is used to provide exemplary instances of the item in discussion, not an exhaustive or limiting list thereof; the terms “a” or “an” should be read as meaning “at least one,” “one or more” or the like; and adjectives such as “conventional,” “traditional,” “normal,” “standard,” “known” and terms of similar meaning should not be construed as limiting the item described to a given time period or to an item available as of a given time, but instead should be read to encompass conventional, traditional, normal, or standard technologies that may be available or known now or at any time in the future. Likewise, where this document refers to technologies that would be apparent or known to one of ordinary skill in the art, such technologies encompass those apparent or known to the skilled artisan now or at any time in the future.
- Additionally, the various embodiments set forth herein are described in terms of exemplary block diagrams, flow charts and other illustrations. As will become apparent to one of ordinary skill in the art after reading this document, the illustrated embodiments and their various alternatives can be implemented without confinement to the illustrated examples. For example, block diagrams and their accompanying description should not be construed as mandating a particular architecture or configuration.
- Moreover, various embodiments described herein are described in the general context of method steps or processes, which may be implemented in one embodiment by a computer program product, embodied in, e.g., a non-transitory computer-readable memory, including computer-executable instructions, such as program code, executed by computers in networked environments. A computer-readable memory may include removable and non-removable storage devices including, but not limited to, Read Only Memory (ROM), Random Access Memory (RAM), compact discs (CDs), digital versatile discs (DVD), etc. Generally, program modules may include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. Computer-executable instructions, associated data structures, and program modules represent examples of program code for executing steps of the methods disclosed herein. The particular sequence of such executable instructions or associated data structures represents examples of corresponding acts for implementing the functions described in such steps or processes.
- As used herein, the term module can describe a given unit of functionality that can be performed in accordance with one or more embodiments. As used herein, a module might be implemented utilizing any form of hardware, software, or a combination thereof. For example, one or more processors, controllers, application-specific integrated circuits (ASICs), programmable logic arrays (PLAs), programmable array logic (PALs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), logical components, software routines or other mechanisms might be implemented to make up a module. In implementation, the various modules described herein might be implemented as discrete modules or the functions and features described can be shared in part or in total among one or more modules. In other words, as would be apparent to one of ordinary skill in the art after reading this description, the various features and functionality described herein may be implemented in any given application and can be implemented in one or more separate or shared modules in various combinations and permutations. Even though various features or elements of functionality may be individually described or claimed as separate modules, one of ordinary skill in the art will understand that these features and functionality can be shared among one or more common software and hardware elements, and such description shall not require or imply that separate hardware or software components are used to implement such features or functionality. Where components or modules of the invention are implemented in whole or in part using software, in one embodiment, these software elements can be implemented to operate with a computing or processing module capable of carrying out the functionality described with respect thereto. The presence of broadening words and phrases such as “one or more,” “at least,” “but not limited to” or other like phrases in some instances shall not be read to mean that the narrower case is intended or required in instances where such broadening phrases may be absent.
Claims (20)
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US10181124B2 (en) * | 2013-05-30 | 2019-01-15 | Dell Products, L.P. | Verifying OEM components within an information handling system using original equipment manufacturer (OEM) identifier |
US9230137B2 (en) * | 2013-05-30 | 2016-01-05 | Dell Products, L.P. | Secure original equipment manufacturer (OEM) identifier for OEM devices |
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US9165163B2 (en) | 2015-10-20 |
US20140157000A1 (en) | 2014-06-05 |
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