US20140001563A1 - Semiconductor devices formed on a continuous active region with an isolating conductive structure positioned between such semiconductor devices, and methods of making same - Google Patents
Semiconductor devices formed on a continuous active region with an isolating conductive structure positioned between such semiconductor devices, and methods of making same Download PDFInfo
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- US20140001563A1 US20140001563A1 US13/539,830 US201213539830A US2014001563A1 US 20140001563 A1 US20140001563 A1 US 20140001563A1 US 201213539830 A US201213539830 A US 201213539830A US 2014001563 A1 US2014001563 A1 US 2014001563A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
- H01L27/11807—CMOS gate arrays
Definitions
- the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to a plurality of semiconductor devices formed in and above a continuous active region and a conductive isolating structure formed above the active region between the devices.
- FETs Field effect transistors
- NFET devices NFET devices
- PFET devices NFET devices
- millions of transistors e.g., NFET transistors and/or PFET transistors, are formed on a substrate including a crystalline semiconductor layer.
- a field effect transistor typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, referred to as a channel region, disposed between the highly doped source/drain regions.
- the channel length of a transistor is generally considered to be the lateral distance between the source/drain regions.
- FIGS. 1 and 2 depict an illustrative prior art device 10 comprised of first and second cells (“Cell 1” and “Cell 2”).
- the cells are intended to be representative in nature.
- Cell 1 may be a NAND circuit and Cell 2 may also be a NAND circuit.
- Cell 1 may be an inverter and Cell 2 may be a flip-flop.
- a plurality of spaced apart active regions 12 PA, 12 PB, 12 NA and 12 NB are defined in a semiconducting substrate by one or more isolation structures.
- a plurality of PFET devices 20 P 1 - 2 are formed in and above the active region 12 PA and a plurality of PFET devices 20 P 3 - 4 are formed in and above the active region 12 PB.
- the PFET devices comprise P-doped source/drain regions 32 P, while the NFET devices 22 N 1 - 4 comprise N-doped source/drain regions 32 N.
- the various PFET and NFET devices share a common electrode structure 30 that extends across the separated active regions and the isolation region therebetween.
- PFET transistor 20 P 1 and NFET transistor 22 N 1 share a common gate electrode structure 30 that extends across both of the active regions 12 PA, 12 NA and the isolation region between those two active regions.
- the structures 14 may be dummy gate structures that are provided in an attempt to improve dimensional accuracy when forming the gate structures 30 for the device 10 .
- FIG. 2 depicts another illustrative prior art device 50 .
- the device comprises illustrative PFET devices 20 P 1 and 20 P 2 formed above spaced apart active regions.
- the device 50 also includes illustrative NFET transistors 22 N 1 , 22 N 2 that are also formed above spaced apart active regions.
- FIG. 2 depicts an illustrative relatively high voltage power rail 40 H that is conductively coupled to the illustrative source regions (“S”) of the PFET devices 20 P 1 , 20 P 2 via illustrative contacts 52 H.
- Also depicted in FIG. 2 is an illustrative relatively low voltage power rail 40 L that is conductively coupled to the source regions of the NFET devices 22 N 1 , 22 N 2 via illustrative contacts 52 L.
- the lateral spacing 39 (see FIG. 1 ) between adjacent active regions, e.g., the lateral spacing 39 between the active regions 12 PA and 12 PB, also decreases. In some cases, the lateral spacing 39 may be as little as about 40 nm. As this lateral spacing decreases, there is an increased risk of creating short circuits between the two adjacent cells. Of course, one way to rectify this problem would be to simply increase the spacing between adjacent active regions. However, such an approach would be very costly in terms of the plot space on the device that is lost and would run counter to the trend in integrated circuit products of reducing the size of such products. Other techniques have been tried to alleviate this problem, e.g., a so-called Rx-tuck process, but such processes also tend to consume excessive amounts of chip plot space and may result in considerable device performance degradation.
- the present disclosure is directed to a plurality of semiconductor devices formed in and above a continuous active region and a conductive isolating structure formed above the active region between the devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.
- the present disclosure is directed to a device that comprises a plurality of semiconductor devices formed in and above a continuous active region and a conductive isolating structure formed above the active region between the devices, and various methods of making such a device.
- One illustrative device disclosed herein includes a continuous active region defined in a semiconducting substrate, first and second transistors formed in and above the continuous active region, each of the first and second transistors comprising a plurality of doped regions formed in the continuous active region, a conductive isolating electrode positioned above the continuous active region between the first and second transistors and a power rail conductively coupled to the conductive isolating electrode.
- Another illustrative device disclosed herein includes first and second continuous active regions defined in a semiconducting substrate, first and second PFET transistors formed in and above the first continuous active region, and first and second NFET transistors formed in and above the second continuous active region.
- This embodiment of the device further includes a first conductive isolating electrode positioned above the first continuous active region between the first and second PFET transistors, a first power rail conductively coupled to the first conductive isolating electrode, wherein the first power rail is adapted to be at a logically high voltage level, a second conductive isolating electrode positioned above the second continuous active region between the first and second NFET transistors and a second power rail conductively coupled to the second conductive isolating electrode, wherein the second power rail is adapted to be at a logically low voltage level.
- FIGS. 1 and 2 depict illustrative examples of various prior art semiconductor devices formed in a semiconducting substrate
- FIGS. 3A-3C are schematic depictions of illustrative embodiments of semiconductor devices formed on continuous active regions that employ illustrative examples of the isolating electrode structures disclosed herein;
- FIGS. 4A-4C are schematic depictions of illustrative examples of various possible configurations of illustrative semiconductor devices disclosed herein;
- FIGS. 5A-5E are plan and cross-sectional views depicting various possible configurations of illustrative semiconductor devices disclosed herein;
- FIGS. 6A-6D are various cross-sectional views depicting another possible configuration of illustrative semiconductor devices disclosed herein.
- FIGS. 7A-7D are various cross-sectional views depicting yet another possible configuration of illustrative semiconductor devices disclosed herein.
- the present disclosure is directed to a device that comprises a plurality of semiconductor devices formed in and above a continuous active region and a conductive isolating structure formed above the active region between the devices, and various methods of making such a device.
- a device that comprises a plurality of semiconductor devices formed in and above a continuous active region and a conductive isolating structure formed above the active region between the devices, and various methods of making such a device.
- the presently disclosed subject matter may be used with a variety of different devices and technologies, e.g., NFET, PFET, CMOS, etc., and it may be readily employed on a variety of integrated circuit products, including, but not limited to, ASIC's, logic devices, memory devices, etc.
- FIG. 3A-3C are various schematic drawings that explain certain aspects of the various devices disclose herein.
- an illustrative device 100 comprises a first continuous active region 112 P and a second continuous active region 112 N formed in a semiconducting substrate.
- the active regions 112 P, 112 N are defined in the semiconducting substrate by isolation structures 113 that may be formed using traditional techniques.
- the substrate may take the form of a silicon-on-insulator (SOI) substrate that is comprised of a bulk substrate, a buried insulation layer (a so-called BOX layer) and an active layer positioned above the box layer. In such an embodiment, the active regions 112 P, 112 N would be formed in the active layer.
- the substrate may also be in bulk form.
- the substrate may also be made of materials other than silicon.
- the terms substrate or semiconducting substrate as used herein and in the appended claims should not be considered as limited to any particular configuration or material.
- a plurality of PFET devices 120 P 1 - 4 are formed in and above the active region 112 P and a plurality of NFET devices 122 N 1 - 4 are formed in and above the active region 112 N.
- the PFET devices 120 and the NFET devices 122 may be formed using traditional materials and techniques.
- the PFET devices 120 may be comprised of various P-doped regions 132 P, e.g., P-doped source/drain regions, and the NFET devices 122 may be comprised of various N-doped regions 132 N.
- the device 100 is a CMOS device that comprises a plurality of common gate structures 130 that are shared by the various PFET devices 120 and NFET devices 122 .
- the common gate structures 130 are positioned above both of the active regions 112 P, 112 N and they each span the isolation material positioned between the active regions 112 P, 112 N.
- the device 100 may not have this illustrative common gate structure configuration.
- the gate structures 130 may be formed using a variety of different materials and by performing a variety of known techniques.
- the gate insulation layer in such a gate structure 130 may be comprised of a variety of different insulating materials, e.g., silicon dioxide, a so-called high-k insulating material (k value greater than 10).
- the gate electrode in such a gate structure 130 may be comprised of polysilicon or it may contain at least one metal layer.
- the gate structures 130 of the transistor 100 may be made using so-called “gate first” or “gate last” techniques. Thus, the presently disclosed inventions should not be considered as limited to any particular materials of construction for the gate structures 130 nor the manner in which such a gate structure 130 is formed.
- the device 100 further comprises an isolating electrode 150 PG that is conductively coupled to a schematically depicted power rail 140 H at a logically high voltage, e.g., V dd .
- the device also includes an isolating electrode 150 NG that is conductively coupled to a power rail 140 L that is at a logically low voltage, e.g., ground.
- a logically low voltage e.g., ground.
- the absolute magnitude of the voltages on the power rails 140 H, 140 L may vary depending upon the particular application, but the voltage on the power rail 140 H will be relatively higher than the voltage on the power rail 140 L. In the illustrative example shown in FIG.
- the isolating electrodes 150 PG, 150 NG are separated by a distance 142 .
- the isolating electrode 150 PG spans across the entirety of the active region 112 P, while the isolating electrode 150 NG spans across the entirety of the active region 112 N.
- the isolating electrodes 150 PG and 150 NG have the same structure and configuration as the gate structures 130 , and they may be initially formed at the same time the gate structures 130 are formed. In other cases, the isolating electrodes 150 PG and 150 NG may be comprised of different materials, may be a different physical size and/or may be formed at different times as compared to the gate structures 130 .
- the isolating electrodes 150 PG and 150 NG and the gate structures 130 are all initially formed as elongated continuous line-type structures. Thereafter, the isolating electrodes 150 PG and 150 NG are defined by performing another etching process.
- the isolating electrodes 150 PG and 150 NG may be conductively coupled to the power rails 140 H, 140 L, respectively, by any of a variety of different conductive structures that are formed in a layer of insulating material positioned above the substrate.
- the isolating electrodes 150 PG and 150 NG each have a long axis and, in one embodiment, the long axis of the isolating electrode 150 PG is substantially aligned with the long axis of the isolating electrode 150 NG.
- FIG. 3B depicts one illustrative embodiment of an illustrative unit cell 100 A of the device 100 .
- the unit cell 100 A comprises PFET transistors 120 P 2 and 120 P 3 that are positioned on opposite sides of the isolating electrode 150 PG and NFET transistors 122 N 2 and 122 N 3 that are positioned on opposite sides of the isolating electrode 150 NG.
- the isolating electrode 150 PG is positioned above a space between the adjacent doped regions of the transistors 120 P 2 and 120 P 3
- the isolating electrode 150 NG is positioned above a space between the adjacent doped regions of the transistors 122 N 2 and 122 N 3 .
- the inventions disclosed herein are not limited in terms of how many transistors may be formed in the active regions 112 P, 112 N, the number of isolating electrodes 150 PG and 150 NG formed on the device 100 , nor the number of transistors that may be associated with each of the isolating electrodes 150 PG and 150 NG. Moreover, the number of transistors associated with each of the isolating electrodes 150 PG and 150 NG need not be the same for either of the active regions 112 P or 112 N, and it need not be uniform within either of the active regions 112 P, 112 N.
- the devices 100 disclosed herein may be employed in situations wherein there are hundreds if not thousands of transistors formed in each of the active regions 112 P, 112 N and hundreds of isolating electrodes 150 PG and 150 NG.
- FIG. 3C is a simplistic line-based drawing indicating one example of a device 100 comprised of fourteen PFET devices 120 , five isolating electrodes 150 PG that are coupled to the power rail 140 H, fourteen NFET devices 122 and five isolating electrodes 150 NG that are coupled to the power rail 140 L.
- the presently disclosed inventions should not be considered as limited to any particular number or arrangement of transistor devices or any particular number or arrangement of the isolating electrodes 150 PG, 150 NG.
- FIG. 4A-4C depict various illustrative examples that schematically depict how the device 100 may be configured in various situations.
- FIG. 4A depicts the illustrative example wherein the isolating electrodes 150 PG, 150 NG are positioned between source regions (“S”) of the respective transistors.
- the drain regions (“D”) of the various transistors are also depicted in FIG. 4A . More specifically, in FIG. 4A , the isolating electrode 150 PG is positioned between the source regions of the PFET devices 120 P 2 and 120 P 3 , while the isolating electrode 150 NG is positioned between the source regions of the NFET devices 122 N 2 and 122 N 3 .
- the source regions of the PFET devices 120 P 2 - 3 are coupled to the power rail 140 H by schematically depicted conductive structures 144
- the source regions of the NFET devices 122 N 2 - 3 are coupled to the power rail 140 L by schematically depicted conductive structures 146 .
- FIG. 4B depicts the illustrative example wherein the isolating electrodes 150 PG, 150 NG are positioned between a source region (“S”) on one adjacent transistor and a drain region (“D”) on the other adjacent transistor. More specifically, in FIG. 4B , the isolating electrode 150 PG is positioned between the source region of the PFET device 120 P 2 and the drain region of the PFET device 120 P 3 , while the isolating electrode 150 NG is positioned between the source region of the NFET device 122 N 2 and the drain region of the NFET device 122 N 3 .
- the source region of the PFET device 120 P 2 is conductively coupled to the power rail 140 H by schematically depicted conductive structures 144
- the source region of the NFET device 122 N 2 is coupled to the power rail 140 L by schematically depicted conductive structures 146
- the drain region of the PFET device 120 P 3 and the drain region of the NFET device 122 N 3 are conductively coupled to one another via a conductive strap 148 and illustrative contacts.
- FIG. 4C depicts the illustrative example wherein the isolating electrodes 150 PG, 150 NG are positioned between drain regions (“D”) of the respective transistors. More specifically, in FIG. 4C , the isolating electrode 150 PG is positioned between the drain regions of the PFET devices 120 P 2 and 120 P 3 , while the isolating electrode 150 NG is positioned between the drain regions of the NFET devices 122 N 2 and 122 N 3 . In this illustrative example, only the isolating electrodes 150 PG, 150 NG are coupled to the power rails 140 H, 140 L, respectively.
- the drain region of the PFET device 120 P 3 and the drain region of the NFET device 122 N 3 are conductively coupled to one another via a conductive strap 148 and illustrative contacts
- the drain region of the PFET device 120 P 2 and the drain region of the NFET device 122 N 2 are conductively coupled to one another via a conductive strap 149 and illustrative contacts.
- the various conductive structures 144 , 146 , 148 , 149 and the depicted contacts may be of any desired configuration or material, they may be formed in one or more layers of insulating materials positioned above the substrate, and they may be formed using a variety of different techniques.
- FIG. 5A is a schematic plan view of one illustrative embodiment of the device 100 wherein the isolating electrode 150 PG is positioned between the source regions 120 S of the PFET devices 120 P 2 and 120 P 3 , while the isolating electrode 150 NG is positioned between the source regions 122 S of the NFET devices 122 N 2 and 122 N 3 , a configuration that also corresponds to FIG. 4A .
- the drain regions for the PFET devices are denoted with the reference number 120 D while the drain regions for the NFET devices are denoted with the reference number 122 D.
- conductive line-type device level contacts 175 are formed on each of the source/drain regions for the various transistor devices.
- these illustrative device level contacts 175 may be referred to within the industry as so-called trench silicide regions.
- the device level contacts 175 that contact the source regions 120 S of the transistors 120 P 2 and 120 P 3 are conductively coupled to the power rail 140 H by a plurality of conductive contacts 190 P and the isolating electrode 150 PG is conductively coupled to the power rail 140 H by a conductive contact 192 P.
- the device level contacts 175 that contact the source regions 122 S of the transistors 122 N 2 and 122 N 3 are conductively coupled to the power rail 140 L by a plurality of conductive contacts 190 N, and the isolating electrode 150 NG is conductively coupled to the power rail 140 L by a conductive contact 192 N.
- the device level contacts 175 that are coupled to the drain regions 120 D of the PFET devices are conductively contacted by contacts 131 P.
- the contacts 131 P are conductively coupled to a conductive structure (not shown), such as a metal line, that is formed in a metallization layer, e.g., the metal 1 layer, formed above the substrate.
- the device level contacts 175 that are coupled to the drain regions 122 D of the NFET devices are conductively contacted by contacts 131 N.
- the contacts 131 N are conductively coupled to a conductive structure (not shown), such as a metal line, that is formed in a metallization layer, e.g., the metal 1 layer, formed above the substrate.
- the power rails 140 H, 140 L and the previously described contacts 190 P, 192 P, 190 N and 192 N may all be formed in the so-called local interconnect level of the device 100 . That is, the power rails 140 H, 140 L and the previously described contacts 190 P, 192 P, 190 N and 192 N may be formed in a level that is between the device level contacts 175 and the so-called “metal 1” layer that is typically the first general wiring layer formed above the substrate. Further explanation of this unique configuration will be explained in connection with the cross-sectional views “A-A”, “B-B” and “C-C” taken where indicated in FIG. 5A .
- various layers of insulating material 180 , 181 , 182 , 183 and 184 are formed above the substrate.
- the various layers of insulating material may be comprised of a variety of different material, e.g., silicon dioxide, silicon nitride, a low-k material (k value less than 3.5), and they may be arranged in any desired order.
- the insulating layer 181 may serve as an etch stop layer and it may be comprised of a material that may be selectively etched with respect to the insulating layers 180 , 182 .
- the insulating layers 180 , 182 may be comprised of silicon dioxide and the insulating layer 181 may be comprised of silicon nitride.
- the thickness of the various layers of insulating material may vary depending upon the particular application and they may be formed by performing a variety of known techniques, e.g., chemical vapor deposition (CVD), atomic layer deposition (ALD), or plasma enhanced versions of those processes.
- the various conductive structures may be comprised of a variety of different materials, e.g., copper, aluminum, tungsten, etc., and they may be formed by performing a variety of known techniques, e.g., damascene techniques.
- the cross-sectional views “A-A”, “B-B” and “C-C” are taken through the active region 112 N (where the NMOS devices 122 are formed) and the power rail 140 L.
- the cross-sectional view “A-A” is taken through the power rail 140 L as indicated.
- the power rail 140 L and the contacts 190 N, 192 N are formed in the same layer of insulating material 182 (not shown in view “A-A”).
- the contacts 190 N, 192 N are depicted with dashed lines as they are positioned behind the power rail 140 L in this view.
- the power rail 140 L is positioned above the isolation region 113 .
- the cross-sectional view “B-B” is taken through the contacts 190 N, 192 N above the isolation region 113 .
- the contact 192 N contacts the isolating electrode 150 NG.
- the insulating layer 182 is depicted in this view.
- the cross-sectional view “C-C” is taken through the contacts 190 N above the active region 112 N.
- the contacts 190 N contact the device level contacts 175 .
- the transistor width can be larger, for example, up to 15-20% larger as compared to prior art arrangements involving connections to the metal 1 layer.
- This increase in transistor width may result in increased circuit performance, e.g., about a 10-15% increase as compared to prior art devices.
- the increase in performance is due to the fact that a traditional connection scheme at a level above the local interconnect level requires the width of the transistors to be reduced in order to make room for the connections.
- FIG. 5B-5C are cross-sectional views of one illustrative embodiment of various devices disclosed herein. More specifically, FIG. 5B is a cross-sectional view of the various PFET devices that are formed above the P-active region 112 P, while FIG. 5C is a cross-sectional view of the various NFET devices that are formed above the N-active region 112 N. As shown therein, the previously mentioned layers of insulating material 180 , 181 , 182 , 183 and 184 are formed above the substrate. In one illustrative example, the insulating layers 180 , 182 may be comprised of silicon dioxide and the insulating layer 181 may be comprised of silicon nitride.
- Conductive structures corresponding to “via 0 ” 177 and a metal line 179 in the “metal-1” layer are formed in layers of insulating material 183 , 184 , respectively.
- the gate structures 130 are comprised of an illustrative gate insulation layer 130 A and an illustrative gate electrode 130 B.
- the materials of construction of the gate structures 130 and the manner in which they are made may vary depending upon the particular application. In the examples depicted in FIGS.
- the isolating gate electrodes 150 PG, 150 NG are part of a corresponding structure that is formed at the same time the illustrative gate structures 130 are formed, although that is not required in all instances.
- FIGS. 5B-5C depict the device 100 wherein the power rails 140 H, 140 L and the contacts 190 P, 192 P, 190 N and 192 N are all formed in the local interconnect level, i.e., in the insulating layer 182 .
- the power rails 140 H, 140 L are formed in the so-called metal 1 layer in the layer of insulating material 184 . As shown in FIG.
- a conductive structure 194 P conductively couples the contacts 190 P, 192 P to the power rail 140 H.
- a conductive structure 194 N conductively couples the contacts 190 N, 192 N to the power rail 140 L.
- FIGS. 6A-6D depict further illustrative embodiments of various inventions disclosed herein. More specifically, FIGS. 6A and 6C depict the situation where the isolating electrode 150 PG is positioned between the source region 120 S of the PFET device 120 P 2 and the drain region 120 D of the PFET device 120 P 3 , a configuration that corresponds to FIG. 4B . FIGS. 6B and 6D depict the situation where the isolating electrode 150 NG is positioned between the source region 122 S of the NFET device 122 N 2 and the drain region 122 D of the NFET device 122 N 3 , a configuration that also corresponds to FIG. 4B . Note that, in FIGS.
- FIGS. 6A-6D depict the drain region 120 D of the PFET transistor 120 P 3 wherein the power rails 140 H, 140 L and the contacts 190 P, 192 P, 190 N and 192 N are all formed in the local interconnect level, i.e., in the insulating layer 182 .
- the power rails 140 H, 140 L are formed in the so-called “metal 1” layer in the layer of insulating material 184 .
- a conductive structure 194 P conductively couples the contacts 190 P, 192 P to the power rail 140 H.
- a conductive structure 194 N conductively couples the contacts 190 N, 192 N to the power rail 140 L.
- FIGS. 7A-7D depict further illustrative embodiments of various inventions disclosed herein. More specifically, FIGS. 7A and 7C depict the situation where the isolating electrode 150 PG is positioned between the drain region 120 D of the PFET device 120 P 2 and the drain region 120 D of the PFET device 120 P 3 , a configuration that corresponds to FIG. 4C .
- FIGS. 7A-7D only the isolating electrode 150 PG is connected to the power rail 140 H, and only the isolating electrode 150 NG is connected to power rail 140 L.
- the drain region 120 D of the PFET transistor 120 P 3 and the drain region 122 D of the NFET transistor 122 N 3 are coupled to one another by a conductive structure 148 (not shown in FIGS. 7A-7D ), while the drain region 120 D of the PFET transistor 120 P 2 and the drain region 122 D of the NFET transistor 122 N 2 are coupled to one another by a conductive structure 149 (also not shown in FIGS. 7A-7D ).
- FIGS. 7C-7B depict the device 100 wherein the power rails 140 H, 140 L and the contacts 192 P and 192 N are all formed in the local interconnect level, i.e., in the insulating layer 182 .
- the power rails 140 H, 140 L are formed in the so-called “metal 1” layer in the layer of insulating material 184 .
- a conductive structure 194 P conductively couples the contact 192 P to the power rail 140 H.
- a conductive structure 194 N conductively couples the contact 192 N to the power rail 140 L.
- applying a relatively high voltage to the isolating electrode 150 PG via the power rail 140 H electrically blocks or isolates the adjacent PFET transistors formed in the continuous active region 112 P.
- applying a relatively low voltage to the isolating electrode 150 NG via the power rail 140 L electrically blocks or isolates the adjacent NFET transistors formed in the continuous active region 112 N.
- the voltage applied to the gate of the PMOS device must be smaller than the voltage applied to the source by at least the threshold voltage of the PMOS device.
- the PMOS transistor When the applied voltage on the gate of the PMOS device is larger than the voltage applied to the source (or at least a voltage greater than the threshold of the transistor), the PMOS transistor is turned-off, meaning the active regions on both sides of the isolation electrode 150 PG become electrically isolated.
- the voltage applied on the gate of an NMOS device when the voltage applied on the gate of an NMOS device is greater than the voltage applied on the source by at least the threshold voltage of the NMOS device, a channel region is established under the gate that electrically connects the source and the drain of the NMOS device.
- the NMOS transistor By applying a voltage on the gate of the NMOS device that is less than the voltage applied to the source region (or at least lesser than the threshold voltage of the NMOS transistor), the NMOS transistor is turned-off, i.e., the active regions on both sides of the isolation electrode 150 NG become electrically isolated.
- the minimum voltage or ground is used to bias the P-well body of the N-type CMOS transistors.
- the same minimum voltage can be applied to the N-side isolation electrode 150 NG to effectively isolate the adjacent NMOS transistors.
- the maximum voltage is used to bias the N-well body of the P-type transistors in CMOS architecture.
- the same maximum voltage can be applied to the P-side isolation electrode 150 PG to effectively isolate the adjacent PMOS transistors.
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Abstract
Description
- 1. Field of the Invention
- Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to a plurality of semiconductor devices formed in and above a continuous active region and a conductive isolating structure formed above the active region between the devices.
- 2. Description of the Related Art
- The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout. Field effect transistors (FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. Field effect transistors are typically either NFET devices or PFET devices. During the fabrication of complex integrated circuits, millions of transistors, e.g., NFET transistors and/or PFET transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an NFET transistor or a PFET transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, referred to as a channel region, disposed between the highly doped source/drain regions. The channel length of a transistor is generally considered to be the lateral distance between the source/drain regions.
- As device dimensions have continued to shrink over recent years, it is becoming more challenging to accurately and repeatedly manufacture integrated circuit products that meet performance criteria established for such integrated circuit products. Typically, semiconductor devices are formed on discrete islands of semiconducting substrate, i.e., active regions that are defined in the substrate by isolation structures. For example,
FIGS. 1 and 2 depict an illustrativeprior art device 10 comprised of first and second cells (“Cell 1” and “Cell 2”). The cells are intended to be representative in nature. For example, in one illustrative example,Cell 1 may be a NAND circuit andCell 2 may also be a NAND circuit. In another example,Cell 1 may be an inverter andCell 2 may be a flip-flop. - With continuing reference to
FIGS. 1 and 2 , a plurality of spaced apart active regions 12PA, 12PB, 12NA and 12NB are defined in a semiconducting substrate by one or more isolation structures. A plurality of PFET devices 20P1-2 are formed in and above the active region 12PA and a plurality of PFET devices 20P3-4 are formed in and above the active region 12PB. The PFET devices comprise P-doped source/drain regions 32P, while the NFET devices 22N1-4 comprise N-doped source/drain regions 32N. In the depicted example, the various PFET and NFET devices share acommon electrode structure 30 that extends across the separated active regions and the isolation region therebetween. For example, PFET transistor 20P1 and NFET transistor 22N1 share a commongate electrode structure 30 that extends across both of the active regions 12PA, 12NA and the isolation region between those two active regions. Thestructures 14 may be dummy gate structures that are provided in an attempt to improve dimensional accuracy when forming thegate structures 30 for thedevice 10. -
FIG. 2 depicts another illustrativeprior art device 50. The device comprises illustrative PFET devices 20P1 and 20P2 formed above spaced apart active regions. Thedevice 50 also includes illustrative NFET transistors 22N1, 22N2 that are also formed above spaced apart active regions.FIG. 2 depicts an illustrative relatively highvoltage power rail 40H that is conductively coupled to the illustrative source regions (“S”) of the PFET devices 20P1, 20P2 viaillustrative contacts 52H. Also depicted inFIG. 2 is an illustrative relatively lowvoltage power rail 40L that is conductively coupled to the source regions of the NFET devices 22N1, 22N2 viaillustrative contacts 52L. - With each new technology generation, all dimensions of the integrated circuit product are typically reduced. For example, as device dimensions are reduced, the lateral spacing 39 (see
FIG. 1 ) between adjacent active regions, e.g., thelateral spacing 39 between the active regions 12PA and 12PB, also decreases. In some cases, thelateral spacing 39 may be as little as about 40 nm. As this lateral spacing decreases, there is an increased risk of creating short circuits between the two adjacent cells. Of course, one way to rectify this problem would be to simply increase the spacing between adjacent active regions. However, such an approach would be very costly in terms of the plot space on the device that is lost and would run counter to the trend in integrated circuit products of reducing the size of such products. Other techniques have been tried to alleviate this problem, e.g., a so-called Rx-tuck process, but such processes also tend to consume excessive amounts of chip plot space and may result in considerable device performance degradation. - The present disclosure is directed to a plurality of semiconductor devices formed in and above a continuous active region and a conductive isolating structure formed above the active region between the devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.
- The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an exhaustive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
- Generally, the present disclosure is directed to a device that comprises a plurality of semiconductor devices formed in and above a continuous active region and a conductive isolating structure formed above the active region between the devices, and various methods of making such a device. One illustrative device disclosed herein includes a continuous active region defined in a semiconducting substrate, first and second transistors formed in and above the continuous active region, each of the first and second transistors comprising a plurality of doped regions formed in the continuous active region, a conductive isolating electrode positioned above the continuous active region between the first and second transistors and a power rail conductively coupled to the conductive isolating electrode.
- Another illustrative device disclosed herein includes first and second continuous active regions defined in a semiconducting substrate, first and second PFET transistors formed in and above the first continuous active region, and first and second NFET transistors formed in and above the second continuous active region. This embodiment of the device further includes a first conductive isolating electrode positioned above the first continuous active region between the first and second PFET transistors, a first power rail conductively coupled to the first conductive isolating electrode, wherein the first power rail is adapted to be at a logically high voltage level, a second conductive isolating electrode positioned above the second continuous active region between the first and second NFET transistors and a second power rail conductively coupled to the second conductive isolating electrode, wherein the second power rail is adapted to be at a logically low voltage level.
- The disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:
-
FIGS. 1 and 2 depict illustrative examples of various prior art semiconductor devices formed in a semiconducting substrate; -
FIGS. 3A-3C are schematic depictions of illustrative embodiments of semiconductor devices formed on continuous active regions that employ illustrative examples of the isolating electrode structures disclosed herein; -
FIGS. 4A-4C are schematic depictions of illustrative examples of various possible configurations of illustrative semiconductor devices disclosed herein; -
FIGS. 5A-5E are plan and cross-sectional views depicting various possible configurations of illustrative semiconductor devices disclosed herein; -
FIGS. 6A-6D are various cross-sectional views depicting another possible configuration of illustrative semiconductor devices disclosed herein; and -
FIGS. 7A-7D are various cross-sectional views depicting yet another possible configuration of illustrative semiconductor devices disclosed herein. - While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
- Various illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.
- The present subject matter will now be described with reference to the attached figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details that are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present disclosure. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary and customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase.
- The present disclosure is directed to a device that comprises a plurality of semiconductor devices formed in and above a continuous active region and a conductive isolating structure formed above the active region between the devices, and various methods of making such a device. As will be readily apparent to those skilled in the art upon a complete reading of the present application, the presently disclosed subject matter may be used with a variety of different devices and technologies, e.g., NFET, PFET, CMOS, etc., and it may be readily employed on a variety of integrated circuit products, including, but not limited to, ASIC's, logic devices, memory devices, etc. With reference to the attached drawings, various illustrative embodiments of the devices and methods disclosed herein will now be described in more detail.
-
FIG. 3A-3C are various schematic drawings that explain certain aspects of the various devices disclose herein. As shown inFIG. 3A , anillustrative device 100 comprises a first continuousactive region 112P and a second continuousactive region 112N formed in a semiconducting substrate. Theactive regions isolation structures 113 that may be formed using traditional techniques. The substrate may take the form of a silicon-on-insulator (SOI) substrate that is comprised of a bulk substrate, a buried insulation layer (a so-called BOX layer) and an active layer positioned above the box layer. In such an embodiment, theactive regions - With continuing reference to
FIG. 3A , a plurality of PFET devices 120P1-4 are formed in and above theactive region 112P and a plurality of NFET devices 122N1-4 are formed in and above theactive region 112N. ThePFET devices 120 and theNFET devices 122 may be formed using traditional materials and techniques. For example, thePFET devices 120 may be comprised of various P-dopedregions 132P, e.g., P-doped source/drain regions, and theNFET devices 122 may be comprised of various N-dopedregions 132N. In the depicted example, thedevice 100 is a CMOS device that comprises a plurality ofcommon gate structures 130 that are shared by thevarious PFET devices 120 andNFET devices 122. Thecommon gate structures 130 are positioned above both of theactive regions active regions device 100 may not have this illustrative common gate structure configuration. As will be appreciated by one skilled in the art after a complete reading of the present application, thegate structures 130 may be formed using a variety of different materials and by performing a variety of known techniques. For example, the gate insulation layer in such agate structure 130 may be comprised of a variety of different insulating materials, e.g., silicon dioxide, a so-called high-k insulating material (k value greater than 10). The gate electrode in such agate structure 130 may be comprised of polysilicon or it may contain at least one metal layer. Thegate structures 130 of thetransistor 100 may be made using so-called “gate first” or “gate last” techniques. Thus, the presently disclosed inventions should not be considered as limited to any particular materials of construction for thegate structures 130 nor the manner in which such agate structure 130 is formed. - Still with continuing reference to
FIG. 3A , thedevice 100 further comprises an isolating electrode 150PG that is conductively coupled to a schematically depictedpower rail 140H at a logically high voltage, e.g., Vdd. The device also includes an isolating electrode 150NG that is conductively coupled to apower rail 140L that is at a logically low voltage, e.g., ground. Of course, the absolute magnitude of the voltages on the power rails 140H, 140L may vary depending upon the particular application, but the voltage on thepower rail 140H will be relatively higher than the voltage on thepower rail 140L. In the illustrative example shown inFIG. 3A , the isolating electrodes 150PG, 150NG are separated by adistance 142. In the depicted embodiment, the isolating electrode 150PG spans across the entirety of theactive region 112P, while the isolating electrode 150NG spans across the entirety of theactive region 112N. In one illustrative embodiment, the isolating electrodes 150PG and 150NG have the same structure and configuration as thegate structures 130, and they may be initially formed at the same time thegate structures 130 are formed. In other cases, the isolating electrodes 150PG and 150NG may be comprised of different materials, may be a different physical size and/or may be formed at different times as compared to thegate structures 130. In one illustrative embodiment, the isolating electrodes 150PG and 150NG and thegate structures 130 are all initially formed as elongated continuous line-type structures. Thereafter, the isolating electrodes 150PG and 150NG are defined by performing another etching process. The isolating electrodes 150PG and 150NG may be conductively coupled to the power rails 140H, 140L, respectively, by any of a variety of different conductive structures that are formed in a layer of insulating material positioned above the substrate. The isolating electrodes 150PG and 150NG each have a long axis and, in one embodiment, the long axis of the isolating electrode 150PG is substantially aligned with the long axis of the isolating electrode 150NG. -
FIG. 3B depicts one illustrative embodiment of anillustrative unit cell 100A of thedevice 100. In this example, theunit cell 100A comprises PFET transistors 120P2 and 120P3 that are positioned on opposite sides of the isolating electrode 150PG and NFET transistors 122N2 and 122N3 that are positioned on opposite sides of the isolating electrode 150NG. Stated another way, the isolating electrode 150PG is positioned above a space between the adjacent doped regions of the transistors 120P2 and 120P3, while the isolating electrode 150NG is positioned above a space between the adjacent doped regions of the transistors 122N2 and 122N3. Of course, as will be appreciated by one skilled in the art after a complete reading of the present application, the inventions disclosed herein are not limited in terms of how many transistors may be formed in theactive regions device 100, nor the number of transistors that may be associated with each of the isolating electrodes 150PG and 150NG. Moreover, the number of transistors associated with each of the isolating electrodes 150PG and 150NG need not be the same for either of theactive regions active regions devices 100 disclosed herein may be employed in situations wherein there are hundreds if not thousands of transistors formed in each of theactive regions FIG. 3C is a simplistic line-based drawing indicating one example of adevice 100 comprised of fourteenPFET devices 120, five isolating electrodes 150PG that are coupled to thepower rail 140H, fourteenNFET devices 122 and five isolating electrodes 150NG that are coupled to thepower rail 140L. Thus, the presently disclosed inventions should not be considered as limited to any particular number or arrangement of transistor devices or any particular number or arrangement of the isolating electrodes 150PG, 150NG. -
FIG. 4A-4C depict various illustrative examples that schematically depict how thedevice 100 may be configured in various situations.FIG. 4A depicts the illustrative example wherein the isolating electrodes 150PG, 150NG are positioned between source regions (“S”) of the respective transistors. The drain regions (“D”) of the various transistors are also depicted inFIG. 4A . More specifically, inFIG. 4A , the isolating electrode 150PG is positioned between the source regions of the PFET devices 120P2 and 120P3, while the isolating electrode 150NG is positioned between the source regions of the NFET devices 122N2 and 122N3. In this illustrative example, the source regions of the PFET devices 120P2-3 are coupled to thepower rail 140H by schematically depictedconductive structures 144, while the source regions of the NFET devices 122N2-3 are coupled to thepower rail 140L by schematically depictedconductive structures 146. -
FIG. 4B depicts the illustrative example wherein the isolating electrodes 150PG, 150NG are positioned between a source region (“S”) on one adjacent transistor and a drain region (“D”) on the other adjacent transistor. More specifically, inFIG. 4B , the isolating electrode 150PG is positioned between the source region of the PFET device 120P2 and the drain region of the PFET device 120P3, while the isolating electrode 150NG is positioned between the source region of the NFET device 122N2 and the drain region of the NFET device 122N3. In this illustrative example, the source region of the PFET device 120P2 is conductively coupled to thepower rail 140H by schematically depictedconductive structures 144, while the source region of the NFET device 122N2 is coupled to thepower rail 140L by schematically depictedconductive structures 146. The drain region of the PFET device 120P3 and the drain region of the NFET device 122N3 are conductively coupled to one another via aconductive strap 148 and illustrative contacts. -
FIG. 4C depicts the illustrative example wherein the isolating electrodes 150PG, 150NG are positioned between drain regions (“D”) of the respective transistors. More specifically, inFIG. 4C , the isolating electrode 150PG is positioned between the drain regions of the PFET devices 120P2 and 120P3, while the isolating electrode 150NG is positioned between the drain regions of the NFET devices 122N2 and 122N3. In this illustrative example, only the isolating electrodes 150PG, 150NG are coupled to the power rails 140H, 140L, respectively. In this example, the drain region of the PFET device 120P3 and the drain region of the NFET device 122N3 are conductively coupled to one another via aconductive strap 148 and illustrative contacts, while the drain region of the PFET device 120P2 and the drain region of the NFET device 122N2 are conductively coupled to one another via aconductive strap 149 and illustrative contacts. The variousconductive structures - With reference to
FIGS. 5A-5E , further illustrative embodiments of various inventions disclosed herein will be further described.FIG. 5A is a schematic plan view of one illustrative embodiment of thedevice 100 wherein the isolating electrode 150PG is positioned between thesource regions 120S of the PFET devices 120P2 and 120P3, while the isolating electrode 150NG is positioned between thesource regions 122S of the NFET devices 122N2 and 122N3, a configuration that also corresponds toFIG. 4A . The drain regions for the PFET devices are denoted with thereference number 120D while the drain regions for the NFET devices are denoted with thereference number 122D. At the point of fabrication depicted inFIG. 5A , conductive line-typedevice level contacts 175 are formed on each of the source/drain regions for the various transistor devices. In some cases, these illustrativedevice level contacts 175 may be referred to within the industry as so-called trench silicide regions. - With continuing reference to
FIGS. 5A-5C , in one illustrative embodiment, thedevice level contacts 175 that contact thesource regions 120S of the transistors 120P2 and 120P3 are conductively coupled to thepower rail 140H by a plurality ofconductive contacts 190P and the isolating electrode 150PG is conductively coupled to thepower rail 140H by aconductive contact 192P. Thedevice level contacts 175 that contact thesource regions 122S of the transistors 122N2 and 122N3 are conductively coupled to thepower rail 140L by a plurality ofconductive contacts 190N, and the isolating electrode 150NG is conductively coupled to thepower rail 140L by aconductive contact 192N. Thedevice level contacts 175 that are coupled to thedrain regions 120D of the PFET devices are conductively contacted bycontacts 131P. Thecontacts 131P are conductively coupled to a conductive structure (not shown), such as a metal line, that is formed in a metallization layer, e.g., themetal 1 layer, formed above the substrate. Thedevice level contacts 175 that are coupled to thedrain regions 122D of the NFET devices are conductively contacted bycontacts 131N. Thecontacts 131N are conductively coupled to a conductive structure (not shown), such as a metal line, that is formed in a metallization layer, e.g., themetal 1 layer, formed above the substrate. - In one illustrative embodiment disclosed herein, the power rails 140H, 140L and the previously described
contacts device 100. That is, the power rails 140H, 140L and the previously describedcontacts device level contacts 175 and the so-called “metal 1” layer that is typically the first general wiring layer formed above the substrate. Further explanation of this unique configuration will be explained in connection with the cross-sectional views “A-A”, “B-B” and “C-C” taken where indicated inFIG. 5A . As shown therein, various layers of insulatingmaterial layer 181 may serve as an etch stop layer and it may be comprised of a material that may be selectively etched with respect to the insulatinglayers layers layer 181 may be comprised of silicon nitride. The thickness of the various layers of insulating material may vary depending upon the particular application and they may be formed by performing a variety of known techniques, e.g., chemical vapor deposition (CVD), atomic layer deposition (ALD), or plasma enhanced versions of those processes. The various conductive structures, such as the power rails 140H, 140L and the previously describedcontacts - The cross-sectional views “A-A”, “B-B” and “C-C” are taken through the
active region 112N (where theNMOS devices 122 are formed) and thepower rail 140L. However, the arrangement of the contacts and the power rail depicted in these various views applies equally to the contacts and arrangement for thePMOS devices 120 and thepower rail 140H, The cross-sectional view “A-A” is taken through thepower rail 140L as indicated. Thepower rail 140L and thecontacts contacts power rail 140L in this view. As can be seen, thepower rail 140L is positioned above theisolation region 113. Also depicted in the view “A-A” is the so-calledmetal 1layer 179 with a connecting via 177 to thepower rail 140L. The cross-sectional view “B-B” is taken through thecontacts isolation region 113. As can be seen in the view “B-B”, thecontact 192N contacts the isolating electrode 150NG. The insulatinglayer 182 is depicted in this view. The cross-sectional view “C-C” is taken through thecontacts 190N above theactive region 112N. As can be seen in the view “C-C”, thecontacts 190N contact thedevice level contacts 175. By positioning the power rails 140H, 140L and thevarious contacts device 100, various advantages may be realized. Due to this local interconnect arrangement approach, the transistor width can be larger, for example, up to 15-20% larger as compared to prior art arrangements involving connections to themetal 1 layer. This increase in transistor width may result in increased circuit performance, e.g., about a 10-15% increase as compared to prior art devices. The increase in performance is due to the fact that a traditional connection scheme at a level above the local interconnect level requires the width of the transistors to be reduced in order to make room for the connections. -
FIG. 5B-5C are cross-sectional views of one illustrative embodiment of various devices disclosed herein. More specifically,FIG. 5B is a cross-sectional view of the various PFET devices that are formed above the P-active region 112P, whileFIG. 5C is a cross-sectional view of the various NFET devices that are formed above the N-active region 112N. As shown therein, the previously mentioned layers of insulatingmaterial layers layer 181 may be comprised of silicon nitride. Conductive structures corresponding to “via 0” 177 and ametal line 179 in the “metal-1” layer are formed in layers of insulatingmaterial FIGS. 5B-5E , thegate structures 130 are comprised of an illustrativegate insulation layer 130A and anillustrative gate electrode 130B. As noted earlier, the materials of construction of thegate structures 130 and the manner in which they are made may vary depending upon the particular application. In the examples depicted inFIGS. 5B-5D , the isolating gate electrodes 150PG, 150NG are part of a corresponding structure that is formed at the same time theillustrative gate structures 130 are formed, although that is not required in all instances.FIGS. 5B-5C depict thedevice 100 wherein the power rails 140H, 140L and thecontacts layer 182. In the embodiment shown inFIGS. 5D-5E , the power rails 140H, 140L are formed in the so-calledmetal 1 layer in the layer of insulatingmaterial 184. As shown inFIG. 5D , aconductive structure 194P conductively couples thecontacts power rail 140H. As shown inFIG. 5E , aconductive structure 194N conductively couples thecontacts power rail 140L. -
FIGS. 6A-6D depict further illustrative embodiments of various inventions disclosed herein. More specifically,FIGS. 6A and 6C depict the situation where the isolating electrode 150PG is positioned between thesource region 120S of the PFET device 120P2 and thedrain region 120D of the PFET device 120P3, a configuration that corresponds toFIG. 4B .FIGS. 6B and 6D depict the situation where the isolating electrode 150NG is positioned between thesource region 122S of the NFET device 122N2 and thedrain region 122D of the NFET device 122N3, a configuration that also corresponds toFIG. 4B . Note that, inFIGS. 6A-6D , thedrain region 120D of the PFET transistor 120P3 is not connected to thepower rail 140H, and thedrain region 122D of the NFET transistor 122N3 is not connected to thepower rail 140L. Rather, as shown inFIG. 4B , thedrain region 120D of the PFET transistor 120P3 and thedrain region 122D of the NFET transistor 122N3 are coupled to one another by a conductive structure 148 (not shown inFIGS. 6A-6D ).FIGS. 6A-6B depict thedevice 100 wherein the power rails 140H, 140L and thecontacts layer 182. In the embodiment shown inFIGS. 6C-6D , the power rails 140H, 140L are formed in the so-called “metal 1” layer in the layer of insulatingmaterial 184. As shown inFIG. 6C , aconductive structure 194P conductively couples thecontacts power rail 140H. As shown inFIG. 6D , aconductive structure 194N conductively couples thecontacts power rail 140L. -
FIGS. 7A-7D depict further illustrative embodiments of various inventions disclosed herein. More specifically,FIGS. 7A and 7C depict the situation where the isolating electrode 150PG is positioned between thedrain region 120D of the PFET device 120P2 and thedrain region 120D of the PFET device 120P3, a configuration that corresponds toFIG. 4C .FIGS. 7B and 7D depict the situation where the isolating electrode 150NG is positioned between thedrain region 122D of the NFET device 122N2 and thedrain region 122D of the NFET device 122N3, a configuration that also corresponds toFIG. 4B . Note that, inFIGS. 7A-7D , only the isolating electrode 150PG is connected to thepower rail 140H, and only the isolating electrode 150NG is connected topower rail 140L. As shown inFIG. 4C , thedrain region 120D of the PFET transistor 120P3 and thedrain region 122D of the NFET transistor 122N3 are coupled to one another by a conductive structure 148 (not shown inFIGS. 7A-7D ), while thedrain region 120D of the PFET transistor 120P2 and thedrain region 122D of the NFET transistor 122N2 are coupled to one another by a conductive structure 149 (also not shown inFIGS. 7A-7D ).FIGS. 7A-7B depict thedevice 100 wherein the power rails 140H, 140L and thecontacts layer 182. In the embodiment shown inFIGS. 7C-7D , the power rails 140H, 140L are formed in the so-called “metal 1” layer in the layer of insulatingmaterial 184. As shown inFIG. 7C , aconductive structure 194P conductively couples thecontact 192P to thepower rail 140H. As shown inFIG. 7D , aconductive structure 194N conductively couples thecontact 192N to thepower rail 140L. - In operation, applying a relatively high voltage to the isolating electrode 150PG via the
power rail 140H electrically blocks or isolates the adjacent PFET transistors formed in the continuousactive region 112P. Similarly, applying a relatively low voltage to the isolating electrode 150NG via thepower rail 140L electrically blocks or isolates the adjacent NFET transistors formed in the continuousactive region 112N. In CMOS technology, to reach conduction in a PMOS channel, the voltage applied to the gate of the PMOS device must be smaller than the voltage applied to the source by at least the threshold voltage of the PMOS device. When the applied voltage on the gate of the PMOS device is larger than the voltage applied to the source (or at least a voltage greater than the threshold of the transistor), the PMOS transistor is turned-off, meaning the active regions on both sides of the isolation electrode 150PG become electrically isolated. For an NMOS transistor, when the voltage applied on the gate of an NMOS device is greater than the voltage applied on the source by at least the threshold voltage of the NMOS device, a channel region is established under the gate that electrically connects the source and the drain of the NMOS device. By applying a voltage on the gate of the NMOS device that is less than the voltage applied to the source region (or at least lesser than the threshold voltage of the NMOS transistor), the NMOS transistor is turned-off, i.e., the active regions on both sides of the isolation electrode 150NG become electrically isolated. - In typical cell architecture, the minimum voltage or ground is used to bias the P-well body of the N-type CMOS transistors. The same minimum voltage can be applied to the N-side isolation electrode 150NG to effectively isolate the adjacent NMOS transistors. The maximum voltage is used to bias the N-well body of the P-type transistors in CMOS architecture. The same maximum voltage can be applied to the P-side isolation electrode 150PG to effectively isolate the adjacent PMOS transistors.
- The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Accordingly, the protection sought herein is as set forth in the claims below.
Claims (36)
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