US20130275709A1 - Methods for reading data from a storage buffer including delaying activation of a column select - Google Patents
Methods for reading data from a storage buffer including delaying activation of a column select Download PDFInfo
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- US20130275709A1 US20130275709A1 US13/445,659 US201213445659A US2013275709A1 US 20130275709 A1 US20130275709 A1 US 20130275709A1 US 201213445659 A US201213445659 A US 201213445659A US 2013275709 A1 US2013275709 A1 US 2013275709A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
Definitions
- Embodiments of the invention relate generally to the field of memory devices. More specifically, embodiments of the present invention may provide one or more techniques for reading data from a storage buffer.
- Computer systems are generally employed in numerous configurations to provide a variety of computing functions. Processing speeds, system flexibility, and size constraints are typically considered by design engineers tasked with developing computer systems and system components. Computer systems generally include a plurality of memory devices which may be used to store data (e.g., programs and user data) and which may be accessible to other system components such as processors or peripheral devices. Such memory devices may include volatile and non-volatile memory devices.
- a memory device such as a synchronous dynamic random access memory (SDRAM)
- SDRAM synchronous dynamic random access memory
- a memory array divided into a plurality of memory banks, or other divisions. Based upon addressing information received by the memory device during operation, data may be stored into and read out of appropriate banks of the memory array.
- an activate (e.g., active) command may be sent to the memory array.
- the activate command activates a row of the memory array.
- a column select command may be sent to the memory array.
- the column select command selects a column of the memory array. With the row activated and the column selected, data may be retrieved from selected memory cells of the memory array.
- a memory device or a portion of a memory device may be used as a storage buffer.
- the storage buffer may use registers to temporarily hold data before the data is output, thereby seamlessly outputting data.
- the storage buffer may use 1024 or 2048 registers. Such a large number of registers may adversely affect the cost of the storage buffer. Further, a die manufactured to hold the registers may take up a significant amount of space.
- embodiments of the present invention may be directed to one or more of the problems set forth above.
- FIG. 1 illustrates a block diagram of a processor-based device in accordance with embodiments of the present invention
- FIG. 2 is a partial schematic illustration of an integrated circuit, incorporating an array of memory cells fabricated in accordance with embodiments of the present invention
- FIG. 3 illustrates a partial functional block diagram of an architecture of a storage buffer in accordance with embodiments of the present invention
- FIG. 4 illustrates a timing diagram of data retrieval from a storage buffer in accordance with embodiments of the present invention
- FIG. 5 illustrates a flowchart of a method for reading data from a storage buffer in accordance with embodiments of the present invention.
- FIG. 6 illustrates a block diagram of a state machine engine that may include a storage buffer in accordance with embodiments of the present invention.
- Some of the subsequently discussed embodiments may facilitate the manufacture of storage buffers with a limited number of registers, thereby conserving space and cost.
- the number of registers may be reduced by stalling column cycles during an array access. For example, a first set of data may be retrieved during a first period of time. The first set of data may be twice the amount of data that can be output during the first period of time. Therefore, following the first period of time, data retrieving may be delayed during a second period of time to allow the remaining portion of the first set of data to be output.
- the first period of time may be substantially similar to the second period of time.
- FIG. 1 a block diagram depicting a processor-based system, generally designated by reference numeral 10 , is illustrated.
- the system 10 may be any of a variety of types such as a computer, pager, cellular phone, personal organizer, control circuit, etc.
- processors 12 such as a microprocessor, control the processing of system functions and requests in the system 10 .
- the processor 12 may include an embedded North or South bridge (not shown), for coupling each of the aforementioned components thereto.
- the bridges may include separate bridges coupled between the processor 12 and the various components of the system 10 .
- the system 10 typically includes a power supply 14 .
- the power supply 14 may advantageously include permanent batteries, replaceable batteries, and/or rechargeable batteries.
- the power supply 14 may also include an AC adapter, so the system 10 may be plugged into a wall outlet, for instance.
- the power supply 14 may include a DC adapter such that the system 10 may be plugged into a vehicle cigarette lighter, for instance.
- Various other devices may be coupled to the processor 12 depending on the functions that the system 10 performs.
- a user interface 16 may be coupled to the processor 12 .
- the user interface 16 may include buttons, switches, a keyboard, a light pen, a mouse, and/or a voice recognition system, for instance.
- a display 18 may also be coupled to the processor 12 .
- the display 18 may include an LCD display, a CRT, LEDs, and/or an audio display, for example. In some embodiments, the display 18 may be part of the user interface 16 (e.g., touch screen tablets).
- an RF sub-system/baseband processor 20 may also be coupled to the processor 12 .
- the RF sub-system/baseband processor 20 may include an antenna that is coupled to an RF receiver and to an RF transmitter (not shown).
- One or more communication ports 22 may also be coupled to the processor 12 .
- the communication port 22 may be adapted to be coupled to one or more peripheral devices 24 such as a modem, a printer, a computer, or to a network, such as a local area network, remote area network, intranet, or the Internet, for instance.
- memory is operably coupled to the processor 12 to store and facilitate execution of various programs.
- the processor 12 may be coupled to the volatile memory 26 which may include Dynamic Random Access Memory (DRAM) and/or Static Random Access Memory (SRAM).
- the volatile memory 26 may include a number of memory modules, such as single inline memory modules (SIMMs) or dual inline memory modules (DIMMs).
- SIMMs single inline memory modules
- DIMMs dual inline memory modules
- the volatile memory 26 may simply be referred to as the “system memory.”
- the volatile memory 26 is typically quite large so that it can store dynamically loaded data (e.g., applications).
- the processor(s) 12 may also be coupled to non-volatile memory 28 .
- the non-volatile memory 28 may include a read-only memory (ROM), such as an EPROM, and/or flash memory to be used in conjunction with the volatile memory.
- ROM read-only memory
- the size of the ROM is typically selected to be just large enough to store any necessary operating system, application programs, and fixed data.
- the non-volatile memory 28 may include a high capacity memory such as a tape or disk drive memory.
- the volatile memory 26 , or the non-volatile memory 28 may be considered a non-transitory tangible machine-readable medium for storing code (e.g., instructions).
- FIGS. 2-3 illustrates an array of memory cells that may be part of the storage buffer
- FIG. 3 illustrates a functional block diagram that may be associated with the architecture of the storage buffer.
- FIGS. 4-5 describe the timing of signals of the storage buffer and methods of operating the storage buffer.
- the memory device 29 includes an array of memory cells which may be part of a storage buffer operating in accordance with the techniques described herein.
- the memory device 29 may comprise a dynamic random access memory (DRAM) device.
- the memory device 29 includes a number of memory cells 30 arranged in a grid pattern and comprising a number of rows and columns. The number of memory cells 30 (and corresponding rows and columns) may vary depending on system requirements and fabrication technology.
- Each memory cell 30 may include an access device (e.g., a MOSFET 32 ), and a storage device (e.g., a capacitor 34 ).
- the memory cell 30 may not include an access device (e.g., some cross-point memories). In other embodiments, the memory cell 30 may include an access device that is part of its storage device (e.g., 1T0C devices, such as floating body devices).
- the MOSFET 32 includes a drain terminal 36 , a source terminal 38 , and a gate 40 .
- the capacitor 34 is coupled to the source terminal 38 .
- the terminal of the capacitor 34 that is not coupled to the MOSFET 32 may be coupled to a ground plane.
- the drain 36 is coupled to a bit line (BL) and the gate 40 is coupled to a word line (WL).
- the MOSFET 32 may be operated such that each of the terminals 36 and 38 operates at one time or another as a source or a drain. Accordingly, for purposes of further discussion it should be recognized that whenever a terminal is identified as a “source” or a “drain,” it is only for convenience and that in fact during operation of the MOSFET 32 either terminal could be a source or a drain depending on the manner in which the MOSFET 32 is being controlled by the voltages applied to the terminals 36 , 38 and 40 .
- embodiments of a memory device 29 may include p-type MOSFETs, n-type MOSFETs, or a combination of both.
- the memory array is arranged in a series of rows and columns.
- an electrical charge is placed on the drain 36 of the MOSFET 32 via a bit line (BL).
- BL bit line
- WL word line
- the depletion region between the gate 40 and the channel may be narrowed such that the electrical charge at the drain 36 can flow to the capacitor 34 .
- the charge may be interpreted as a binary data value in the memory cell 30 .
- a positive charge above a known threshold voltage stored in the capacitor 34 may be interpreted as binary “1.” If the charge in the capacitor 34 is below the threshold value, a binary value of “0” is said to be stored in the memory cell 30 .
- the bit lines BL are used to read and write data to and from the memory cells 30 .
- the word lines WL are used to activate the MOSFET 32 to access a particular row of memory cells 30 .
- the memory device 29 also includes a periphery portion which may include an address buffer 42 , row decoder 44 and column decoder 46 .
- the row decoder 44 and column decoder 46 selectively access the memory cells 30 in response to address signals that are provided on the address bus 48 during read, write, and refresh operations.
- the address signals are typically provided by an external controller such as a microprocessor, or another type of memory controller, but in some embodiment the address signals may be internally generated.
- the column decoder 46 may also include sense amplifiers and input/output circuitry to further facilitate the transfer of data to and from the memory cells 30 via the bit lines BL.
- the memory device 29 receives the address of a particular memory cell(s) 30 at the address buffer 42 .
- the address buffer 42 passes the address to the row decoder 44 .
- the row decoder 44 selectively activates the particular word line WL identified by the address to activate the MOSFET's 32 of each memory cell 30 that is connected to the selected word line WL.
- the column decoder 46 selects the bit line (or bit lines) BL of the memory cell(s) 30 corresponding to the address.
- data received by the input/output circuitry is coupled to the selected bit line (or bit lines) BL and provides for the charge or discharge of the capacitor 34 of the selected memory cell(s) 30 through the activated MOSFET 32 .
- the charge typically corresponds to binary data, as previously described.
- data stored in the selected memory cell(s) 30 represented by the charge stored in the capacitor(s) 34 , is coupled to the select bit line (or bit lines) BL, amplified by the sense amplifier and a corresponding voltage level is provided to the input/output circuitry in the column decoder 46 .
- a memory device 29 may be part of a storage buffer operating in accordance with the techniques described herein and may have a smaller die size than other storage buffers.
- memory device 29 may be part of a storage buffer that includes a limited number of registers.
- the cost to manufacture the storage buffer may be reduced.
- the storage buffer 50 includes multiple memory banks 52 , 54 , 56 , and 58 .
- the storage buffer 50 may include sixteen memory banks (e.g., in an ⁇ 16 configuration).
- each of the memory banks 52 , 54 , 56 , and 58 includes a memory array having a plurality of memory cells 30 .
- each of the memory banks 52 , 54 , 56 , and 58 may be coupled to sense amplifiers for amplifying data read from the memory banks. It should be noted that in certain embodiments, the storage buffer 50 may be only a portion of another memory device.
- a row address 60 is used to select a row (e.g., activate a word line) of the storage buffer 50 , thereby activating a certain number of memory cells 30 for performing a read and/or write operation. For example, activating a word line may activate 2048 memory cells 30 for performing a read operation.
- a column address 62 is used to select a column (e.g., one or more bit lines) of the storage buffer 50 for writing data to and/or reading data from the memory cells 30 . It should be noted that selecting one or more bit lines of the storage buffer 50 may select multiple memory cells 30 for reading and/or writing concurrently. For example, selecting one or more bit lines may select 256 memory cells 30 to be concurrently read from.
- the row address 60 or column address 62 may be used to select one of the memory banks 52 , 54 , 56 , and 58 to be accessed. In other embodiments, a separate bank address may be used to select one of the memory banks 52 , 54 , 56 , and 58 to be accessed.
- data may be transferred from the memory banks 52 , 54 , 56 , and 58 to registers 64 .
- the registers 64 may include any number of data storage locations (e.g., latches, etc.) for temporarily storing data.
- the registers 64 may include approximately 384 data storage locations.
- Data may be transferred from the registers 64 via a data bus 66 to data output circuitry 68 which conditions the data for being output from the storage buffer 50 .
- the data bus 66 may be a 128 bit data bus for concurrently transferring 128 bits from the registers 64 .
- the data output circuitry 68 provides a data output 70 via data nodes (e.g., pins) 72 (e.g., DQ(15:0)). Therefore, the data output circuitry 68 is limited to outputting data based on the number of output data nodes 72 . For example, in a storage buffer 50 with 16 data nodes, 16 bits of data may be output at a time.
- data may be output from the storage buffer 50 seamlessly. For example, when a read request is made to the storage buffer 50 , data may be transferred out via the output data nodes 72 without interruptions.
- the storage buffer 50 may be designed to include a limited number of registers to reduce manufacturing cost and to obtain a limited die size. In certain embodiments, the storage buffer 50 may be designed to completely eliminate the registers 64 .
- the timing diagram 80 includes timing relating to a clock 82 , an activate command 84 , a read command 86 , a row address 88 , a wordline_ 0 90 , a column select 92 , a column address 94 , a register data out 96 , and a buffer data out 98 .
- the clock 82 provides a timing signal to synchronize the operations of the storage buffer 50 .
- the clock 82 consistently provides an alternating signal (e.g., logic low, logic high, logic low, logic high, etc.) during operation of the storage buffer 50 .
- the clock 82 may operate at any suitable frequency.
- the clock 82 may operate at 500 MHz, 750 MHz, 800 MHz, 1.000 GHz, 1.150 GHz, 1.500 GHz, and so forth.
- the activate command 84 is used to activate (e.g., open) a row of memory cells 30 in the storage buffer 50 .
- the activate command 84 may activate the row of memory cells 30 within a selected bank of the storage buffer 50 .
- a pulse 100 illustrates the activate command 84 being applied to the storage buffer 50 .
- the row address 88 is set to “0.” Therefore, wordline_ 0 90 is activated and transitions at a time 102 to a logic high 104 . Accordingly, wordline_ 0 90 is activated from the time 102 through the remaining time shown in the timing diagram 80 .
- the wordline_ 0 90 is activated for performing read and/or write operations.
- the wordline_ 0 90 may activate a specific number of memory cells 30 that corresponds to the particular architecture of the storage buffer 50 . For example, the wordline_ 0 90 may activate 2048 memory cells 30 .
- the read command 86 is used to retrieve data from a selected column of memory cells 30 in the storage buffer 50 .
- a pulse 106 illustrates the read command 86 being applied to the storage buffer 50 .
- the column select 92 transitions to a logic high as illustrated by a pulse 108 .
- the column address 94 is set to “0” (e.g., segment 110 ). Therefore, data is transferred from row “0,” column “0” of the storage buffer 50 into the registers 64 .
- 256 bits of data are transferred into the registers 64 .
- Data is then transferred out of the registers 64 to the data output circuitry 68 responsive to a pulse 112 of the register data out 96 .
- data may be transferred out of the registers 64 at a rate that is less than (e.g., half) the rate that data is transferred into the registers 64 .
- data may be transferred out of the registers 64 (e.g., data output rate) in sets of 128 bits over a period of time of approximately 3.5 ns (e.g., 4.57 GB/s), while data may be transferred into the registers 64 (e.g., retrieval rate) in sets of 256 bits over a period of time of approximately 3.5 ns (e.g., 9.14 GB/s).
- the data may be transferred out of the registers 64 to the data output circuitry 68 using the data bus 66 (e.g., 128 bit data bus).
- a series of pulses 114 illustrate data being output from the data output circuitry 68 onto data nodes (e.g., output data nodes 72 ).
- data may be output 16 bits at a time.
- the series of pulses 114 includes four pulses.
- Data may be output onto the 16 output data nodes 72 with each rising edge (i.e., four times) and each falling edge (i.e., four times) of the series of pulses 114 .
- a pulse 116 illustrates the read command 86 again being applied to the storage buffer 50 .
- the column select 92 transitions to a logic high as illustrated by a pulse 118 .
- the time from the rising edge of the pulse 108 to the rising edge of the pulse 118 (e.g., array cycle time 119 ) may be approximately 3.5 ns.
- the time from the falling edge of the pulse 108 to the falling edge of the pulse 118 may be approximately 3.5 ns.
- the array cycle time 119 may be 2 ns, 4 ns, 5 ns, 10 ns, and so forth.
- the column address 94 is set to “1” (e.g., segment 120 ). Therefore, data is transferred from row “0,” column “1” of the storage buffer 50 into the registers 64 .
- Data is transferred out of the registers 64 to the data output circuitry 68 responsive to a pulse 122 of the register data out 96 .
- a series of pulses 124 illustrate data again being output from the data output circuitry 68 onto data nodes (e.g., output data nodes 72 ). Accordingly, during the series of pulses 124 , the data from the data output circuitry 68 will be output from the storage buffer 50 onto the output data nodes 72 .
- a pulse 126 illustrates the read command 86 again being applied to the storage buffer 50 .
- the column select 92 does not transition, as illustrated by a segment 128 .
- the column select 92 may not transition for a total of two array cycle times beyond an array cycle time 129 that includes pulse 118 (e.g., the array cycle time 129 may be approximately twice the time of the pulse 118 ).
- the column select 92 may not transition for 7.0 ns after the array cycle time 129 , or 8.75 ns after the pulse 118 .
- the column select 92 may not transition for 4 ns, 8 ns, 10 ns, 20 ns, and so forth, after the array cycle time 129 .
- the column select 92 With the column select 92 not transitioning during the segment 128 , no data is transferred from the storage buffer 50 into the registers 64 .
- the registers 64 are able to transfer out any remaining data stored thereon. Accordingly, data is transferred out of the registers 64 to the data output circuitry 68 responsive to a pulse 130 of the register data out 96 .
- a series of pulses 132 illustrate data again being output from the data output circuitry 68 onto data nodes (e.g., output data nodes 72 ). Therefore, during the series of pulses 132 , the data from the data output circuitry 68 will be output from the storage buffer 50 onto the output data nodes 72 .
- a pulse 134 illustrates the read command 86 again being applied to the storage buffer 50 .
- the column select 92 again does not transition, as illustrated by the segment 128 .
- data is transferred out of the registers 64 to the data output circuitry 68 responsive to a pulse 136 of the register data out 96 .
- a series of pulses 138 illustrate data again being output from the data output circuitry 68 onto data nodes (e.g., output data nodes 72 ). Therefore, during the series of pulses 138 , the data from the data output circuitry 68 will be output from the storage buffer 50 onto the output data nodes 72 .
- a pulse 140 illustrates the read command 86 again being applied to the storage buffer 50 .
- This read command 86 initiates a repetition of the cycle that started with the pulse 106 .
- the column select 92 transitions to a logic high as illustrated by a pulse 142 .
- the column address 94 is set to “2” (e.g., segment 144 ). Therefore, data is transferred from row “0,” column “2” of the storage buffer 50 into the registers 64 . Data is then transferred out of the registers 64 to the data output circuitry 68 responsive to a pulse 146 of the register data out 96 .
- a series of pulses 148 illustrate data being output from the data output circuitry 68 onto data nodes (e.g., output data nodes 72 ). Accordingly, during the series of pulses 148 , the data from the data output circuitry 68 will be output from the storage buffer 50 onto the output data nodes 72 .
- a pulse 150 illustrates the read command 86 again being applied to the storage buffer 50 .
- the column select 92 transitions to a logic high as illustrated by a pulse 152 .
- the column address 94 is set to “3” (e.g., segment 154 ). Therefore, data is transferred from row “0,” column “3” of the storage buffer 50 into the registers 64 . Data is then transferred out of the registers 64 to the data output circuitry 68 responsive to a pulse 156 of the register data out 96 .
- a series of pulses 158 illustrate data again being output from the data output circuitry 68 onto data nodes (e.g., output data nodes 72 ). Accordingly, during the series of pulses 158 , the data from the data output circuitry 68 will be output from the storage buffer 50 onto the output data nodes 72 .
- a pulse 160 illustrates the read command 86 again being applied to the storage buffer 50 .
- the column select 92 does not transition, as illustrated by a segment 162 .
- the column select 92 may not transition for a total of two array cycle times beyond an array cycle time (e.g., approximately 3.5 ns) that includes pulse 152 .
- the column select 92 may not transition for 7.0 ns after the array cycle time that includes pulse 152 , or 8.75 ns after the pulse 152 .
- no data is transferred from the storage buffer 50 into the registers 64 .
- the registers 64 are able to transfer out any remaining data. Accordingly, data is transferred out of the registers 64 to the data output circuitry 68 responsive to a pulse 164 of the register data out 96 .
- a series of pulses 166 illustrate data again being output from the data output circuitry 68 onto data nodes (e.g., output data nodes 72 ). Therefore, during the series of pulses 166 , the data from the data output circuitry 68 will be output from the storage buffer 50 onto the output data nodes 72 .
- a pulse 168 illustrates the read command 86 again being applied to the storage buffer 50 .
- the column select 92 again does not transition, as illustrated by the segment 162 .
- data is transferred out of the registers 64 to the data output circuitry 68 responsive to a pulse 170 of the register data out 96 .
- a series of pulses 172 illustrate data again being output from the data output circuitry 68 onto data nodes (e.g., output data nodes 72 ). Therefore, during the series of pulses 172 , the data from the data output circuitry 68 will be output from the storage buffer 50 onto the output data nodes 72 .
- data may be read from the storage buffer 50 by activating a first column select followed by activating a second column select (e.g., this may take a total of approximately 7.0 ns). Because data is retrieved from the columns at twice the rate that data is transferred out of the storage buffer 50 , no column select is applied for two array cycle times (e.g., approximately 7.0 ns). This pattern is then repeated until all data is read out of a particular word line of the storage buffer 50 .
- the timing diagram 80 as illustrated may read out approximately 1024 bits of data over a time period of approximately 28 ns. In certain embodiments, the timing diagram 80 may represent timing for outputting only half of the data from wordline_ 0 90 .
- the timing diagram 80 may be repeated for more columns (e.g., data may be transferred from columns 4 through 7 in a similar manner as described above).
- the storage buffer 50 may output approximately 2048 bits of data over a time period of approximately 56 ns. Further, the same method may be repeated with each word line. Using such a method, data may be seamlessly output from the storage buffer 50 . Further, die space for the storage buffer 50 may be minimized enabling the storage buffer 50 to be manufactured at a lower cost than other storage buffers.
- data may be read from the storage buffer 50 at four times the rate that data is transferred out of the storage buffer 50 . Accordingly, data may be read from the storage buffer 50 by activating a first column select followed by activating a second column select. To transfer all of the data read out of the storage buffer 50 during the first and second column selects, no column select may be applied for four array cycle times. Furthermore, the same pattern of reading data and delaying column selects may be applied to any type of storage buffer 50 configuration.
- a flowchart of a method 180 for retrieving (e.g., fetching) data from a storage buffer 50 is illustrated.
- a first column select is activated during a first period of time to retrieve a first set of data.
- the first period of time may include the time it takes for a full array cycle, including activating and deactivating the first column select.
- the first period of time may be approximately 3.5 ns (e.g., 1.75 ns activated and 1.75 ns deactivated).
- the first set of data may be data including any number of bits.
- the first set of data may include 256 bits.
- a second column select is activated during a second period of time to retrieve a second set of data.
- the second period of time may include the time it takes for a full array cycle, including activating and deactivating the second column select.
- the second period of time may be approximately 3.5 ns (e.g., 1.75 ns activated and 1.75 ns deactivated).
- the second set of data may be data including any number of bits.
- the second set of data may include 256 bits.
- activation of a column select is delayed during a third period of time to inhibit additional data retrieval (e.g., to allow the first and second sets of data to be output from the storage buffer 50 ).
- the third period of time may be substantially the same as a sum of the first period of time and the second period of time. For example, if the first period of time is approximately 3.5 ns and the second period of time is approximately 3.5 ns, the third period of time may be approximately 7.0 ns.
- a third column select is activated during a fourth period of time to retrieve a third set of data.
- a fourth column select is activated during a fifth period of time to retrieve a fourth set of data.
- activation of a column select is delayed during a sixth period of time to inhibit additional data retrieval (e.g., to allow the third and fourth sets of data to be output from the storage buffer 50 ).
- a fifth column select is activated during a seventh period of time to retrieve a fifth set of data.
- a sixth column select is activated during an eighth period of time to retrieve a sixth set of data.
- activation of a column select is delayed during a ninth period of time to inhibit additional data retrieval (e.g., to allow the fifth and sixth sets of data to be output from the storage buffer 50 ).
- a seventh column select is activated during a tenth period of time to retrieve a seventh set of data.
- an eighth column select is activated during an eleventh period of time to retrieve an eighth set of data.
- activation of a column select is delayed during a twelfth period of time to inhibit additional data retrieval (e.g., to allow the seventh and eighth sets of data to be output from the storage buffer 50 ).
- a sum of the twelve periods of time may be a total time that it takes to retrieve all of the data from a word line (e.g., wordline_ 0 90 ).
- the sum of the twelve periods of time may be approximately 56 ns. In other embodiments, the sum of the twelve period of time may be less than or greater than 56 ns.
- the storage buffer 50 may be precharged during a period of time (e.g., to be ready to retrieve data from another word line).
- some embodiments may only include blocks 182 through 186 , while other embodiments may only include blocks 182 through 192 . It should be noted that the method 180 may include fewer or more blocks than illustrated.
- data may be retrieved from the storage buffer 50 at a retrieval rate that is greater than the output rate of the storage buffer 50 .
- the retrieval of data from the storage buffer 50 may be delayed to allow the output of the storage buffer 50 time to output the data.
- the ideas presented above may be applied to any mismatch between the retrieval rate and the output rate of the storage buffer 50 in order to provide for seamless data output from the storage buffer 50 .
- the storage buffer 50 provides the seamless data output with few registers which allows the storage buffer 50 to be manufactured at a lower cost than other storage buffers.
- the storage buffer 50 as described in the present application may be used in a variety of different applications.
- the storage buffer 50 may be used in a state machine engine 206 illustrated in FIG. 6 , which may operate under control of the processor 12 of FIG. 1 .
- the state machine engine 206 may employ any one of a number of state machine architectures, including, but not limited to Mealy architectures, Moore architectures, Finite State Machines (FSMs), Deterministic FSMs (DFSMs), Bit-Parallel State Machines (BPSMs), etc. Though a variety of architectures may be used, for discussion purposes, this application refers to FSMs. However, those skilled in the art will appreciate that the described techniques may be employed using any one of a variety of state machine architectures.
- the state machine engine 206 may include a number of (e.g., one or more) finite state machine (FSM) lattices 208 .
- FSM finite state machine
- Each FSM lattice 208 may include multiple FSMs that each receive and analyze the same data in parallel.
- the FSM lattices 208 may be arranged in groups (e.g., clusters), such that clusters of FSM lattices 208 may analyze the same input data in parallel.
- clusters of FSM lattices 208 of the state machine engine 206 may be arranged in a hierarchical structure wherein outputs from state machine lattices 208 on a lower level of the hierarchical structure may be used as inputs to state machine lattices 208 on a higher level.
- outputs from state machine lattices 208 on a lower level of the hierarchical structure may be used as inputs to state machine lattices 208 on a higher level.
- the state machine engine 206 can be employed for pattern recognition in systems that utilize high processing speeds. For instance, embodiments described herein may be incorporated in systems with processing speeds of 1 GByte/sec. Accordingly, utilizing the state machine engine 206 , data from high speed memory devices or other external devices may be rapidly analyzed for various patterns.
- the state machine engine 206 may analyze a data stream according to several criteria, and their respective search terms, at about the same time, e.g., during a single device cycle.
- Each of the FSM lattices 208 within a cluster of FSMs on a level of the state machine engine 206 may each receive the same search term from the data stream at about the same time, and each of the parallel FSM lattices 208 may determine whether the term advances the state machine engine 206 to the next state in the processing criterion.
- the state machine engine 206 may analyze terms according to a relatively large number of criteria, e.g., more than 100, more than 110, or more than 10,000. Because they operate in parallel, they may apply the criteria to a data stream having a relatively high bandwidth, e.g., a data stream of greater than or generally equal to 1 GByte/sec, without slowing the data stream.
- the state machine engine 206 may be configured to recognize (e.g., detect) a great number of patterns in a data stream. For instance, the state machine engine 206 may be utilized to detect a pattern in one or more of a variety of types of data streams that a user or other entity might wish to analyze. For example, the state machine engine 206 may be configured to analyze a stream of data received over a network, such as packets received over the Internet or voice or data received over a cellular network. In one example, the state machine engine 206 may be configured to analyze a data stream for spam or malware. The data stream may be received as a serial data stream, in which the data is received in an order that has meaning, such as in a temporally, lexically, or semantically significant order.
- the data stream may be received in parallel or out of order and, then, converted into a serial data stream, e.g., by reordering packets received over the Internet.
- the data stream may present terms serially, but the bits expressing each of the terms may be received in parallel.
- the data stream may be received from a source external to the system 10 , or may be formed by interrogating a memory device, such as the volatile memory 26 or non-volatile memory 28 , and forming the data stream from data stored in the memory 26 , 28 .
- the state machine engine 206 may be configured to recognize a sequence of characters that spell a certain word, a sequence of genetic base pairs that specify a gene, a sequence of bits in a picture or video file that form a portion of an image, a sequence of bits in an executable file that form a part of a program, or a sequence of bits in an audio file that form a part of a song or a spoken phrase.
- the stream of data to be analyzed may include multiple bits of data in a binary format or other formats, e.g., base ten, ASCII, etc.
- the stream may encode the data with a single digit or multiple digits, e.g., several binary digits.
- the FSM lattice 208 comprises an array of blocks.
- Each block may include a plurality of selectively couple-able hardware elements (e.g., programmable elements and/or special purpose elements) that correspond to a plurality of states in a FSM. Similar to a state in a FSM, a hardware element can analyze an input stream and activate a downstream hardware element, based on the input stream.
- programmable elements and/or special purpose elements e.g., programmable elements and/or special purpose elements
- the programmable elements can be programmed to implement many different functions.
- the programmable elements may include state machine elements (SMEs) that are hierarchically organized into rows and blocks.
- SMEs state machine elements
- a hierarchy of programmable switching elements can be used, including inter-block switching elements, intra-block switching elements, and intra-row switching elements.
- the switching elements may include routing structures and buffers.
- An SME can correspond to a state of a FSM implemented by the FSM lattice 208 .
- a FSM can be implemented on the FSM lattice 208 by programming the SMEs to correspond to the functions of states and by selectively coupling together the SMEs to correspond to the transitions between states in the FSM.
- the state machine engine 206 is configured to receive data from a source, such as the volatile memory 26 and/or the non-volatile 28 , over a data bus.
- data may be sent to the state machine engine 206 through a bus interface, such as a DDR3 bus interface 210 .
- the DDR3 bus interface 210 may be capable of exchanging data at a rate greater than or equal to 1 GByte/sec.
- the bus interface 210 may be any suitable bus interface for exchanging data to and from a data source to the state machine engine 206 , such as a NAND Flash interface, PCI interface, etc.
- the state machine engine 206 includes one or more FSM lattices 208 configured to analyze data.
- Each FSM lattice 208 may be divided into two half-lattices.
- each half lattice may include 24K SMEs, such that the lattice 208 includes 48K SMEs.
- the lattice 208 may comprise any desirable number of SMEs.
- the state machine engine 206 may include multiple FSM lattices 208 , as previously described.
- Data to be analyzed may be received at the bus interface 210 and transmitted to the FSM lattice 208 through a number of buffers and buffer interfaces.
- the data path includes data buffers 212 , process buffers 214 and an inter-rank (IR) bus and process buffer interface 216 .
- the data buffers 212 are configured to receive and temporarily store data to be analyzed.
- there are two data buffers 212 (data buffer A and data buffer B). Data may be stored in one of the two data buffers 212 , while data is being emptied from the other data buffer 212 , for analysis by the FSM lattice 208 .
- the data buffers 212 may be 32 KBytes each.
- the IR bus and process buffer interface 216 may facilitate the transfer of data to the process buffer 214 .
- the IR bus and process buffer 216 ensures that data is processed by the FSM lattice 208 in order.
- the IR bus and process buffer 216 may coordinate the exchange of data, timing information, packing instructions, etc. such that data is received and analyzed in the correct order.
- the IR bus and process buffer 216 allows the analyzing of multiple data sets in parallel through logical ranks of FSM lattices 208 .
- the state machine engine 206 also includes a de-compressor 218 and a compressor 220 to aid in the transfer of the large amounts of data through the state machine engine 206 .
- the compressor 220 and de-compressor 218 work in conjunction such that data can be compressed to minimize the data transfer times. By compressing the data to be analyzed, the bus utilization time may be minimized.
- a mask may be provided to the state machine engine 206 to provide information on which state machines are likely to be unused.
- the compressor 220 and de-compressor 218 can also be configured to handle data of varying burst lengths. By padding compressed data and including an indicator as to when each compressed region ends, the compressor 220 may improve the overall processing speed through the state machine engine 206 .
- the compressor 220 and de-compressor 218 may also be used to compress and decompress match results data after analysis by the FSM lattice 208 .
- the output of the FSM lattice 208 can comprise a state vector.
- the state vector comprises the state (e.g., activated or not activated) of programmable elements of the FSM lattice 208 .
- Each state vector may be temporarily stored in the state vector cache memory 222 for further hierarchical processing and analysis. That is, the state of each state machine may be stored, such that the final state may be used in further analysis, while freeing the state machines for reprogramming and/or further analysis of a new data set.
- the state vector cache memory 222 allows storage of information, here state vectors, for quick retrieval and use, here by the FSM lattice 208 , for instance.
- Additional buffers such as the state vector memory buffer 224 , state vector intermediate input buffer 226 , and state vector intermediate output buffer 228 , may be utilized in conjunction with the state vector cache memory 222 to accommodate rapid analysis and storage of state vectors, while adhering to packet transmission protocol through the state machine engine 206 .
- match results may be stored in a match results memory 230 . That is, a “match vector” indicating a match (e.g., detection of a pattern of interest) may be stored in the match results memory 230 .
- the match result can then be sent to a match buffer 232 for transmission over the bus interface 210 to the processor 12 , for example.
- the match results may be compressed.
- Additional registers and buffers may be provided in the state machine engine 206 , as well.
- the state machine engine 206 may include control and status registers 234 .
- restore and program buffers 236 may be provided for using in programming the FSM lattice 208 initially, or restoring the state of the machines in the FSM lattice 208 during analysis.
- save and repair map buffers 238 may also be provided for storage of save and repair maps for setup and usage.
- the state machine engine 206 includes many different buffers.
- any of the buffers described herein may include the features of the storage buffer 50 described above.
- any of the following may include features of the storage buffer 50 : the data buffers 212 , the process buffers 214 , the state vector memory buffer 224 , the state vector intermediate input buffer 226 , the state vector intermediate output buffer 228 , the match buffers 232 , the restore and program buffers 236 , the save and repair map buffers 238 , and so forth.
Abstract
Description
- 1. Field of Invention
- Embodiments of the invention relate generally to the field of memory devices. More specifically, embodiments of the present invention may provide one or more techniques for reading data from a storage buffer.
- 2. Description of Related Art
- Computer systems are generally employed in numerous configurations to provide a variety of computing functions. Processing speeds, system flexibility, and size constraints are typically considered by design engineers tasked with developing computer systems and system components. Computer systems generally include a plurality of memory devices which may be used to store data (e.g., programs and user data) and which may be accessible to other system components such as processors or peripheral devices. Such memory devices may include volatile and non-volatile memory devices.
- Typically, a memory device, such as a synchronous dynamic random access memory (SDRAM), includes a memory array divided into a plurality of memory banks, or other divisions. Based upon addressing information received by the memory device during operation, data may be stored into and read out of appropriate banks of the memory array. For example, during operation of SDRAM, an activate (e.g., active) command may be sent to the memory array. The activate command activates a row of the memory array. Further, a column select command may be sent to the memory array. The column select command selects a column of the memory array. With the row activated and the column selected, data may be retrieved from selected memory cells of the memory array.
- In certain architectures, a memory device or a portion of a memory device may be used as a storage buffer. When data is read from the storage buffer, it may be beneficial for the data to be output seamlessly (e.g., without interruption). However, in some cases, a column select of the memory device retrieves more data than is desirable. Therefore, the storage buffer may use registers to temporarily hold data before the data is output, thereby seamlessly outputting data. As will be appreciated, there may be a large number of registers. For example, the storage buffer may use 1024 or 2048 registers. Such a large number of registers may adversely affect the cost of the storage buffer. Further, a die manufactured to hold the registers may take up a significant amount of space.
- Accordingly, embodiments of the present invention may be directed to one or more of the problems set forth above.
-
FIG. 1 illustrates a block diagram of a processor-based device in accordance with embodiments of the present invention; -
FIG. 2 is a partial schematic illustration of an integrated circuit, incorporating an array of memory cells fabricated in accordance with embodiments of the present invention; -
FIG. 3 illustrates a partial functional block diagram of an architecture of a storage buffer in accordance with embodiments of the present invention; -
FIG. 4 illustrates a timing diagram of data retrieval from a storage buffer in accordance with embodiments of the present invention; -
FIG. 5 illustrates a flowchart of a method for reading data from a storage buffer in accordance with embodiments of the present invention; and -
FIG. 6 illustrates a block diagram of a state machine engine that may include a storage buffer in accordance with embodiments of the present invention. - Some of the subsequently discussed embodiments may facilitate the manufacture of storage buffers with a limited number of registers, thereby conserving space and cost. As is described in detail below, the number of registers may be reduced by stalling column cycles during an array access. For example, a first set of data may be retrieved during a first period of time. The first set of data may be twice the amount of data that can be output during the first period of time. Therefore, following the first period of time, data retrieving may be delayed during a second period of time to allow the remaining portion of the first set of data to be output. As will be appreciated, in certain embodiments, the first period of time may be substantially similar to the second period of time. As such, the following discussion describes devices and methods in accordance with embodiments of the present technique.
- Turning now to the drawings, and referring initially to
FIG. 1 , a block diagram depicting a processor-based system, generally designated byreference numeral 10, is illustrated. Thesystem 10 may be any of a variety of types such as a computer, pager, cellular phone, personal organizer, control circuit, etc. In a typical processor-based device, one ormore processors 12, such as a microprocessor, control the processing of system functions and requests in thesystem 10. As will be appreciated, theprocessor 12 may include an embedded North or South bridge (not shown), for coupling each of the aforementioned components thereto. Alternatively, the bridges may include separate bridges coupled between theprocessor 12 and the various components of thesystem 10. - The
system 10 typically includes apower supply 14. For instance, if thesystem 10 is a portable system, thepower supply 14 may advantageously include permanent batteries, replaceable batteries, and/or rechargeable batteries. Thepower supply 14 may also include an AC adapter, so thesystem 10 may be plugged into a wall outlet, for instance. In addition, thepower supply 14 may include a DC adapter such that thesystem 10 may be plugged into a vehicle cigarette lighter, for instance. Various other devices may be coupled to theprocessor 12 depending on the functions that thesystem 10 performs. For instance, auser interface 16 may be coupled to theprocessor 12. Theuser interface 16 may include buttons, switches, a keyboard, a light pen, a mouse, and/or a voice recognition system, for instance. Adisplay 18 may also be coupled to theprocessor 12. Thedisplay 18 may include an LCD display, a CRT, LEDs, and/or an audio display, for example. In some embodiments, thedisplay 18 may be part of the user interface 16 (e.g., touch screen tablets). Furthermore, an RF sub-system/baseband processor 20 may also be coupled to theprocessor 12. The RF sub-system/baseband processor 20 may include an antenna that is coupled to an RF receiver and to an RF transmitter (not shown). One ormore communication ports 22 may also be coupled to theprocessor 12. Thecommunication port 22 may be adapted to be coupled to one or moreperipheral devices 24 such as a modem, a printer, a computer, or to a network, such as a local area network, remote area network, intranet, or the Internet, for instance. - Because the
processor 12 generally controls the functioning of thesystem 10 by implementing software programs, memory is operably coupled to theprocessor 12 to store and facilitate execution of various programs. For instance, theprocessor 12 may be coupled to thevolatile memory 26 which may include Dynamic Random Access Memory (DRAM) and/or Static Random Access Memory (SRAM). Thevolatile memory 26 may include a number of memory modules, such as single inline memory modules (SIMMs) or dual inline memory modules (DIMMs). As can be appreciated, thevolatile memory 26 may simply be referred to as the “system memory.” Thevolatile memory 26 is typically quite large so that it can store dynamically loaded data (e.g., applications). - The processor(s) 12 may also be coupled to
non-volatile memory 28. Thenon-volatile memory 28 may include a read-only memory (ROM), such as an EPROM, and/or flash memory to be used in conjunction with the volatile memory. The size of the ROM is typically selected to be just large enough to store any necessary operating system, application programs, and fixed data. Additionally, thenon-volatile memory 28 may include a high capacity memory such as a tape or disk drive memory. As will be appreciated, thevolatile memory 26, or thenon-volatile memory 28 may be considered a non-transitory tangible machine-readable medium for storing code (e.g., instructions). - One or more components of the
system 10 may include a storage buffer that functions in accordance with embodiments described herein. Some examples of devices that may be part of a storage buffer are illustrated inFIGS. 2-3 . Specifically,FIG. 2 illustrates an array of memory cells that may be part of the storage buffer, andFIG. 3 illustrates a functional block diagram that may be associated with the architecture of the storage buffer.FIGS. 4-5 describe the timing of signals of the storage buffer and methods of operating the storage buffer. - Referring now to
FIG. 2 , a partial schematic illustration of an integrated circuit, such as amemory device 29, which may be implemented in thevolatile memory 26, is illustrated. Thememory device 29 includes an array of memory cells which may be part of a storage buffer operating in accordance with the techniques described herein. In some embodiments, thememory device 29 may comprise a dynamic random access memory (DRAM) device. Thememory device 29 includes a number ofmemory cells 30 arranged in a grid pattern and comprising a number of rows and columns. The number of memory cells 30 (and corresponding rows and columns) may vary depending on system requirements and fabrication technology. Eachmemory cell 30 may include an access device (e.g., a MOSFET 32), and a storage device (e.g., a capacitor 34). In certain embodiments, thememory cell 30 may not include an access device (e.g., some cross-point memories). In other embodiments, thememory cell 30 may include an access device that is part of its storage device (e.g., 1T0C devices, such as floating body devices). TheMOSFET 32 includes adrain terminal 36, asource terminal 38, and agate 40. Thecapacitor 34 is coupled to thesource terminal 38. The terminal of thecapacitor 34 that is not coupled to theMOSFET 32 may be coupled to a ground plane. As described further below, thedrain 36 is coupled to a bit line (BL) and thegate 40 is coupled to a word line (WL). - It should be noted that although the above description depicts the terminal of the access device coupled to the
capacitor 34 as the “source” 38 and the other non-gate terminal of the access device as the “drain” 36, during read and write operations, theMOSFET 32 may be operated such that each of theterminals MOSFET 32 either terminal could be a source or a drain depending on the manner in which theMOSFET 32 is being controlled by the voltages applied to theterminals memory device 29 may include p-type MOSFETs, n-type MOSFETs, or a combination of both. - As previously described, the memory array is arranged in a series of rows and columns. To implement the data storage capabilities of a
memory cell 30, an electrical charge is placed on thedrain 36 of theMOSFET 32 via a bit line (BL). By controlling the voltage at thegate 40 via the word line (WL), the depletion region between thegate 40 and the channel may be narrowed such that the electrical charge at thedrain 36 can flow to thecapacitor 34. By storing electrical charge in thecapacitor 34, the charge may be interpreted as a binary data value in thememory cell 30. For instance, for a single-bit storage device, a positive charge above a known threshold voltage stored in thecapacitor 34 may be interpreted as binary “1.” If the charge in thecapacitor 34 is below the threshold value, a binary value of “0” is said to be stored in thememory cell 30. - The bit lines BL are used to read and write data to and from the
memory cells 30. The word lines WL are used to activate theMOSFET 32 to access a particular row ofmemory cells 30. Accordingly, thememory device 29 also includes a periphery portion which may include anaddress buffer 42,row decoder 44 andcolumn decoder 46. Therow decoder 44 andcolumn decoder 46 selectively access thememory cells 30 in response to address signals that are provided on theaddress bus 48 during read, write, and refresh operations. The address signals are typically provided by an external controller such as a microprocessor, or another type of memory controller, but in some embodiment the address signals may be internally generated. Thecolumn decoder 46 may also include sense amplifiers and input/output circuitry to further facilitate the transfer of data to and from thememory cells 30 via the bit lines BL. - In one mode of operation, the
memory device 29 receives the address of a particular memory cell(s) 30 at theaddress buffer 42. Theaddress buffer 42 passes the address to therow decoder 44. Therow decoder 44 selectively activates the particular word line WL identified by the address to activate the MOSFET's 32 of eachmemory cell 30 that is connected to the selected word line WL. Thecolumn decoder 46 selects the bit line (or bit lines) BL of the memory cell(s) 30 corresponding to the address. For a write operation, data received by the input/output circuitry is coupled to the selected bit line (or bit lines) BL and provides for the charge or discharge of thecapacitor 34 of the selected memory cell(s) 30 through the activatedMOSFET 32. The charge typically corresponds to binary data, as previously described. For a read operation, data stored in the selected memory cell(s) 30, represented by the charge stored in the capacitor(s) 34, is coupled to the select bit line (or bit lines) BL, amplified by the sense amplifier and a corresponding voltage level is provided to the input/output circuitry in thecolumn decoder 46. - As described below, a
memory device 29 may be part of a storage buffer operating in accordance with the techniques described herein and may have a smaller die size than other storage buffers. For example,memory device 29 may be part of a storage buffer that includes a limited number of registers. Furthermore, because the storage buffer includes a limited number of registers, the cost to manufacture the storage buffer may be reduced. - Referring now to
FIG. 3 , a partial functional block diagram of an architecture of astorage buffer 50 is illustrated. Thestorage buffer 50 includesmultiple memory banks storage buffer 50 may include sixteen memory banks (e.g., in an ×16 configuration). As will be appreciated, each of thememory banks memory cells 30. Furthermore, each of thememory banks storage buffer 50 may be only a portion of another memory device. Arow address 60 is used to select a row (e.g., activate a word line) of thestorage buffer 50, thereby activating a certain number ofmemory cells 30 for performing a read and/or write operation. For example, activating a word line may activate 2048memory cells 30 for performing a read operation. Further, acolumn address 62 is used to select a column (e.g., one or more bit lines) of thestorage buffer 50 for writing data to and/or reading data from thememory cells 30. It should be noted that selecting one or more bit lines of thestorage buffer 50 may selectmultiple memory cells 30 for reading and/or writing concurrently. For example, selecting one or more bit lines may select 256memory cells 30 to be concurrently read from. In certain embodiments, therow address 60 orcolumn address 62 may be used to select one of thememory banks memory banks - During a memory read, data may be transferred from the
memory banks registers 64 may include any number of data storage locations (e.g., latches, etc.) for temporarily storing data. For example, theregisters 64 may include approximately 384 data storage locations. Data may be transferred from theregisters 64 via adata bus 66 todata output circuitry 68 which conditions the data for being output from thestorage buffer 50. In certain embodiments, thedata bus 66 may be a 128 bit data bus for concurrently transferring 128 bits from theregisters 64. Thedata output circuitry 68 provides adata output 70 via data nodes (e.g., pins) 72 (e.g., DQ(15:0)). Therefore, thedata output circuitry 68 is limited to outputting data based on the number ofoutput data nodes 72. For example, in astorage buffer 50 with 16 data nodes, 16 bits of data may be output at a time. - Using the
storage buffer 50 as described above, data may be output from thestorage buffer 50 seamlessly. For example, when a read request is made to thestorage buffer 50, data may be transferred out via theoutput data nodes 72 without interruptions. Further, thestorage buffer 50 may be designed to include a limited number of registers to reduce manufacturing cost and to obtain a limited die size. In certain embodiments, thestorage buffer 50 may be designed to completely eliminate theregisters 64. - Turning to
FIG. 4 , a timing diagram 80 of data retrieval from thestorage buffer 50 is illustrated. The timing diagram 80 includes timing relating to a clock 82, an activatecommand 84, aread command 86, arow address 88, awordline_0 90, a column select 92, acolumn address 94, a register data out 96, and a buffer data out 98. The clock 82 provides a timing signal to synchronize the operations of thestorage buffer 50. As illustrated, the clock 82 consistently provides an alternating signal (e.g., logic low, logic high, logic low, logic high, etc.) during operation of thestorage buffer 50. The clock 82 may operate at any suitable frequency. For example, the clock 82 may operate at 500 MHz, 750 MHz, 800 MHz, 1.000 GHz, 1.150 GHz, 1.500 GHz, and so forth. - The activate
command 84 is used to activate (e.g., open) a row ofmemory cells 30 in thestorage buffer 50. In certain embodiments, the activatecommand 84 may activate the row ofmemory cells 30 within a selected bank of thestorage buffer 50. Apulse 100 illustrates the activatecommand 84 being applied to thestorage buffer 50. At the time thepulse 100 is applied, therow address 88 is set to “0.” Therefore, wordline_0 90 is activated and transitions at atime 102 to a logic high 104. Accordingly, wordline_0 90 is activated from thetime 102 through the remaining time shown in the timing diagram 80. As such, thewordline_0 90 is activated for performing read and/or write operations. As will be appreciated, thewordline_0 90 may activate a specific number ofmemory cells 30 that corresponds to the particular architecture of thestorage buffer 50. For example, thewordline_0 90 may activate 2048memory cells 30. - The read
command 86 is used to retrieve data from a selected column ofmemory cells 30 in thestorage buffer 50. Apulse 106 illustrates the readcommand 86 being applied to thestorage buffer 50. After thepulse 106 is issued, the column select 92 transitions to a logic high as illustrated by apulse 108. While thepulse 108 is applied, thecolumn address 94 is set to “0” (e.g., segment 110). Therefore, data is transferred from row “0,” column “0” of thestorage buffer 50 into theregisters 64. In certain embodiments, with a single column select 92, 256 bits of data are transferred into theregisters 64. Data is then transferred out of theregisters 64 to thedata output circuitry 68 responsive to apulse 112 of the register data out 96. As will be appreciated, data may be transferred out of theregisters 64 at a rate that is less than (e.g., half) the rate that data is transferred into theregisters 64. For example, data may be transferred out of the registers 64 (e.g., data output rate) in sets of 128 bits over a period of time of approximately 3.5 ns (e.g., 4.57 GB/s), while data may be transferred into the registers 64 (e.g., retrieval rate) in sets of 256 bits over a period of time of approximately 3.5 ns (e.g., 9.14 GB/s). The data may be transferred out of theregisters 64 to thedata output circuitry 68 using the data bus 66 (e.g., 128 bit data bus). A series ofpulses 114 illustrate data being output from thedata output circuitry 68 onto data nodes (e.g., output data nodes 72). As discussed above, data may beoutput 16 bits at a time. For example, the series ofpulses 114 includes four pulses. Data may be output onto the 16output data nodes 72 with each rising edge (i.e., four times) and each falling edge (i.e., four times) of the series ofpulses 114. Thus, 128 bits of data may be output during the series of pulses 114 (i.e., 16×8=128). Accordingly, during the series ofpulses 114, the data from thedata output circuitry 68 will be output from thestorage buffer 50 onto theoutput data nodes 72. - A
pulse 116 illustrates the readcommand 86 again being applied to thestorage buffer 50. After thepulse 116 is issued, the column select 92 transitions to a logic high as illustrated by apulse 118. It should be noted that, in certain embodiments, the time from the rising edge of thepulse 108 to the rising edge of the pulse 118 (e.g., array cycle time 119) may be approximately 3.5 ns. Likewise, the time from the falling edge of thepulse 108 to the falling edge of thepulse 118 may be approximately 3.5 ns. In other embodiments, thearray cycle time 119 may be 2 ns, 4 ns, 5 ns, 10 ns, and so forth. While thepulse 118 is applied, thecolumn address 94 is set to “1” (e.g., segment 120). Therefore, data is transferred from row “0,” column “1” of thestorage buffer 50 into theregisters 64. - As will be appreciated, just prior to the
pulse 118, theregisters 64 may contain approximately half of the data transferred from row “0,” column “0” of thestorage buffer 50. For example, if 256 bits of data were transferred from row “0,” column “0” into theregisters 64, only 128 bits of data may remain in theregisters 64 due to 128 bits of data being transferred from theregisters 64 to thedata output circuitry 68 responsive topulse 112. Therefore, theregisters 64 may have 256 available temporary storage locations to store the data transferred from row “0,” column “1.” Accordingly, theregisters 64 may include one and a half times the amount of storage locations that are used for transferring data from a single column of a row (e.g., 1.5×256=384). Data is transferred out of theregisters 64 to thedata output circuitry 68 responsive to apulse 122 of the register data out 96. A series ofpulses 124 illustrate data again being output from thedata output circuitry 68 onto data nodes (e.g., output data nodes 72). Accordingly, during the series ofpulses 124, the data from thedata output circuitry 68 will be output from thestorage buffer 50 onto theoutput data nodes 72. - Furthermore, a
pulse 126 illustrates the readcommand 86 again being applied to thestorage buffer 50. After thepulse 126 is issued, the column select 92 does not transition, as illustrated by asegment 128. In certain embodiments, the column select 92 may not transition for a total of two array cycle times beyond anarray cycle time 129 that includes pulse 118 (e.g., thearray cycle time 129 may be approximately twice the time of the pulse 118). For example, duringsegment 128, the column select 92 may not transition for 7.0 ns after thearray cycle time 129, or 8.75 ns after thepulse 118. In other embodiments, the column select 92 may not transition for 4 ns, 8 ns, 10 ns, 20 ns, and so forth, after thearray cycle time 129. With the column select 92 not transitioning during thesegment 128, no data is transferred from thestorage buffer 50 into theregisters 64. Thus, during thesegment 128, theregisters 64 are able to transfer out any remaining data stored thereon. Accordingly, data is transferred out of theregisters 64 to thedata output circuitry 68 responsive to apulse 130 of the register data out 96. A series ofpulses 132 illustrate data again being output from thedata output circuitry 68 onto data nodes (e.g., output data nodes 72). Therefore, during the series ofpulses 132, the data from thedata output circuitry 68 will be output from thestorage buffer 50 onto theoutput data nodes 72. - Likewise, a
pulse 134 illustrates the readcommand 86 again being applied to thestorage buffer 50. After thepulse 134 is issued, the column select 92 again does not transition, as illustrated by thesegment 128. Accordingly, data is transferred out of theregisters 64 to thedata output circuitry 68 responsive to apulse 136 of the register data out 96. A series ofpulses 138 illustrate data again being output from thedata output circuitry 68 onto data nodes (e.g., output data nodes 72). Therefore, during the series ofpulses 138, the data from thedata output circuitry 68 will be output from thestorage buffer 50 onto theoutput data nodes 72. - A
pulse 140 illustrates the readcommand 86 again being applied to thestorage buffer 50. This readcommand 86 initiates a repetition of the cycle that started with thepulse 106. After thepulse 140 is issued, the column select 92 transitions to a logic high as illustrated by apulse 142. While thepulse 142 is applied, thecolumn address 94 is set to “2” (e.g., segment 144). Therefore, data is transferred from row “0,” column “2” of thestorage buffer 50 into theregisters 64. Data is then transferred out of theregisters 64 to thedata output circuitry 68 responsive to apulse 146 of the register data out 96. A series ofpulses 148 illustrate data being output from thedata output circuitry 68 onto data nodes (e.g., output data nodes 72). Accordingly, during the series ofpulses 148, the data from thedata output circuitry 68 will be output from thestorage buffer 50 onto theoutput data nodes 72. - Furthermore, a
pulse 150 illustrates the readcommand 86 again being applied to thestorage buffer 50. After thepulse 150 is issued, the column select 92 transitions to a logic high as illustrated by apulse 152. While thepulse 152 is applied, thecolumn address 94 is set to “3” (e.g., segment 154). Therefore, data is transferred from row “0,” column “3” of thestorage buffer 50 into theregisters 64. Data is then transferred out of theregisters 64 to thedata output circuitry 68 responsive to apulse 156 of the register data out 96. A series ofpulses 158 illustrate data again being output from thedata output circuitry 68 onto data nodes (e.g., output data nodes 72). Accordingly, during the series ofpulses 158, the data from thedata output circuitry 68 will be output from thestorage buffer 50 onto theoutput data nodes 72. - A
pulse 160 illustrates the readcommand 86 again being applied to thestorage buffer 50. After thepulse 160 is issued, the column select 92 does not transition, as illustrated by asegment 162. In certain embodiments, the column select 92 may not transition for a total of two array cycle times beyond an array cycle time (e.g., approximately 3.5 ns) that includespulse 152. For example, duringsegment 162, the column select 92 may not transition for 7.0 ns after the array cycle time that includespulse 152, or 8.75 ns after thepulse 152. With the column select 92 not transitioning during thesegment 162, no data is transferred from thestorage buffer 50 into theregisters 64. Thus, during thesegment 162, theregisters 64 are able to transfer out any remaining data. Accordingly, data is transferred out of theregisters 64 to thedata output circuitry 68 responsive to apulse 164 of the register data out 96. A series ofpulses 166 illustrate data again being output from thedata output circuitry 68 onto data nodes (e.g., output data nodes 72). Therefore, during the series ofpulses 166, the data from thedata output circuitry 68 will be output from thestorage buffer 50 onto theoutput data nodes 72. - Likewise, a
pulse 168 illustrates the readcommand 86 again being applied to thestorage buffer 50. After thepulse 168 is issued, the column select 92 again does not transition, as illustrated by thesegment 162. Accordingly, data is transferred out of theregisters 64 to thedata output circuitry 68 responsive to apulse 170 of the register data out 96. A series ofpulses 172 illustrate data again being output from thedata output circuitry 68 onto data nodes (e.g., output data nodes 72). Therefore, during the series ofpulses 172, the data from thedata output circuitry 68 will be output from thestorage buffer 50 onto theoutput data nodes 72. - As described above, data may be read from the
storage buffer 50 by activating a first column select followed by activating a second column select (e.g., this may take a total of approximately 7.0 ns). Because data is retrieved from the columns at twice the rate that data is transferred out of thestorage buffer 50, no column select is applied for two array cycle times (e.g., approximately 7.0 ns). This pattern is then repeated until all data is read out of a particular word line of thestorage buffer 50. For example, the timing diagram 80 as illustrated may read out approximately 1024 bits of data over a time period of approximately 28 ns. In certain embodiments, the timing diagram 80 may represent timing for outputting only half of the data fromwordline_0 90. In such an embodiment, the timing diagram 80 may be repeated for more columns (e.g., data may be transferred from columns 4 through 7 in a similar manner as described above). As such, thestorage buffer 50 may output approximately 2048 bits of data over a time period of approximately 56 ns. Further, the same method may be repeated with each word line. Using such a method, data may be seamlessly output from thestorage buffer 50. Further, die space for thestorage buffer 50 may be minimized enabling thestorage buffer 50 to be manufactured at a lower cost than other storage buffers. - As will be appreciated, in certain embodiments (e.g., an ×4 configuration), data may be read from the
storage buffer 50 at four times the rate that data is transferred out of thestorage buffer 50. Accordingly, data may be read from thestorage buffer 50 by activating a first column select followed by activating a second column select. To transfer all of the data read out of thestorage buffer 50 during the first and second column selects, no column select may be applied for four array cycle times. Furthermore, the same pattern of reading data and delaying column selects may be applied to any type ofstorage buffer 50 configuration. - Referring now to
FIG. 5 , a flowchart of amethod 180 for retrieving (e.g., fetching) data from astorage buffer 50 is illustrated. Atblock 182, a first column select is activated during a first period of time to retrieve a first set of data. As will be appreciated, the first period of time may include the time it takes for a full array cycle, including activating and deactivating the first column select. For example, the first period of time may be approximately 3.5 ns (e.g., 1.75 ns activated and 1.75 ns deactivated). Further, the first set of data may be data including any number of bits. For example, the first set of data may include 256 bits. - Next, at
block 184, a second column select is activated during a second period of time to retrieve a second set of data. Again, as will be appreciated, the second period of time may include the time it takes for a full array cycle, including activating and deactivating the second column select. For example, the second period of time may be approximately 3.5 ns (e.g., 1.75 ns activated and 1.75 ns deactivated). Further, the second set of data may be data including any number of bits. For example, the second set of data may include 256 bits. - Then, at
block 186, activation of a column select is delayed during a third period of time to inhibit additional data retrieval (e.g., to allow the first and second sets of data to be output from the storage buffer 50). It should be noted that the third period of time may be substantially the same as a sum of the first period of time and the second period of time. For example, if the first period of time is approximately 3.5 ns and the second period of time is approximately 3.5 ns, the third period of time may be approximately 7.0 ns. - At
block 188, a third column select is activated during a fourth period of time to retrieve a third set of data. Next, atblock 190, a fourth column select is activated during a fifth period of time to retrieve a fourth set of data. Then, atblock 192, activation of a column select is delayed during a sixth period of time to inhibit additional data retrieval (e.g., to allow the third and fourth sets of data to be output from the storage buffer 50). - Furthermore, at
block 194, a fifth column select is activated during a seventh period of time to retrieve a fifth set of data. Next, atblock 196, a sixth column select is activated during an eighth period of time to retrieve a sixth set of data. Then, atblock 198, activation of a column select is delayed during a ninth period of time to inhibit additional data retrieval (e.g., to allow the fifth and sixth sets of data to be output from the storage buffer 50). - In addition, at
block 200, a seventh column select is activated during a tenth period of time to retrieve a seventh set of data. Next, atblock 202, an eighth column select is activated during an eleventh period of time to retrieve an eighth set of data. Then, atblock 204, activation of a column select is delayed during a twelfth period of time to inhibit additional data retrieval (e.g., to allow the seventh and eighth sets of data to be output from the storage buffer 50). - As will be appreciated, a sum of the twelve periods of time may be a total time that it takes to retrieve all of the data from a word line (e.g., wordline_0 90). In certain embodiments, the sum of the twelve periods of time may be approximately 56 ns. In other embodiments, the sum of the twelve period of time may be less than or greater than 56 ns. When data is retrieved from the word line, the
storage buffer 50 may be precharged during a period of time (e.g., to be ready to retrieve data from another word line). Further, some embodiments, may only includeblocks 182 through 186, while other embodiments may only includeblocks 182 through 192. It should be noted that themethod 180 may include fewer or more blocks than illustrated. - Using the
method 180 described above, data may be retrieved from thestorage buffer 50 at a retrieval rate that is greater than the output rate of thestorage buffer 50. As such, the retrieval of data from thestorage buffer 50 may be delayed to allow the output of thestorage buffer 50 time to output the data. As will be appreciated, the ideas presented above may be applied to any mismatch between the retrieval rate and the output rate of thestorage buffer 50 in order to provide for seamless data output from thestorage buffer 50. Further, thestorage buffer 50 provides the seamless data output with few registers which allows thestorage buffer 50 to be manufactured at a lower cost than other storage buffers. - The
storage buffer 50 as described in the present application may be used in a variety of different applications. For example, thestorage buffer 50 may be used in astate machine engine 206 illustrated inFIG. 6 , which may operate under control of theprocessor 12 ofFIG. 1 . Thestate machine engine 206 may employ any one of a number of state machine architectures, including, but not limited to Mealy architectures, Moore architectures, Finite State Machines (FSMs), Deterministic FSMs (DFSMs), Bit-Parallel State Machines (BPSMs), etc. Though a variety of architectures may be used, for discussion purposes, this application refers to FSMs. However, those skilled in the art will appreciate that the described techniques may be employed using any one of a variety of state machine architectures. - As discussed further below, the
state machine engine 206 may include a number of (e.g., one or more) finite state machine (FSM)lattices 208. EachFSM lattice 208 may include multiple FSMs that each receive and analyze the same data in parallel. Further, theFSM lattices 208 may be arranged in groups (e.g., clusters), such that clusters ofFSM lattices 208 may analyze the same input data in parallel. Further, clusters ofFSM lattices 208 of thestate machine engine 206 may be arranged in a hierarchical structure wherein outputs fromstate machine lattices 208 on a lower level of the hierarchical structure may be used as inputs tostate machine lattices 208 on a higher level. By cascading clusters ofparallel FSM lattices 208 of thestate machine engine 206 in series through the hierarchical structure, increasingly complex patterns may be analyzed (e.g., evaluated, searched, etc.). - Further, based on the hierarchical parallel configuration of the
state machine engine 206, thestate machine engine 206 can be employed for pattern recognition in systems that utilize high processing speeds. For instance, embodiments described herein may be incorporated in systems with processing speeds of 1 GByte/sec. Accordingly, utilizing thestate machine engine 206, data from high speed memory devices or other external devices may be rapidly analyzed for various patterns. Thestate machine engine 206 may analyze a data stream according to several criteria, and their respective search terms, at about the same time, e.g., during a single device cycle. Each of theFSM lattices 208 within a cluster of FSMs on a level of thestate machine engine 206 may each receive the same search term from the data stream at about the same time, and each of theparallel FSM lattices 208 may determine whether the term advances thestate machine engine 206 to the next state in the processing criterion. Thestate machine engine 206 may analyze terms according to a relatively large number of criteria, e.g., more than 100, more than 110, or more than 10,000. Because they operate in parallel, they may apply the criteria to a data stream having a relatively high bandwidth, e.g., a data stream of greater than or generally equal to 1 GByte/sec, without slowing the data stream. - In one embodiment, the
state machine engine 206 may be configured to recognize (e.g., detect) a great number of patterns in a data stream. For instance, thestate machine engine 206 may be utilized to detect a pattern in one or more of a variety of types of data streams that a user or other entity might wish to analyze. For example, thestate machine engine 206 may be configured to analyze a stream of data received over a network, such as packets received over the Internet or voice or data received over a cellular network. In one example, thestate machine engine 206 may be configured to analyze a data stream for spam or malware. The data stream may be received as a serial data stream, in which the data is received in an order that has meaning, such as in a temporally, lexically, or semantically significant order. Alternatively, the data stream may be received in parallel or out of order and, then, converted into a serial data stream, e.g., by reordering packets received over the Internet. In some embodiments, the data stream may present terms serially, but the bits expressing each of the terms may be received in parallel. The data stream may be received from a source external to thesystem 10, or may be formed by interrogating a memory device, such as thevolatile memory 26 ornon-volatile memory 28, and forming the data stream from data stored in thememory state machine engine 206 may be configured to recognize a sequence of characters that spell a certain word, a sequence of genetic base pairs that specify a gene, a sequence of bits in a picture or video file that form a portion of an image, a sequence of bits in an executable file that form a part of a program, or a sequence of bits in an audio file that form a part of a song or a spoken phrase. The stream of data to be analyzed may include multiple bits of data in a binary format or other formats, e.g., base ten, ASCII, etc. The stream may encode the data with a single digit or multiple digits, e.g., several binary digits. - In an example, the
FSM lattice 208 comprises an array of blocks. Each block may include a plurality of selectively couple-able hardware elements (e.g., programmable elements and/or special purpose elements) that correspond to a plurality of states in a FSM. Similar to a state in a FSM, a hardware element can analyze an input stream and activate a downstream hardware element, based on the input stream. - The programmable elements can be programmed to implement many different functions. For instance, the programmable elements may include state machine elements (SMEs) that are hierarchically organized into rows and blocks. To route signals between the hierarchically organized SMEs, a hierarchy of programmable switching elements can be used, including inter-block switching elements, intra-block switching elements, and intra-row switching elements. The switching elements may include routing structures and buffers. An SME can correspond to a state of a FSM implemented by the
FSM lattice 208. Accordingly, a FSM can be implemented on theFSM lattice 208 by programming the SMEs to correspond to the functions of states and by selectively coupling together the SMEs to correspond to the transitions between states in the FSM. - As previously described, the
state machine engine 206 is configured to receive data from a source, such as thevolatile memory 26 and/or the non-volatile 28, over a data bus. In the illustrated embodiment, data may be sent to thestate machine engine 206 through a bus interface, such as aDDR3 bus interface 210. TheDDR3 bus interface 210 may be capable of exchanging data at a rate greater than or equal to 1 GByte/sec. As will be appreciated, depending on the source of the data to be analyzed, thebus interface 210 may be any suitable bus interface for exchanging data to and from a data source to thestate machine engine 206, such as a NAND Flash interface, PCI interface, etc. As previously described, thestate machine engine 206 includes one ormore FSM lattices 208 configured to analyze data. EachFSM lattice 208 may be divided into two half-lattices. In the illustrated embodiment, each half lattice may include 24K SMEs, such that thelattice 208 includes 48K SMEs. Thelattice 208 may comprise any desirable number of SMEs. Further, while only oneFSM lattice 208 is illustrated, thestate machine engine 206 may includemultiple FSM lattices 208, as previously described. - Data to be analyzed may be received at the
bus interface 210 and transmitted to theFSM lattice 208 through a number of buffers and buffer interfaces. In the illustrated embodiment, the data path includes data buffers 212, process buffers 214 and an inter-rank (IR) bus andprocess buffer interface 216. The data buffers 212 are configured to receive and temporarily store data to be analyzed. In one embodiment, there are two data buffers 212 (data buffer A and data buffer B). Data may be stored in one of the twodata buffers 212, while data is being emptied from theother data buffer 212, for analysis by theFSM lattice 208. In the illustrated embodiment, the data buffers 212 may be 32 KBytes each. The IR bus andprocess buffer interface 216 may facilitate the transfer of data to theprocess buffer 214. The IR bus andprocess buffer 216 ensures that data is processed by theFSM lattice 208 in order. The IR bus andprocess buffer 216 may coordinate the exchange of data, timing information, packing instructions, etc. such that data is received and analyzed in the correct order. Generally, the IR bus andprocess buffer 216 allows the analyzing of multiple data sets in parallel through logical ranks ofFSM lattices 208. - In the illustrated embodiment, the
state machine engine 206 also includes a de-compressor 218 and acompressor 220 to aid in the transfer of the large amounts of data through thestate machine engine 206. Thecompressor 220 and de-compressor 218 work in conjunction such that data can be compressed to minimize the data transfer times. By compressing the data to be analyzed, the bus utilization time may be minimized. In certain embodiments, a mask may be provided to thestate machine engine 206 to provide information on which state machines are likely to be unused. Thecompressor 220 and de-compressor 218 can also be configured to handle data of varying burst lengths. By padding compressed data and including an indicator as to when each compressed region ends, thecompressor 220 may improve the overall processing speed through thestate machine engine 206. Thecompressor 220 and de-compressor 218 may also be used to compress and decompress match results data after analysis by theFSM lattice 208. - As previously described, the output of the
FSM lattice 208 can comprise a state vector. The state vector comprises the state (e.g., activated or not activated) of programmable elements of theFSM lattice 208. Each state vector may be temporarily stored in the statevector cache memory 222 for further hierarchical processing and analysis. That is, the state of each state machine may be stored, such that the final state may be used in further analysis, while freeing the state machines for reprogramming and/or further analysis of a new data set. Like a typical cache, the statevector cache memory 222 allows storage of information, here state vectors, for quick retrieval and use, here by theFSM lattice 208, for instance. Additional buffers, such as the statevector memory buffer 224, state vectorintermediate input buffer 226, and state vectorintermediate output buffer 228, may be utilized in conjunction with the statevector cache memory 222 to accommodate rapid analysis and storage of state vectors, while adhering to packet transmission protocol through thestate machine engine 206. - Once a result of interest is produced by the
FSM lattice 208, match results may be stored in a match resultsmemory 230. That is, a “match vector” indicating a match (e.g., detection of a pattern of interest) may be stored in the match resultsmemory 230. The match result can then be sent to amatch buffer 232 for transmission over thebus interface 210 to theprocessor 12, for example. As previously described, the match results may be compressed. - Additional registers and buffers may be provided in the
state machine engine 206, as well. For instance, thestate machine engine 206 may include control and status registers 234. In addition, restore and program buffers 236 may be provided for using in programming theFSM lattice 208 initially, or restoring the state of the machines in theFSM lattice 208 during analysis. Similarly, save and repair map buffers 238 may also be provided for storage of save and repair maps for setup and usage. - As described, the
state machine engine 206 includes many different buffers. As will be appreciated, any of the buffers described herein may include the features of thestorage buffer 50 described above. For example, any of the following may include features of the storage buffer 50: the data buffers 212, the process buffers 214, the statevector memory buffer 224, the state vectorintermediate input buffer 226, the state vectorintermediate output buffer 228, the match buffers 232, the restore and program buffers 236, the save and repair map buffers 238, and so forth. - While the invention may be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, it should be understood that the invention is not intended to be limited to the particular forms disclosed. Rather, the invention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the following appended claims.
Claims (30)
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US20180247682A1 (en) | 2018-08-30 |
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