US20130067203A1

US20130067203A1 - Processing device and a swizzle pattern generator

Info

Publication number: US20130067203A1
Application number: US13/618,309
Authority: US
Inventors: Moo-Kyoung CHUNG; Woong Seo; Ho-Young Kim; Soo-jung Ryu; Dong-hoon Yoo; Jin-Seok Lee; Yeon-gon Cho; Chang-Moo Kim; Seung-Hun Jin
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2011-09-14
Filing date: 2012-09-14
Publication date: 2013-03-14
Also published as: WO2013039335A1; EP2758866A1; CN103797458A; CN103797458B; KR20130029274A; US20190155601A1; JP2014530408A; US11003449B2; EP2758866A4; KR101918464B1; EP2758866B1

Abstract

A swizzle pattern generator is provided to reduce an overhead due to execution of a swizzle instruction in vector processing. The swizzle pattern generator is configured to provide swizzle patterns with respect to data sets of at least one vector register or vector processing unit. The swizzle pattern generator may be reconfigurable to generate various swizzle patterns for different vector operations.

Description

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims the benefit under 35 U.S.C. §119(a) of Korean Patent Application No. 10-2011-0092604, filed on Sep. 14, 2011, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference for all purposes.

BACKGROUND

1. Field
The following description relates to processing devices and swizzle instructions for vector operations.
2. Description of the Related Art
In recent years, processing data loads have drastically increased in many different fields, such as, multimedia, communication, and graphic applications to name but a few. Such an increase in data processing loads has had a significant effect on the performance of any number of processing devices, such as high-performance server computers, general personal computers (PCs), and even mobile devices. Typically, a processing device is required to process as much data as possible within a limited amount of time. As a result, many state-of-art processors increase the width of data processed at one time to satisfy this demand. One example, of such a processing device is a single instruction multiple data (SIMD) processor also known as a vector processor.
SIMD and vector processors excel at data processing since these processors concurrently operate on multiple data sets. When performing a vector or SIMD operation (herein after simply referred to as a “vector operation”), pieces of vector data or vector data elements are placed in a desired order. For example, a data set for a corresponding vector operation is placed in a specific vector register related to a vector processing unit performing the operation. To produce the data set, a plurality of scalar data is collected and stored as data elements in the vector register. When the data set is transferred between vector operations, data elements of the data set are rearranged in an appropriate order. In addition, data elements are also placed in an appropriate order when storing the result of the vector operation in a scalar form. In one example, a swizzle instruction is used to order or rearrange data elements of a data set for a related vector operation.
A swizzle instruction arranges a data set that has been read as input for a vector operation. Swizzle instructions also may be interposed between various instructions of vector operations. For example, the swizzle instruction may be interposed between a load instruction and a vector operation instruction to arrange data elements of a data set corresponding to the vector operation. In addition, a swizzle instruction may be interposed between vector operation instructions to rearrange the data set and allow the result of the preceding vector operation to be used by the subsequent vector operation. Moreover, a swizzle instruction may be interposed between a vector operation instruction and a store instruction to rearrange the data set and transfer the rearranged data set for output from the vector operation.
However, when a swizzle instruction is interposed between other instructions, such as a load instruction, a vector instruction, and a store instruction the performance of a processor executing the instructions may be degraded. In some cases, one or more swizzle instructions are interposed between all load, store, and vector operation instructions of the vector operation. As a result, processor performance can be significantly degraded.

SUMMARY

In another general aspect, a processing device comprises: a vector register configured to store a data set including data elements of a vector operation; a vector processing unit configured to perform the vector operation; and a swizzle pattern generator connected to the vector register and the vector processing unit configured to create a swizzle pattern with respect to the data set.
The swizzle pattern generator may be further configured to combine or change the order of the data elements of the data set to create the swizzle pattern.
The processing device may further include another vector register configured to store another data set including other data elements of the vector operation wherein the swizzle pattern generator is further connected to the another vector register and configured to combine the data elements of the data set and the other data elements of the another data set to create the swizzle pattern.
The processing device may further include another vector register configured to store another data set including other data elements of the vector operation wherein the swizzle pattern generator is further connected to the another vector register and configured to combine the data elements of the data set and the other data elements of the another data set to create the swizzle pattern and another swizzle pattern. The swizzle pattern may be input to the vector processor as a data set for the vector operation.
The swizzle pattern generator may include a swizzling network configured to create the swizzle pattern. The swizzling network may include a plurality of data lines configured to create the swizzle pattern, each data line having one end connected to an output of the vector register and another end connected to an input of the vector processing unit. Similarly, the swizzling network may include a plurality of data lines configured to create the swizzle pattern, each data line having one end connected to an output of the vector processing unit.
The swizzle pattern generator also may include a swizzled register configured to store the swizzle pattern.
In addition, the swizzling network may include a plurality of data lines configured to create the swizzle pattern, each data line including an end connected to an output of the vector processing unit and another end connected to an input of the swizzled register. Similarly, the swizzling network may include a plurality of data lines configured to create the swizzle pattern, each data line including an end connected to an output of the vector register and another end connected to an input of the swizzled register.
The swizzling network may include a plurality of data lines that are reconfigurable to create various swizzle patterns. For example, the swizzling network may include a switch including reconfigurable connections for each of the plurality of data lines configured to generate the various swizzle patterns based on the reconfigurable connections; and a switching table connected to the switch configured to store various switch connections for the reconfigurable connections for the plurality of data lines corresponding to the various swizzle patterns.
The swizzle pattern generator may be further configured to create the swizzle pattern substantially, simultaneously upon output of the data set from the vector register. Similarly, the swizzle pattern generator may be further configured to create the swizzle pattern substantially, simultaneously upon input of the data set to the vector register.
In another general aspect, a processing device comprises: a vector register configured to store a data set related to a vector operation; a vector processing unit configured to perform the vector operation; and a swizzle pattern generator connected to an output of the vector register and an input of the vector processing unit configured to combined or change an order of data elements of the data set to create a swizzle pattern as an input for the vector operation.
Another vector register may be configured to store another data set related to the vector operation, wherein the swizzle pattern generator is further connected to an output of the another vector register and is further configured to combined or change an order of data elements of the data set and the another data set to create the swizzle pattern and another second swizzle pattern as an input for the vector operation.
In another general aspect, a processing device comprises: a vector processing unit configured to perform a vector operation; a vector register configured to store a data set corresponding to a vector operation result received from the vector processing unit; a swizzling network connected to an output of the vector processing unit configured to combined or change an order of data elements of the data set to create a swizzle pattern simultaneously with storing the data set in the vector register; and a swizzled register connected to the swizzling network configured to stored the swizzle pattern.
Another vector register may be configured to store another data set corresponding to the vector operation result received from the vector processing unit and another swizzled register may be configured to store another swizzle pattern, wherein the swizzle pattern generator is further configured to combined or change an order of data elements of the data set and the another data set to create the swizzle pattern and the another second swizzle pattern.
In another general aspect, a swizzle pattern generating apparatus comprises: a first data end;
a second data end connected to an output of at least one vector register or a vector processing unit; and a swizzling network including a plurality of data connections connected to the first data end and the second data end and configured to generate swizzle patterns based on the plurality of data connections at the first data end with respect to data sets output from the at least one vector register or the vector processor.
The plurality of data connections of the swizzling network may be reconfigurable to generate various arrangements of data connections and to generate various swizzle patterns corresponding to the various arrangements of data connections.
The swizzling network may include: a reconfigurable switch configured to make the plurality of data connections from the first end to the second end to generate various swizzle patterns based on an arrangement of the data connections; and a switching table connected to the switch configured to store various arrangements of data connections from the first end to the second end for the reconfigurable switch corresponding to the various swizzle patterns.
At least one swizzled register may be connected to the first end and configured to store data elements in an order corresponding to the swizzle patterns. Similarly, at least one swizzled register connected to the first end and configured to store data elements in an order corresponding to the various swizzle patterns.
The data elements output from the swizzling network at the first end may provide at least one virtual swizzled register and swizzle patterns corresponding to an arrangement of the output data elements.
Other features and aspects may be apparent from the following detailed description, the drawings, and the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram illustrating an example of a processing device.

FIG. 2A is a diagram illustrating examples of swizzle patterns.

FIG. 2B is a diagram illustrating other examples swizzle patterns.

FIG. 3 is a diagram illustrating an example of a swizzle pattern generator.

FIG. 4 is a diagram illustrating another example of a swizzle pattern generator.

FIG. 5 is a diagram illustrating another example of a swizzle pattern generator.

FIG. 6 is a diagram illustrating an example of a processing device applied to a coarse grained array (CGA).

FIG. 7 is a diagram illustrating another example of a processing device that is applied to a CGA.

FIG. 8A is a diagram depicting an operation flow of a general processor processing two consecutive vector operations.

FIG. 8B is a diagram applying the operation flow from the example shown in FIG. 8A to a CGA.

FIG. 9A is a diagram showing an operation flow to a processor using a swizzle pattern generator.

FIG. 9B is a diagram applying the operation flow from the example shown in FIG. 9A to a CGA.

Throughout the drawings and the detailed description, unless otherwise described, the same drawing reference numerals refer to the same elements, features, and structures. The relative size and depiction of these elements may be exaggerated for clarity, illustration, and convenience.

DETAILED DESCRIPTION

The following description is provided to assist the reader in gaining a comprehensive understanding of the methods, apparatuses, and/or systems described herein. Accordingly, various changes, modifications, and equivalents of the methods, apparatuses, and/or systems described herein will be suggested to those of ordinary skill in the art. Also, descriptions of well-known functions and constructions may be omitted for increased clarity and conciseness.
FIG. 1 illustrates an example of a processing device 100. The processor device 100 may be implemented, for example, using a processor equipped with a single core, a processor equipped with multiple cores, a reconfigurable coarse grained array (CGA) machine or a very long instruction word (VLIW) machine.
Referring to FIG. 1, the processing device 100 includes a vector processing unit 101, a plurality of vector registers (e.g., vector registers 102 a, 102 b, and 102 c), and a swizzle pattern generator 103.
The vector processing unit 101 performs vector operations. For example, the vector processing unit 101 calculates the sum or product of input vectors and provides a result.
Each of the plurality of vector registers (e.g., 102 a, 102 b, and 102 c) stores a data set comprising a number of data elements that are related to a vector operation (i.e., vector data). For example, the data set may include a plurality of scalar data arranged as data elements.
The swizzle pattern generator 103 may create a swizzle pattern with respect to the data set stored by vector register 102 c. A swizzle pattern is the result of arranging the data elements of at least one data set in a desired order. For example, the swizzle pattern may be obtained by combining or changing the order of the data elements in a data set of at least one vector register (e.g., the vector register 102 c). The swizzle pattern also may be obtained by combining the data elements of a data set stored in a first vector register and the data elements of a data set stored in a second vector register (e.g., as shown in FIGS. 3 and 4, and described in further detail below). The swizzle pattern generated by the swizzle pattern generator 103 for one or more data set may be the same as or equivalent to the swizzle pattern the result from executing a swizzle instruction on the one or more of the data sets. However, the swizzle pattern generator 103 provides substantially the same result (i.e., a swizzle pattern) as executing a swizzle instruction on the one or more data sets without actually executing a swizzle instruction. As result, overhead associated with executing the swizzle instruction is reduced or eliminated thereby improving overall processing performance.
In one example, the swizzle pattern generator 103 includes a swizzled register 110 and a swizzling network 120. The swizzled register 110 may be a physical vector register as shown in FIG. 1, for example, a register having the same properties as vector registers 102 a, 102 b, and 102 c, or the swizzled register 110 may be a virtual register that does not utilize an actual storage device (as described in further detail below). As shown in FIG. 1, the swizzled register 110 is a physical or virtual vector register that stores/provides a swizzle pattern related to one or more related vector registers (e.g., vector register 102 c).
The swizzling network 120 includes a plurality of wires or data lines. Each wire or data line has at least two ends. In one example, as shown in FIG. 1, one end of the wire or data line is connected to an input of the vector register 102 c and another end is connected to the swizzled register 110. The swizzling network 120 facilitates generation of the various swizzle patterns, and the generated swizzle patterns may be stored by the swizzled register 110. For example, when data elements (e.g., x1, x2, x3, and x4) are input to the vector register 102 c having an order of x1, x2, x3, x4, upon inputting the data elements to the vector register, a swizzle pattern (e.g., a data set arranged in the order of x3, x2, x4, x1) may be generated by the swizzling network 120 (as described in further detail below) and stored by the swizzled register 110.
FIG. 1 illustrates the swizzling network 120 connected to an input of the vector register 102 c. However, this is only one example of an embodiment of a swizzling network. For example, an output of a vector register and another end connected to the swizzled register (e.g., as shown in FIG. 6 and in further detail below). In addition, FIG. 1 illustrates that the swizzle pattern generated with respect to the single data set stored in the vector register 102 c. However, this is only one example, and a swizzle pattern generated by combining data elements from two or more vector registers also may be stored in the swizzled register (e.g., as shown in FIG. 3 and in further detail below).
FIGS. 2A and 2B illustrate examples of swizzle patterns. The swizzle patterns illustrated in FIG. 2A may be generated based on a data set of a given vector register.
Referring to FIG. 2A, each of the vector registers (e.g., vr0, vr1, vr2, vr3) stores a vector data set (e.g., {a3, a2, a1, a0}, {b3, b2, b1, b0}, {c3, c2, c1, c0}, and {d3, d2, d1, d0}). In this example, each vector data set includes four data elements. Each of the swizzled registers (e.g., svr0, svr1, svr2, svr3, svr4, svr5, svr6, and svr7) stores a swizzle pattern with respect to the data set of a corresponding vector register. In other words, the swizzled registers store a result obtained by combining data elements of one vector register or a result obtained by altering the order of data elements of one vector register.
For example, the swizzled register svr0 stores a swizzle pattern “a3, a3, a2, a2” with respect to the data set {a3, a2, a1, a0} of vector register vr0. In this example, the swizzle pattern “a3, a3, a2, a2” stored by swizzled register svr0 is obtained by combining the data element a3 and the data element a2 of the vector data set {a3, a2, a1, a0} stored by the vector register vr0.
FIG. 2B illustrates other examples of swizzle patterns. The swizzle patterns illustrated in FIG. 2B are generated based on a data set of a plurality of vector registers.
Referring to FIG. 2B, each of the vector registers (e.g., vr0, vr1, vr2, vr3) stores a vector data set (e.g., {a3, a2, a1, a0}, {b3, b2, b1, b0}, {c3, c2, c1, c0}, and {d3, d2, d1, d0}). In this example, each vector data set includes four data elements. Each of the swizzled registers (e.g., svr0, svr1, svr2, svr3, svr4, svr5, svr6, and svr7) stores a swizzle pattern with respect to the data sets of a plurality of the vector registers. In other words, each swizzled register stores a result obtained by combining data elements from of a plurality of data sets stored by a number of vector registers.
For example, a swizzled register svr0 stores a swizzle pattern (e.g., a3, a3, b1, b1) with respect to the data set {a3, a2, a1, a0} stored by vector register vr0 and the data set {b3, b2, b1, b0} stored by vector register vr1. In this example, the swizzle pattern “a3, a3, b1, b1” stored by the swizzled register is obtained by combining a data element a3 of the vector register vr0 and a data element b1 of the vector register vr1.
Of course, the swizzle patterns illustrated in FIGS. 2A and 2B are only some of the possible examples of possible swizzle patterns. In addition, a swizzle pattern may be defined according to a type of a running application. In addition, a predetermined number of swizzle patterns may be used.
FIG. 3 illustrates another example of a swizzle pattern generator. The swizzle pattern generator illustrated in FIG. 3 utilizes a physical storage device. Referring to FIG. 3, the swizzle pattern generator 300 includes a swizzling network 301 and a swizzle pattern storage device 302, such as swizzled registers 302 a and 302 b.
The swizzling network 301 includes a plurality of data lines or wires having at least two ends. One end of each wire is connected to an input of a vector register and another end of the wire is connected to at least one of the swizzled registers 302 a and 302 b to create a predetermined swizzle pattern based on the connections.
The swizzled registers 302 a and 302 b may be vector registers that are physically the same type of register as vector registers vr0 and vr1. For example, the swizzled registers 302 a and 302 b may be implemented using hardware, such as various flip-flops, latches, in addition to other known memory or storage devices.
As shown in FIG. 3, a first region of the swizzled register svr0 is connected to a first region of the vector register vr0 via the swizzling network 301. A second region of the swizzled register svr0 is connected to the first region of the vector register vr0 via the swizzling network 301. In a similar way, the third and fourth regions of the swizzled virtual register svr0 are connected to a second region of the vector register vr0. Accordingly, when the vector register vr0 is enabled to store a data set having an order of a3, a2, a1, and a0, substantially simultaneously a data set is stored in the swizzled register svr0 having an order (e.g., a3, a3, a2, and a2) thereby creating the swizzle pattern “a3, a3, a2, and a2” with respect to the data set {a3, a2, a1, a0} stored in the vector register vr0.
Furthermore, the swizzled register svr1 stores a swizzle pattern corresponding to a result obtained by combining data elements from the vector register vr0 and data elements from the vector register vr1. For example, a first region of the swizzled register svr1 is connected to a first region of the vector register vr0 via the swizzling network 301. A second region of the swizzled register svr1 is connected to the second region of the vector register vr0 via the swizzling network 301. In a similar way, the third and fourth regions of the swizzled register svr1 are connected to the first and third regions of the vector register vr1, respectively. Accordingly, when the vector registers vr0 and vr1 are enabled to store data sets having orders of a3, a2, a1, and a0 and b3, b2, b1, and b0, substantially simultaneously a data set is stored in the swizzled register svr1 having an order (e.g., a0, a1, b0, and b1) thereby creating a swizzle pattern “a0, a1, b0, and b1” with respect to combining the data sets {a3, a2, a1, a0} and {b3, b2, b1, b0} stored in the vector register vr0 and vr1.
Therefore, when a vector processing unit requires or needs the result an executed swizzle instruction, a swizzle pattern stored in each of the swizzled registers 302 a and 302 b may be used instead of having the vector processing unit execute the swizzle instruction. As a result, overhead due to execution of a swizzle instruction is reduced or eliminated.
FIG. 4 illustrates another example of a swizzle pattern generator. The swizzle pattern generator illustrated in FIG. 4 does not utilize a physical storage device. Referring to FIG. 4, a swizzle pattern generator 400 includes a swizzling network 401 and virtual swizzled registers 402 a and 402 b.
The swizzled network 401 includes a plurality of data lines or wires, each having at least two ends. One end of each data line is connected to an output of a vector register and another end is “connected” to at least one of the virtual swizzled registers 402 a and 402 b. Unlike the example illustrated in FIG. 3, the virtual swizzled registers 402 a and 402 b are virtual registers (e.g., indicated in FIG. 4 by dotted lines) for purpose of illustrating this example and are not actual physical storage devices or spaces. That is, each of the virtual swizzled virtual registers 402 a and 402 b is formed by the combination of wires output from the swizzling network 401 with respect to the vector registers vr0 and vr1 connected to the input of the swizzling network 401.
As shown in FIG. 4, a first region of a virtual swizzled register svr0 is “connected” to a first region of a vector register vr0 via the swizzling network 401. A second region of the virtual swizzled register svr0 is “connected” to the first region of the vector register vr0 via the swizzling network 401. In a similar manner, the third and fourth regions of the virtual swizzled register svr0 are “connected” to the second region of the vector register vr0. Accordingly, when the vector register vr0 is enabled to store a data set having an order of a3, a2, a1, and a0, substantially simultaneously a data set is “stored” by the virtual swizzled register svr0 having an order (e.g., a3, a3, a2, and a2) thereby creating the swizzle pattern “a3, a3, a2, and a2” with respect to the data set {a3, a2, a1, and a0} stored in the vector register vr0.
Furthermore, the virtual swizzled register svr1 “stores” a swizzle pattern corresponding to a result obtained by combining data elements from the vector register vr0 and data elements from the vector register vr1. For example, a first region of the virtual swizzled register svr1 is “connected” to a first region of the vector register vr0 via the swizzling network 401. A second region of the virtual swizzled register svr1 is “connected” to the second region of the vector register vr0 via the swizzling network 401. In a similar way, the third and fourth regions of the virtual swizzled register svr1 are “connected” to the first and third regions of the vector register vr1, respectively. Accordingly, when the vector registers vr0 and vr1 are enabled to store data sets having an order of a3, a2, a1, and a0 and b3, b2, b1, and b0, substantially simultaneously a data set is “stored” in the virtual swizzled register svr1 having an order (e.g., a0, a1, b0, and b1) thereby creating a swizzle pattern “a0, a1, b0, and b1” with respect to combining the data sets {a3, a2, a1, a0} and {b3, b2, b1, b0} stored in the vector register vr0 and vr1.
Therefore, when a vector processing unit requires or needs the result of an executed swizzle instruction, a swizzle pattern “stored” in each of the virtual swizzled registers 402 a and 402 b may be used instead of having the vector processing unit execute the swizzle instruction. As a result, overhead due to execution of the swizzle instruction is reduced or eliminated.
Using the swizzle patterns described above as examples, a swizzle pattern frequently used by an application may be generated by logic supplied by hardware for a swizzle pattern that has been previously defined. However, when a processor executes a number of different applications where the frequently used swizzle pattern or patterns differ among the various applications, a swizzle pattern or patterns may be defined for each application prior to the execution of the application. Therefore, reconfigurable hardware may be used to provide logic for each application. One such example is described below with regard to FIG. 5.
FIG. 5 illustrates another example of a swizzle pattern generator. The swizzle pattern generator illustrated in FIG. 5 includes a reconfigurable swizzling network including, for example, a reconfigurable switching device allowing inputs and outputs of data connections of the switching device to be reconfigured according to instructions or input received from a corresponding controller, memory or other storage device.
For example, referring to FIG. 5, a swizzle pattern generator 500 includes a reconfigurable swizzling network. The reconfigurable swizzling network includes a reconfigurable switching device 501 and a controller/storage device 502 for the switching device. The switching device 501 includes a number of lead-in lines 503 and lead-out lines 504. The switching device 501 is a device that controls the connections between the various lead-in lines 503 and the lead-out lines 504. The switching device 501 may be used to generate an arbitrary or specific swizzle pattern for each application based on the connections of the switching device.
The controller/storage device 502 stores configuration information for the switching device 501 to configure the connections between the lead-in lines 503 and the lead-out lines 504 of the switching device. Under the assumption that the number of lead-in lines is m and the number of lead-out lines is n, the switching device 501 controls m×n different connections with m+n−1 control elements.
In one example, the switching device 501 may be implemented using a crossbar switch and the controller/storage device 502 may be implemented using a switching table. When the content of the switching table is changed, the connection state (i.e., the connections between the lead-in lines and the lead out lines) of the crossbar switch is changed. As a result, the swizzle patterns generated by the swizzle pattern generator may be altered simply by changing, storing, or loading a new switching table. Therefore, a frequently used swizzle pattern for each application may be stored using the switching table so that the swizzle pattern is generated when the corresponding application is executed.
Since frequently used swizzle patterns (hereinafter, referred to as a “swizzle pattern set”) may be different by application, a reconfigurable swizzling network as shown in FIG. 5 may be used to enable a swizzled register corresponding to a swizzle pattern set for a different application. Applications using the same swizzle pattern set can share the same swizzle pattern. In addition, if swizzle patterns frequently used for one section of an application are different from swizzle patterns frequently used for other sections of the application, the application can use two or more swizzle pattern sets. In other words, in the course of executing the application, the reconfigurable swizzling network is reconfigured to generate a new swizzle pattern set. Therefore, a number of applications can share a swizzle pattern set (share a switching table), and one application can use different swizzle pattern sets (or switching tables) over time.
FIG. 6 illustrates an example an array block of a coarse grained array (CGA). In this example, the array block 600 includes inputs from a number of other array blocks (e.g., a, b, c, and d), a swizzle pattern generator 602, including a swizzling network 604 and a swizzled register file 606 (e.g., include eight swizzle patterns or registers), multiplexers (MUXs) 607 and 608, a vector processing unit (VPU) 609, and an output vector register 610. In this example, the swizzle pattern generator 602 is connected to the inputs of the CGA array block 600.
Referring to FIG. 6, inputs from a number of array blocks (e.g., arrays a, b, c, and d) are combined by the swizzle pattern generator 602 in units of data elements to form various swizzle patterns (e.g., a3, a2, b1, b1) via the swizzling network. The VPU 609 selects the inputs received from various array blocks and/or the swizzled registers as operands related to a vector operation. In FIG. 6, the VPU 609 receives a plurality of inputs to generate an output. One input selects one of the plurality of vector registers and the plurality of swizzled registers.
As shown in FIG. 6, outputs from the vector registers are inputted to the MUX 607 and 608 in an input side of the VPU 609, and are substantially simultaneously inputted to the swizzling network 604 to form swizzled registers. Outputs from the swizzled registers are inputted to the MUXs 607 and 608 in the input side of the VPU 609.
One of the vector registers and the swizzled registers is selected as an input to the VPU 609. In the example shown in FIG. 6, a swizzled register file 606 has eight swizzle registers. Outputs from all eight registers are available to the first input (left-side) of the VPU 609. In the example shown in FIG. 6, a configuration in which all vector registers and all swizzled registers can be the first inputs of the VPU 609. To simplify the drawing, the outputs from the remaining registers are represented as dots.
FIG. 7 illustrates another array block of a CGA. The array block 700 includes inputs, a vector processing unit 702, an output vector register 704, and a swizzle pattern generator 706 including a swizzling network 708 and a swizzled register file 710 (e.g., including four swizzle registers. In this example, the swizzle pattern generator is disposed between a vector register and an output of the CGA array block.
Referring to FIG. 7, it is appreciated that the output from the vector processing unit 702 is combined in units of data elements to form various swizzled patterns by the swizzle pattern generator 706. The vector register 704 stores the output from the vector processing unit 702 and the data elements stored by the vector register (e.g., x1, x3, x2, x4) may be combined to form swizzle patterns (e.g., x1, x3, x2, x4) by the swizzling network 708 of the swizzle generator 706. The swizzled virtual register file 710 may be used as an input of the corresponding array block, or may be sent to an output of the corresponding array block to be used as an input of another array block. Hereinafter, operations of the CGA blocks illustrated in FIGS. 6 and 7 are described in comparison with those of a general processor.
FIG. 8A shows an operation flow diagram of a general processor processing two consecutive vector operations. Referring to FIG. 8A, the general processor requires six cycles to process the two consecutive vector operations. In Cycle 0, a load instruction is performed to input a data set (e.g., {x1, x2, x3, x4}) from a memory to a vector register. In Cycle 1, a swizzle instruction is executed by the vector processing unit to determine a swizzle pattern (e.g., x1, x2, x3, x4) for the data set and the result is stored in the vector register. In Cycle 2, a vector operation instruction is executed by the vector processing unit and the result (e.g., y1, y2, y3, y4) is stored in the vector register. In Cycle 3, a swizzle instruction is executed by the vector processing unit to determine a swizzle pattern (e.g., y4, y3, y2, y1) which is stored in the vector register. In Cycle 4, a vector operation instruction is executed by the vector processing unit and the result (e.g., z1, z2, z3, z4) is stored in the vector register. In Cycle 5, a swizzle instruction is executed by the vector processing unit to determine a swizzle pattern (e.g., z3, z4, z1, z2) for the data set and the result is stored in the vector register. In Cycle 6, a store instruction reading the vector register is executed and the resulting data set is stored in the memory. A swizzle instruction is performed at execution of cycles 1, 3, and 5. Since the general processor executes three swizzle instructions for two vector operations, the general processor cannot consecutively perform the vector operations. As a result, the operational efficiency of the general processor decreases with the number of vector operation instructions performed.
FIG. 8B shows applying the example shown in FIG. 8A to a processor operation of a CGA. Referring to FIG. 8B, twelve array blocks of the CGA are shown.
Array Block 0 performs a load instruction from a memory for a data set (e.g., x1, x2, x3, x4) input to a vector register. Array Block 1 performs a swizzle instruction by the vector processing unit to determine a swizzle pattern (e.g., x1, x2, x3, x4) for the data set and stores the result in the vector register. Array Block 2 performs a vector operation instruction by the vector processing unit and stores the result (e.g., y1, y2, y3, y4) in the vector register. Array Block 3 performs a swizzle instruction by the vector processing unit to determine a swizzle pattern (e.g., y4, y3, y2, y1) which is stored in the vector register. Array Block 4 performs a vector operation instruction by the vector processing unit and stores the result (e.g., z1, z2, z3, z4) in the vector register. Array Block 5 performs a swizzle instruction by the vector processing unit to determine a swizzle pattern (e.g., z3, z4, z1, z2) for the data set and stores the result in the vector register. Array Block 6 performs a store instruction reading the vector register and storing the data set in the memory. Array Blocks 7-11 store a scalar register for input to the vector processing units of Array Blocks 1-5, respectively. As shown in FIG. 8B, the processor implemented by the CGA shown uses five vector processing units for two vector operations. That is, three of the five vector processing units of the array cannot perform a vector operation because they are performing a swizzle instruction instead.
FIG. 9A shows a result obtained by applying the vector operations in the example with regard to the process flow shown in FIG. 8A to a processor implementing a swizzle pattern generator including a swizzled register.
Referring to FIG. 9A, the processor uses four cycles to process the two consecutive vector operations. In cycle 0, a load instruction inputs a data set (e.g., x1, x2, x3, x4) from a memory to a vector register and a swizzle pattern (e.g., x1, x2, x3, x4) for the data set is created by the swizzle pattern generator and the swizzle pattern is stored in the swizzled register. In Cycle 1, a vector operation instruction is executed by the vector processing unit, the result (e.g., y1, y2, y3, y4) is stored in the vector register, a swizzle pattern (e.g., y4, y3, y2, y1) is created by the swizzle pattern generator, and the result is stored in the swizzled register and provided as in input for cycle 2. In Cycle 2, a vector operation instruction is executed by the vector processing unit on the output swizzle pattern, the result (e.g., z1, z2, z3, z4) is stored in the vector register, a swizzle pattern (e.g., z3, z4, z1, z2) is created by the swizzle pattern generator, and the swizzle pattern is stored in the swizzled register. In Cycle 3, a store instruction reads the swizzled register and stores a data set corresponding to the swizzle pattern in the memory.
Referring to FIG. 9A, swizzle patterns corresponding to results of executing three swizzle instructions are stored in swizzled registers, so that it is possible to simply read out a data set of the swizzled register without executing a swizzle instruction.
Comparing FIG. 8A and FIG. 9A, after a vector operation is performed at cycle 2 of FIG. 8A, a swizzle instruction is executed for a subsequent vector operation at cycle 3. In marked contrast, in FIG. 9A a vector operation is performed at cycle 1, the vector operation result is stored in a vector register, and, at the same time, a predefined swizzle pattern is created and stored in a swizzled register for output. As a result, the output of cycle 1 is suitable as an input for immediate execution of a subsequent vector operation at cycle 2. Therefore, the number of processing cycles is reduced from six to four.
Moreover, FIG. 9B illustrates a result obtained by applying the vector operations in the example with regard to the process flow shown in FIG. 8B to a processor implemented using a CGA with array blocks including a swizzle pattern generator and a swizzled register.
Referring to FIG. 9B, the CGA includes six array blocks to process the two consecutive vector operations. Array Block 0 performs a load instruction from a memory for a data set (e.g., x1, x2, x3, x4) input to a vector register and a swizzle pattern generator creates a swizzle pattern (e.g., x1, x2, x3, x4) for the data set which is stored in a swizzled register. Array Block 1 performs a vector operation instruction by the vector processing unit using the swizzle pattern read from the swizzed register of array block 0. The result (e.g., y1, y2, y3, y4) is stored in the vector register, and swizzle pattern generator creates a corresponding swizzle pattern (e.g., y4, y3, y2, y1) which is stored in the swizzled register. Array Block 2 performs a vector operation instruction by the vector processing unit using the swizzle pattern read from the swizzed register of array block 1. The result (e.g., z1, z2, z3, z4) is stored in the vector register and the swizzle pattern generator creates a corresponding swizzle pattern (e.g., z3, z4, z1, z2) which is stored in the swizzled register. Array Block 3 performs a store instruction reading the swizzled register of array block 2 and stores the data set in the memory. Array Blocks 4 and 5 store a scalar register for input to the vector processing units of Array Blocks 1 and 2, respectively, for the vector operations.
Comparing FIG. 8B and FIG. 9B, the array FIG. 9B does not require the additional vector processing units to perform swizzle instructions as shown in FIG. 8B. Therefore, the number of array blocks needed to perform the vector operations is reduced (e.g., from 13 to 5).
Therefore, according to this description, the same swizzle pattern that results from executing a swizzle instruction is simultaneously generated when a corresponding data set of a vector register is input or output without having a vector processing unit execute an actual swizzle instruction. Accordingly unnecessary overhead caused by executing swizzle instructions is reduced and processing performance is enhanced.
A number of examples have been described above. Nevertheless, it should be understood that various modifications may be made. For example, suitable results may be achieved if the described techniques are performed in a different order and/or if components in a described system, architecture, device, or circuit are combined in a different manner and/or replaced or supplemented by other components or their equivalents. Accordingly, other implementations are within the scope of the following claims.

Claims

1. A processing device comprising:

a vector register configured to store a data set including data elements of a vector operation;

a vector processing unit configured to perform the vector operation; and

a swizzle pattern generator connected to the vector register and the vector processing unit configured to create a swizzle pattern with respect to the data set.

2. The processing device of claim 1, wherein the swizzle pattern generator is further configured to combine or change the order of the data elements of the data set to create the swizzle pattern.

3. The processing device of claim 1, further comprising another vector register configured to store another data set including other data elements of the vector operation wherein the swizzle pattern generator is further connected to the another vector register and configured to combine the data elements of the data set and the other data elements of the another data set to create the swizzle pattern.

4. The processing device of claim 1, further comprising another vector register configured to store another data set including other data elements of the vector operation wherein the swizzle pattern generator is further connected to the another vector register and configured to combine the data elements of the data set and the other data elements of the another data set to create the swizzle pattern and another swizzle pattern.

5. The processing device of claim 3, wherein the swizzle pattern is input to the vector processor as a data set for the vector operation.

6. The processing device of claim 1, wherein the swizzle pattern generator includes a swizzling network configured to create the swizzle pattern.

7. The processing device of claim 6, wherein the swizzling network includes a plurality of data lines configured to create the swizzle pattern, each data line having one end connected to an output of the vector register and another end connected to an input of the vector processing unit.

8. The processing device of claim 6, wherein the swizzling network includes a plurality of data lines configured to create the swizzle pattern, each data line having one end connected to an output of the vector processing unit.

9. The processing device of claim 6, wherein the swizzle pattern generator includes a swizzled register configured to store the swizzle pattern.

10. The processing device of claim 9, wherein the swizzling network includes a plurality of data lines configured to create the swizzle pattern, each data line including an end connected to an output of the vector processing unit and another end connected to an input of the swizzled register.

11. The processing device of claim 9, wherein the swizzling network includes a plurality of data lines configured to create the swizzle pattern, each data line including an end connected to an output of the vector register and another end connected to an input of the swizzled register.

12. The processing device of claim 1, wherein the swizzle pattern generator includes a swizzled register configured to store the swizzle pattern.

13. The processing device of claim 6, wherein the swizzling network includes a plurality of data lines that are reconfigurable to create various swizzle patterns.

14. The processing device of claim 13, wherein the swizzling network includes:

a switch including reconfigurable connections for each of the plurality of data lines configured to generate the various swizzle patterns based on the reconfigurable connections; and

is a switching table connected to the switch configured to store various switch connections for the reconfigurable connections for the plurality of data lines corresponding to the various swizzle patterns.

15. The processing device of claim 1, wherein the swizzle pattern generator is further configured to create the swizzle pattern substantially, simultaneously upon output of the data set from the vector register.

16. The processing device of claim 1, wherein the swizzle pattern generator is further configured to create the swizzle pattern substantially, simultaneously upon input of the data set to the vector register.

17. A processing device comprising:

a vector register configured to store a data set related to a vector operation;

a vector processing unit configured to perform the vector operation; and

a swizzle pattern generator connected to an output of the vector register and an input of the vector processing unit configured to combined or change an order of data elements of the data set to create a swizzle pattern as an input for the vector operation.

18. The processing device of claim 17 further comprising:

another vector register configured to store another data set related to the vector operation, wherein

the swizzle pattern generator is further connected to an output of the another vector register and is further configured to combined or change an order of data elements of the data set and the another data set to create the swizzle pattern and another second swizzle pattern as an input for the vector operation.

19. A processing device comprising:

a vector processing unit configured to perform a vector operation;

a vector register configured to store a data set corresponding to a vector operation result received from the vector processing unit;

a swizzling network connected to an output of the vector processing unit configured to combined or change an order of data elements of the data set to create a swizzle pattern simultaneously with storing the data set in the vector register; and

a swizzled register connected to the swizzling network configured to store the swizzle pattern.

20. The processing device of claim 19 further comprising:

another vector register configured to store another data set corresponding to the vector operation result received from the vector processing unit;

another swizzled register configured to store another swizzle pattern, wherein

the swizzle pattern generator is further configured to combined or change an order of data elements of the data set and the another data set to create the swizzle pattern and the another second swizzle pattern.

21. A swizzle pattern generating apparatus comprising:

a first data end;

a second data end connected to an output of at least one vector register or a vector processing unit; and

a swizzling network including a plurality of data connections connected to the first data end and the second data end and configured to generate swizzle patterns based on the plurality of data connections at the first data end with respect to data sets output from the at least one vector register or the vector processor.

22. The apparatus of claim 21, wherein the plurality of data connections of the swizzling network are reconfigurable to generate various arrangements of data connections and to generate various swizzle patterns corresponding to the various arrangements of data connections.

23. The apparatus of claim 21, wherein the swizzling network includes:

a reconfigurable switch configured to make the plurality of data connections from the first end to the second end to generate various swizzle patterns based on an arrangement of the data connections; and

a switching table connected to the switch configured to store various arrangements of data connections from the first end to the second end for the reconfigurable switch corresponding to the various swizzle patterns.

24. The apparatus of claim 21, further comprising at least one swizzled register connected to the first end and configured to store data elements in an order corresponding to the swizzle patterns.

25. The apparatus of claim 22, further comprising at least one swizzled register connected to the first end and configured to store data elements in an order corresponding to the various swizzle patterns.

26. The swizzle pattern providing apparatus of claim 21, wherein data elements output from the swizzling network at the first end provide at least one virtual swizzled register and swizzle patterns corresponding to an arrangement of the output data elements.

27. The apparatus of claim 22, wherein data elements output from the swizzling network at the first end provide at least one virtual swizzled register and swizzle patterns corresponding to the arrangement of the data connections and the output data element each connection.