US20120247677A1 - Substrate processing method - Google Patents

Substrate processing method Download PDF

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Publication number
US20120247677A1
US20120247677A1 US13/434,989 US201213434989A US2012247677A1 US 20120247677 A1 US20120247677 A1 US 20120247677A1 US 201213434989 A US201213434989 A US 201213434989A US 2012247677 A1 US2012247677 A1 US 2012247677A1
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Prior art keywords
high frequency
voltage
power supply
susceptor
frequency power
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US13/434,989
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Shinji Himori
Norikazu Yamada
Ohse Takeshi
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Tokyo Electron Ltd
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Tokyo Electron Ltd
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Priority to US13/434,989 priority Critical patent/US20120247677A1/en
Assigned to TOKYO ELECTRON LIMITED reassignment TOKYO ELECTRON LIMITED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: OHSE, TAKESHI, YAMADA, NORIKAZU, HIMORI, SHINJI
Publication of US20120247677A1 publication Critical patent/US20120247677A1/en
Priority to US15/391,108 priority patent/US10032611B2/en
Abandoned legal-status Critical Current

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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05HPLASMA TECHNIQUE; PRODUCTION OF ACCELERATED ELECTRICALLY-CHARGED PARTICLES OR OF NEUTRONS; PRODUCTION OR ACCELERATION OF NEUTRAL MOLECULAR OR ATOMIC BEAMS
    • H05H1/00Generating plasma; Handling plasma
    • H05H1/24Generating plasma
    • H05H1/46Generating plasma using applied electromagnetic fields, e.g. high frequency or microwave energy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32Gas-filled discharge tubes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32Gas-filled discharge tubes
    • H01J37/32431Constructional details of the reactor
    • H01J37/32697Electrostatic control
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32Gas-filled discharge tubes
    • H01J37/32009Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32082Radio frequency generated discharge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32Gas-filled discharge tubes
    • H01J37/32009Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32082Radio frequency generated discharge
    • H01J37/32091Radio frequency generated discharge the radio frequency energy being capacitively coupled to the plasma
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32Gas-filled discharge tubes
    • H01J37/32009Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32082Radio frequency generated discharge
    • H01J37/32137Radio frequency generated discharge controlling of the discharge by modulation of energy
    • H01J37/32155Frequency modulation
    • H01J37/32165Plural frequencies
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32Gas-filled discharge tubes
    • H01J37/32431Constructional details of the reactor
    • H01J37/32697Electrostatic control
    • H01J37/32706Polarising the substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065Plasma etching; Reactive-ion etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2237/00Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
    • H01J2237/32Processing objects by plasma generation
    • H01J2237/327Arrangements for generating the plasma
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32Gas-filled discharge tubes
    • H01J37/32009Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32366Localised processing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32Gas-filled discharge tubes
    • H01J37/32431Constructional details of the reactor
    • H01J37/32623Mechanical discharge control means
    • H01J37/32642Focus rings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32Gas-filled discharge tubes
    • H01J37/32431Constructional details of the reactor
    • H01J37/32715Workpiece holder
    • H01J37/32724Temperature

Definitions

  • the present disclosure relates to a substrate processing method for performing a certain process on a substrate by using plasma.
  • a substrate processing apparatus performs a certain plasma process on a semiconductor wafer (hereinafter, referred to as simply a “wafer”) serving as a substrate by using plasma.
  • the substrate processing apparatus includes a depressurized processing chamber; a mounting table provided in the processing chamber; a HF (High Frequency) high frequency power supply configured to be connected to the mounting table and apply a high frequency voltage of a relatively high frequency (hereinafter, referred to as a “HF high frequency voltage”) to a susceptor serving as the mounting table; and a LF (Low Frequency) high frequency power supply configured to be connected to the susceptor and apply a high frequency voltage of a relatively low frequency (hereinafter, referred to as a “LF high frequency voltage”) to the susceptor.
  • HF High Frequency
  • LF Low Frequency
  • a processing gas introduced into the processing chamber is excited into plasma by applying the HF high frequency voltage.
  • a bias voltage is generated in the susceptor by applying the LF high frequency voltage.
  • a self bias is generated in the susceptor.
  • an electric potential of the susceptor is time-averaged, the electric potential has a negative value. Accordingly, ions are attracted to the susceptor by the electric potential difference.
  • etching by ions of relatively low energy is strongly isotropic.
  • Etching by ions of relatively high energy is strongly anisotropic. Accordingly, if a bias voltage is generated in a susceptor by applying the LF high frequency voltage, anisotropy in etching becomes strong even when isotropy in the etching is needed. Also, isotropy in etching becomes strong even when anisotropy in the etching is needed. As a result, a desired shape of a hole or a trench may not be formed by the etching. That is, when the bias voltage is generated in the susceptor by using the LF high frequency voltage, processing controllability in an etching process is not so good.
  • the present illustrative embodiments provide a substrate processing apparatus capable of improving the processing controllability in the etching process.
  • a substrate processing apparatus including a depressurized processing room; a mounting table that is provided in the processing room and configured to mount a substrate thereon; a first high frequency power supply configured to apply a high frequency voltage of a relatively high frequency; a second high frequency power supply configured to apply a high frequency voltage of a relatively low frequency to the mounting table; and a DC voltage applying unit configured to apply a DC voltage of a rectangle-shaped wave to the mounting table.
  • the substrate processing apparatus may further include a connection changeover switch configured to connect or disconnect the DC voltage applying unit to or from the second high frequency power supply and the mounting table.
  • the substrate processing apparatus may further include a low pass filter configured to block the high frequency voltage of the relatively high frequency applied from the first high frequency power supply.
  • the first high frequency power supply may be connected to the mounting table. Further, the low pass filter may be provided between the first high frequency power supply and the second high frequency power supply, and between the first high frequency power supply and the DC voltage applying unit.
  • the substrate processing apparatus may further include a facing electrode provided in the processing chamber to face the mounting table.
  • the first high frequency power supply may be connected to the facing electrode.
  • the relatively high frequency may be in a range of about 40 MHz to about 300 MHz.
  • the relatively low frequency may be in a range of about 380 KHz to 20 MHz.
  • a frequency of the DC voltage of the rectangle-shaped wave may be equal to or smaller than about 3 MHz.
  • a second high frequency power supply applies a high frequency voltage of a relatively low frequency to the mounting table.
  • a DC voltage applying unit applies a DC voltage of a rectangle-shaped wave to the mounting table. If a bias voltage is generated on the mounting table by applying the high frequency voltage of the relatively low frequency to the mounting table, it is possible to obtain an ion energy distribution, formed in a certain range, having a peak of relatively low energy and a peak of relatively high energy. If the bias voltage is generated on the mounting table by applying the DC voltage of the rectangle-shaped wave to the mounting table, the ion energy distribution is locally formed and has only one peak.
  • the intensity of anisotropy and the intensity of isotropy in the etching process vary depending on positions or the number of peaks in the ion energy distribution. Accordingly, by adjusting a ratio of an output value from the second high frequency power supply to an output value from the DC voltage applying unit, the intensity of anisotropy and the intensity of isotropy in the etching process can be controlled. As a result, the processing controllability in the etching process can be improved.
  • FIG. 1 is a schematic cross-sectional view showing configuration of a substrate processing apparatus in accordance with an illustrative embodiment
  • FIG. 2 is a schematic view of electric circuit of a DC voltage applying unit in FIG. 1 ;
  • FIG. 3 is an explanatory view illustrating a DC voltage of a rectangle-shaped wave applied by the DC voltage applying unit in FIG. 1 ;
  • FIG. 4 is a graph for showing an energy distribution of ions attracted to a susceptor in FIG. 1 ;
  • FIG. 5 is a schematic cross-sectional view showing configuration of a modified example of the substrate processing apparatus of FIG. 1 ;
  • FIG. 6 is a schematic cross sectional view showing configuration of a substrate processing apparatus in accordance with a second illustrative embodiment
  • FIG. 7 illustrates a modified example of a connection changeover switch in FIG. 6
  • FIG. 7(A) illustrates a modified illustrative embodiment
  • FIG. 7(B) illustrates another modified illustrative embodiment
  • FIG. 8 is a cross-sectional view schematically showing configuration of a modified example of the substrate processing apparatus in FIG. 6 ;
  • FIG. 9 is a graph for an energy distribution of ions attracted to a susceptor in a conventional substrate processing apparatus
  • FIG. 1 is a schematic configuration view of a substrate processing apparatus in accordance with an illustrative embodiment.
  • a plasma etching process is performed on a semiconductor device wafer (hereinafter, simply referred to as a “wafer”) as a substrate.
  • wafer semiconductor device wafer
  • a substrate processing apparatus 10 includes a chamber 11 for accommodating a wafer W having a diameter of, e.g., about 300 mm, and a circular column-shaped susceptor 12 (mounting table) for mounting there on the wafer W is provided within the chamber 11 .
  • a side exhaust path 13 is formed between an inner sidewall of the chamber 11 and a side surface of the susceptor 12 .
  • An exhaust plate 14 is provided at a certain portion of the side exhaust path 13 .
  • the exhaust plate 14 is a plate-shaped member having a multiple number of through holes, and the exhaust plate 14 serves as a partition plate that divides the chamber 11 into an upper part and a lower part.
  • plasma is generated in an inner space of the upper part 15 (hereinafter, referred to as “processing room”) of the chamber 11 .
  • an exhaust pipe 17 for exhausting a gas within the chamber 11 is connected to the lower portion (hereinafter, referred to as “exhaust room (manifold)”) of the chamber 11 .
  • the exhaust plate 14 confines or reflects the plasma generated within the processing room 15 so as to prevent leakage of the plasma into the manifold 16 .
  • a TMP Teurbo Molecular Pump
  • a DP Dry Pump
  • the exhaust pipe 17 evacuates and depressurizes the inside of the chamber 11 .
  • the DP depressurizes the inside of the chamber 11 to an intermediate vacuum state from an atmospheric pressure.
  • the TMP depressurizes the inside of the chamber 11 to a high vacuum state lower than the intermediate vacuum state.
  • an internal pressure of the chamber 11 is controlled by an APC valve (not shown).
  • a HF high frequency power supply 18 (first high frequency power supply) is connected to the susceptor 12 in the chamber 11 via a HF matching unit 19 .
  • the HF high frequency power supply 18 applies a high frequency voltage having a relatively high frequency (hereinafter, referred to as a “high frequency voltage for plasma generation”), e.g., about 40 MHz to about 300 MHz to the susceptor 12 .
  • a LF high frequency power supply 20 (second high frequency power supply) is connected to the susceptor 12 via an LF matching unit 21 and a low pass filter 22 .
  • the LF high frequency power supply 20 applies a high frequency voltage having a relatively low frequency (hereinafter, referred to as a “high frequency voltage for bias voltage generation”), e.g., about 380 KHz to about 20 MHz to the susceptor 12 .
  • a DC voltage applying unit 23 is connected to the susceptor 12 via the low pass filter 22 .
  • the DC voltage applying unit 23 applies a DC voltage of a rectangle-shaped wave to the susceptor 12 as described later.
  • the susceptor 12 serves as a lower electrode.
  • a wiring from the HF high frequency power supply 18 to the susceptor 12 and a wiring from the low pass filter 22 to the susceptor 12 do not intersect with each other.
  • the low pass filter 22 is provided between the HF high frequency power supply 18 and the LF high frequency power supply 20 , and between the HF high frequency power supply 18 and the DC voltage applying unit 23 , in terms of the electric circuit.
  • the HF matching unit 19 matches impedance between plasma and the HF high frequency power supply 18 so that applying efficiency of the high frequency voltage for plasma generation to the susceptor 12 is improved.
  • the LF matching unit 21 matches impedance between plasma and the LF high frequency power supply 20 so that applying efficiency of the high frequency voltage for bias voltage generation to the susceptor 12 is improved.
  • the low pass filter 22 blocks the high frequency voltage for plasma generation so as to prevent the high frequency voltage for plasma generation from being introduced into the LF high frequency power supply 20 and the DC voltage applying unit 23 .
  • a processing gas is excited by applying the high frequency voltage for plasma generation to the susceptor 12 , and plasma is generated in the processing room 15 , as described later.
  • a bias voltage is generated in the susceptor 12 by applying the high frequency voltage for bias voltage generation and the DC voltage of the rectangle-shaped wave to the susceptor 12 .
  • the bias voltage in the susceptor 12 varies in a negative range, ions of the plasma are attracted to the susceptor 12 by the electric potential difference.
  • a step-shaped portion is formed in an upper peripheral portion of the susceptor 12 such that a center portion of the susceptor 12 protrudes upward in the drawing.
  • a plate-shaped electrostatic chuck 25 made of ceramics, having an electrostatic electrode plate 24 therein is provided on the central portion of the susceptor 12 .
  • the electrostatic electrode plate 24 is connected with a DC power supply (not illustrated).
  • a positive DC voltage is applied to the electrostatic electrode plate 24
  • a negative potential is generated on a bottom surface (hereinafter, referred to as a “rear surface”) of the wafer facing the electrostatic chuck 25 .
  • the electric potential difference is generated between the electrostatic electrode plate 24 and the rear surface of the wafer W.
  • the wafer W is attracted to and held on the electrostatic chuck 25 by a Coulomb force or a Johnsen-Rahbek force generated by the electric potential difference.
  • the susceptor 12 includes therein a cooling unit (not shown) formed of a coolant path.
  • the cooling unit absorbs heat of the wafer W, of which temperature can be increased by being in contact with plasma, via the susceptor 12 . Therefore, it is possible to prevent a temperature of the wafer W from being increased higher than a desired level.
  • the susceptor 12 is made of a conductor such as aluminum in consideration of the heat transfer efficiency and a function as an electrode. However, in order to prevent the conductor from being exposed to the processing room 15 where plasma is generated, a side surface of the susceptor 12 is covered with a side surface protection member 26 made of a dielectric material such as quartz (SiO 2 ).
  • annular focus ring 27 is mounted on the step-shaped portion in the upper portion of the susceptor 12 and the side surface protection member 26 so as to surround the wafer W held on the electrostatic chuck 25 . Furthermore, a shield ring 28 is provided on the side surface protection member 26 so as to surround the focus ring 27 .
  • the focus ring 27 is made of silicon (Si) or silicon carbide (SiC). Accordingly, the plasma is distributed above the wafer W and the focus ring 27 .
  • a shower head 29 is provided at a ceiling of the chamber 11 so as to face the susceptor 12 .
  • the shower head 29 includes an upper electrode plate 30 (facing electrode) formed of a conductor having its surface covered with an insulating film or a simple substance semiconductor, e.g., silicon; a cooling plate 31 supporting the upper electrode plate 30 in a detachable manner; and a cover 32 covering the cooling plate 31 .
  • the upper electrode plate 30 is a plate-shaped member having a multiple number of gas holes 33 formed through the upper electrode plate 30 in the thickness direction, and the upper electrode plate 30 is electrically grounded. Therefore, an electric potential of the upper electrode plate 30 is a ground potential.
  • a buffer room 34 is formed in the cooling plate 31 .
  • a processing gas inlet line 35 is connected to the buffer room 34 .
  • the substrate processing apparatus 10 further includes a control unit 36 .
  • the control unit 36 controls operation of each component according to a program stored in an internal memory so as to perform a plasma etching process.
  • the control unit 36 controls an operation of each component, so that a processing gas supplied to the buffer room 34 from the processing gas inlet line 35 is introduced to the inner space of the processing room 15 ; the introduced processing gas is excited into plasma with the high frequency power for plasma generation applied to the inner space of the processing room 15 from the HF high frequency power supply 18 ; ions or radicals of the plasma are attracted toward the wafer W with the bias voltage generated in the susceptor 12 from the LF high frequency power supply 20 and the DC voltage applying unit 23 ; and a plasma etching process is performed to the wafer W.
  • FIG. 2 is a schematic view of an electric circuit of the DC voltage applying unit in FIG. 1 .
  • the DC voltage applying unit 23 has a first and second ground wirings 38 , 39 branched from the wiring 37 connected to the low pass filter 22 .
  • the first ground wiring 38 has a switching device 41 including, for example, a FET (field effect transistor), and a DC power supply 42 in this order from a branch point 37 a of the wiring 37 and a ground 40 .
  • the second ground wiring 39 has a switching device 44 including, for example, FET, between the branch point 37 a and a ground 43 .
  • the switching devices 41 , 44 are synchronized with each other to be alternatively ON/OFF. Specifically, when the switching device 41 becomes ON, the switching device 44 becomes OFF. When the switching device 44 becomes ON, the switching device 41 becomes OFF. As a result, the DC voltage applied from the DC voltage applying unit 23 shows a rectangle-shaped wave as illustrated in FIG. 3 .
  • the DC voltage applied from the DC voltage applying unit 23 shows a rectangle-shaped wave having a certain negative electric potential.
  • the rectangle-shaped wave has about ⁇ 500 V and a ground potential, alternately.
  • the DC voltage applying unit 23 controls the ON/OFF timing of the switching devices 41 , 44 to apply the DC voltage of the rectangle-shaped wave having a frequency equal to or smaller than 3 MHz to the susceptor 12 .
  • the bias voltage is generated in the susceptor 12 .
  • the susceptor is charged with a negative electric potential as described above, the bias voltage varies in the negative range. Ions of the plasma are attracted to the susceptor 12 by the electric potential difference from the negative bias voltage. In this case, since acceleration velocity of the ions varies depending on the electric potential difference, energy of the ions attracted to the susceptor 12 also varies depending on the electric potential difference from the bias voltage.
  • the bias voltage also shows a sine wave.
  • the voltage showing the sine wave times during which the voltage stays near a minimum voltage and a maximum voltage become long. Accordingly, a time during which the electric potential difference between the ions and the bias voltage is maximum becomes long, and a time during which the electric potential difference is minimum also becomes long.
  • a time during which the energy of the ions attracted to the susceptor 12 is maximum becomes long, and a time during which the energy of the ions is minimum becomes long. Accordingly, as presented by a dashed line in the graph of FIG.
  • a peak near a maximum value and a peak near a minimum value are formed. Since the bias voltage gradually varies between the maximum value and the minimum value of the sine wave, the electric potential difference between the ions and the bias voltage also gradually varies. As a result, the energy of the ions gradually also varies between the maximum value and the minimum value. As presented by the dashed line in FIG. 4 , the energy of the ions is distributed over a range between the maximum value and the minimum value.
  • the bias voltage varying in the negative range is generated in the susceptor 12 .
  • the bias voltage since the DC voltage shows the rectangle-shaped wave, the bias voltage also shows the rectangular-shaped wave.
  • the bias voltage shows the rectangle-shaped wave, there are only a maximum value and a minimum value in the bias voltage.
  • an electric potential of the maximum value in the bias voltage is controlled to be the same as the electric potential of the ions, the ions are affected only by the electric potential difference from the minimum value of the bias voltage.
  • applying the high frequency voltage for bias voltage generation from the LF high frequency power supply 20 and applying the DC voltage from the DC voltage applying unit 23 are separately performed depending on a type of the plasma etching process. Specifically, a ratio of an output value from the LF high frequency power supply 20 to an output value from the DC voltage applying unit 23 is adjusted depending on the type of the plasma etching process. For example, compared to the DC voltage, the high frequency voltage can easily reach a high voltage value. Accordingly, by increasing the electric potential difference between the bias voltage and the ions, etching by ions with high energy can be performed. Thus, if a proportion of the output value from the LF high frequency power supply 20 is increased, it is possible to etch a material difficult to be etched with ions having high energy.
  • the ion energy distribution is formed in a narrow range and has only one peak. Thus, it is possible to prevent the isotropic etching and the anisotropic etching from being performed together.
  • the position of the peak in the ion energy distribution can be changed. Thus, it is possible to allow one of the anisotropy and the isotropy to be mainly performed in the plasma etching process.
  • the LF high frequency power supply 20 applies the high frequency voltage for bias voltage generation of the sine-shaped wave to the susceptor 12 .
  • the DC voltage applying unit 23 applies the DC voltage of the rectangle-shaped wave to the susceptor 12 .
  • the ion energy distribution is locally formed and has only one peak.
  • the intensity of the anisotropy and the intensity of the isotropy in the etching process vary depending on positions or the number of the peaks in the ion energy distribution.
  • the low pass filter 22 is provided between the HF high frequency power supply 18 and the LF high frequency power supply 20 , and between the HF high frequency power supply 18 and the DC voltage applying unit 23 .
  • the low pass filter 22 prevents the high frequency voltage for plasma generation applied from the HF high frequency power supply from being introduced into the LF high frequency power supply 20 and the DC voltage applying unit 23 .
  • the LF high frequency power supply 20 and the DC voltage applying unit 23 are prevented from being damaged by the high frequency voltage for plasma generation.
  • the LF high frequency power supply 20 and the DC voltage applying unit 23 can share the low pass filter 22 . Accordingly, the electric circuit configuration in the substrate processing apparatus 10 can be simplified.
  • FIG. 5 is a cross sectional view schematically showing configuration of a modified example of the substrate processing apparatus in FIG. 1 .
  • the HF high frequency power supply 18 is connected to an upper electrode plate 30 , instead of the susceptor 12 , via the HF matching unit 19 .
  • the LF high frequency power supply 20 is connected to the susceptor 12 only via the LF matching unit 21 .
  • the DC voltage applying unit 23 is directly connected to the susceptor 12 .
  • the other configuration of the substrate processing apparatus 45 is the same as that of the substrate processing apparatus 10 .
  • components and parts corresponding to those of the substrate processing apparatus 10 are denoted with the same reference numerals as shown in the substrate processing apparatus 10 .
  • the HF high frequency power supply 18 is not connected to the susceptor 12 .
  • the high frequency voltage for plasma generation applied from the HF high frequency power supply 18 is not introduced into the LF high frequency power supply 20 and the DC voltage applying unit 23 via the susceptor 12 .
  • the electric circuit in the substrate processing apparatus 45 can be simplified.
  • FIG. 6 is a cross-sectional view schematically showing configuration of a substrate processing apparatus in accordance with the illustrative embodiment.
  • the configuration of the substrate processing apparatus 46 in accordance with the illustrative embodiment is the same as that of the substrate processing apparatus 10 in FIG. 1 , except for a connection changeover switch 47 described below.
  • FIG. 6 components and parts corresponding to those of the substrate processing apparatus 10 are denoted with the same reference numerals as shown in the substrate processing apparatus 10 .
  • the DC voltage applying unit 23 is connected to the susceptor 12 .
  • the wiring 37 connected to the low pass filter 22 is grounded through the first and second ground wirings 38 and 39 . Accordingly, when the DC voltage applying unit 23 is continuously connected to the susceptor 12 , the electric potential of the susceptor 12 becomes close to the ground potential, and the electric potential difference between the electrically floating wafer W and the susceptor 12 is increased. As a result, an abnormal electric discharge may occur between the wafer W and the susceptor 12 .
  • the DC voltage applying unit 23 is connected to the LF high frequency power supply 20 via the LF matching unit 21 .
  • the high frequency voltage for bias voltage generation applied from the LF high frequency power supply 20 can be introduced into the DC voltage applying unit 23 .
  • the switching devices 41 and 44 in the DC voltage applying unit can be damaged by a high load caused by the high frequency voltage for bias voltage generation.
  • the substrate processing apparatus 46 of FIG. 6 includes a connection changeover switch 47 provided between a wiring 48 connecting the low pass filter 22 with the LF matching unit 21 and the DC voltage applying unit 23 .
  • the connection changeover switch 47 includes an opening/closing member.
  • the DC voltage applying unit 23 can be connected to and disconnected from the LF high frequency power supply 20 and the susceptor 12 by the connection changeover switch 47 .
  • the DC voltage applying unit 23 is disconnected from the LF high frequency power supply 20 and the susceptor 12 .
  • the LF high frequency power supply 20 and the susceptor 12 are connected to the DC voltage applying unit 23 .
  • the DC voltage applying unit 23 is separated from the susceptor 12 if necessary. In such case, it is possible to prevent the susceptor 12 from being close to the ground potential via the DC voltage applying unit 23 . Therefore, it is possible to prevent an abnormal electric discharge caused by the increase of the electric potential difference between the susceptor 12 and the wafer W. Furthermore, the DC voltage applying unit 23 is separated from the LF high frequency power supply 20 if necessary. In such case, it is possible to prevent the high frequency voltage for bias voltage generation from the LF high frequency power supply 20 from being introduced into the DC voltage applying unit 23 . As a result, the switching devices 41 and 44 in the DC voltage applying unit 23 are prevented from being damaged.
  • the connection changeover switch 47 is provided between the wiring 48 and the DC voltage applying unit 23 .
  • the arrangement position of the connection changeover switch is not limited thereto.
  • the substrate processing apparatus 46 may include a connection changeover switch 49 provided between the low pass filter 22 and the LF matching unit 21 and between the low pass filter 22 and the DC voltage applying unit 23 .
  • the connection changeover switch 49 may select one of connection between the low pass filter 22 and the LF high frequency power supply 20 via the LF matching unit 21 , and connection between the low pass filter 22 and the DC voltage applying unit 23 .
  • FIG. 7(A) the substrate processing apparatus 46 may include a connection changeover switch 49 provided between the low pass filter 22 and the LF matching unit 21 and between the low pass filter 22 and the DC voltage applying unit 23 .
  • the substrate processing apparatus 46 may include connection changeover switches 50 a and 50 b .
  • the connection changeover switch 50 a is provided between the low pass filter 22 and the LF matching unit 21 to control connection/disconnection between the low pass filter 22 and the LF high frequency power supply 20 via the LF matching unit 21 .
  • the connection changeover switch 50 b is provided between the low pass filter 22 and the DC voltage applying unit 23 to control connection/disconnection between the low pass filter 22 and the DC voltage applying unit 23 .
  • the HF high frequency power supply 18 may be connected to the upper electrode plate 30 , instead of the susceptor 12 , via the HF matching unit 19 .
  • the LF high frequency power supply 20 may be connected to the susceptor 12 only via the LF matching unit 21 .
  • the DC voltage applying unit 23 may be connected to the susceptor only via the connection changeover switch 47 . Accordingly, the low pass filter 22 does not need to be provided so that the electric circuit in the substrate processing apparatus 46 can be simplified.
  • the object of the illustrative embodiments can also be achieved by supplying a storage medium storing a software program for implementing the function in the aforementioned embodiments to a computer or the like, and by causing a CPU of the computer to read out and execute the program stored in the storage medium.
  • the program itself read out from the storage medium may implement the function of the aforementioned embodiments, and the illustrative embodiments may be embodied by the program and the storage medium storing the program.
  • the storage medium may include, for example, RAM, NV-RAM, a floppy (registered trademark) disk, a hard disk, a magneto-optical disk, an optical disk such as CD-ROM, CD-R, CD-RW, and DVD (DVD-ROM, DVD-RAM, DVD-RW, and DVD+RW), a magnetic tape, a nonvolatile memory card, and other ROMs.
  • the program may be supplied into the computer by downloading it from another computer (not shown) connected to the Internet, a commercial network, a local area network, or database.
  • each embodiment described above can be implemented by executing the program read by the CPU of the computer, and an OS (operation system) operated on the CPU may perform a part of actual processes in response to instructions of the program, and the function of each embodiment may be implemented by the processes.
  • OS operation system
  • the program read from the storage medium may be written in a memory of a function extension board inserted into the computer or a function extension unit connected to the computer, and a CPU of the function extension board or the function extension unit may perform a part or all of the actual process in response to instructions of the program, and the function of each embodiment may be implemented by the process.
  • the program may include an object code, a program executable by an interpreter, script data supplied to an OS, or the like.

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Abstract

A substrate processing apparatus capable of improving a processing controllability in an etching process is provided. The substrate processing apparatus (10) includes a depressurized processing room (11); a susceptor (12) that is provided in the processing room (11) and configured to mount a wafer (W) thereon; a HF high frequency power supply (18) configured to apply a high frequency voltage for plasma generation to the susceptor (12); a LF high frequency power supply (20) configured to apply a high frequency voltage for a bias voltage generation to the susceptor (12); and a DC voltage applying unit (23) configured to apply a DC voltage of a rectangle-shaped wave to the susceptor (12).

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • This application claims the benefit of Japanese Patent Application No. 2011-079733 filed on Mar. 31, 2011, and U.S. Provisional Application Ser. No. 61/477,634 on Apr. 21, 2011, the entire disclosures of which are incorporated herein by reference.
  • FIELD OF THE INVENTION
  • The present disclosure relates to a substrate processing method for performing a certain process on a substrate by using plasma.
  • BACKGROUND OF THE INVENTION
  • A substrate processing apparatus performs a certain plasma process on a semiconductor wafer (hereinafter, referred to as simply a “wafer”) serving as a substrate by using plasma. The substrate processing apparatus includes a depressurized processing chamber; a mounting table provided in the processing chamber; a HF (High Frequency) high frequency power supply configured to be connected to the mounting table and apply a high frequency voltage of a relatively high frequency (hereinafter, referred to as a “HF high frequency voltage”) to a susceptor serving as the mounting table; and a LF (Low Frequency) high frequency power supply configured to be connected to the susceptor and apply a high frequency voltage of a relatively low frequency (hereinafter, referred to as a “LF high frequency voltage”) to the susceptor.
  • A processing gas introduced into the processing chamber is excited into plasma by applying the HF high frequency voltage. A bias voltage is generated in the susceptor by applying the LF high frequency voltage. In this case, a self bias is generated in the susceptor. When an electric potential of the susceptor is time-averaged, the electric potential has a negative value. Accordingly, ions are attracted to the susceptor by the electric potential difference.
  • However, since the LF high frequency voltage is a sine wave, it is known that in the case where the bias voltage is generated in the susceptor by applying the LF high frequency voltage, an energy distribution of ions attracted to the susceptor has a peak value of relatively low energy and a peak value of relatively high energy, and further, has a certain range as shown in FIG. 9. (see, for example, Patent Document 1)
    • Patent Document 1: Japanese Patent Laid-Open Application No. 2009-187975 (FIG. 14)
  • However, etching by ions of relatively low energy is strongly isotropic. Etching by ions of relatively high energy is strongly anisotropic. Accordingly, if a bias voltage is generated in a susceptor by applying the LF high frequency voltage, anisotropy in etching becomes strong even when isotropy in the etching is needed. Also, isotropy in etching becomes strong even when anisotropy in the etching is needed. As a result, a desired shape of a hole or a trench may not be formed by the etching. That is, when the bias voltage is generated in the susceptor by using the LF high frequency voltage, processing controllability in an etching process is not so good.
  • The present illustrative embodiments provide a substrate processing apparatus capable of improving the processing controllability in the etching process.
  • BRIEF SUMMARY OF THE INVENTION
  • In order to achieve the present object, in accordance with one aspect of an illustrative embodiment, there is provided a substrate processing apparatus including a depressurized processing room; a mounting table that is provided in the processing room and configured to mount a substrate thereon; a first high frequency power supply configured to apply a high frequency voltage of a relatively high frequency; a second high frequency power supply configured to apply a high frequency voltage of a relatively low frequency to the mounting table; and a DC voltage applying unit configured to apply a DC voltage of a rectangle-shaped wave to the mounting table.
  • The substrate processing apparatus may further include a connection changeover switch configured to connect or disconnect the DC voltage applying unit to or from the second high frequency power supply and the mounting table.
  • The substrate processing apparatus may further include a low pass filter configured to block the high frequency voltage of the relatively high frequency applied from the first high frequency power supply. The first high frequency power supply may be connected to the mounting table. Further, the low pass filter may be provided between the first high frequency power supply and the second high frequency power supply, and between the first high frequency power supply and the DC voltage applying unit.
  • The substrate processing apparatus may further include a facing electrode provided in the processing chamber to face the mounting table. The first high frequency power supply may be connected to the facing electrode.
  • The relatively high frequency may be in a range of about 40 MHz to about 300 MHz. The relatively low frequency may be in a range of about 380 KHz to 20 MHz. A frequency of the DC voltage of the rectangle-shaped wave may be equal to or smaller than about 3 MHz.
  • In accordance with the illustrative embodiments, a second high frequency power supply applies a high frequency voltage of a relatively low frequency to the mounting table. A DC voltage applying unit applies a DC voltage of a rectangle-shaped wave to the mounting table. If a bias voltage is generated on the mounting table by applying the high frequency voltage of the relatively low frequency to the mounting table, it is possible to obtain an ion energy distribution, formed in a certain range, having a peak of relatively low energy and a peak of relatively high energy. If the bias voltage is generated on the mounting table by applying the DC voltage of the rectangle-shaped wave to the mounting table, the ion energy distribution is locally formed and has only one peak. The intensity of anisotropy and the intensity of isotropy in the etching process vary depending on positions or the number of peaks in the ion energy distribution. Accordingly, by adjusting a ratio of an output value from the second high frequency power supply to an output value from the DC voltage applying unit, the intensity of anisotropy and the intensity of isotropy in the etching process can be controlled. As a result, the processing controllability in the etching process can be improved.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • Non-limiting and non-exhaustive embodiments will be described in conjunction with the accompanying drawings. Understanding that these drawings depict only several embodiments in accordance with the disclosure and are, therefore, not to be intended to limit its scope, the disclosure will be described with specificity and detail through use of the accompanying drawings, in which:
  • FIG. 1 is a schematic cross-sectional view showing configuration of a substrate processing apparatus in accordance with an illustrative embodiment;
  • FIG. 2 is a schematic view of electric circuit of a DC voltage applying unit in FIG. 1;
  • FIG. 3 is an explanatory view illustrating a DC voltage of a rectangle-shaped wave applied by the DC voltage applying unit in FIG. 1;
  • FIG. 4 is a graph for showing an energy distribution of ions attracted to a susceptor in FIG. 1;
  • FIG. 5 is a schematic cross-sectional view showing configuration of a modified example of the substrate processing apparatus of FIG. 1;
  • FIG. 6 is a schematic cross sectional view showing configuration of a substrate processing apparatus in accordance with a second illustrative embodiment;
  • FIG. 7 illustrates a modified example of a connection changeover switch in FIG. 6, FIG. 7(A) illustrates a modified illustrative embodiment, and FIG. 7(B) illustrates another modified illustrative embodiment;
  • FIG. 8 is a cross-sectional view schematically showing configuration of a modified example of the substrate processing apparatus in FIG. 6; and
  • FIG. 9 is a graph for an energy distribution of ions attracted to a susceptor in a conventional substrate processing apparatus;
  • DETAILED DESCRIPTION OF THE INVENTION
  • Hereinafter, illustrative embodiments will be described with reference to the accompanying drawings.
  • FIG. 1 is a schematic configuration view of a substrate processing apparatus in accordance with an illustrative embodiment. In the substrate processing apparatus, a plasma etching process is performed on a semiconductor device wafer (hereinafter, simply referred to as a “wafer”) as a substrate.
  • In FIG. 1, a substrate processing apparatus 10 includes a chamber 11 for accommodating a wafer W having a diameter of, e.g., about 300 mm, and a circular column-shaped susceptor 12 (mounting table) for mounting there on the wafer W is provided within the chamber 11. In the substrate processing apparatus 10, a side exhaust path 13 is formed between an inner sidewall of the chamber 11 and a side surface of the susceptor 12. An exhaust plate 14 is provided at a certain portion of the side exhaust path 13.
  • The exhaust plate 14 is a plate-shaped member having a multiple number of through holes, and the exhaust plate 14 serves as a partition plate that divides the chamber 11 into an upper part and a lower part. As will be described later, plasma is generated in an inner space of the upper part 15 (hereinafter, referred to as “processing room”) of the chamber 11. Further, an exhaust pipe 17 for exhausting a gas within the chamber 11 is connected to the lower portion (hereinafter, referred to as “exhaust room (manifold)”) of the chamber 11. The exhaust plate 14 confines or reflects the plasma generated within the processing room 15 so as to prevent leakage of the plasma into the manifold 16.
  • A TMP (Turbo Molecular Pump) and a DP (Dry Pump) (both not shown) are connected to the exhaust pipe 17, and these pumps evacuate and depressurize the inside of the chamber 11. To be specific, the DP depressurizes the inside of the chamber 11 to an intermediate vacuum state from an atmospheric pressure. Further, in cooperation with the DP, the TMP depressurizes the inside of the chamber 11 to a high vacuum state lower than the intermediate vacuum state. Further, an internal pressure of the chamber 11 is controlled by an APC valve (not shown).
  • A HF high frequency power supply 18 (first high frequency power supply) is connected to the susceptor 12 in the chamber 11 via a HF matching unit 19. The HF high frequency power supply 18 applies a high frequency voltage having a relatively high frequency (hereinafter, referred to as a “high frequency voltage for plasma generation”), e.g., about 40 MHz to about 300 MHz to the susceptor 12. Further, a LF high frequency power supply 20 (second high frequency power supply) is connected to the susceptor 12 via an LF matching unit 21 and a low pass filter 22. The LF high frequency power supply 20 applies a high frequency voltage having a relatively low frequency (hereinafter, referred to as a “high frequency voltage for bias voltage generation”), e.g., about 380 KHz to about 20 MHz to the susceptor 12. A DC voltage applying unit 23 is connected to the susceptor 12 via the low pass filter 22. The DC voltage applying unit 23 applies a DC voltage of a rectangle-shaped wave to the susceptor 12 as described later. The susceptor 12, where the high frequency voltage and the DC voltage are applied, serves as a lower electrode. In the substrate processing apparatus 10, a wiring from the HF high frequency power supply 18 to the susceptor 12 and a wiring from the low pass filter 22 to the susceptor 12 do not intersect with each other. Thus, the low pass filter 22 is provided between the HF high frequency power supply 18 and the LF high frequency power supply 20, and between the HF high frequency power supply 18 and the DC voltage applying unit 23, in terms of the electric circuit.
  • The HF matching unit 19 matches impedance between plasma and the HF high frequency power supply 18 so that applying efficiency of the high frequency voltage for plasma generation to the susceptor 12 is improved. The LF matching unit 21 matches impedance between plasma and the LF high frequency power supply 20 so that applying efficiency of the high frequency voltage for bias voltage generation to the susceptor 12 is improved. The low pass filter 22 blocks the high frequency voltage for plasma generation so as to prevent the high frequency voltage for plasma generation from being introduced into the LF high frequency power supply 20 and the DC voltage applying unit 23.
  • A processing gas is excited by applying the high frequency voltage for plasma generation to the susceptor 12, and plasma is generated in the processing room 15, as described later. A bias voltage is generated in the susceptor 12 by applying the high frequency voltage for bias voltage generation and the DC voltage of the rectangle-shaped wave to the susceptor 12. As described above, since the bias voltage in the susceptor 12 varies in a negative range, ions of the plasma are attracted to the susceptor 12 by the electric potential difference.
  • A step-shaped portion is formed in an upper peripheral portion of the susceptor 12 such that a center portion of the susceptor 12 protrudes upward in the drawing. A plate-shaped electrostatic chuck 25, made of ceramics, having an electrostatic electrode plate 24 therein is provided on the central portion of the susceptor 12. The electrostatic electrode plate 24 is connected with a DC power supply (not illustrated). When a positive DC voltage is applied to the electrostatic electrode plate 24, a negative potential is generated on a bottom surface (hereinafter, referred to as a “rear surface”) of the wafer facing the electrostatic chuck 25. As a result, the electric potential difference is generated between the electrostatic electrode plate 24 and the rear surface of the wafer W. The wafer W is attracted to and held on the electrostatic chuck 25 by a Coulomb force or a Johnsen-Rahbek force generated by the electric potential difference.
  • The susceptor 12 includes therein a cooling unit (not shown) formed of a coolant path. The cooling unit absorbs heat of the wafer W, of which temperature can be increased by being in contact with plasma, via the susceptor 12. Therefore, it is possible to prevent a temperature of the wafer W from being increased higher than a desired level.
  • The susceptor 12 is made of a conductor such as aluminum in consideration of the heat transfer efficiency and a function as an electrode. However, in order to prevent the conductor from being exposed to the processing room 15 where plasma is generated, a side surface of the susceptor 12 is covered with a side surface protection member 26 made of a dielectric material such as quartz (SiO2).
  • Further, an annular focus ring 27 is mounted on the step-shaped portion in the upper portion of the susceptor 12 and the side surface protection member 26 so as to surround the wafer W held on the electrostatic chuck 25. Furthermore, a shield ring 28 is provided on the side surface protection member 26 so as to surround the focus ring 27. The focus ring 27 is made of silicon (Si) or silicon carbide (SiC). Accordingly, the plasma is distributed above the wafer W and the focus ring 27.
  • A shower head 29 is provided at a ceiling of the chamber 11 so as to face the susceptor 12. The shower head 29 includes an upper electrode plate 30 (facing electrode) formed of a conductor having its surface covered with an insulating film or a simple substance semiconductor, e.g., silicon; a cooling plate 31 supporting the upper electrode plate 30 in a detachable manner; and a cover 32 covering the cooling plate 31. The upper electrode plate 30 is a plate-shaped member having a multiple number of gas holes 33 formed through the upper electrode plate 30 in the thickness direction, and the upper electrode plate 30 is electrically grounded. Therefore, an electric potential of the upper electrode plate 30 is a ground potential. A buffer room 34 is formed in the cooling plate 31. A processing gas inlet line 35 is connected to the buffer room 34.
  • The substrate processing apparatus 10 further includes a control unit 36. The control unit 36 controls operation of each component according to a program stored in an internal memory so as to perform a plasma etching process. To be Specific, the control unit 36 controls an operation of each component, so that a processing gas supplied to the buffer room 34 from the processing gas inlet line 35 is introduced to the inner space of the processing room 15; the introduced processing gas is excited into plasma with the high frequency power for plasma generation applied to the inner space of the processing room 15 from the HF high frequency power supply 18; ions or radicals of the plasma are attracted toward the wafer W with the bias voltage generated in the susceptor 12 from the LF high frequency power supply 20 and the DC voltage applying unit 23; and a plasma etching process is performed to the wafer W.
  • FIG. 2 is a schematic view of an electric circuit of the DC voltage applying unit in FIG. 1.
  • In FIG. 2, the DC voltage applying unit 23 has a first and second ground wirings 38, 39 branched from the wiring 37 connected to the low pass filter 22. The first ground wiring 38 has a switching device 41 including, for example, a FET (field effect transistor), and a DC power supply 42 in this order from a branch point 37 a of the wiring 37 and a ground 40. The second ground wiring 39 has a switching device 44 including, for example, FET, between the branch point 37 a and a ground 43.
  • In the DC voltage applying unit 23, the switching devices 41, 44 are synchronized with each other to be alternatively ON/OFF. Specifically, when the switching device 41 becomes ON, the switching device 44 becomes OFF. When the switching device 44 becomes ON, the switching device 41 becomes OFF. As a result, the DC voltage applied from the DC voltage applying unit 23 shows a rectangle-shaped wave as illustrated in FIG. 3. Here, since a cathode of the DC power supply 42 is connected to the ground wiring 38 at the branch point 37 a, the DC voltage applied from the DC voltage applying unit 23 shows a rectangle-shaped wave having a certain negative electric potential. The rectangle-shaped wave has about −500 V and a ground potential, alternately. In the substrate processing apparatus 10, the DC voltage applying unit 23 controls the ON/OFF timing of the switching devices 41, 44 to apply the DC voltage of the rectangle-shaped wave having a frequency equal to or smaller than 3 MHz to the susceptor 12.
  • However, when the high frequency voltage for bias voltage generation is applied from the LF high frequency power supply 20 to the susceptor 12, the bias voltage is generated in the susceptor 12. However, since the susceptor is charged with a negative electric potential as described above, the bias voltage varies in the negative range. Ions of the plasma are attracted to the susceptor 12 by the electric potential difference from the negative bias voltage. In this case, since acceleration velocity of the ions varies depending on the electric potential difference, energy of the ions attracted to the susceptor 12 also varies depending on the electric potential difference from the bias voltage.
  • Here, since the high frequency voltage for bias voltage generation applied from the LF high frequency power supply 20 shows a sine wave, the bias voltage also shows a sine wave. In the variation of the voltage showing the sine wave, times during which the voltage stays near a minimum voltage and a maximum voltage become long. Accordingly, a time during which the electric potential difference between the ions and the bias voltage is maximum becomes long, and a time during which the electric potential difference is minimum also becomes long. As a result, a time during which the energy of the ions attracted to the susceptor 12 is maximum becomes long, and a time during which the energy of the ions is minimum becomes long. Accordingly, as presented by a dashed line in the graph of FIG. 4, in the ion energy distribution, a peak near a maximum value and a peak near a minimum value are formed. Since the bias voltage gradually varies between the maximum value and the minimum value of the sine wave, the electric potential difference between the ions and the bias voltage also gradually varies. As a result, the energy of the ions gradually also varies between the maximum value and the minimum value. As presented by the dashed line in FIG. 4, the energy of the ions is distributed over a range between the maximum value and the minimum value.
  • When the DC voltage is applied from the DC voltage applying unit 23 to the susceptor 12, the bias voltage varying in the negative range is generated in the susceptor 12. However, since the DC voltage shows the rectangle-shaped wave, the bias voltage also shows the rectangular-shaped wave. In this case, since the bias voltage shows the rectangle-shaped wave, there are only a maximum value and a minimum value in the bias voltage. However, if an electric potential of the maximum value in the bias voltage is controlled to be the same as the electric potential of the ions, the ions are affected only by the electric potential difference from the minimum value of the bias voltage. As a result, in the energy distribution of the ions attracted to the susceptor 12, there is only a peak corresponding to the electric potential difference from the minimum value of the bias voltage, as presented by a solid line in the graph of FIG. 4. That is, when the DC voltage is applied from the DC voltage applying unit 23 to the susceptor 12, the energy distribution of ions attracted to the susceptor 12 has only one peak. Further, the energy distribution is locally formed in a narrow range.
  • In the illustrative embodiment, applying the high frequency voltage for bias voltage generation from the LF high frequency power supply 20 and applying the DC voltage from the DC voltage applying unit 23 are separately performed depending on a type of the plasma etching process. Specifically, a ratio of an output value from the LF high frequency power supply 20 to an output value from the DC voltage applying unit 23 is adjusted depending on the type of the plasma etching process. For example, compared to the DC voltage, the high frequency voltage can easily reach a high voltage value. Accordingly, by increasing the electric potential difference between the bias voltage and the ions, etching by ions with high energy can be performed. Thus, if a proportion of the output value from the LF high frequency power supply 20 is increased, it is possible to etch a material difficult to be etched with ions having high energy.
  • If a proportion of the output value from the DC voltage applying unit 23 is increased, the ion energy distribution is formed in a narrow range and has only one peak. Thus, it is possible to prevent the isotropic etching and the anisotropic etching from being performed together. By changing the minimum value of the bias voltage, the position of the peak in the ion energy distribution can be changed. Thus, it is possible to allow one of the anisotropy and the isotropy to be mainly performed in the plasma etching process.
  • In accordance with the substrate processing apparatus of the illustrative embodiment, the LF high frequency power supply 20 applies the high frequency voltage for bias voltage generation of the sine-shaped wave to the susceptor 12. The DC voltage applying unit 23 applies the DC voltage of the rectangle-shaped wave to the susceptor 12. When the bias voltage is generated in the susceptor 12 by applying the high frequency voltage for bias voltage generation to the susceptor 12, it is possible to obtain the ion energy distribution formed over the range between the maximum value and the minimum value and the ion energy distribution having a peak near the minimum value and a peak near the maximum value can be obtained. Meanwhile, when the bias voltage is generated in the susceptor 12 by applying the DC voltage of the rectangle-shaped wave to the susceptor 12, the ion energy distribution is locally formed and has only one peak. The intensity of the anisotropy and the intensity of the isotropy in the etching process vary depending on positions or the number of the peaks in the ion energy distribution. Thus, by adjusting the ratio of the output value from the LF high frequency power supply 20 to the output value from the DC voltage applying unit 23, it is possible to control the intensity of the anisotropy and the intensity of the isotropy in the etching process. As a result, the processing controllability in the etching process can be improved.
  • In the above-described substrate processing apparatus 10, the low pass filter 22 is provided between the HF high frequency power supply 18 and the LF high frequency power supply 20, and between the HF high frequency power supply 18 and the DC voltage applying unit 23. Thus, the low pass filter 22 prevents the high frequency voltage for plasma generation applied from the HF high frequency power supply from being introduced into the LF high frequency power supply 20 and the DC voltage applying unit 23. As a result, the LF high frequency power supply 20 and the DC voltage applying unit 23 are prevented from being damaged by the high frequency voltage for plasma generation. Further, the LF high frequency power supply 20 and the DC voltage applying unit 23 can share the low pass filter 22. Accordingly, the electric circuit configuration in the substrate processing apparatus 10 can be simplified.
  • FIG. 5 is a cross sectional view schematically showing configuration of a modified example of the substrate processing apparatus in FIG. 1.
  • In the substrate processing apparatus 45 of FIG. 5, the HF high frequency power supply 18 is connected to an upper electrode plate 30, instead of the susceptor 12, via the HF matching unit 19. The LF high frequency power supply 20 is connected to the susceptor 12 only via the LF matching unit 21. The DC voltage applying unit 23 is directly connected to the susceptor 12. The other configuration of the substrate processing apparatus 45 is the same as that of the substrate processing apparatus 10. In FIG. 5, components and parts corresponding to those of the substrate processing apparatus 10 are denoted with the same reference numerals as shown in the substrate processing apparatus 10.
  • In the substrate processing apparatus 45, the HF high frequency power supply 18 is not connected to the susceptor 12. Thus, the high frequency voltage for plasma generation applied from the HF high frequency power supply 18 is not introduced into the LF high frequency power supply 20 and the DC voltage applying unit 23 via the susceptor 12. Accordingly, in the substrate processing apparatus 45, it is not necessary to provide the low pass filter 22 between the susceptor 12 and the LF high frequency power supply 20 and between the susceptor 12 and the DC voltage applying unit 23. As a result, the electric circuit in the substrate processing apparatus 45 can be simplified.
  • Now, a substrate processing apparatus in accordance with a second illustrative embodiment will be described.
  • FIG. 6 is a cross-sectional view schematically showing configuration of a substrate processing apparatus in accordance with the illustrative embodiment.
  • The configuration of the substrate processing apparatus 46 in accordance with the illustrative embodiment is the same as that of the substrate processing apparatus 10 in FIG. 1, except for a connection changeover switch 47 described below. In FIG. 6, components and parts corresponding to those of the substrate processing apparatus 10 are denoted with the same reference numerals as shown in the substrate processing apparatus 10.
  • In the above-described substrate processing apparatus 10 in FIG. 1, the DC voltage applying unit 23 is connected to the susceptor 12. However, in the DC voltage applying unit 23, the wiring 37 connected to the low pass filter 22 is grounded through the first and second ground wirings 38 and 39. Accordingly, when the DC voltage applying unit 23 is continuously connected to the susceptor 12, the electric potential of the susceptor 12 becomes close to the ground potential, and the electric potential difference between the electrically floating wafer W and the susceptor 12 is increased. As a result, an abnormal electric discharge may occur between the wafer W and the susceptor 12.
  • Further, in the substrate processing apparatus 10, the DC voltage applying unit 23 is connected to the LF high frequency power supply 20 via the LF matching unit 21. Thus, the high frequency voltage for bias voltage generation applied from the LF high frequency power supply 20 can be introduced into the DC voltage applying unit 23. The switching devices 41 and 44 in the DC voltage applying unit can be damaged by a high load caused by the high frequency voltage for bias voltage generation.
  • The substrate processing apparatus 46 of FIG. 6 includes a connection changeover switch 47 provided between a wiring 48 connecting the low pass filter 22 with the LF matching unit 21 and the DC voltage applying unit 23. The connection changeover switch 47 includes an opening/closing member. The DC voltage applying unit 23 can be connected to and disconnected from the LF high frequency power supply 20 and the susceptor 12 by the connection changeover switch 47. During a plasma etching process, which does not require applying the DC voltage from the DC voltage applying unit 23, e.g., an etching process by ions with high energy, the DC voltage applying unit 23 is disconnected from the LF high frequency power supply 20 and the susceptor 12. During a plasma etching process, which requires allowing only one of the anisotropy and the isotropy to be strong, the LF high frequency power supply 20 and the susceptor 12 are connected to the DC voltage applying unit 23.
  • In the substrate processing apparatus 46, the DC voltage applying unit 23 is separated from the susceptor 12 if necessary. In such case, it is possible to prevent the susceptor 12 from being close to the ground potential via the DC voltage applying unit 23. Therefore, it is possible to prevent an abnormal electric discharge caused by the increase of the electric potential difference between the susceptor 12 and the wafer W. Furthermore, the DC voltage applying unit 23 is separated from the LF high frequency power supply 20 if necessary. In such case, it is possible to prevent the high frequency voltage for bias voltage generation from the LF high frequency power supply 20 from being introduced into the DC voltage applying unit 23. As a result, the switching devices 41 and 44 in the DC voltage applying unit 23 are prevented from being damaged.
  • In the substrate processing apparatus 46 of FIG. 6, the connection changeover switch 47 is provided between the wiring 48 and the DC voltage applying unit 23. However, the arrangement position of the connection changeover switch is not limited thereto. For example, as illustrated in FIG. 7(A), the substrate processing apparatus 46 may include a connection changeover switch 49 provided between the low pass filter 22 and the LF matching unit 21 and between the low pass filter 22 and the DC voltage applying unit 23. As a result, the connection changeover switch 49 may select one of connection between the low pass filter 22 and the LF high frequency power supply 20 via the LF matching unit 21, and connection between the low pass filter 22 and the DC voltage applying unit 23. As illustrated in FIG. 7(B), the substrate processing apparatus 46 may include connection changeover switches 50 a and 50 b. The connection changeover switch 50 a is provided between the low pass filter 22 and the LF matching unit 21 to control connection/disconnection between the low pass filter 22 and the LF high frequency power supply 20 via the LF matching unit 21. Further, the connection changeover switch 50 b is provided between the low pass filter 22 and the DC voltage applying unit 23 to control connection/disconnection between the low pass filter 22 and the DC voltage applying unit 23.
  • As illustrated in FIG. 8, the HF high frequency power supply 18 may be connected to the upper electrode plate 30, instead of the susceptor 12, via the HF matching unit 19. The LF high frequency power supply 20 may be connected to the susceptor 12 only via the LF matching unit 21. The DC voltage applying unit 23 may be connected to the susceptor only via the connection changeover switch 47. Accordingly, the low pass filter 22 does not need to be provided so that the electric circuit in the substrate processing apparatus 46 can be simplified.
  • The illustrative embodiments are described above. However, the illustrative embodiments are not limited thereto.
  • The object of the illustrative embodiments can also be achieved by supplying a storage medium storing a software program for implementing the function in the aforementioned embodiments to a computer or the like, and by causing a CPU of the computer to read out and execute the program stored in the storage medium.
  • In such a case, the program itself read out from the storage medium may implement the function of the aforementioned embodiments, and the illustrative embodiments may be embodied by the program and the storage medium storing the program.
  • If a storage medium for supplying a program can store the above-described program, the storage medium may include, for example, RAM, NV-RAM, a floppy (registered trademark) disk, a hard disk, a magneto-optical disk, an optical disk such as CD-ROM, CD-R, CD-RW, and DVD (DVD-ROM, DVD-RAM, DVD-RW, and DVD+RW), a magnetic tape, a nonvolatile memory card, and other ROMs. Alternatively, the program may be supplied into the computer by downloading it from another computer (not shown) connected to the Internet, a commercial network, a local area network, or database.
  • Further, The function of each embodiment described above can be implemented by executing the program read by the CPU of the computer, and an OS (operation system) operated on the CPU may perform a part of actual processes in response to instructions of the program, and the function of each embodiment may be implemented by the processes.
  • Further, the program read from the storage medium may be written in a memory of a function extension board inserted into the computer or a function extension unit connected to the computer, and a CPU of the function extension board or the function extension unit may perform a part or all of the actual process in response to instructions of the program, and the function of each embodiment may be implemented by the process.
  • The program may include an object code, a program executable by an interpreter, script data supplied to an OS, or the like.

Claims (5)

1. A substrate processing apparatus comprising:
a depressurized processing room;
a mounting table that is provided in the processing room and configured to mount a substrate thereon;
a first high frequency power supply configured to apply a high frequency voltage of a relatively high frequency;
a second high frequency power supply configured to apply a high frequency voltage of a relatively low frequency to the mounting table; and
a DC voltage applying unit configured to apply a DC voltage of a rectangle-shaped wave to the mounting table.
2. The substrate processing apparatus of claim 1, further comprising:
a connection changeover switch configured to connect or disconnect the DC voltage applying unit to or from the second high frequency power supply and the mounting table.
3. The substrate processing apparatus of claim 1, further comprising:
a low pass filter configured to block the high frequency voltage of the relatively high frequency applied from the first high frequency power supply,
wherein the first high frequency power supply is connected to the mounting table, and
the low pass filter is provided between the first high frequency power supply and the second high frequency power supply, and between the first high frequency power supply and the DC voltage applying unit.
4. The substrate processing apparatus of claim 1, further comprising:
a facing electrode provided in the processing chamber to face the mounting table,
wherein the first high frequency power supply is connected to the facing electrode.
5. The substrate processing apparatus of claim 1,
wherein the relatively high frequency is in a range of about 40 MHz to about 300 MHz,
the relatively low frequency is in a range of about 380 KHz to 20 MHz, and
a frequency of the DC voltage of the rectangle-shaped wave is equal to or smaller than about 3 MHz.
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Cited By (91)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160225652A1 (en) * 2015-02-03 2016-08-04 Applied Materials, Inc. Low temperature chuck for plasma processing systems
US9865484B1 (en) 2016-06-29 2018-01-09 Applied Materials, Inc. Selective etch using material modification and RF pulsing
US9881805B2 (en) 2015-03-02 2018-01-30 Applied Materials, Inc. Silicon selective removal
US9934942B1 (en) 2016-10-04 2018-04-03 Applied Materials, Inc. Chamber with flow-through source
US9947549B1 (en) 2016-10-10 2018-04-17 Applied Materials, Inc. Cobalt-containing material removal
US9966240B2 (en) 2014-10-14 2018-05-08 Applied Materials, Inc. Systems and methods for internal surface conditioning assessment in plasma processing equipment
US9978564B2 (en) 2012-09-21 2018-05-22 Applied Materials, Inc. Chemical control features in wafer process equipment
US10026621B2 (en) 2016-11-14 2018-07-17 Applied Materials, Inc. SiN spacer profile patterning
US10032606B2 (en) 2012-08-02 2018-07-24 Applied Materials, Inc. Semiconductor processing with DC assisted RF power for improved control
US10043674B1 (en) 2017-08-04 2018-08-07 Applied Materials, Inc. Germanium etching systems and methods
US10043684B1 (en) 2017-02-06 2018-08-07 Applied Materials, Inc. Self-limiting atomic thermal etching systems and methods
US10049891B1 (en) 2017-05-31 2018-08-14 Applied Materials, Inc. Selective in situ cobalt residue removal
US10062579B2 (en) 2016-10-07 2018-08-28 Applied Materials, Inc. Selective SiN lateral recess
US10062578B2 (en) 2011-03-14 2018-08-28 Applied Materials, Inc. Methods for etch of metal and metal-oxide films
US10062587B2 (en) 2012-07-18 2018-08-28 Applied Materials, Inc. Pedestal with multi-zone temperature control and multiple purge capabilities
US10062575B2 (en) 2016-09-09 2018-08-28 Applied Materials, Inc. Poly directional etch by oxidation
US10062585B2 (en) 2016-10-04 2018-08-28 Applied Materials, Inc. Oxygen compatible plasma source
US10128086B1 (en) 2017-10-24 2018-11-13 Applied Materials, Inc. Silicon pretreatment for nitride removal
US10134605B2 (en) 2013-07-11 2018-11-20 Lam Research Corporation Dual chamber plasma etcher with ion accelerator
US10147620B2 (en) 2015-08-06 2018-12-04 Applied Materials, Inc. Bolted wafer chuck thermal management systems and methods for wafer processing systems
US10163696B2 (en) 2016-11-11 2018-12-25 Applied Materials, Inc. Selective cobalt removal for bottom up gapfill
US10170336B1 (en) 2017-08-04 2019-01-01 Applied Materials, Inc. Methods for anisotropic control of selective silicon removal
US10186428B2 (en) 2016-11-11 2019-01-22 Applied Materials, Inc. Removal methods for high aspect ratio structures
US10224210B2 (en) 2014-12-09 2019-03-05 Applied Materials, Inc. Plasma processing system with direct outlet toroidal plasma source
US10224221B2 (en) 2013-04-05 2019-03-05 Lam Research Corporation Internal plasma grid for semiconductor fabrication
US10242908B2 (en) 2016-11-14 2019-03-26 Applied Materials, Inc. Airgap formation with damage-free copper
US20190096636A1 (en) * 2017-09-27 2019-03-28 Samsung Electronics Co., Ltd. Plasma processing apparatus, plasma processing method and method of manufacturing semiconductor device using the same
US10256079B2 (en) 2013-02-08 2019-04-09 Applied Materials, Inc. Semiconductor processing systems having multiple plasma configurations
US10256112B1 (en) 2017-12-08 2019-04-09 Applied Materials, Inc. Selective tungsten removal
US10283324B1 (en) 2017-10-24 2019-05-07 Applied Materials, Inc. Oxygen treatment for nitride etching
US10283321B2 (en) 2011-01-18 2019-05-07 Applied Materials, Inc. Semiconductor processing system and methods using capacitively coupled plasma
US10297458B2 (en) 2017-08-07 2019-05-21 Applied Materials, Inc. Process window widening using coated parts in plasma etch processes
US10319739B2 (en) 2017-02-08 2019-06-11 Applied Materials, Inc. Accommodating imperfectly aligned memory holes
US10319649B2 (en) 2017-04-11 2019-06-11 Applied Materials, Inc. Optical emission spectroscopy (OES) for remote plasma monitoring
US10319600B1 (en) 2018-03-12 2019-06-11 Applied Materials, Inc. Thermal silicon etch
US10354889B2 (en) 2017-07-17 2019-07-16 Applied Materials, Inc. Non-halogen etching of silicon-containing materials
US10403507B2 (en) 2017-02-03 2019-09-03 Applied Materials, Inc. Shaped etch profile with oxidation
US10424464B2 (en) 2015-08-07 2019-09-24 Applied Materials, Inc. Oxide etch selectivity systems and methods
US10424485B2 (en) 2013-03-01 2019-09-24 Applied Materials, Inc. Enhanced etching processes using remote plasma sources
US10431429B2 (en) 2017-02-03 2019-10-01 Applied Materials, Inc. Systems and methods for radial and azimuthal control of plasma uniformity
US10468276B2 (en) 2015-08-06 2019-11-05 Applied Materials, Inc. Thermal management systems and methods for wafer processing systems
US10468267B2 (en) 2017-05-31 2019-11-05 Applied Materials, Inc. Water-free etching methods
US10468285B2 (en) 2015-02-03 2019-11-05 Applied Materials, Inc. High temperature chuck for plasma processing systems
US10490406B2 (en) 2018-04-10 2019-11-26 Appled Materials, Inc. Systems and methods for material breakthrough
US10497573B2 (en) 2018-03-13 2019-12-03 Applied Materials, Inc. Selective atomic layer etching of semiconductor materials
US10504700B2 (en) 2015-08-27 2019-12-10 Applied Materials, Inc. Plasma etching systems and methods with secondary plasma injection
US10504754B2 (en) 2016-05-19 2019-12-10 Applied Materials, Inc. Systems and methods for improved semiconductor etching and component protection
US10522371B2 (en) 2016-05-19 2019-12-31 Applied Materials, Inc. Systems and methods for improved semiconductor etching and component protection
CN110718441A (en) * 2016-10-26 2020-01-21 东京毅力科创株式会社 Impedance matching method for plasma processing apparatus and plasma processing apparatus
US10541246B2 (en) 2017-06-26 2020-01-21 Applied Materials, Inc. 3D flash memory cells which discourage cross-cell electrical tunneling
US10541184B2 (en) 2017-07-11 2020-01-21 Applied Materials, Inc. Optical emission spectroscopic techniques for monitoring etching
US10546729B2 (en) 2016-10-04 2020-01-28 Applied Materials, Inc. Dual-channel showerhead with improved profile
US10566206B2 (en) 2016-12-27 2020-02-18 Applied Materials, Inc. Systems and methods for anisotropic material breakthrough
US10573496B2 (en) 2014-12-09 2020-02-25 Applied Materials, Inc. Direct outlet toroidal plasma source
US10573527B2 (en) 2018-04-06 2020-02-25 Applied Materials, Inc. Gas-phase selective etching systems and methods
US10593560B2 (en) 2018-03-01 2020-03-17 Applied Materials, Inc. Magnetic induction plasma source for semiconductor processes and equipment
US10593523B2 (en) 2014-10-14 2020-03-17 Applied Materials, Inc. Systems and methods for internal surface conditioning in plasma processing equipment
US10593519B2 (en) * 2011-12-09 2020-03-17 Tokyo Electron Limited Plasma processing apparatus
US10615047B2 (en) 2018-02-28 2020-04-07 Applied Materials, Inc. Systems and methods to form airgaps
US10615005B2 (en) * 2018-04-12 2020-04-07 Tokyo Electron Limited Plasma generating method
US10629473B2 (en) 2016-09-09 2020-04-21 Applied Materials, Inc. Footing removal for nitride spacer
US10672642B2 (en) 2018-07-24 2020-06-02 Applied Materials, Inc. Systems and methods for pedestal configuration
US10679870B2 (en) 2018-02-15 2020-06-09 Applied Materials, Inc. Semiconductor processing chamber multistage mixing apparatus
US10699879B2 (en) 2018-04-17 2020-06-30 Applied Materials, Inc. Two piece electrode assembly with gap for plasma control
US10727080B2 (en) 2017-07-07 2020-07-28 Applied Materials, Inc. Tantalum-containing material removal
US10755941B2 (en) 2018-07-06 2020-08-25 Applied Materials, Inc. Self-limiting selective etching systems and methods
US10854426B2 (en) 2018-01-08 2020-12-01 Applied Materials, Inc. Metal recess for semiconductor structures
US10872778B2 (en) 2018-07-06 2020-12-22 Applied Materials, Inc. Systems and methods utilizing solid-phase etchants
US10886137B2 (en) 2018-04-30 2021-01-05 Applied Materials, Inc. Selective nitride removal
US10892198B2 (en) 2018-09-14 2021-01-12 Applied Materials, Inc. Systems and methods for improved performance in semiconductor processing
US10903054B2 (en) 2017-12-19 2021-01-26 Applied Materials, Inc. Multi-zone gas distribution systems and methods
US10920319B2 (en) 2019-01-11 2021-02-16 Applied Materials, Inc. Ceramic showerheads with conductive electrodes
US10920320B2 (en) 2017-06-16 2021-02-16 Applied Materials, Inc. Plasma health determination in semiconductor substrate processing reactors
US10943834B2 (en) 2017-03-13 2021-03-09 Applied Materials, Inc. Replacement contact process
US10964512B2 (en) 2018-02-15 2021-03-30 Applied Materials, Inc. Semiconductor processing chamber multistage mixing apparatus and methods
US11049755B2 (en) 2018-09-14 2021-06-29 Applied Materials, Inc. Semiconductor substrate supports with embedded RF shield
US11062887B2 (en) 2018-09-17 2021-07-13 Applied Materials, Inc. High temperature RF heater pedestals
US11081318B2 (en) * 2017-12-16 2021-08-03 Applied Materials, Inc. Geometrically selective deposition of dielectric films utilizing low frequency bias
US11121002B2 (en) 2018-10-24 2021-09-14 Applied Materials, Inc. Systems and methods for etching metals and metal derivatives
US20210358716A1 (en) * 2020-05-13 2021-11-18 Tokyo Electron Limited Plasma processing apparatus and plasma processing method
US11239061B2 (en) 2014-11-26 2022-02-01 Applied Materials, Inc. Methods and systems to enhance process uniformity
US11257693B2 (en) 2015-01-09 2022-02-22 Applied Materials, Inc. Methods and systems to improve pedestal temperature control
US11276590B2 (en) 2017-05-17 2022-03-15 Applied Materials, Inc. Multi-zone semiconductor substrate supports
US11276559B2 (en) 2017-05-17 2022-03-15 Applied Materials, Inc. Semiconductor processing chamber for multiple precursor flow
US11328909B2 (en) 2017-12-22 2022-05-10 Applied Materials, Inc. Chamber conditioning and removal processes
US11417534B2 (en) 2018-09-21 2022-08-16 Applied Materials, Inc. Selective material removal
US11424105B2 (en) * 2019-08-05 2022-08-23 Hitachi High-Tech Corporation Plasma processing apparatus
US11437242B2 (en) 2018-11-27 2022-09-06 Applied Materials, Inc. Selective removal of silicon-containing materials
US11569065B2 (en) 2018-06-21 2023-01-31 Samsung Electronics Co., Ltd. Substrate processing apparatus, signal source device, method of processing material layer, and method of fabricating semiconductor device
US11682560B2 (en) 2018-10-11 2023-06-20 Applied Materials, Inc. Systems and methods for hafnium-containing film removal
US11721527B2 (en) 2019-01-07 2023-08-08 Applied Materials, Inc. Processing chamber mixing systems

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9017526B2 (en) * 2013-07-08 2015-04-28 Lam Research Corporation Ion beam etching system
KR102269344B1 (en) * 2017-07-25 2021-06-28 주식회사 원익아이피에스 Apparatus for processing substrate
JP7045152B2 (en) * 2017-08-18 2022-03-31 東京エレクトロン株式会社 Plasma processing method and plasma processing equipment
US10555412B2 (en) * 2018-05-10 2020-02-04 Applied Materials, Inc. Method of controlling ion energy distribution using a pulse generator with a current-return output stage
JP6846384B2 (en) * 2018-06-12 2021-03-24 東京エレクトロン株式会社 Method of controlling high frequency power supply of plasma processing equipment and plasma processing equipment
JP7349910B2 (en) * 2019-12-27 2023-09-25 住友重機械工業株式会社 Negative ion generation device and negative ion generation method

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4795529A (en) * 1986-10-17 1989-01-03 Hitachi, Ltd. Plasma treating method and apparatus therefor
US5665166A (en) * 1993-01-29 1997-09-09 Tokyo Electron Limited Plasma processing apparatus
US6790766B2 (en) * 2002-03-20 2004-09-14 Sanyo Electric Co., Ltd. Method of fabricating semiconductor device having low dielectric constant insulator film
US20050034674A1 (en) * 2002-03-29 2005-02-17 Tokyo Electron Limited Processing apparatus for object to be processed and processing method using same
US6863018B2 (en) * 2000-03-21 2005-03-08 Shinmaywa Industries, Ltd. Ion plating device and ion plating method
US20090194508A1 (en) * 2008-02-01 2009-08-06 Akio Ui Substrate plasma processing apparatus and plasma processing method
US20090223933A1 (en) * 2004-07-30 2009-09-10 Tokyo Electron Limited Plasma processing apparatus and method

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3445657B2 (en) 1994-06-29 2003-09-08 株式会社神戸製鋼所 ECR plasma etching method for diamond thin film
JP3799073B2 (en) 1994-11-04 2006-07-19 株式会社日立製作所 Dry etching method
CN1983518B (en) * 2004-06-21 2011-06-08 东京毅力科创株式会社 Plasma processing apparatus and method
JP4672456B2 (en) * 2004-06-21 2011-04-20 東京エレクトロン株式会社 Plasma processing equipment
US7740737B2 (en) 2004-06-21 2010-06-22 Tokyo Electron Limited Plasma processing apparatus and method
CN102184830B (en) * 2004-07-30 2012-07-25 东京毅力科创株式会社 Plasma processing apparatus and plasma processing method
CN100539000C (en) * 2004-12-03 2009-09-09 东京毅力科创株式会社 Capacitive coupling plasma processing apparatus
US7692916B2 (en) * 2005-03-31 2010-04-06 Tokyo Electron Limited Capacitive coupling plasma processing apparatus and method
JP5199595B2 (en) * 2007-03-27 2013-05-15 東京エレクトロン株式会社 Plasma processing apparatus and cleaning method thereof
KR20080111627A (en) * 2007-06-19 2008-12-24 삼성전자주식회사 Plasma processing apparatus and method thereof
JP5063520B2 (en) * 2008-08-01 2012-10-31 東京エレクトロン株式会社 Plasma processing method and plasma processing apparatus
JP5395491B2 (en) * 2009-03-31 2014-01-22 東京エレクトロン株式会社 Substrate processing apparatus and substrate processing method
KR101585893B1 (en) * 2009-05-31 2016-01-15 위순임 Compound plasma reactor

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4795529A (en) * 1986-10-17 1989-01-03 Hitachi, Ltd. Plasma treating method and apparatus therefor
US5665166A (en) * 1993-01-29 1997-09-09 Tokyo Electron Limited Plasma processing apparatus
US6863018B2 (en) * 2000-03-21 2005-03-08 Shinmaywa Industries, Ltd. Ion plating device and ion plating method
US6790766B2 (en) * 2002-03-20 2004-09-14 Sanyo Electric Co., Ltd. Method of fabricating semiconductor device having low dielectric constant insulator film
US20050034674A1 (en) * 2002-03-29 2005-02-17 Tokyo Electron Limited Processing apparatus for object to be processed and processing method using same
US20090223933A1 (en) * 2004-07-30 2009-09-10 Tokyo Electron Limited Plasma processing apparatus and method
US20090194508A1 (en) * 2008-02-01 2009-08-06 Akio Ui Substrate plasma processing apparatus and plasma processing method

Cited By (129)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10283321B2 (en) 2011-01-18 2019-05-07 Applied Materials, Inc. Semiconductor processing system and methods using capacitively coupled plasma
US10062578B2 (en) 2011-03-14 2018-08-28 Applied Materials, Inc. Methods for etch of metal and metal-oxide films
US10593519B2 (en) * 2011-12-09 2020-03-17 Tokyo Electron Limited Plasma processing apparatus
US10062587B2 (en) 2012-07-18 2018-08-28 Applied Materials, Inc. Pedestal with multi-zone temperature control and multiple purge capabilities
US10032606B2 (en) 2012-08-02 2018-07-24 Applied Materials, Inc. Semiconductor processing with DC assisted RF power for improved control
US10354843B2 (en) 2012-09-21 2019-07-16 Applied Materials, Inc. Chemical control features in wafer process equipment
US11264213B2 (en) 2012-09-21 2022-03-01 Applied Materials, Inc. Chemical control features in wafer process equipment
US9978564B2 (en) 2012-09-21 2018-05-22 Applied Materials, Inc. Chemical control features in wafer process equipment
US11024486B2 (en) 2013-02-08 2021-06-01 Applied Materials, Inc. Semiconductor processing systems having multiple plasma configurations
US10256079B2 (en) 2013-02-08 2019-04-09 Applied Materials, Inc. Semiconductor processing systems having multiple plasma configurations
US10424485B2 (en) 2013-03-01 2019-09-24 Applied Materials, Inc. Enhanced etching processes using remote plasma sources
US11171021B2 (en) 2013-04-05 2021-11-09 Lam Research Corporation Internal plasma grid for semiconductor fabrication
US10224221B2 (en) 2013-04-05 2019-03-05 Lam Research Corporation Internal plasma grid for semiconductor fabrication
US10134605B2 (en) 2013-07-11 2018-11-20 Lam Research Corporation Dual chamber plasma etcher with ion accelerator
US9966240B2 (en) 2014-10-14 2018-05-08 Applied Materials, Inc. Systems and methods for internal surface conditioning assessment in plasma processing equipment
US10593523B2 (en) 2014-10-14 2020-03-17 Applied Materials, Inc. Systems and methods for internal surface conditioning in plasma processing equipment
US10796922B2 (en) 2014-10-14 2020-10-06 Applied Materials, Inc. Systems and methods for internal surface conditioning assessment in plasma processing equipment
US10490418B2 (en) 2014-10-14 2019-11-26 Applied Materials, Inc. Systems and methods for internal surface conditioning assessment in plasma processing equipment
US10707061B2 (en) 2014-10-14 2020-07-07 Applied Materials, Inc. Systems and methods for internal surface conditioning in plasma processing equipment
US11637002B2 (en) 2014-11-26 2023-04-25 Applied Materials, Inc. Methods and systems to enhance process uniformity
US11239061B2 (en) 2014-11-26 2022-02-01 Applied Materials, Inc. Methods and systems to enhance process uniformity
US10224210B2 (en) 2014-12-09 2019-03-05 Applied Materials, Inc. Plasma processing system with direct outlet toroidal plasma source
US10573496B2 (en) 2014-12-09 2020-02-25 Applied Materials, Inc. Direct outlet toroidal plasma source
US11257693B2 (en) 2015-01-09 2022-02-22 Applied Materials, Inc. Methods and systems to improve pedestal temperature control
US10468285B2 (en) 2015-02-03 2019-11-05 Applied Materials, Inc. High temperature chuck for plasma processing systems
US11594428B2 (en) * 2015-02-03 2023-02-28 Applied Materials, Inc. Low temperature chuck for plasma processing systems
KR102553118B1 (en) * 2015-02-03 2023-07-10 어플라이드 머티어리얼스, 인코포레이티드 Cold Chuck for Plasma Processing Systems
KR20170109050A (en) * 2015-02-03 2017-09-27 어플라이드 머티어리얼스, 인코포레이티드 Low Temperature Chuck for Plasma Processing System
US20160225652A1 (en) * 2015-02-03 2016-08-04 Applied Materials, Inc. Low temperature chuck for plasma processing systems
US20170229326A1 (en) * 2015-02-03 2017-08-10 Applied Materials, Inc. Low temperature chuck for plasma processing systems
US9881805B2 (en) 2015-03-02 2018-01-30 Applied Materials, Inc. Silicon selective removal
US10607867B2 (en) 2015-08-06 2020-03-31 Applied Materials, Inc. Bolted wafer chuck thermal management systems and methods for wafer processing systems
US10147620B2 (en) 2015-08-06 2018-12-04 Applied Materials, Inc. Bolted wafer chuck thermal management systems and methods for wafer processing systems
US11158527B2 (en) 2015-08-06 2021-10-26 Applied Materials, Inc. Thermal management systems and methods for wafer processing systems
US10468276B2 (en) 2015-08-06 2019-11-05 Applied Materials, Inc. Thermal management systems and methods for wafer processing systems
US10424463B2 (en) 2015-08-07 2019-09-24 Applied Materials, Inc. Oxide etch selectivity systems and methods
US10424464B2 (en) 2015-08-07 2019-09-24 Applied Materials, Inc. Oxide etch selectivity systems and methods
US10504700B2 (en) 2015-08-27 2019-12-10 Applied Materials, Inc. Plasma etching systems and methods with secondary plasma injection
US11476093B2 (en) 2015-08-27 2022-10-18 Applied Materials, Inc. Plasma etching systems and methods with secondary plasma injection
US10522371B2 (en) 2016-05-19 2019-12-31 Applied Materials, Inc. Systems and methods for improved semiconductor etching and component protection
US10504754B2 (en) 2016-05-19 2019-12-10 Applied Materials, Inc. Systems and methods for improved semiconductor etching and component protection
US11735441B2 (en) 2016-05-19 2023-08-22 Applied Materials, Inc. Systems and methods for improved semiconductor etching and component protection
US9865484B1 (en) 2016-06-29 2018-01-09 Applied Materials, Inc. Selective etch using material modification and RF pulsing
US20180082861A1 (en) * 2016-06-29 2018-03-22 Applied Materials, Inc. Selective etch using material modification and rf pulsing
US10629473B2 (en) 2016-09-09 2020-04-21 Applied Materials, Inc. Footing removal for nitride spacer
US10062575B2 (en) 2016-09-09 2018-08-28 Applied Materials, Inc. Poly directional etch by oxidation
US11049698B2 (en) 2016-10-04 2021-06-29 Applied Materials, Inc. Dual-channel showerhead with improved profile
US10062585B2 (en) 2016-10-04 2018-08-28 Applied Materials, Inc. Oxygen compatible plasma source
US10224180B2 (en) 2016-10-04 2019-03-05 Applied Materials, Inc. Chamber with flow-through source
US9934942B1 (en) 2016-10-04 2018-04-03 Applied Materials, Inc. Chamber with flow-through source
US10546729B2 (en) 2016-10-04 2020-01-28 Applied Materials, Inc. Dual-channel showerhead with improved profile
US10541113B2 (en) 2016-10-04 2020-01-21 Applied Materials, Inc. Chamber with flow-through source
US10062579B2 (en) 2016-10-07 2018-08-28 Applied Materials, Inc. Selective SiN lateral recess
US10319603B2 (en) 2016-10-07 2019-06-11 Applied Materials, Inc. Selective SiN lateral recess
US9947549B1 (en) 2016-10-10 2018-04-17 Applied Materials, Inc. Cobalt-containing material removal
CN110718441A (en) * 2016-10-26 2020-01-21 东京毅力科创株式会社 Impedance matching method for plasma processing apparatus and plasma processing apparatus
US10186428B2 (en) 2016-11-11 2019-01-22 Applied Materials, Inc. Removal methods for high aspect ratio structures
US10770346B2 (en) 2016-11-11 2020-09-08 Applied Materials, Inc. Selective cobalt removal for bottom up gapfill
US10163696B2 (en) 2016-11-11 2018-12-25 Applied Materials, Inc. Selective cobalt removal for bottom up gapfill
US10242908B2 (en) 2016-11-14 2019-03-26 Applied Materials, Inc. Airgap formation with damage-free copper
US10600639B2 (en) 2016-11-14 2020-03-24 Applied Materials, Inc. SiN spacer profile patterning
US10026621B2 (en) 2016-11-14 2018-07-17 Applied Materials, Inc. SiN spacer profile patterning
US10566206B2 (en) 2016-12-27 2020-02-18 Applied Materials, Inc. Systems and methods for anisotropic material breakthrough
US10903052B2 (en) 2017-02-03 2021-01-26 Applied Materials, Inc. Systems and methods for radial and azimuthal control of plasma uniformity
US10403507B2 (en) 2017-02-03 2019-09-03 Applied Materials, Inc. Shaped etch profile with oxidation
US10431429B2 (en) 2017-02-03 2019-10-01 Applied Materials, Inc. Systems and methods for radial and azimuthal control of plasma uniformity
US10043684B1 (en) 2017-02-06 2018-08-07 Applied Materials, Inc. Self-limiting atomic thermal etching systems and methods
US10325923B2 (en) 2017-02-08 2019-06-18 Applied Materials, Inc. Accommodating imperfectly aligned memory holes
US10529737B2 (en) 2017-02-08 2020-01-07 Applied Materials, Inc. Accommodating imperfectly aligned memory holes
US10319739B2 (en) 2017-02-08 2019-06-11 Applied Materials, Inc. Accommodating imperfectly aligned memory holes
US10943834B2 (en) 2017-03-13 2021-03-09 Applied Materials, Inc. Replacement contact process
US10319649B2 (en) 2017-04-11 2019-06-11 Applied Materials, Inc. Optical emission spectroscopy (OES) for remote plasma monitoring
US11276590B2 (en) 2017-05-17 2022-03-15 Applied Materials, Inc. Multi-zone semiconductor substrate supports
US11276559B2 (en) 2017-05-17 2022-03-15 Applied Materials, Inc. Semiconductor processing chamber for multiple precursor flow
US11361939B2 (en) 2017-05-17 2022-06-14 Applied Materials, Inc. Semiconductor processing chamber for multiple precursor flow
US11915950B2 (en) 2017-05-17 2024-02-27 Applied Materials, Inc. Multi-zone semiconductor substrate supports
US10049891B1 (en) 2017-05-31 2018-08-14 Applied Materials, Inc. Selective in situ cobalt residue removal
US10497579B2 (en) 2017-05-31 2019-12-03 Applied Materials, Inc. Water-free etching methods
US10468267B2 (en) 2017-05-31 2019-11-05 Applied Materials, Inc. Water-free etching methods
US10920320B2 (en) 2017-06-16 2021-02-16 Applied Materials, Inc. Plasma health determination in semiconductor substrate processing reactors
US10541246B2 (en) 2017-06-26 2020-01-21 Applied Materials, Inc. 3D flash memory cells which discourage cross-cell electrical tunneling
US10727080B2 (en) 2017-07-07 2020-07-28 Applied Materials, Inc. Tantalum-containing material removal
US10541184B2 (en) 2017-07-11 2020-01-21 Applied Materials, Inc. Optical emission spectroscopic techniques for monitoring etching
US10354889B2 (en) 2017-07-17 2019-07-16 Applied Materials, Inc. Non-halogen etching of silicon-containing materials
US10043674B1 (en) 2017-08-04 2018-08-07 Applied Materials, Inc. Germanium etching systems and methods
US10593553B2 (en) 2017-08-04 2020-03-17 Applied Materials, Inc. Germanium etching systems and methods
US10170336B1 (en) 2017-08-04 2019-01-01 Applied Materials, Inc. Methods for anisotropic control of selective silicon removal
US11101136B2 (en) 2017-08-07 2021-08-24 Applied Materials, Inc. Process window widening using coated parts in plasma etch processes
US10297458B2 (en) 2017-08-07 2019-05-21 Applied Materials, Inc. Process window widening using coated parts in plasma etch processes
US20190096636A1 (en) * 2017-09-27 2019-03-28 Samsung Electronics Co., Ltd. Plasma processing apparatus, plasma processing method and method of manufacturing semiconductor device using the same
US10283324B1 (en) 2017-10-24 2019-05-07 Applied Materials, Inc. Oxygen treatment for nitride etching
US10128086B1 (en) 2017-10-24 2018-11-13 Applied Materials, Inc. Silicon pretreatment for nitride removal
US10256112B1 (en) 2017-12-08 2019-04-09 Applied Materials, Inc. Selective tungsten removal
US11081318B2 (en) * 2017-12-16 2021-08-03 Applied Materials, Inc. Geometrically selective deposition of dielectric films utilizing low frequency bias
US10903054B2 (en) 2017-12-19 2021-01-26 Applied Materials, Inc. Multi-zone gas distribution systems and methods
US11328909B2 (en) 2017-12-22 2022-05-10 Applied Materials, Inc. Chamber conditioning and removal processes
US10861676B2 (en) 2018-01-08 2020-12-08 Applied Materials, Inc. Metal recess for semiconductor structures
US10854426B2 (en) 2018-01-08 2020-12-01 Applied Materials, Inc. Metal recess for semiconductor structures
US10699921B2 (en) 2018-02-15 2020-06-30 Applied Materials, Inc. Semiconductor processing chamber multistage mixing apparatus
US10964512B2 (en) 2018-02-15 2021-03-30 Applied Materials, Inc. Semiconductor processing chamber multistage mixing apparatus and methods
US10679870B2 (en) 2018-02-15 2020-06-09 Applied Materials, Inc. Semiconductor processing chamber multistage mixing apparatus
US10615047B2 (en) 2018-02-28 2020-04-07 Applied Materials, Inc. Systems and methods to form airgaps
US10593560B2 (en) 2018-03-01 2020-03-17 Applied Materials, Inc. Magnetic induction plasma source for semiconductor processes and equipment
US11004689B2 (en) 2018-03-12 2021-05-11 Applied Materials, Inc. Thermal silicon etch
US10319600B1 (en) 2018-03-12 2019-06-11 Applied Materials, Inc. Thermal silicon etch
US10497573B2 (en) 2018-03-13 2019-12-03 Applied Materials, Inc. Selective atomic layer etching of semiconductor materials
US10573527B2 (en) 2018-04-06 2020-02-25 Applied Materials, Inc. Gas-phase selective etching systems and methods
US10490406B2 (en) 2018-04-10 2019-11-26 Appled Materials, Inc. Systems and methods for material breakthrough
US10615005B2 (en) * 2018-04-12 2020-04-07 Tokyo Electron Limited Plasma generating method
US10699879B2 (en) 2018-04-17 2020-06-30 Applied Materials, Inc. Two piece electrode assembly with gap for plasma control
US10886137B2 (en) 2018-04-30 2021-01-05 Applied Materials, Inc. Selective nitride removal
US11569065B2 (en) 2018-06-21 2023-01-31 Samsung Electronics Co., Ltd. Substrate processing apparatus, signal source device, method of processing material layer, and method of fabricating semiconductor device
US10755941B2 (en) 2018-07-06 2020-08-25 Applied Materials, Inc. Self-limiting selective etching systems and methods
US10872778B2 (en) 2018-07-06 2020-12-22 Applied Materials, Inc. Systems and methods utilizing solid-phase etchants
US10672642B2 (en) 2018-07-24 2020-06-02 Applied Materials, Inc. Systems and methods for pedestal configuration
US10892198B2 (en) 2018-09-14 2021-01-12 Applied Materials, Inc. Systems and methods for improved performance in semiconductor processing
US11049755B2 (en) 2018-09-14 2021-06-29 Applied Materials, Inc. Semiconductor substrate supports with embedded RF shield
US11062887B2 (en) 2018-09-17 2021-07-13 Applied Materials, Inc. High temperature RF heater pedestals
US11417534B2 (en) 2018-09-21 2022-08-16 Applied Materials, Inc. Selective material removal
US11682560B2 (en) 2018-10-11 2023-06-20 Applied Materials, Inc. Systems and methods for hafnium-containing film removal
US11121002B2 (en) 2018-10-24 2021-09-14 Applied Materials, Inc. Systems and methods for etching metals and metal derivatives
US11437242B2 (en) 2018-11-27 2022-09-06 Applied Materials, Inc. Selective removal of silicon-containing materials
US11721527B2 (en) 2019-01-07 2023-08-08 Applied Materials, Inc. Processing chamber mixing systems
US10920319B2 (en) 2019-01-11 2021-02-16 Applied Materials, Inc. Ceramic showerheads with conductive electrodes
US20230058692A1 (en) * 2019-08-05 2023-02-23 Hitachi High-Tech Corporation Plasma processing apparatus
US11424105B2 (en) * 2019-08-05 2022-08-23 Hitachi High-Tech Corporation Plasma processing apparatus
US11978612B2 (en) * 2019-08-05 2024-05-07 Hitachi High-Tech Corporation Plasma processing apparatus
US20210358716A1 (en) * 2020-05-13 2021-11-18 Tokyo Electron Limited Plasma processing apparatus and plasma processing method
US11972925B2 (en) * 2020-05-13 2024-04-30 Tokyo Electron Limited Plasma processing apparatus and plasma processing method

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