US20120164389A1 - Imprint template fabrication and repair based on directed block copolymer assembly - Google Patents

Imprint template fabrication and repair based on directed block copolymer assembly Download PDF

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US20120164389A1
US20120164389A1 US12/979,658 US97965810A US2012164389A1 US 20120164389 A1 US20120164389 A1 US 20120164389A1 US 97965810 A US97965810 A US 97965810A US 2012164389 A1 US2012164389 A1 US 2012164389A1
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Prior art keywords
block
pattern
substrate
block copolymer
polystyrene
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US12/979,658
Inventor
XiaoMin Yang
Zhaoning Yu
Kim Yang Lee
Michael Feldbaum
Yautzong Hsu
Wei Hu
Shuaigang Xiao
Henry Yang
HongYing Wang
Rene Johannes Marinus van de Veerdonk
David Kuo
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Seagate Technology LLC
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Seagate Technology LLC
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Priority to US12/979,658 priority Critical patent/US20120164389A1/en
Assigned to SEAGATE TECHNOLOGY LLC reassignment SEAGATE TECHNOLOGY LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: FELDBAUM, MICHAEL, HSU, YAUTZONG, KUO, DAVID, LEE, KIM YANG, VAN DE VEERDONK, RENE JOHANNES MARINUS, WANG, HONGYING, XIAO, SHUAIGANG, YANG, HENRY, YU, ZHAONING, HU, WEI, YANG, XIAOMIN
Publication of US20120164389A1 publication Critical patent/US20120164389A1/en
Priority to US14/588,865 priority patent/US9626996B2/en
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    • B32B3/30Layered products comprising a layer with external or internal discontinuities or unevennesses, or a layer of non-planar shape; Layered products comprising a layer having particular features of form characterised by a particular shape of the outline of the cross-section of a continuous layer; characterised by a layer with cavities or internal voids ; characterised by an apertured layer characterised by a layer formed with recesses or projections, e.g. hollows, grooves, protuberances, ribs
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    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23FNON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
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Definitions

  • the present disclosure relates generally to imprint template fabrication and repair.
  • bit patterned media In fabricating media for hard disk drives (“HDD”), bit patterned media (“BPM”) are used in the storage industry because of their high storage capacity.
  • the storage capacity of BPM depends on the density of the magnetic islands, or “bits” on the media substrate surface.
  • BPM fabrication has mainly been devoted to creating consistent and uniform patterns of bits on a BPM substrate.
  • a method includes forming a first pattern on a first substrate, transferring the pattern from the first substrate to a second substrate to form a patterned second substrate, and performing block copolymer self-assembly on the patterned second substrate.
  • an apparatus is manufactured by a method.
  • the method includes forming a first pattern on a first substrate, transferring the first pattern from the first substrate to a second substrate, and performing block copolymer self-assembly on the second substrate having the first pattern thereon, forming a second pattern.
  • an apparatus in a further aspect of the disclosure, includes a patterned substrate having a pattern density of at least about 1 Tdpsi.
  • FIG. 1 is a flow chart depicting an example of a process flow for fabricating a patterned apparatus.
  • FIGS. 2A-2G are schematic diagrams depicting an example of a process flow including a BCP self-assembly process.
  • Various apparatuses having high resolution patterns such as Bit-Patterned Media (BPM) templates, semiconductors, and photonic devices will be presented, as well as methods for achieving high resolution patterns using a combination of patterning and self-assembly techniques.
  • BPM Bit-Patterned Media
  • Various methods for integrating patterning techniques with block copolymers may be used to create nanopatterns, which may have a bit density greater than 1 Tdpsi.
  • the various apparatuses produced using these methods may exhibit optimized pattern density, optimized pattern accuracy, or both, when compared to apparatuses produced using other methods.
  • pattern densities may be achieved using these methods that are from about 1.1 to about 10 times more dense than apparatuses produced using other systems and methods, where pattern density is measured in dots per square inch (dpsi).
  • pattern accuracy may be achieved using these methods that are from about 1.1 to about 10 times more accurate than apparatuses produced using others methods, where pattern accuracy is measured in defects per square inch.
  • a patterned BPM template substrate may then be used as a master template for direct fabrication of other patterned media, including daughter templates and BPM.
  • Methods incorporating self-assembly may provide high resolution and acceptable throughput levels, while providing greater reliability, fewer defects in long-range ordering, all without being dependent on e-beam lithography. This may be advantageous because lithography techniques, such as e-beam lithography, typically use lower throughput in order to achieve large areas of dense patterning at acceptable resolutions.
  • the methods may be used to form a patterned substrate by conducting lithography to form a pattern on a substrate, and conducting block-copolymer self-assembly to provide higher resolution and greater accuracy to the pattern.
  • the methods may be used to form a pattern on all or a portion of the substrate.
  • the methods may be performed by lithography techniques in which a mask layer is deposited on the substrate; and a first pattern is formed on the substrate. Some methods further provide a chemical affinity layer on the substrate before conducting block-copolymer self-assembly techniques.
  • the block-copolymer self-assembly comprises coating the substrate with a block copolymer, removing one block from the block copolymer, and transferring the pattern from the remaining block of the block copolymer to the substrate.
  • FIG. 1 is a flow diagram depicting a method for patterning a substrate using lithography and BCP deposition. The methods are further described below.
  • a first substrate is patterned, for example, by using lithography techniques.
  • the first substrate may be a silicon or quartz template, or any other substrate suitable for use as a BPM template.
  • the patterning technique may be selected from techniques such as optical lithography (e.g., DUV), advanced lithography (e.g., e-beam lithography, EUV, or imprint lithography), or any other patterning techniques known to those skilled in the art.
  • the pattern formed in block 102 is transferred from the first substrate to a second substrate.
  • the second substrate may be a silicon or quartz template, or any other substrate suitable for use as a BPM template.
  • the transfer may be carried out using lithography techniques, such as imprint lithography (e.g., UV imprint lithography).
  • a BCP self-assembly process is performed on the second substrate to provide increased pattern density and/or optimized pattern quality (e.g., by replacing missing dots in the pattern, and/or reducing the number of imperfect dots) by using a multiplication factor k.
  • the BCP self-assembly process may be carried out as shown in FIG. 2 , as further described below.
  • pre-pattern marks are imprinted on the substrate using a resist pattern from a low density template (e.g., a 250 Gbpsi template).
  • the resist pattern guides the application of the BCP film.
  • the imprinted resist pattern may have a thickness ranging from about 5 nm to about 50 nm, preferably from about 5 nm to about 20 nm, and more preferably from about 10 nm to about 20 nm.
  • an optional descumming process may be performed.
  • a BCP film is provided on the imprinted substrate, and may be annealed.
  • the BCP film may be applied by any suitable technique, including spin coating.
  • Annealing may be conducted by carrying out thermal annealing, for from about 30 minutes to about 24 hours, at a temperature of from about 165° C. to about 220° C. When a lower temperature is used, annealing may be carried out for a longer time; conversely, when a higher temperature is used, annealing may be carried out for a shorter time.
  • the annealing process may be used to promote self-assembly of the BCP, which may be further facilitated by the addition of an optional chemical affinity layer, such as a polystyrene brush layer such as a hydroxy terminated polystyrene, including mono-hydroxyl-terminated polystyrene, hydroxy terminated poly(4-t-butyl styrene) and diphenylmethyl-ol terminated polystyrene.
  • the polystyrene brush layer may also comprise a neutral polymer that promotes BCP self assembly.
  • the BCP film may range in thickness from about 30 to about 70 nm.
  • the BCP used for the film may be any BCP.
  • BCP include, but are not limited to, BCP that is used in the methods is comprised of at least two constituent units, structural units, or “blocks,” herein termed “block A” and “block B.”
  • Block A and block B may be organic or inorganic, or block A may be organic, and block B inorganic, or block A may be inorganic and block B organic.
  • block A and block B are immiscible.
  • the block copolymer formed by block A and block B is preferably named using the convention polyA-block-polyB.
  • the block copolymers used in the methods may be selected from polystyrene-block-polymethylmethacrylate (PS-b-PMMA), polystyrene-block-poly2-vinylpyridine, polystyrene-block-poly4-vinylpyridine, polystyrene-block-polyethyleneoxide, polystyrene-block-polyisoprene, polystyrene-block-butadiene, polystyrene-block-polydimethylsiloxane (PS-b-PDMS), polyisoprene-block-polydimethylsiloxane, polymethylmethacrylate-block-polydimethylsiloxane, polyisobutylene-block-polydimethylsiloxane, or polystyrene-block-polyferrocenylsilane.
  • PS-b-PMMA polystyrene-block-polymethylmethacrylate
  • a person of ordinary skill in the art will appreciate that the methods described herein may be varied depending upon the chemical characteristics of the BCP selected.
  • selection of the BCP may also depend upon the target pattern to be created using the BCP.
  • the topographical pattern left by the imprinting blocks described below may determine the chosen BCP, since certain BCP blocks may correlate better with certain topographical pattern features and pattern dimensions.
  • One preferred block copolymer is PS-b-PMMA, although one skilled in the art will appreciate that other BCPs may be used depending on the predetermined pattern.
  • one of the blocks of the BCP is removed, and the film comprising the remaining block of the block copolymer may be descummed, if necessary, to prepare the film for mask deposition.
  • the block may be removed by a chemical process, such as by exposing the film to UV light, followed by a wet process using acetic acid. Alternatively, the block may be removed by an O 2 dry etching process. If descumming is performed, it may be carried out using, for example, O 2 dry descumming, O 2 + argon descumming, or CO 2 reactive ion beam aging (RIBE) descumming. When performed, descumming may also remove contaminants from the substrate.
  • O 2 dry descumming O 2 + argon descumming
  • CO 2 reactive ion beam aging (RIBE) descumming When performed, descumming may also remove contaminants from the substrate.
  • a mask layer is deposited on the film comprising the remaining block of the block copolymer.
  • the mask layer may be a hard mask layer, such as a chromium layer (Cr), a tantalum layer (Ta), a carbon layer (C), or an aluminum layer (Al).
  • the mask layer may be from about 3 nm to about 10 nm thick, preferably from about 4 nm to about 8 nm thick, and more preferably from about 5 to about 6 nm thick.
  • a dry lift-off of the mask layer is performed as follows: (1) The top layer of the mask (e.g., Cr) is first removed. This may be performed, for example, by an RIE process using Cl 2 gas. (2) The mask layer deposited on the sidewalls formed during the mask deposition process is then removed by using high-angle ion milling, which may be carried out at 70° C. using an inert gas, such as argon. (3) The remaining block of the block copolymer is finally removed from the substrate. This may be performed, for example, by using an O 2 dry RIE etching process.
  • the resulting pattern is transferred to the substrate, for example, by etching.
  • a RIE dry etching process may be used.
  • any residual mask is removed.
  • the mask may be removed using a wet process, such as by using a Cr etchant, and then the etched template may optionally be cleaned.
  • the second substrate may be inspected to determine if the pattern quality and density specifications are met. If yes, then the process is complete. If not, then the process can proceed to block 112 .
  • the pattern may optionally be transferred from second substrate to a third substrate using imprint lithography as described above in block 104 , and a BCP self-assembly process may optionally be performed on the third substrate, as described above in blocks 106 and 108 .
  • the process of repeating the pattern transfer and block copolymer self assembly process may be repeated multiple times in order to provide optimized pattern density, optimized pattern accuracy, or both.
  • the method may provide optimized quality to nanostructures by increasing pattern density and/or improving pattern quality (e.g., replacing missing dots, correcting deformed and/or joined dots).
  • the optimized pattern density and/or optimized pattern quality may be provided by repeating the blocks of transferring the pattern from one substrate to a new substrate, and performing BCP self-assembly on the new substrate onto which the pattern was transferred. These blocks of transferring the pattern to a new substrate and conducting BCP self-assembly techniques may be repeated once, twice, or as many times as necessary to achieve a particular predetermined density and/or pattern quality level.
  • the method may also reduce or eliminate the problem of lift-off of the mask layer through use of the dry lift-off process described in FIG. 2E .
  • the substrate patterning methods incorporating BCP self-assembly techniques may be used to fabricate templates, increase the density of patterns provided on templates, and/or to repair defects in patterns provided on templates.
  • the methods described herein are not limited to BPM-related applications. In principle, they can be used for many other applications in which high-resolution patterns are desirable, particularly periodic dot or line patterns.

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Abstract

Imprinted apparatuses, such as Bit-Patterned Media (BPM) templates, Discrete Track Recording (DTR) templates, semiconductors, and photonic devices are disclosed. Methods of fabricating imprinted apparatuses using a combination of patterning and block copolymer (BCP) self-assembly techniques are also disclosed.

Description

    FIELD
  • The present disclosure relates generally to imprint template fabrication and repair.
  • BACKGROUND
  • In fabricating media for hard disk drives (“HDD”), bit patterned media (“BPM”) are used in the storage industry because of their high storage capacity. The storage capacity of BPM depends on the density of the magnetic islands, or “bits” on the media substrate surface. As such, research in the area of BPM fabrication has mainly been devoted to creating consistent and uniform patterns of bits on a BPM substrate.
  • As the resolution and pattern density of the BPM increases, an issue may arise regarding how to correct imperfections in the BPM template, such as missing and connected bits. Cr lift-off is another problem encountered in high-density BPM template fabrication.
  • Accordingly, there is a need in the art for BPM templates having high density patterns, and methods for fabricating them, particularly for those BPM having a density greater than 1 Tdpsi. There is also a need for methods of fabricating BPM templates using a combination of lithography and self-assembly techniques.
  • SUMMARY
  • In one aspect of the disclosure, a method includes forming a first pattern on a first substrate, transferring the pattern from the first substrate to a second substrate to form a patterned second substrate, and performing block copolymer self-assembly on the patterned second substrate.
  • In another aspect of the disclosure, an apparatus is manufactured by a method. The method includes forming a first pattern on a first substrate, transferring the first pattern from the first substrate to a second substrate, and performing block copolymer self-assembly on the second substrate having the first pattern thereon, forming a second pattern.
  • In a further aspect of the disclosure, an apparatus includes a patterned substrate having a pattern density of at least about 1 Tdpsi.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a flow chart depicting an example of a process flow for fabricating a patterned apparatus.
  • FIGS. 2A-2G are schematic diagrams depicting an example of a process flow including a BCP self-assembly process.
  • DETAILED DESCRIPTION
  • Various concepts are described more fully hereinafter with reference to the accompanying drawings. These concepts, however, may be embodied in many different forms and should not be construed as being limited by any specific structure or process presented in this disclosure. Rather, the specific details presented throughout this disclosure are provided so that the disclosure will be thorough and complete, and will fully convey the scope of these concepts to those skilled in the art. However, it will be apparent to those skilled in the art that the various concepts presented in this disclosure may be practiced without these specific details. In some instances, well-known aspects of the disclosure may be shown in block diagram form in order to avoid obscuring the various concepts presented throughout this disclosure.
  • Various apparatuses having high resolution patterns, such as Bit-Patterned Media (BPM) templates, semiconductors, and photonic devices will be presented, as well as methods for achieving high resolution patterns using a combination of patterning and self-assembly techniques. Various methods for integrating patterning techniques with block copolymers may be used to create nanopatterns, which may have a bit density greater than 1 Tdpsi. The various apparatuses produced using these methods may exhibit optimized pattern density, optimized pattern accuracy, or both, when compared to apparatuses produced using other methods. In some cases, pattern densities may be achieved using these methods that are from about 1.1 to about 10 times more dense than apparatuses produced using other systems and methods, where pattern density is measured in dots per square inch (dpsi). In other cases, pattern accuracy may be achieved using these methods that are from about 1.1 to about 10 times more accurate than apparatuses produced using others methods, where pattern accuracy is measured in defects per square inch.
  • Various methods are presented in this disclosure for integrating patterning techniques with self-assembly techniques in order to create apparatuses, such as a BPM template, a semiconductor, or a photonic device. A patterned BPM template substrate may then be used as a master template for direct fabrication of other patterned media, including daughter templates and BPM.
  • In order to meet the demands of BPM and DTR media manufacturing, additional specifications may be addressed beyond pattern resolution. Methods incorporating self-assembly, such as block copolymer self-assembly, may provide high resolution and acceptable throughput levels, while providing greater reliability, fewer defects in long-range ordering, all without being dependent on e-beam lithography. This may be advantageous because lithography techniques, such as e-beam lithography, typically use lower throughput in order to achieve large areas of dense patterning at acceptable resolutions.
  • The methods may be used to form a patterned substrate by conducting lithography to form a pattern on a substrate, and conducting block-copolymer self-assembly to provide higher resolution and greater accuracy to the pattern. The methods may be used to form a pattern on all or a portion of the substrate.
  • The methods may be performed by lithography techniques in which a mask layer is deposited on the substrate; and a first pattern is formed on the substrate. Some methods further provide a chemical affinity layer on the substrate before conducting block-copolymer self-assembly techniques. The block-copolymer self-assembly comprises coating the substrate with a block copolymer, removing one block from the block copolymer, and transferring the pattern from the remaining block of the block copolymer to the substrate.
  • Various aspects of these methods are illustrated in FIG. 1, which is a flow diagram depicting a method for patterning a substrate using lithography and BCP deposition. The methods are further described below.
  • In block 102, a first substrate is patterned, for example, by using lithography techniques. The first substrate may be a silicon or quartz template, or any other substrate suitable for use as a BPM template. The patterning technique may be selected from techniques such as optical lithography (e.g., DUV), advanced lithography (e.g., e-beam lithography, EUV, or imprint lithography), or any other patterning techniques known to those skilled in the art.
  • In block 104, the pattern formed in block 102 is transferred from the first substrate to a second substrate. The second substrate may be a silicon or quartz template, or any other substrate suitable for use as a BPM template. The transfer may be carried out using lithography techniques, such as imprint lithography (e.g., UV imprint lithography).
  • In blocks 106 and 108, a BCP self-assembly process is performed on the second substrate to provide increased pattern density and/or optimized pattern quality (e.g., by replacing missing dots in the pattern, and/or reducing the number of imperfect dots) by using a multiplication factor k. When k=1, pattern rectification is provided. When k>1 (e.g., k=2 such that 2×2=4), density multiplication is provided (e.g., 250 Gdpsi×4=1 Tdpsi). The BCP self-assembly process may be carried out as shown in FIG. 2, as further described below.
  • In FIG. 2A, pre-pattern marks are imprinted on the substrate using a resist pattern from a low density template (e.g., a 250 Gbpsi template). The resist pattern guides the application of the BCP film. The imprinted resist pattern may have a thickness ranging from about 5 nm to about 50 nm, preferably from about 5 nm to about 20 nm, and more preferably from about 10 nm to about 20 nm. After the resist pattern is imprinted on the substrate, an optional descumming process may be performed.
  • In FIG. 2B, a BCP film is provided on the imprinted substrate, and may be annealed. The BCP film may be applied by any suitable technique, including spin coating. Annealing may be conducted by carrying out thermal annealing, for from about 30 minutes to about 24 hours, at a temperature of from about 165° C. to about 220° C. When a lower temperature is used, annealing may be carried out for a longer time; conversely, when a higher temperature is used, annealing may be carried out for a shorter time. The annealing process may be used to promote self-assembly of the BCP, which may be further facilitated by the addition of an optional chemical affinity layer, such as a polystyrene brush layer such as a hydroxy terminated polystyrene, including mono-hydroxyl-terminated polystyrene, hydroxy terminated poly(4-t-butyl styrene) and diphenylmethyl-ol terminated polystyrene. The polystyrene brush layer may also comprise a neutral polymer that promotes BCP self assembly. The BCP film may range in thickness from about 30 to about 70 nm.
  • The BCP used for the film may be any BCP. Examples of BCP, include, but are not limited to, BCP that is used in the methods is comprised of at least two constituent units, structural units, or “blocks,” herein termed “block A” and “block B.” Use of the singular “block A” or “block B” also includes use of plural “blocks A” and “blocks B.” Block A and block B may be organic or inorganic, or block A may be organic, and block B inorganic, or block A may be inorganic and block B organic. Preferably, block A and block B are immiscible. The block copolymer formed by block A and block B is preferably named using the convention polyA-block-polyB.
  • The block copolymers used in the methods may be selected from polystyrene-block-polymethylmethacrylate (PS-b-PMMA), polystyrene-block-poly2-vinylpyridine, polystyrene-block-poly4-vinylpyridine, polystyrene-block-polyethyleneoxide, polystyrene-block-polyisoprene, polystyrene-block-butadiene, polystyrene-block-polydimethylsiloxane (PS-b-PDMS), polyisoprene-block-polydimethylsiloxane, polymethylmethacrylate-block-polydimethylsiloxane, polyisobutylene-block-polydimethylsiloxane, or polystyrene-block-polyferrocenylsilane. A person of ordinary skill in the art will appreciate that the methods described herein may be varied depending upon the chemical characteristics of the BCP selected. One will appreciate that selection of the BCP may also depend upon the target pattern to be created using the BCP. For example, the topographical pattern left by the imprinting blocks described below may determine the chosen BCP, since certain BCP blocks may correlate better with certain topographical pattern features and pattern dimensions. One preferred block copolymer is PS-b-PMMA, although one skilled in the art will appreciate that other BCPs may be used depending on the predetermined pattern.
  • In FIG. 2C, one of the blocks of the BCP is removed, and the film comprising the remaining block of the block copolymer may be descummed, if necessary, to prepare the film for mask deposition. The block may be removed by a chemical process, such as by exposing the film to UV light, followed by a wet process using acetic acid. Alternatively, the block may be removed by an O2 dry etching process. If descumming is performed, it may be carried out using, for example, O2 dry descumming, O2+ argon descumming, or CO2 reactive ion beam aging (RIBE) descumming. When performed, descumming may also remove contaminants from the substrate.
  • In FIG. 2D, a mask layer is deposited on the film comprising the remaining block of the block copolymer. The mask layer may be a hard mask layer, such as a chromium layer (Cr), a tantalum layer (Ta), a carbon layer (C), or an aluminum layer (Al). The mask layer may be from about 3 nm to about 10 nm thick, preferably from about 4 nm to about 8 nm thick, and more preferably from about 5 to about 6 nm thick.
  • In FIG. 2E, a dry lift-off of the mask layer is performed as follows: (1) The top layer of the mask (e.g., Cr) is first removed. This may be performed, for example, by an RIE process using Cl2 gas. (2) The mask layer deposited on the sidewalls formed during the mask deposition process is then removed by using high-angle ion milling, which may be carried out at 70° C. using an inert gas, such as argon. (3) The remaining block of the block copolymer is finally removed from the substrate. This may be performed, for example, by using an O2 dry RIE etching process.
  • In FIG. 2F, the resulting pattern is transferred to the substrate, for example, by etching. A RIE dry etching process may be used.
  • In FIG. 2G any residual mask is removed. The mask may be removed using a wet process, such as by using a Cr etchant, and then the etched template may optionally be cleaned.
  • Referring again to FIG. 1, in block 110, following completion of the BCP process and pattern transfer, the second substrate may be inspected to determine if the pattern quality and density specifications are met. If yes, then the process is complete. If not, then the process can proceed to block 112.
  • In block 112, the pattern may optionally be transferred from second substrate to a third substrate using imprint lithography as described above in block 104, and a BCP self-assembly process may optionally be performed on the third substrate, as described above in blocks 106 and 108. The process of repeating the pattern transfer and block copolymer self assembly process may be repeated multiple times in order to provide optimized pattern density, optimized pattern accuracy, or both.
  • One will appreciate that the processes illustrated in FIGS. 1 and 2 and described herein may vary according to the needs and uses of the predetermined template. The method may provide optimized quality to nanostructures by increasing pattern density and/or improving pattern quality (e.g., replacing missing dots, correcting deformed and/or joined dots). The optimized pattern density and/or optimized pattern quality may be provided by repeating the blocks of transferring the pattern from one substrate to a new substrate, and performing BCP self-assembly on the new substrate onto which the pattern was transferred. These blocks of transferring the pattern to a new substrate and conducting BCP self-assembly techniques may be repeated once, twice, or as many times as necessary to achieve a particular predetermined density and/or pattern quality level. The method may also reduce or eliminate the problem of lift-off of the mask layer through use of the dry lift-off process described in FIG. 2E.
  • The substrate patterning methods incorporating BCP self-assembly techniques may be used to fabricate templates, increase the density of patterns provided on templates, and/or to repair defects in patterns provided on templates.
  • The methods described herein are not limited to BPM-related applications. In principle, they can be used for many other applications in which high-resolution patterns are desirable, particularly periodic dot or line patterns.
  • The previous description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects. Thus, the claims are not intended to be limited to the aspects shown herein, but is to be accorded the full scope consistent with the language of the claims, wherein reference to an element in the singular is not intended to mean “one and only one” unless specifically so stated, but rather “one or more.” Unless specifically stated otherwise, the term “some” refers to one or more. A phrase referring to “at least one of” a list of items refers to any combination of those items, including single members. All structural and functional equivalents to the elements of the various aspects described throughout this disclosure that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims. Moreover, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the claims. No claim element is to be construed under the provisions of 35 U.S.C. §112, sixth paragraph, unless the element is expressly recited using the phrase “means for” or, in the case of a method claim, the element is recited using the phrase “step for.”

Claims (22)

1. A method comprising:
forming a first pattern on a first substrate;
transferring the first pattern from the first substrate to a second substrate; and
performing block copolymer self-assembly on the second substrate having the first pattern thereon, forming a second pattern.
2. The method of claim 1, wherein the first pattern is formed on the first substrate by lithography.
3. The method of claim 2, wherein the lithography comprises:
depositing a mask layer on said first substrate; and
forming said first pattern on said first substrate.
4. The method of claim 1, wherein the first pattern has a density of about 250 Gdpsi or lower.
5. The method of claim 1, wherein the block copolymer self-assembly comprises:
coating the second substrate with a block copolymer;
removing one block from the block copolymer; and
transferring the pattern from a remaining block of the block copolymer to said second substrate.
6. The method of claim 1, wherein said transferring the pattern and said performing block copolymer self assembly are repeated.
7. The method of claim 1, wherein the block copolymer self-assembly comprises:
coating the second substrate with a block copolymer,
removing one block from the block copolymer,
depositing a mask on the remaining block of the block copolymer,
transferring the pattern from the remaining block of the block copolymer to the second substrate, and
removing the mask.
8. The method of claim 7, wherein the block copolymer self-assembly increases the density of the second pattern relative to the density of the first pattern.
9. The method of claim 7, wherein the block copolymer self assembly reduces the number of dots missing from the second pattern relative to the number of dots missing from the first pattern.
10. The method of claim 7, wherein the mask removal comprises:
removing a layer of the mask from an upper surface of the remaining block of the block copolymer,
removing a layer of the mask from a side wall of the remaining block of the block copolymer, and
removing the remaining block of the block copolymer from the second substrate.
11. The method of claim 10, wherein the mask is removed from the upper surface using chlorine gas.
12. The method of claim 10, wherein the mask is removed from the side wall using ion milling.
13. The method of claim 10, wherein the remaining block is removed by an oxygen dry etching process.
14. The method of claim 1, wherein the second pattern has a density of about 1 Tbpsi or greater.
15. The method of claim 1, wherein the block copolymer is selected from the group consisting of polystyrene-block-polymethylmethacrylate, polystyrene-block-poly2-vinylpyridine, polystyrene-block-poly4-vinylpyridine, polystyrene-block-polyethyleneoxide, polystyrene-block-polyisoprene, polystyrene-block-butadiene, polystyrene-block-polydimethylsiloxane, polyisoprene-block-polydimethylsiloxane, polyisobutylene-block-polydimethylsiloxane, polymethylmethacrylate-block-polydimethylsiloxane, and polystyrene-block-polyferrocenylsilane
16. An apparatus manufactured by a method comprising:
forming a first pattern on a first substrate;
transferring the first pattern from the first substrate to a second substrate; and
performing block copolymer self-assembly on the second substrate having the first pattern thereon, forming a second pattern.
17. An apparatus, comprising:
a patterned substrate having a pattern density of at least about 1 Tdpsi.
18. The apparatus of claim 17, wherein the substrate comprises silicon.
19. The apparatus of claim 17, wherein the substrate comprises quartz.
20. The apparatus of claim 17, wherein the apparatus comprises a media template.
21. The apparatus of claim 17, wherein comprises a semiconductor.
22. The apparatus of claim 17, wherein the apparatus comprises a photonic device.
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Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130105755A1 (en) * 2011-11-02 2013-05-02 Micron Technology, Inc. Methods of forming semiconductor device structures, and related structures
US8801894B2 (en) 2007-03-22 2014-08-12 Micron Technology, Inc. Sub-10 NM line features via rapid graphoepitaxial self-assembly of amphiphilic monolayers
US8993088B2 (en) 2008-05-02 2015-03-31 Micron Technology, Inc. Polymeric materials in self-assembled arrays and semiconductor structures comprising polymeric materials
US9087699B2 (en) 2012-10-05 2015-07-21 Micron Technology, Inc. Methods of forming an array of openings in a substrate, and related methods of forming a semiconductor device structure
US9142420B2 (en) 2007-04-20 2015-09-22 Micron Technology, Inc. Extensions of self-assembled structures to increased dimensions via a “bootstrap” self-templating method
US9177795B2 (en) 2013-09-27 2015-11-03 Micron Technology, Inc. Methods of forming nanostructures including metal oxides
KR20150136503A (en) * 2013-03-27 2015-12-07 가부시키가이샤 니콘 Mark forming method, mark detecting method, and device manufacturing method
US9229328B2 (en) 2013-05-02 2016-01-05 Micron Technology, Inc. Methods of forming semiconductor device structures, and related semiconductor device structures
US9257256B2 (en) 2007-06-12 2016-02-09 Micron Technology, Inc. Templates including self-assembled block copolymer films
US9315609B2 (en) 2008-03-21 2016-04-19 Micron Technology, Inc. Thermal anneal of block copolymer films with top interface constrained to wet both blocks with equal preference
US20160342592A1 (en) * 2014-02-12 2016-11-24 Commissariat A L'energie Atomique Et Aux Energies Alternatives Method for defining a self-assembling unit of a block copolymer
US9535326B2 (en) 2014-02-12 2017-01-03 Samsung Electronics Co., Ltd. Methods of manufacturing a semiconductor device
US9682857B2 (en) 2008-03-21 2017-06-20 Micron Technology, Inc. Methods of improving long range order in self-assembly of block copolymer films with ionic liquids and materials produced therefrom
US9768021B2 (en) 2007-04-18 2017-09-19 Micron Technology, Inc. Methods of forming semiconductor device structures including metal oxide structures
US10005308B2 (en) 2008-02-05 2018-06-26 Micron Technology, Inc. Stamps and methods of forming a pattern on a substrate
US20180323078A1 (en) * 2015-12-24 2018-11-08 Intel Corporation Pitch division using directed self-assembly

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9552964B2 (en) 2014-06-20 2017-01-24 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating an integrated circuit with a pattern density-outlier-treatment for optimized pattern density uniformity
JP2016054214A (en) * 2014-09-03 2016-04-14 株式会社東芝 Pattern formation method
JP6346115B2 (en) * 2015-03-24 2018-06-20 東芝メモリ株式会社 Pattern formation method
JP6346132B2 (en) * 2015-09-11 2018-06-20 株式会社東芝 Pattern formation method
US11475912B1 (en) 2021-06-11 2022-10-18 Seagate Technology Llc Synchronous writing of patterned media

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090196488A1 (en) * 2007-12-07 2009-08-06 Wisconsin Alumni Research Foundation Density multiplication and improved lithography by directed block copolymer assembly
US20090305173A1 (en) * 2008-06-09 2009-12-10 Seagate Technology Llc Formation of a device using block copolymer lithography

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8069782B2 (en) * 2004-12-20 2011-12-06 Nanoink, Inc. Stamps with micrometer- and nanometer-scale features and methods of fabrication thereof
US8673541B2 (en) * 2010-10-29 2014-03-18 Seagate Technology Llc Block copolymer assembly methods and patterns formed thereby
US20120135159A1 (en) 2010-11-30 2012-05-31 Seagate Technology Llc System and method for imprint-guided block copolymer nano-patterning
KR102012765B1 (en) * 2012-03-02 2019-08-22 에이에스엠엘 네델란즈 비.브이. Methods of providing patterned chemical epitaxy templates for self-assemblable block copolymers for use in device lithography
WO2013160027A1 (en) * 2012-04-27 2013-10-31 Asml Netherlands B.V. Methods and compositions for providing spaced lithography features on a substrate by self-assembly of block copolymers
US8790522B1 (en) * 2013-02-11 2014-07-29 Globalfoundries Inc. Chemical and physical templates for forming patterns using directed self-assembly materials
US10457088B2 (en) * 2013-05-13 2019-10-29 Ridgefield Acquisition Template for self assembly and method of making a self assembled pattern
US10339260B2 (en) * 2013-09-06 2019-07-02 Asml Netherlands B.V. Methodology to generate guiding templates for directed self-assembly
US9508562B2 (en) * 2014-06-27 2016-11-29 Globalfoundries Inc. Sidewall image templates for directed self-assembly materials

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090196488A1 (en) * 2007-12-07 2009-08-06 Wisconsin Alumni Research Foundation Density multiplication and improved lithography by directed block copolymer assembly
US20090305173A1 (en) * 2008-06-09 2009-12-10 Seagate Technology Llc Formation of a device using block copolymer lithography

Cited By (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8801894B2 (en) 2007-03-22 2014-08-12 Micron Technology, Inc. Sub-10 NM line features via rapid graphoepitaxial self-assembly of amphiphilic monolayers
US9768021B2 (en) 2007-04-18 2017-09-19 Micron Technology, Inc. Methods of forming semiconductor device structures including metal oxide structures
US9142420B2 (en) 2007-04-20 2015-09-22 Micron Technology, Inc. Extensions of self-assembled structures to increased dimensions via a “bootstrap” self-templating method
US9257256B2 (en) 2007-06-12 2016-02-09 Micron Technology, Inc. Templates including self-assembled block copolymer films
US10005308B2 (en) 2008-02-05 2018-06-26 Micron Technology, Inc. Stamps and methods of forming a pattern on a substrate
US11560009B2 (en) 2008-02-05 2023-01-24 Micron Technology, Inc. Stamps including a self-assembled block copolymer material, and related methods
US10828924B2 (en) 2008-02-05 2020-11-10 Micron Technology, Inc. Methods of forming a self-assembled block copolymer material
US9682857B2 (en) 2008-03-21 2017-06-20 Micron Technology, Inc. Methods of improving long range order in self-assembly of block copolymer films with ionic liquids and materials produced therefrom
US10153200B2 (en) 2008-03-21 2018-12-11 Micron Technology, Inc. Methods of forming a nanostructured polymer material including block copolymer materials
US11282741B2 (en) 2008-03-21 2022-03-22 Micron Technology, Inc. Methods of forming a semiconductor device using block copolymer materials
US9315609B2 (en) 2008-03-21 2016-04-19 Micron Technology, Inc. Thermal anneal of block copolymer films with top interface constrained to wet both blocks with equal preference
US8993088B2 (en) 2008-05-02 2015-03-31 Micron Technology, Inc. Polymeric materials in self-assembled arrays and semiconductor structures comprising polymeric materials
US9431605B2 (en) 2011-11-02 2016-08-30 Micron Technology, Inc. Methods of forming semiconductor device structures
US20130105755A1 (en) * 2011-11-02 2013-05-02 Micron Technology, Inc. Methods of forming semiconductor device structures, and related structures
US8900963B2 (en) * 2011-11-02 2014-12-02 Micron Technology, Inc. Methods of forming semiconductor device structures, and related structures
US9087699B2 (en) 2012-10-05 2015-07-21 Micron Technology, Inc. Methods of forming an array of openings in a substrate, and related methods of forming a semiconductor device structure
KR20150136503A (en) * 2013-03-27 2015-12-07 가부시키가이샤 니콘 Mark forming method, mark detecting method, and device manufacturing method
US20160079179A1 (en) * 2013-03-27 2016-03-17 Nikon Corporation Mark forming method, mark detecting method, and device manufacturing method
KR101951989B1 (en) * 2013-03-27 2019-02-25 가부시키가이샤 니콘 Mark forming method, mark detecting method, and device manufacturing method
US9972574B2 (en) * 2013-03-27 2018-05-15 Nikon Corporation Mark forming method, mark detecting method, and device manufacturing method
US10354959B2 (en) 2013-03-27 2019-07-16 Nikon Corporation Mark forming method, mark detecting method, and device manufacturing method using self-assembled block copolymer
TWI672788B (en) * 2013-03-27 2019-09-21 日商尼康股份有限公司 Mark forming method, mark detecting method, and component manufacturing method
US9229328B2 (en) 2013-05-02 2016-01-05 Micron Technology, Inc. Methods of forming semiconductor device structures, and related semiconductor device structures
US9177795B2 (en) 2013-09-27 2015-11-03 Micron Technology, Inc. Methods of forming nanostructures including metal oxides
US10049874B2 (en) 2013-09-27 2018-08-14 Micron Technology, Inc. Self-assembled nanostructures including metal oxides and semiconductor structures comprised thereof
US11532477B2 (en) 2013-09-27 2022-12-20 Micron Technology, Inc. Self-assembled nanostructures including metal oxides and semiconductor structures comprised thereof
US10255298B2 (en) * 2014-02-12 2019-04-09 Commissariat A L'energie Atomique Et Aux Energies Alternatives Method for defining a self-assembling unit of a block copolymer
US20160342592A1 (en) * 2014-02-12 2016-11-24 Commissariat A L'energie Atomique Et Aux Energies Alternatives Method for defining a self-assembling unit of a block copolymer
US9535326B2 (en) 2014-02-12 2017-01-03 Samsung Electronics Co., Ltd. Methods of manufacturing a semiconductor device
US20180323078A1 (en) * 2015-12-24 2018-11-08 Intel Corporation Pitch division using directed self-assembly

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