US20120152752A1 - Seed layer deposition in microscale features - Google Patents

Seed layer deposition in microscale features Download PDF

Info

Publication number
US20120152752A1
US20120152752A1 US12/971,744 US97174410A US2012152752A1 US 20120152752 A1 US20120152752 A1 US 20120152752A1 US 97174410 A US97174410 A US 97174410A US 2012152752 A1 US2012152752 A1 US 2012152752A1
Authority
US
United States
Prior art keywords
tin
layer
workpiece
substantially pure
silver
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US12/971,744
Other versions
US20120325671A2 (en
Inventor
Arthur Keigler
Johannes Chiu
Zhenqiu Liu
Daniel Goodman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ASM Nexx Inc
Original Assignee
Nexx Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nexx Systems Inc filed Critical Nexx Systems Inc
Priority to US12/971,744 priority Critical patent/US20120325671A2/en
Assigned to NEXX SYSTEMS, INC. reassignment NEXX SYSTEMS, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHIU, JOHANNES, GOODMAN, DANIEL, KEIGLER, ARTHUR, LIU, ZHENQIU
Priority to CN2011800599578A priority patent/CN103430287A/en
Priority to JP2013544802A priority patent/JP2013546205A/en
Priority to PCT/US2011/065324 priority patent/WO2012083100A2/en
Priority to KR1020137016821A priority patent/KR20130130000A/en
Priority to TW100147137A priority patent/TW201241242A/en
Assigned to NEXX SYSTEMS, INC. reassignment NEXX SYSTEMS, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KEIGLER, ARTHUR, LIU, ZHENQIU, ZHANG, ZHONGQIN
Publication of US20120152752A1 publication Critical patent/US20120152752A1/en
Publication of US20120325671A2 publication Critical patent/US20120325671A2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02Electroplating of selected surface areas
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/10Electroplating with more than one layer of the same or of different metals
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/48After-treatment of electroplated surfaces
    • C25D5/50After-treatment of electroplated surfaces by heat-treatment
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/60Electroplating characterised by the structure or texture of the layers
    • C25D5/615Microstructure of the layers, e.g. mixed structure
    • C25D5/617Crystalline layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/228Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a liquid phase, e.g. alloy diffusion processes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/114Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146Plating
    • H01L2224/11462Electroplating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/115Manufacturing methods by chemical or physical modification of a pre-existing or pre-deposited material
    • H01L2224/11502Pre-existing or pre-deposited material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/118Post-treatment of the bump connector
    • H01L2224/11848Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849Reflowing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/119Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/11901Methods of manufacturing bump connectors involving a specific sequence of method steps with repetition of the same manufacturing step
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

Definitions

  • the disclosed embodiments relate generally to a method and apparatus for applying metal structures to a workpiece, and more particularly to a method and apparatus for depositing a lead-free solder into micro-scale patterns in the surface of a workpiece coated with a photo-resist patterning film, and more particularly to a method and apparatus for electroplating tin-silver alloy solder bumps.
  • Electrodepositon of lead-free solder such as using through mask patterned deposition, is a technology capable of providing tight pitch bumping (connection pitch less than approximately 300 microns) or microbumping for advanced electronic packaging.
  • An alloy of tin (Sn) and silver (Ag) is the leading candidate metal for these applications.
  • Substantially pure tin has many desirable properties of a solder metal, for example fatigue, resistance, thermal cycling and ductile mechanical properties, however the industry has found that tin whisker growth in substantially pure tin solder makes it an unreliable joining solder for advanced packaging applications. It has been found that a small addition of silver, between approximately 1% and 4% Ag by weight, may significantly reduce the likelihood of Sn whisker formation in the solder joint. Tin-silver alloy (SnAg) solder plating in a conventional manner is more difficult than substantially pure tin electroplating or lead-tin (PbSn) electroplating because of the large difference in electrochemical reduction potential between tin ( ⁇ 0.13 volts SHE) and silver (+0.799 volts SHE).
  • SnAg Tin-silver alloy solder plating in a conventional manner is more difficult than substantially pure tin electroplating or lead-tin (PbSn) electroplating because of the large difference in electrochemical reduction potential between tin ( ⁇
  • This reduction potential difference causes Ag + ions in the solution to spontaneously react with metallic Sn and or the stannous ion (Sn +2 ) oxidizing the Sn or Sn +2 to Sn +2 or Sn +4 and thereby immersion depositing metallic Ag on the Sn surface.
  • the Ag + ion in the plating solution can immersion deposit on other metals such as nickel or copper.
  • Chemical suppliers have developed organic molecules that are to complex the Ag + ion to bring its reduction potential close to that of Sn +2 and thereby stabilize the Ag + ion in the plating solution.
  • the organic Ag + ion complex in the plating solution does not eliminate the likelihood of unwanted Ag immersion deposition on the Under Bump Metal (UBM), which is typically Nickel or Copper, when electroplating SnAg lead free solder on such UBM structures.
  • UBM Under Bump Metal
  • This unwanted immersion deposition may cause void defects at the UBM/SnAg interface, said voids are observable after reflowing the solder, and such voids can cause mechanical and electrical failures of the chip to package joint.
  • UBM Under Bump Metal
  • FIG. 1 shows a cross sectional view of prior art after the deposition step
  • FIG. 2 shows a cross sectional view of prior art after the deposition step
  • FIG. 3 shows a cross sectional view of solder bump after thermal treatment
  • FIG. 4 shows a top-down section of prior art showing the presence of voids at the UBM to SnAg interface
  • FIG. 5 shows a top-down section of the present disclosed embodiments showing absence of voids at the UBM to SnAg interface
  • FIG. 6 shows a cross sectional view of the present disclosed embodiments after the second deposition step
  • FIG. 7 shows a commercial wafer electro-deposition machine suitable for a manufacturing process using the present disclosed embodiments
  • FIG. 8 shows a electro-deposition module
  • FIG. 9 shows a process flow diagram.
  • FIG. 1 there is shown a cross section of a single bump at the workpiece surface where the workpiece has been prepared for electrodeposition.
  • An electrical contact element 101 is substantially surrounded by an insulating film 100 , these type of features are disposed in a semi-periodic array over the integrated circuit workpiece, for example a 300 millimeter silicon wafer may have 1,000 to 100,000 of such electrical contact elements distributed across the surface.
  • any suitable workpiece or substrate may be provided, for example, gallium arsenide or otherwise.
  • the workpiece is coated with a seed layer 102 and then coated with photoresist 104 which is photo patterned to provide openings into which an under bump metal 106 , such as nickel (Ni) or copper (Cu) or a series of Ni and Cu layers, is electrodeposited.
  • Solder metal 120 is electrodeposited onto the under bump metal 106 using the same resist pattern mask layer 104 .
  • U.S. Pat. No. 7,012,333 which is hereby incorporated by reference herein in its entirety teaches deposition of a SnAg solder alloy with the alloy being deposited at lower than the SnAg eutectic point which is about 3.5% by weight.
  • FIG. 2 there is shown another prior art method of providing lead-free bump, for example a SnAg or SnAgCu alloy where more noble substantially pure metal layer(s) 131 are deposited on the under bump metal prior to the deposition of a substantially pure tin layer 130 .
  • U.S. Pat. No. 6,596,621 which is hereby incorporated by reference in its entirety, teaches forming a lead-free SnAgCu bump by using a under bump metal layer 106 comprised of about 2 micron thick Ni and then coating layer 106 with Ag/Cu 131 in proportions to the substantially pure Sn 130 necessary to form a SnAgCu alloy bump with proportions of about 3.5% Ag and about 0.6% Cu and with the balance Sn.
  • FIG. 3 shows a cross section of the solder bump after the thermal reflow process.
  • a thermal reflow process is advantageous to stabilize the solder bump structure prior to subsequent processing.
  • the photoresist 104 (not shown) is removed and the seed layer 102 is etched away everywhere except where it is protected by the under bump metal 106 .
  • the wafer is thermally treated in a so-called reflow process step.
  • reflow involves heating the workpiece in a controlled atmosphere so that the tin-oxides are substantially removed before the solder melts, which may occur between about 221° C. and about 232° C.
  • IMCs intermetallic compounds
  • intermetallic structure between the underbump metal (UBM) and the solder, along with a well controlled grain structure within the solder, may influence both the mechanical and electromigration reliability of the solder bump.
  • IMC intermetallic structure
  • the nucleation and growth of the solder grain structure is strongly influenced by the IMCs that were formed. Prohibiting the presence of Ag away at the underbump metal interface during the initial phase of reflow is advantageous as is demonstrated by comparing FIGS.
  • Workpiece 250 is prepared with a structure 252 having electrical contact element 101 that is substantially surrounded by an insulating film 100 , where these type of features are disposed in a semi-periodic array where the workpiece is coated with a seed layer 102 and then coated with photoresist 104 which is photopatterned to provide openings into which an underbump metal 106 , such as nickel (Ni) or copper (Cu) or a series of Ni and Cu layers, is electrodeposited. It is noted that any suitable underbump metal may be provided.
  • a substantially pure tin layer 121 is electrodeposited using an electroplating bath with a metal ion content containing no other metal ion besides tin.
  • the workpiece 250 may be rinsed to remove the electroplating bath.
  • a tin-silver layer 122 is then electrodeposited using the same resist pattern mask layer 104 in another plating bath having a metal ion content including tin and silver ions.
  • the thicknesses of the substantially pure Sn layer, T Sn , and of the SnAg layer, T SnAg , and the % Ag in the SnAg layer, C SnAg are adjusted to provide a final composition % Ag according to the following equation:
  • % Ag CSnAg ⁇ TSnAg/(TSnAg+TSn).
  • the presence of Ag between the Sn and the UBM causes the formation of voids in the intermetallic layer, and these voids reduce the reliability of the solder joint.
  • the present disclosed embodiments provide some of the economic benefit of the substantially pure Ag and substantially pure Sn method, for example reducing the solder deposition cost by approximately 50% or more, without the associated disadvantage of worsening the solder joint reliability.
  • FIG. 7 there is shown a commercial wafer electro-deposition machine suitable for a manufacturing process using the present disclosed embodiments.
  • the disclosed embodiments may be implemented in a commercially available electrodeposition machine such as the Stratus from NEXX Systems in Billerica MA.
  • System 200 may incorporate features as disclosed in the International Application WO 2005/042804 A2 published under the Patent Cooperation Treaty and having publication date May 12, 2005 which is hereby incorporated by reference herein in its entirety.
  • System 200 is shown in block diagram form as an exemplary system. It is noted that more or less modules may be provided having different configurations and locations.
  • the industrial electrodeposition machine 200 may contain load ports 206 by which substrates previously patterned with photoresist as described above are inserted and withdrawn from the system.
  • Loading station 204 may have a robotic arm which transfers substrates 278 into substrate-holders 270 , 272 , 274 which are then transferred by transport 280 to modules 210 , 212 , 214 , 216 , 260 , 262 , 264 , 266 and processed in succession,
  • the succession may include a copper (Cu) electrodeposition module 216 , a nickel (Ni) electrodeposition module 214 , a tin (Sn) electrodeposition module 212 , a tin-silver (SnAg) electrodeposition module 210 .
  • the substrates may then be returned to the loading station 204 which unloads the substrates and passes them through a substrate cleaning module 202 from which they are returned to the load ports 206 .
  • Cleaning steps using de-ionized water for example, may be disposed before and after the electrodeposition steps, for example, cleaning modules 260 , 262 , 264 , 266 may be provided. Alternately, modules 260 , 262 , 264 and 266 may be rinse or thermal treatment modules as well as clean modules.
  • Controller(s) 220 may be provided within each station or module to sequence the process and/or transport within the station or module.
  • a system controller(s) 222 may be provided within the system 200 to sequence substrates between the stations or process modules and to coordinate system actions, such as, host communication, lot loading and unloading or otherwise those actions that are required to control the system 200 .
  • Controller 222 may be programmable to plate the workpiece with substantially pure tin in process module 212 disposed to support a plating bath having a suitable metal ion content (e.g. such as that described above). It is noted that the process module 212 may include either a pure tin anode or an insoluble platinum-titanium (Pt—Ti) anode. Controller 222 may be further programmable to rinse the workpiece in a rinse tank disposed to support rinsing substantially all of the substantially pure tin plating chemistry from the workpiece. Controller 222 may further be programmable to plate the workpiece with tin and silver in process module 210 disposed to support a plating bath with a suitable metal ion content (e.g.
  • the process module may include, for example, an insoluble Pt—Ti anode or any other suitable anode.
  • Controller 222 or any other suitable controller may further be programmable to thermally treat the workpiece in a thermal treatment module disposed to thermally treat the workpiece to cause the tin and tin-silver layers to intermix and form a substantially uniform tin-silver alloy feature.
  • Controller 222 may be further programmable to deposit copper on the workpiece with copper electrodeposition module 216 .
  • Controller 222 may further be programmable to deposit nickel on the workpiece with nickel electrodeposition module 214 .
  • Controller 222 may further be programmable to clean the workpiece with clean module 260 .
  • Electrodeposition modules 210 , 212 , 214 , 216 and four cleaning modules 260 , 262 , 264 , 266 are shown. It is noted, however, that more or less modules may be provided. By way of example, only tin (Sn) electrodeposition module(s) and tin-silver (SnAg) electrodeposition module(s) may be provided. As a further example, separate tools having tin (Sn) electrodeposition module(s) and tin-silver (SnAg) electrodeposition module(s) may be provided. As a further example, multiple duplicate electrodeposition modules may be provided to allow multiple workpieces to be processed in parallel to increase the throughput of the system. As such, all such variations, alternatives and modifications of system configurations are embraced.
  • Electrodeposition module 210 may incorporate features as do modules found in Stratus tools from NEXX Systems in Billerica MA and may incorporate features as disclosed in the International Application WO 2005/042804 A2 published under the Patent Cooperation Treaty and having publication date May 12, 2005 which is hereby incorporated by reference herein in its entirety.
  • Exemplary electrodeposition module has housing 300 which contains fluid 302 where fluid 302 may flow through housing 300 and where fluid 302 may be a circulated electrolyte.
  • Workpiece holder 272 may be removable from housing 300 by handler 280 and may hold substrates 278 . Although two substrates are shown, holder may hold more or less substrate(s).
  • Anodes 310 , 312 are provided with shield plates 314 , 316 and paddle or fluid agitation assemblies 318 and 320 . It is noted that more or less assemblies may be provided. For example, a single anode may be provided. By way of further example, the anode may be part of housing 300 or shield plates 314 , 316 and paddle or fluid agitation assemblies 318 and 320 may not be provided.
  • controller(s) 220 may be suitably programmed to effect the process at least in part in an automatic manner.
  • FIG. 9 there is shown an exemplary process flow diagram 400 showing a method for forming a lead free solder bump on a workpiece.
  • a workpiece with an electrically conducting seed layer covered by a patterned resist mask layer having a plurality of openings may be provided, block 402 , for instance in the apparatus.
  • the workpiece may be immersed, block 404 , in a tin plating bath containing, for example, a substantially pure tin anode or an insoluble platinum-titanium anode.
  • electrical contact to the seed layer may be formed and electrical potential applied between the workpiece and the anode to cause substantially pure tin to be deposited, for example, between about 2 and about 150 microns of tin to deposit in the resist pattern features.
  • the workpiece may be moved to a rinse tank.
  • substantially all of the substantially pure tin plating chemistry from the workpiece may be rinsed.
  • the workpiece may be removed from the rinse tank, block 412 , and immersed in a plating bath containing tin and silver ions and an anode (e.g. such as, for example, an insoluble platinum-titanium anode), block 414 .
  • an anode e.g. such as, for example, an insoluble platinum-titanium anode
  • Electrical contact to the seed layer may be formed as per block 416 , and electrical potential applied between the workpiece and the anode to cause tin-silver alloy to deposit. For example, between about 2 and about 150 microns of a tin-silver alloy may be deposited in the resist pattern features.
  • the photoresist patterning layer may be removed, and substantially all of the seed layer not covered by the plated tin and tin-silver alloy may be removed, per block 420 .
  • Thermally treating the workpiece such as in block 422 , for example, at between about 210° C. to about 230° C.
  • the tin and tin-silver layers may have any suitable thickness or composition, for example, the tin layer may be about 30 microns and the tin-silver alloy layer is about 30 microns and the tin-silver alloy composition may be between about 1% and about 7% silver by weight before thermal treatment and about 0.5% to about 3.5% silver by weight after thermal treatment.
  • the tin layer may be about 10 microns and the tin-silver alloy layer may be about 10 microns and the tin-silver alloy composition may be between about 1% and about 7% silver by weight before thermal treatment and about 0.5% to about 3.5% silver by weight after thermal treatment.
  • the tin layer may be about one-fourth the thickness of the tin-silver layer.
  • process 400 may provide more or less steps or one or more steps may be combined in one or more step or process.
  • the tin layer may be about 1 micron or 10 microns and the tin-silver layer may be between about 20 microns to about 120 microns.
  • a method of forming a metal feature on a workpiece with deposition is provided.
  • the workpiece is provided with an under bump metal layer for solder of an electronic device.
  • a substantially pure tin layer is deposited directly to the under bump metal layer.
  • a tin silver alloy layer is deposited onto the substantially pure tin layer.
  • substantially all of the substantially pure tin plating chemistry from the workpiece may be rinsed.
  • the deposition is accomplished by electrodeposition.
  • the under bump metal comprises either copper or nickel.
  • an apparatus for forming a lead free solder bump on a workpiece having an electrically conducting seed layer, the electrically conducting seed layer covered by a patterned resist mask layer having a plurality of feature openings has a first plating bath with a metal ion content adapted to deposit a substantially pure tin layer in the resist pattern features.
  • a rinse tank may be provided and adapted to rinse substantially all of the substantially pure tin plating chemistry from the workpiece.
  • a second plating bath is provided with a metal ion content adapted to deposit a tin-silver alloy layer in the resist pattern features.
  • a copper electrodeposition module is provided.
  • a copper electrodeposition module and a nickel electrodeposition module are provided.
  • a cleaning module is provided.
  • an electronic device having a lead free solder feature is prepared by a process having a step of depositing a substantially pure tin layer directly to a layer of under bump metal for solder of the electronic device.
  • a step of depositing a tin silver alloy layer onto the substantially pure tin layer is provided.
  • a step of rinsing substantially all of the substantially pure tin plating chemistry from the electronic device may be provided.
  • the deposition is accomplished by electrodeposition.
  • the under bump metal comprises either copper or nickel.
  • a method for forming a lead free solder bump on a workpiece comprising providing a step of providing the workpiece with an electrically conducting seed layer, the electrically conducting seed layer covered by a patterned resist mask layer having a plurality of feature openings.
  • the workpiece is immersed in a first plating bath with a metal ion content.
  • the method comprises providing electrical contact to the seed layer and providing an electrical potential through the metal ion content of the first plating bath to cause between about 2 and about 150 microns of substantially pure tin to deposit in the resist pattern features.
  • the workpiece is immersed in a second plating bath with a metal ion content. Electrical contact to the seed layer is formed and an electrical potential between through the metal ion content in the second plating bath is provided to cause between about 2 and about 150 microns of a tin-silver alloy to deposit in the resist pattern features is provided.
  • the method may include moving the workpiece to a rinse tank, rinsing substantially all of the substantially pure tin plating chemistry from the workpiece is provided, and removing the workpiece from the rinse tank is provided.
  • removal of the photoresist patterning layer is provided.
  • substantially all of the seed layer not covered by the plated tin and tin-silver alloy is removed.
  • thermally treating the workpiece at between about 210 to about 230 degrees centigrade to cause the tin and tin-silver layers to intermix and form a substantially uniform tin-silver alloy feature is provided.
  • the tin layer is about 30 microns and the tin-silver alloy layer is about 30 microns, and wherein the tin-silver alloy composition is between about 1% and about 7% silver by weight before thermal treatment and about 0.5% to about 3.5% silver by weight after thermal treatment.
  • the tin layer is about 1 micron or about 10 microns and the tin-silver alloy layer is between about 20 microns to about 120 microns.
  • the tin layer is 10 microns and the tin-silver alloy layer is about 10 microns, and wherein the tin-silver alloy composition is between about 1% and about 7% silver by weight before thermal treatment and about 0.5% to about 3.5% silver by weight after thermal treatment.
  • the tin layer is about one-fourth the thickness of the tin-silver layer.
  • an apparatus for forming a lead free solder bump on a workpiece having an electrically conducting seed layer, the electrically conducting seed layer covered by a patterned resist mask layer having a plurality of feature openings has a controller programmable to plate the workpiece with substantially pure tin in a first process module disposed to support a first plating bath having a metal ion content adapted to deposit a substantially pure tin layer on the workpiece.
  • the controller is further programmable to plate the workpiece with tin and silver in a second process module disposed to support a second plating bath with a metal ion content adapted to deposit a tin and silver layer on the workpiece.
  • the controller is further programmable to rinse the workpiece in a rinse tank disposed to support rinsing substantially all of the substantially pure tin plating chemistry from the workpiece.
  • the controller is further programmable to deposit copper on the workpiece with a copper electrodeposition module.
  • the controller is further programmable to deposit nickel on the workpiece with a nickel electrodeposition module.
  • the controller is further programmable to clean the workpiece with a clean module.
  • a method for processing one or more workpieces to electrochemically form a pattern of lead-free bumps on a workpiece is provided.
  • the lead-free bump is formed by a substantially two step deposition process, the first step being through mask deposition of substantially pure tin from an electroplating solution containing tin-ions (e.g. a metal ion content), and a second step being through mask deposition of tin-silver alloy from an electroplating solution containing a controlled mixture of tin-ions and silver ions (e.g.
  • the two steps being controlled to provide target layer 1 and layer 2 thicknesses, T1 and T2, along with the second step being controlled to provide X% alloy composition, such that after a subsequent thermal treatment the two layers intermix and form a substantially uniform alloy of tin-silver (SnAg), said alloy having a concentration intermediate between the deposited X% Ag in the alloy deposition step and the 0% Ag in the substantially pure tin deposition step.
  • the disclosed embodiments prevent the immersion deposition of noble metal ion, such as Ag, and organic complexor on the Under Bump Material (UBM) surface to eliminate the potential forming of voids between the UBM and solder interface.
  • noble metal ion such as Ag
  • UBM Under Bump Material
  • a less noble metal layer such as substantially pure Tin, is electrodeposited on the UBM before the lead-free solder alloy of Sn and more noble metal such as Ag and/or Cu is co-deposited with Sn as a SnAg or SnAgCu alloy to form a bump for electronic packaging.

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Electrochemistry (AREA)
  • Organic Chemistry (AREA)
  • Metallurgy (AREA)
  • Materials Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Wire Bonding (AREA)

Abstract

A method of forming a metal feature on a workpiece with deposition is provided. The method includes providing an under bump metal layer for solder of an electronic device on the workpiece, depositing a substantially pure tin layer directly to the under bump metal layer, and depositing a tin silver alloy layer onto the substantially pure tin layer.

Description

    BACKGROUND
  • 1. Field
  • The disclosed embodiments relate generally to a method and apparatus for applying metal structures to a workpiece, and more particularly to a method and apparatus for depositing a lead-free solder into micro-scale patterns in the surface of a workpiece coated with a photo-resist patterning film, and more particularly to a method and apparatus for electroplating tin-silver alloy solder bumps.
  • 2. Brief Description of Related Developments
  • The semiconductor industry has been working towards eliminating lead in electronics, as required under the European Union's Restriction of Hazardous Substances (RoHS) Directive. The industry is moving faster than the regulation to offer “green” consumer's electronics with lead-free packaging. Electrodepositon of lead-free solder such as using through mask patterned deposition, is a technology capable of providing tight pitch bumping (connection pitch less than approximately 300 microns) or microbumping for advanced electronic packaging. An alloy of tin (Sn) and silver (Ag) is the leading candidate metal for these applications. Substantially pure tin has many desirable properties of a solder metal, for example fatigue, resistance, thermal cycling and ductile mechanical properties, however the industry has found that tin whisker growth in substantially pure tin solder makes it an unreliable joining solder for advanced packaging applications. It has been found that a small addition of silver, between approximately 1% and 4% Ag by weight, may significantly reduce the likelihood of Sn whisker formation in the solder joint. Tin-silver alloy (SnAg) solder plating in a conventional manner is more difficult than substantially pure tin electroplating or lead-tin (PbSn) electroplating because of the large difference in electrochemical reduction potential between tin (−0.13 volts SHE) and silver (+0.799 volts SHE). This reduction potential difference causes Ag+ ions in the solution to spontaneously react with metallic Sn and or the stannous ion (Sn+2) oxidizing the Sn or Sn+2 to Sn+2 or Sn+4 and thereby immersion depositing metallic Ag on the Sn surface. Similarly the Ag+ ion in the plating solution can immersion deposit on other metals such as nickel or copper. Chemical suppliers have developed organic molecules that are to complex the Ag+ ion to bring its reduction potential close to that of Sn+2 and thereby stabilize the Ag+ ion in the plating solution. The organic Ag+ ion complex in the plating solution does not eliminate the likelihood of unwanted Ag immersion deposition on the Under Bump Metal (UBM), which is typically Nickel or Copper, when electroplating SnAg lead free solder on such UBM structures. This unwanted immersion deposition may cause void defects at the UBM/SnAg interface, said voids are observable after reflowing the solder, and such voids can cause mechanical and electrical failures of the chip to package joint. There is therefore a need for an alternate method of electroplating SnAg solder to form reliable lead-free bump attachment to the underlying metal to solve the problem facing the electronics industry as it moves toward eliminating all lead from integrated circuit products. Further, the industry also needs to develop economical methods of replacing the lead-tin (PbSn) plated bump structures with a lead-free (SnAg) plated bump structures. Due to the high cost of the Ag-complexor and other components in commercial SnAg plating chemistries, the typical cost of SnAg plated bumps is several multiples of the PbSn bumps. Existing methods of electrodepositing SnAg bumps involve expensive control systems in the manufacturing equipment, for example as described in U.S. patent application Ser. No. 11/840,748, which is hereby incorporated by reference in its entirety discloses a commercial plating equipment with a control system to ensure that a constant alloy composition is provided in the solder metal throughout the deposition. There is therefore a need for a method of SnAg electroplating that minimizes the use of expensive chemistry while providing a reliable interface between the SnAg and the underlying metal.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The foregoing aspects and other features of the embodiments are explained in the following description, taken in connection with the accompanying drawings. The technology described above may be better understood by referring to the following description taken in conjunction with the accompanying drawings. In the drawings, like reference characters generally refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the technology.
  • FIG. 1 shows a cross sectional view of prior art after the deposition step;
  • FIG. 2 shows a cross sectional view of prior art after the deposition step;
  • FIG. 3 shows a cross sectional view of solder bump after thermal treatment;
  • FIG. 4 shows a top-down section of prior art showing the presence of voids at the UBM to SnAg interface;
  • FIG. 5 shows a top-down section of the present disclosed embodiments showing absence of voids at the UBM to SnAg interface;
  • FIG. 6 shows a cross sectional view of the present disclosed embodiments after the second deposition step;
  • FIG. 7 shows a commercial wafer electro-deposition machine suitable for a manufacturing process using the present disclosed embodiments;
  • FIG. 8 shows a electro-deposition module; and
  • FIG. 9 shows a process flow diagram.
  • DETAILED DESCRIPTION OF THE EMBODIMENTS
  • Although the present embodiments will be described with reference to the embodiments shown in the drawings, it should be understood that the embodiments can be embodied in many alternate forms of embodiments. In addition, any suitable size, shape or type of elements or materials could be used. The present disclosed embodiments provide a method of providing a reliable interface between an electrodeposited lead-free solder bump and an underlying bump metal (UBM).
  • Referring now to FIG. 1, there is shown a cross section of a single bump at the workpiece surface where the workpiece has been prepared for electrodeposition. An electrical contact element 101 is substantially surrounded by an insulating film 100, these type of features are disposed in a semi-periodic array over the integrated circuit workpiece, for example a 300 millimeter silicon wafer may have 1,000 to 100,000 of such electrical contact elements distributed across the surface. It is noted that any suitable workpiece or substrate may be provided, for example, gallium arsenide or otherwise. The workpiece is coated with a seed layer 102 and then coated with photoresist 104 which is photo patterned to provide openings into which an under bump metal 106, such as nickel (Ni) or copper (Cu) or a series of Ni and Cu layers, is electrodeposited. Solder metal 120 is electrodeposited onto the under bump metal 106 using the same resist pattern mask layer 104. For example, U.S. Pat. No. 7,012,333 which is hereby incorporated by reference herein in its entirety teaches deposition of a SnAg solder alloy with the alloy being deposited at lower than the SnAg eutectic point which is about 3.5% by weight.
  • Referring now to FIG. 2, there is shown another prior art method of providing lead-free bump, for example a SnAg or SnAgCu alloy where more noble substantially pure metal layer(s) 131 are deposited on the under bump metal prior to the deposition of a substantially pure tin layer 130. U.S. Pat. No. 6,596,621, which is hereby incorporated by reference in its entirety, teaches forming a lead-free SnAgCu bump by using a under bump metal layer 106 comprised of about 2 micron thick Ni and then coating layer 106 with Ag/Cu 131 in proportions to the substantially pure Sn 130 necessary to form a SnAgCu alloy bump with proportions of about 3.5% Ag and about 0.6% Cu and with the balance Sn.
  • Referring now to FIG. 3, the potential drawbacks of these prior art approaches will be discussed where FIG. 3 shows a cross section of the solder bump after the thermal reflow process. A thermal reflow process is advantageous to stabilize the solder bump structure prior to subsequent processing. After the electrodeposition step, the photoresist 104 (not shown) is removed and the seed layer 102 is etched away everywhere except where it is protected by the under bump metal 106. Subsequently the wafer is thermally treated in a so-called reflow process step. Briefly described, reflow involves heating the workpiece in a controlled atmosphere so that the tin-oxides are substantially removed before the solder melts, which may occur between about 221° C. and about 232° C. for SnAg alloy; about 221° C. being the SnAg eutectic at composition of about 3.5% Ag and about 232° C. being the substantially pure Sn melting point, when the solder changes phase from solid to liquid the surface tension causes the metal volume to change shape, transforming into a substantially spherical shape 126 as the liquid surface tension minimizes the surface area. Also occurring at the elevated temperature is the formation of a layer of intermetallic compounds (IMCs) 128 which are a mixture of several alloy phases, for example at a Cu/Sn interface the IMCs will be a combination of Cu5Sn6 and Cu3Sn alloy phases. Also occurring at the elevated temperature is the vaporization and outgassing of various organic molecules that may be incorporated into the solder during the deposition process. These elevated temperature processes are halted by cooling down the wafer or substrate, causing the solder to solidify, wherein the solid solder is composed of many sub-micron sized grains which can have different sizes and compositions. For example, U.S. Pat. No. 6,805,974, which is hereby incorporated by reference herein in its entirety, teaches the importance of controlling the alloy composition and the cool-down rate to avoid the unwanted formation of large Ag3Sn plate shaped grains and instead form a fine grained dispersion of Sn grains and Ag3Sn small grains.
  • The importance of providing a repeatable and well controlled intermetallic structure (IMC) between the underbump metal (UBM) and the solder, along with a well controlled grain structure within the solder, may influence both the mechanical and electromigration reliability of the solder bump. In addition, during cooldown the nucleation and growth of the solder grain structure is strongly influenced by the IMCs that were formed. Prohibiting the presence of Ag away at the underbump metal interface during the initial phase of reflow is advantageous as is demonstrated by comparing FIGS. 4 and 5 which show optical microscope images 230, 240 of bumps that have been lapped and polished to the interface region 232, 242 between the underbump metal and the solder, where light and dark colors correspond to the different materials of solder, UBM, and IMC, where the very dark spots are voids. Using a nickel UBM layer and about a 2.5% Ag alloy single step electrodeposition of SnAg shown in FIG. 4 for example, frequent occurrence of interface voids 234, 236, 238 in the region between the UBM and SnAg may occur. By contrast, the disclosed embodiments using a first layer of substantially pure tin and a second layer of tin-silver repeatedly as shown in FIG. 5, no such occurrence of interface voids occur. The substantially pure Sn layer/bath may be referred to as, for example, a commercially available substantially pure Sn material or bath such as available from Dow Chemical.
  • Referring now to FIG. 6, there is shown a single bump structure in cross section. Workpiece 250 is prepared with a structure 252 having electrical contact element 101 that is substantially surrounded by an insulating film 100, where these type of features are disposed in a semi-periodic array where the workpiece is coated with a seed layer 102 and then coated with photoresist 104 which is photopatterned to provide openings into which an underbump metal 106, such as nickel (Ni) or copper (Cu) or a series of Ni and Cu layers, is electrodeposited. It is noted that any suitable underbump metal may be provided. A substantially pure tin layer 121 is electrodeposited using an electroplating bath with a metal ion content containing no other metal ion besides tin. It is noted that the workpiece 250 may be rinsed to remove the electroplating bath. A tin-silver layer 122 is then electrodeposited using the same resist pattern mask layer 104 in another plating bath having a metal ion content including tin and silver ions. The thicknesses of the substantially pure Sn layer, TSn, and of the SnAg layer, TSnAg, and the % Ag in the SnAg layer, CSnAg, are adjusted to provide a final composition % Ag according to the following equation:

  • % Ag=CSnAg×TSnAg/(TSnAg+TSn).
  • For example, to achieve a final composition % Ag equal to 1.5% Ag the TSn=TSnAg and CSnAg=3.0% .
  • It has been considered to apply substantially pure silver (Ag) and substantially pure tin (Sn) to facilitate fabrication of the SnAg alloy, or even to apply Ag, then Cu, then Sn which would then be reflowed to form a SnAgCu alloy, this method could have particular cost advantages since substantially pure Ag and substantially pure Sn plating materials are less expensive then SnAg alloy plating. When using a combination of substantially pure metal layers it is necessary to apply the more noble metals prior to applying the substantially pure tin for two reasons: (1) electrodeposition of Ag onto a Sn surface is difficult to control because of the problem of uncontrolled Ag immersion deposition on Sn, thereby producing an unstable Sn/Ag interface which will cause production control problems between the deposition step and the thermal treatment reflow step; (2) during the thermal reflow process the substantially pure Ag doesn't melt, instead it dissolves into the Sn, and therefore a Ag metal layer would be unstable on the melted tin solder ball, drifting around during the period between Sn melting and Ag fully dissolving into the Sn. However, to apply the Ag directly on top of the UBM material during the reflow process where the intermetallic layer is formed, the presence of Ag between the Sn and the UBM causes the formation of voids in the intermetallic layer, and these voids reduce the reliability of the solder joint. Because the SnAg materials are several times more expensive than Sn materials the present disclosed embodiments provide some of the economic benefit of the substantially pure Ag and substantially pure Sn method, for example reducing the solder deposition cost by approximately 50% or more, without the associated disadvantage of worsening the solder joint reliability.
  • Referring now to FIG. 7, there is shown a commercial wafer electro-deposition machine suitable for a manufacturing process using the present disclosed embodiments. The disclosed embodiments may be implemented in a commercially available electrodeposition machine such as the Stratus from NEXX Systems in Billerica MA. System 200 may incorporate features as disclosed in the International Application WO 2005/042804 A2 published under the Patent Cooperation Treaty and having publication date May 12, 2005 which is hereby incorporated by reference herein in its entirety. System 200 is shown in block diagram form as an exemplary system. It is noted that more or less modules may be provided having different configurations and locations. The industrial electrodeposition machine 200 may contain load ports 206 by which substrates previously patterned with photoresist as described above are inserted and withdrawn from the system. Loading station 204 may have a robotic arm which transfers substrates 278 into substrate- holders 270, 272, 274 which are then transferred by transport 280 to modules 210, 212, 214, 216, 260, 262, 264, 266 and processed in succession, The succession may include a copper (Cu) electrodeposition module 216, a nickel (Ni) electrodeposition module 214, a tin (Sn) electrodeposition module 212, a tin-silver (SnAg) electrodeposition module 210. The substrates may then be returned to the loading station 204 which unloads the substrates and passes them through a substrate cleaning module 202 from which they are returned to the load ports 206. Cleaning steps, using de-ionized water for example, may be disposed before and after the electrodeposition steps, for example, cleaning modules 260, 262, 264, 266 may be provided. Alternately, modules 260, 262, 264 and 266 may be rinse or thermal treatment modules as well as clean modules. Controller(s) 220 may be provided within each station or module to sequence the process and/or transport within the station or module. A system controller(s) 222 may be provided within the system 200 to sequence substrates between the stations or process modules and to coordinate system actions, such as, host communication, lot loading and unloading or otherwise those actions that are required to control the system 200. Controller 222 may be programmable to plate the workpiece with substantially pure tin in process module 212 disposed to support a plating bath having a suitable metal ion content (e.g. such as that described above). It is noted that the process module 212 may include either a pure tin anode or an insoluble platinum-titanium (Pt—Ti) anode. Controller 222 may be further programmable to rinse the workpiece in a rinse tank disposed to support rinsing substantially all of the substantially pure tin plating chemistry from the workpiece. Controller 222 may further be programmable to plate the workpiece with tin and silver in process module 210 disposed to support a plating bath with a suitable metal ion content (e.g. such as that described above). It is noted that the process module may include, for example, an insoluble Pt—Ti anode or any other suitable anode. Controller 222 or any other suitable controller may further be programmable to thermally treat the workpiece in a thermal treatment module disposed to thermally treat the workpiece to cause the tin and tin-silver layers to intermix and form a substantially uniform tin-silver alloy feature. Controller 222 may be further programmable to deposit copper on the workpiece with copper electrodeposition module 216. Controller 222 may further be programmable to deposit nickel on the workpiece with nickel electrodeposition module 214. Controller 222 may further be programmable to clean the workpiece with clean module 260. In the embodiment shown, four electrodeposition modules 210, 212, 214, 216 and four cleaning modules 260, 262, 264, 266 are shown. It is noted, however, that more or less modules may be provided. By way of example, only tin (Sn) electrodeposition module(s) and tin-silver (SnAg) electrodeposition module(s) may be provided. As a further example, separate tools having tin (Sn) electrodeposition module(s) and tin-silver (SnAg) electrodeposition module(s) may be provided. As a further example, multiple duplicate electrodeposition modules may be provided to allow multiple workpieces to be processed in parallel to increase the throughput of the system. As such, all such variations, alternatives and modifications of system configurations are embraced.
  • Referring now to FIG. 8, there is shown a block diagram of an exemplary electrodeposition process module 210. Electrodeposition module 210 may incorporate features as do modules found in Stratus tools from NEXX Systems in Billerica MA and may incorporate features as disclosed in the International Application WO 2005/042804 A2 published under the Patent Cooperation Treaty and having publication date May 12, 2005 which is hereby incorporated by reference herein in its entirety. Exemplary electrodeposition module has housing 300 which contains fluid 302 where fluid 302 may flow through housing 300 and where fluid 302 may be a circulated electrolyte. Workpiece holder 272 may be removable from housing 300 by handler 280 and may hold substrates 278. Although two substrates are shown, holder may hold more or less substrate(s). Anodes 310, 312 are provided with shield plates 314, 316 and paddle or fluid agitation assemblies 318 and 320. It is noted that more or less assemblies may be provided. For example, a single anode may be provided. By way of further example, the anode may be part of housing 300 or shield plates 314, 316 and paddle or fluid agitation assemblies 318 and 320 may not be provided.
  • The illustrated process may be performed, such as will be described further below with apparatus 200 for example. As may be realized, controller(s) 220 may be suitably programmed to effect the process at least in part in an automatic manner.
  • Referring now to FIG. 9, there is shown an exemplary process flow diagram 400 showing a method for forming a lead free solder bump on a workpiece. In accordance with the exemplary embodiment, for example, a workpiece with an electrically conducting seed layer covered by a patterned resist mask layer having a plurality of openings may be provided, block 402, for instance in the apparatus. The workpiece may be immersed, block 404, in a tin plating bath containing, for example, a substantially pure tin anode or an insoluble platinum-titanium anode. In block 404, electrical contact to the seed layer may be formed and electrical potential applied between the workpiece and the anode to cause substantially pure tin to be deposited, for example, between about 2 and about 150 microns of tin to deposit in the resist pattern features. In block 408, the workpiece may be moved to a rinse tank. In block 410, substantially all of the substantially pure tin plating chemistry from the workpiece may be rinsed. The workpiece may be removed from the rinse tank, block 412, and immersed in a plating bath containing tin and silver ions and an anode (e.g. such as, for example, an insoluble platinum-titanium anode), block 414. Electrical contact to the seed layer may be formed as per block 416, and electrical potential applied between the workpiece and the anode to cause tin-silver alloy to deposit. For example, between about 2 and about 150 microns of a tin-silver alloy may be deposited in the resist pattern features. In block 418, the photoresist patterning layer may be removed, and substantially all of the seed layer not covered by the plated tin and tin-silver alloy may be removed, per block 420. Thermally treating the workpiece such as in block 422, for example, at between about 210° C. to about 230° C. (degrees centigrade) may cause the tin and tin-silver layers to intermix and form a substantially uniform tin-silver alloy feature as desired. In the exemplary process 400, the tin and tin-silver layers may have any suitable thickness or composition, for example, the tin layer may be about 30 microns and the tin-silver alloy layer is about 30 microns and the tin-silver alloy composition may be between about 1% and about 7% silver by weight before thermal treatment and about 0.5% to about 3.5% silver by weight after thermal treatment. By way of further example, the tin layer may be about 10 microns and the tin-silver alloy layer may be about 10 microns and the tin-silver alloy composition may be between about 1% and about 7% silver by weight before thermal treatment and about 0.5% to about 3.5% silver by weight after thermal treatment. By way of further example, the tin layer may be about one-fourth the thickness of the tin-silver layer. Further, in the embodiments, process 400 may provide more or less steps or one or more steps may be combined in one or more step or process. By way of further example, the tin layer may be about 1 micron or 10 microns and the tin-silver layer may be between about 20 microns to about 120 microns.
  • In accordance with an embodiment, a method of forming a metal feature on a workpiece with deposition is provided. The workpiece is provided with an under bump metal layer for solder of an electronic device. A substantially pure tin layer is deposited directly to the under bump metal layer. A tin silver alloy layer is deposited onto the substantially pure tin layer.
  • In the embodiment, substantially all of the substantially pure tin plating chemistry from the workpiece may be rinsed.
  • In the embodiment, the deposition is accomplished by electrodeposition.
  • In the embodiment, the under bump metal comprises either copper or nickel.
  • In the embodiment, an apparatus for forming a lead free solder bump on a workpiece having an electrically conducting seed layer, the electrically conducting seed layer covered by a patterned resist mask layer having a plurality of feature openings is provided. The apparatus has a first plating bath with a metal ion content adapted to deposit a substantially pure tin layer in the resist pattern features. A rinse tank may be provided and adapted to rinse substantially all of the substantially pure tin plating chemistry from the workpiece. A second plating bath is provided with a metal ion content adapted to deposit a tin-silver alloy layer in the resist pattern features.
  • In the embodiment, a copper electrodeposition module is provided.
  • In the embodiment, a copper electrodeposition module and a nickel electrodeposition module are provided.
  • In the embodiment, a cleaning module is provided.
  • In the embodiment, an electronic device having a lead free solder feature is prepared by a process having a step of depositing a substantially pure tin layer directly to a layer of under bump metal for solder of the electronic device. A step of depositing a tin silver alloy layer onto the substantially pure tin layer is provided.
  • In the embodiment, a step of rinsing substantially all of the substantially pure tin plating chemistry from the electronic device may be provided.
  • In the embodiment, the deposition is accomplished by electrodeposition.
  • In the embodiment, the under bump metal comprises either copper or nickel.
  • In the embodiment, a method for forming a lead free solder bump on a workpiece is provided, the method comprising providing a step of providing the workpiece with an electrically conducting seed layer, the electrically conducting seed layer covered by a patterned resist mask layer having a plurality of feature openings. The workpiece is immersed in a first plating bath with a metal ion content. The method comprises providing electrical contact to the seed layer and providing an electrical potential through the metal ion content of the first plating bath to cause between about 2 and about 150 microns of substantially pure tin to deposit in the resist pattern features. The workpiece is immersed in a second plating bath with a metal ion content. Electrical contact to the seed layer is formed and an electrical potential between through the metal ion content in the second plating bath is provided to cause between about 2 and about 150 microns of a tin-silver alloy to deposit in the resist pattern features is provided.
  • In the embodiment, the method may include moving the workpiece to a rinse tank, rinsing substantially all of the substantially pure tin plating chemistry from the workpiece is provided, and removing the workpiece from the rinse tank is provided.
  • In the embodiment, removal of the photoresist patterning layer is provided.
  • In the embodiment, substantially all of the seed layer not covered by the plated tin and tin-silver alloy is removed.
  • In the embodiment, thermally treating the workpiece at between about 210 to about 230 degrees centigrade to cause the tin and tin-silver layers to intermix and form a substantially uniform tin-silver alloy feature is provided.
  • In the embodiment, the tin layer is about 30 microns and the tin-silver alloy layer is about 30 microns, and wherein the tin-silver alloy composition is between about 1% and about 7% silver by weight before thermal treatment and about 0.5% to about 3.5% silver by weight after thermal treatment.
  • In the embodiment, the tin layer is about 1 micron or about 10 microns and the tin-silver alloy layer is between about 20 microns to about 120 microns.
  • In the embodiment, the tin layer is 10 microns and the tin-silver alloy layer is about 10 microns, and wherein the tin-silver alloy composition is between about 1% and about 7% silver by weight before thermal treatment and about 0.5% to about 3.5% silver by weight after thermal treatment.
  • In the embodiment, the tin layer is about one-fourth the thickness of the tin-silver layer.
  • In the embodiment, an apparatus for forming a lead free solder bump on a workpiece having an electrically conducting seed layer, the electrically conducting seed layer covered by a patterned resist mask layer having a plurality of feature openings is provided. The apparatus has a controller programmable to plate the workpiece with substantially pure tin in a first process module disposed to support a first plating bath having a metal ion content adapted to deposit a substantially pure tin layer on the workpiece. The controller is further programmable to plate the workpiece with tin and silver in a second process module disposed to support a second plating bath with a metal ion content adapted to deposit a tin and silver layer on the workpiece.
  • In the embodiment, the controller is further programmable to rinse the workpiece in a rinse tank disposed to support rinsing substantially all of the substantially pure tin plating chemistry from the workpiece.
  • In the embodiment, the controller is further programmable to deposit copper on the workpiece with a copper electrodeposition module.
  • In the embodiment, the controller is further programmable to deposit nickel on the workpiece with a nickel electrodeposition module.
  • In the embodiment, the controller is further programmable to clean the workpiece with a clean module.
  • In the exemplary embodiment, a method for processing one or more workpieces to electrochemically form a pattern of lead-free bumps on a workpiece is provided. In one embodiment the lead-free bump is formed by a substantially two step deposition process, the first step being through mask deposition of substantially pure tin from an electroplating solution containing tin-ions (e.g. a metal ion content), and a second step being through mask deposition of tin-silver alloy from an electroplating solution containing a controlled mixture of tin-ions and silver ions (e.g. a metal ion content), the two steps being controlled to provide target layer 1 and layer 2 thicknesses, T1 and T2, along with the second step being controlled to provide X% alloy composition, such that after a subsequent thermal treatment the two layers intermix and form a substantially uniform alloy of tin-silver (SnAg), said alloy having a concentration intermediate between the deposited X% Ag in the alloy deposition step and the 0% Ag in the substantially pure tin deposition step. The disclosed embodiments prevent the immersion deposition of noble metal ion, such as Ag, and organic complexor on the Under Bump Material (UBM) surface to eliminate the potential forming of voids between the UBM and solder interface. A less noble metal layer, such as substantially pure Tin, is electrodeposited on the UBM before the lead-free solder alloy of Sn and more noble metal such as Ag and/or Cu is co-deposited with Sn as a SnAg or SnAgCu alloy to form a bump for electronic packaging.
  • It should be understood that the foregoing description is only illustrative of the invention. Various alternatives and modifications can be devised by those skilled in the art without departing from the invention. Accordingly, the present invention is intended to embrace all such alternatives, modifications and variances which fall within the scope of the appended claims.

Claims (28)

1. A method of forming a metal feature on a workpiece with deposition, the method comprising:
providing an under bump metal layer for solder of an electronic device on the workpiece;
depositing a substantially pure tin layer directly to the under bump metal layer; and
depositing a tin silver alloy layer onto the substantially pure tin layer.
2. The method of claim 1, wherein substantially all of the substantially pure tin plating chemistry from the workpiece is rinsed.
3. The method of claim 1, wherein the deposition is accomplished by electrodeposition.
4. The method of claim 1, wherein the under bump metal comprises either copper or nickel.
5. The method of claim 1, wherein the workpiece is thermally treated.
6. An apparatus for forming a substantially lead free solder bump on a workpiece having an electrically conducting seed layer, the electrically conducting seed layer being covered by a patterned resist mask layer having a plurality of feature openings is provided, the apparatus comprising:
a first plating bath with a metal ion content configured to deposit a substantially pure tin layer in the resist pattern features;
a second plating bath with a metal ion content configured to deposit a tin-silver alloy layer in the resist pattern features.
7. The apparatus of claim 6, further comprising a rinse tank configured to rinse substantially all of the substantially pure tin plating chemistry from the workpiece; and.
8. The apparatus of claim 6, further comprising a copper electrodeposition module.
9. The apparatus of claim 6, further comprising a copper electrodeposition module and a nickel electrodeposition module.
10. The apparatus of claim 6, further comprising a cleaning module.
11. A method for forming an electronic device having a lead free solder feature, the method comprising:
depositing a substantially pure tin layer directly to a layer of under bump metal for solder of the electronic device; and
depositing a tin silver alloy layer onto the pure tin layer.
12. The method of claim 11, wherein the deposition is accomplished by electrodeposition.
13. The method of claim 11, wherein the under bump metal comprises either copper or nickel.
14. The method of claim 11, further comprising rinsing substantially all of the substantially pure tin plating chemistry from the electronic device.
15. A method for forming a lead free solder bump on a workpiece, the method comprising:
providing the workpiece with an electrically conducting seed layer, the electrically conducting seed layer being covered by a patterned resist mask layer having a plurality of feature openings;
immersing the workpiece in a first plating bath, the first plating bath having a metal ion content;
providing electrical contact to the seed layer and providing an electrical potential through the metal ion content of the first plating bath to cause between about 2 and about 150 microns of substantially pure tin to deposit in the resist pattern features;
immersing the workpiece in a second plating bath with a metal ion content; and
forming electrical contact to the seed layer to form an electrical potential through the metal ion content of the second plating bath to cause between about 2 and about 150 microns of a tin-silver alloy to deposit in the resist pattern features.
16. The method of claim 15, further comprising removing the photoresist patterning layer.
17. The method of claim 15, wherein substantially all of the seed layer not covered by the plated tin and tin-silver alloy is removed.
18. The method of claim 15, further comprising thermally treating the workpiece at between about 210 to about 230 degrees centigrade to cause the substantially pure tin and tin-silver layers to intermix and form a substantially uniform tin-silver alloy feature.
19. The method of claim 15, wherein the substantially pure tin layer is about 30 microns and the tin-silver alloy layer is about 30 microns, and wherein the tin-silver alloy composition is between about 1% and about 7% silver by weight before thermal treatment and about 0.5% to about 3.5% silver by weight after thermal treatment.
20. The method of claim 15, wherein the substantially pure tin layer is about 10 microns and the tin-silver alloy layer is about 10 microns, and wherein the tin-silver alloy composition is between about 1% and about 7% silver by weight before thermal treatment and about 0.5% to about 3.5% silver by weight after thermal treatment.
21. The method of claim 15, wherein the substantially pure tin layer is about 1 micron or about 10 microns and the tin-silver alloy layer is between about 20 microns to about 120 microns.
22. The method of claim 15, wherein the substantially pure tin layer is about one-fourth the thickness of the tin-silver layer.
23. The method of claim 15, further comprising moving the workpiece to a rinse tank, rinsing substantially all of the substantially pure tin plating chemistry from the workpiece, and removing the workpiece from the rinse tank.
24. An apparatus for forming a lead free solder bump on a workpiece having an electrically conducting seed layer, the electrically conducting seed layer being covered by a patterned resist mask layer having a plurality of feature openings, the apparatus comprising:
a first process module disposed to support a first plating bath having a metal ion content adapted to deposit a substantially pure tin layer on the workpiece;
a second process module disposed to support a second plating bath with a metal ion content adapted to deposit a tin and silver layer on the workpiece; and
a controller programmable to plate the workpiece with the substantially pure tin layer in the first process module and to plate the workpiece with the tin and silver layer in the second process module.
25. The apparatus of claim 24, further comprising a rinse tank disposed to support rinsing substantially all of the pure tin plating chemistry from the workpiece, wherein the controller is further programmable to rinse the workpiece in the rinse tank.
26. The apparatus of claim 24, further comprising a copper electrodeposition module, wherein the controller is further programmable to deposit copper on the workpiece with the copper electrodeposition module.
27. The apparatus of claim 24, further comprising a nickel electrodeposition module, wherein the controller is further programmable to deposit nickel on the workpiece with the nickel electrodeposition module.
28. The apparatus of claim 24, further comprising a cleaning module, wherein the controller is further programmable to clean the workpiece with the cleaning module.
US12/971,744 2010-12-17 2010-12-17 Electroplated lead-free bump deposition Abandoned US20120325671A2 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
US12/971,744 US20120325671A2 (en) 2010-12-17 2010-12-17 Electroplated lead-free bump deposition
CN2011800599578A CN103430287A (en) 2010-12-17 2011-12-16 Electroplated lead-free bump deposition
JP2013544802A JP2013546205A (en) 2010-12-17 2011-12-16 Lead-free bump deposition by electroplating
PCT/US2011/065324 WO2012083100A2 (en) 2010-12-17 2011-12-16 Electroplated lead-free bump deposition
KR1020137016821A KR20130130000A (en) 2010-12-17 2011-12-16 Electroplated lead-free bump deposition
TW100147137A TW201241242A (en) 2010-12-17 2011-12-19 Electroplated lead-free bump deposition

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/971,744 US20120325671A2 (en) 2010-12-17 2010-12-17 Electroplated lead-free bump deposition

Publications (2)

Publication Number Publication Date
US20120152752A1 true US20120152752A1 (en) 2012-06-21
US20120325671A2 US20120325671A2 (en) 2012-12-27

Family

ID=46232956

Family Applications (1)

Application Number Title Priority Date Filing Date
US12/971,744 Abandoned US20120325671A2 (en) 2010-12-17 2010-12-17 Electroplated lead-free bump deposition

Country Status (6)

Country Link
US (1) US20120325671A2 (en)
JP (1) JP2013546205A (en)
KR (1) KR20130130000A (en)
CN (1) CN103430287A (en)
TW (1) TW201241242A (en)
WO (1) WO2012083100A2 (en)

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140255844A1 (en) * 2013-03-06 2014-09-11 Tokyo Electron Limited Substrate treatment method, non-transitory computer storage medium and substrate treatment system
US20150352476A1 (en) * 2014-06-09 2015-12-10 International Business Machines Corporation Filtering lead from photoresist stripping solution
US9280052B2 (en) 2013-03-06 2016-03-08 Tokyo Electron Limited Substrate treatment method, non-transitory computer storage medium and substrate treatment system
US9329483B2 (en) 2012-12-17 2016-05-03 Tokyo Electron Limited Film forming method, non-transitory computer storage medium and film forming apparatus
US9576922B2 (en) 2015-05-04 2017-02-21 Globalfoundries Inc. Silver alloying post-chip join
US20170110392A1 (en) * 2015-10-15 2017-04-20 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same structure
US9842956B2 (en) 2015-12-21 2017-12-12 Tesla, Inc. System and method for mass-production of high-efficiency photovoltaic structures
US9865754B2 (en) 2012-10-10 2018-01-09 Tesla, Inc. Hole collectors for silicon photovoltaic cells
US9887306B2 (en) 2011-06-02 2018-02-06 Tesla, Inc. Tunneling-junction solar cell with copper grid for concentrated photovoltaic application
US9899546B2 (en) 2014-12-05 2018-02-20 Tesla, Inc. Photovoltaic cells with electrodes adapted to house conductive paste
US9947822B2 (en) 2015-02-02 2018-04-17 Tesla, Inc. Bifacial photovoltaic module using heterojunction solar cells
US20180218971A1 (en) * 2015-10-30 2018-08-02 International Business Machines Corporation Method for forming solder bumps using sacrificial layer
US10074755B2 (en) 2013-01-11 2018-09-11 Tesla, Inc. High efficiency solar panel
US10084107B2 (en) 2010-06-09 2018-09-25 Tesla, Inc. Transparent conducting oxide for photovoltaic devices
US10084099B2 (en) 2009-11-12 2018-09-25 Tesla, Inc. Aluminum grid as backside conductor on epitaxial silicon thin film solar cells
US10115838B2 (en) 2016-04-19 2018-10-30 Tesla, Inc. Photovoltaic structures with interlocking busbars
US10115839B2 (en) 2013-01-11 2018-10-30 Tesla, Inc. Module fabrication of solar cells with low resistivity electrodes
US10164127B2 (en) 2013-01-11 2018-12-25 Tesla, Inc. Module fabrication of solar cells with low resistivity electrodes
US10181536B2 (en) 2015-10-22 2019-01-15 Tesla, Inc. System and method for manufacturing photovoltaic structures with a metal seed layer
US10309012B2 (en) 2014-07-03 2019-06-04 Tesla, Inc. Wafer carrier for reducing contamination from carbon particles and outgassing
US10672919B2 (en) 2017-09-19 2020-06-02 Tesla, Inc. Moisture-resistant solar cells for solar roof tiles
US11190128B2 (en) 2018-02-27 2021-11-30 Tesla, Inc. Parallel-connected solar roof tile modules

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2405469B1 (en) * 2010-07-05 2016-09-21 ATOTECH Deutschland GmbH Method to form solder alloy deposits on substrates
JP5659821B2 (en) * 2011-01-26 2015-01-28 三菱マテリアル株式会社 Manufacturing method of Sn alloy bump
US8877630B1 (en) * 2013-11-12 2014-11-04 Chipmos Technologies Inc. Semiconductor structure having a silver alloy bump body and manufacturing method thereof
US9368340B2 (en) * 2014-06-02 2016-06-14 Lam Research Corporation Metallization of the wafer edge for optimized electroplating performance on resistive substrates
JP6557466B2 (en) * 2014-12-24 2019-08-07 ローム・アンド・ハース・エレクトロニック・マテリアルズ・コリア・リミテッド Nickel plating solution
US10049970B2 (en) 2015-06-17 2018-08-14 Samsung Electronics Co., Ltd. Methods of manufacturing printed circuit board and semiconductor package

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6391166B1 (en) * 1998-02-12 2002-05-21 Acm Research, Inc. Plating apparatus and method
US6638847B1 (en) * 2000-04-19 2003-10-28 Advanced Interconnect Technology Ltd. Method of forming lead-free bump interconnections
US6596621B1 (en) * 2002-05-17 2003-07-22 International Business Machines Corporation Method of forming a lead-free tin-silver-copper based solder alloy on an electronic substrate
US7547623B2 (en) * 2002-06-25 2009-06-16 Unitive International Limited Methods of forming lead free solder bumps
US7012333B2 (en) * 2002-12-26 2006-03-14 Ebara Corporation Lead free bump and method of forming the same
US20080128019A1 (en) * 2006-12-01 2008-06-05 Applied Materials, Inc. Method of metallizing a solar cell substrate
US8314500B2 (en) * 2006-12-28 2012-11-20 Ultratech, Inc. Interconnections for flip-chip using lead-free solders and having improved reaction barrier layers
US7915741B2 (en) * 2009-02-24 2011-03-29 Unisem Advanced Technologies Sdn. Bhd. Solder bump UBM structure

Cited By (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10084099B2 (en) 2009-11-12 2018-09-25 Tesla, Inc. Aluminum grid as backside conductor on epitaxial silicon thin film solar cells
US10084107B2 (en) 2010-06-09 2018-09-25 Tesla, Inc. Transparent conducting oxide for photovoltaic devices
US9887306B2 (en) 2011-06-02 2018-02-06 Tesla, Inc. Tunneling-junction solar cell with copper grid for concentrated photovoltaic application
US9865754B2 (en) 2012-10-10 2018-01-09 Tesla, Inc. Hole collectors for silicon photovoltaic cells
US9329483B2 (en) 2012-12-17 2016-05-03 Tokyo Electron Limited Film forming method, non-transitory computer storage medium and film forming apparatus
US10164127B2 (en) 2013-01-11 2018-12-25 Tesla, Inc. Module fabrication of solar cells with low resistivity electrodes
US10115839B2 (en) 2013-01-11 2018-10-30 Tesla, Inc. Module fabrication of solar cells with low resistivity electrodes
US10074755B2 (en) 2013-01-11 2018-09-11 Tesla, Inc. High efficiency solar panel
US9341952B2 (en) * 2013-03-06 2016-05-17 Tokyo Electron Limited Substrate treatment method, non-transitory computer storage medium and substrate treatment system
US9280052B2 (en) 2013-03-06 2016-03-08 Tokyo Electron Limited Substrate treatment method, non-transitory computer storage medium and substrate treatment system
US20140255844A1 (en) * 2013-03-06 2014-09-11 Tokyo Electron Limited Substrate treatment method, non-transitory computer storage medium and substrate treatment system
US9804498B2 (en) * 2014-06-09 2017-10-31 International Business Machines Corporation Filtering lead from photoresist stripping solution
US20150352476A1 (en) * 2014-06-09 2015-12-10 International Business Machines Corporation Filtering lead from photoresist stripping solution
US10309012B2 (en) 2014-07-03 2019-06-04 Tesla, Inc. Wafer carrier for reducing contamination from carbon particles and outgassing
US9899546B2 (en) 2014-12-05 2018-02-20 Tesla, Inc. Photovoltaic cells with electrodes adapted to house conductive paste
US9947822B2 (en) 2015-02-02 2018-04-17 Tesla, Inc. Bifacial photovoltaic module using heterojunction solar cells
US9576922B2 (en) 2015-05-04 2017-02-21 Globalfoundries Inc. Silver alloying post-chip join
US20170110392A1 (en) * 2015-10-15 2017-04-20 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same structure
US10181536B2 (en) 2015-10-22 2019-01-15 Tesla, Inc. System and method for manufacturing photovoltaic structures with a metal seed layer
US20180218971A1 (en) * 2015-10-30 2018-08-02 International Business Machines Corporation Method for forming solder bumps using sacrificial layer
US10535592B2 (en) * 2015-10-30 2020-01-14 International Business Machines Corporation Method for forming solder bumps using sacrificial layer
US9842956B2 (en) 2015-12-21 2017-12-12 Tesla, Inc. System and method for mass-production of high-efficiency photovoltaic structures
US10115838B2 (en) 2016-04-19 2018-10-30 Tesla, Inc. Photovoltaic structures with interlocking busbars
US10672919B2 (en) 2017-09-19 2020-06-02 Tesla, Inc. Moisture-resistant solar cells for solar roof tiles
US11190128B2 (en) 2018-02-27 2021-11-30 Tesla, Inc. Parallel-connected solar roof tile modules

Also Published As

Publication number Publication date
TW201241242A (en) 2012-10-16
WO2012083100A8 (en) 2013-06-20
WO2012083100A2 (en) 2012-06-21
KR20130130000A (en) 2013-11-29
US20120325671A2 (en) 2012-12-27
CN103430287A (en) 2013-12-04
JP2013546205A (en) 2013-12-26
WO2012083100A3 (en) 2013-04-25

Similar Documents

Publication Publication Date Title
US20120152752A1 (en) Seed layer deposition in microscale features
TWI609100B (en) Cleaning electroplating substrate holders using reverse current deplating
JP4758614B2 (en) Electroplating composition and method
KR101688262B1 (en) Method to form solder alloy deposits on substrates
US20060113185A1 (en) Plating apparatus
CN113260739A (en) Electrodeposition of nano-twin copper structures
KR102343207B1 (en) Treatment method of electrodeposited copper for wafer-level-packaging process flow
US11587858B2 (en) Zinc-cobalt barrier for interface in solder bond applications
JP6149306B2 (en) Semiconductor structure and manufacturing method thereof
US20060011482A1 (en) Electrocodeposition of lead free tin alloys
US20050092611A1 (en) Bath and method for high rate copper deposition
JP2010040691A (en) Lead-free bump forming method
Kim et al. Electrodeposition of near-eutectic SnAg solders for wafer-level packaging
US20220396894A1 (en) Wafer shielding for prevention of lipseal plate-out
Kiumi et al. Process development of electroplate bumping for ULSI flip chip technology
Kiumi et al. Composition control for lead-free alloy electroplating on flip chip bumping
Lee et al. Effect of bath contamination on electroplated solder bumps
Töpper et al. Bumping technologies
Hsiung et al. Study on Sn-2.3 Ag Electroplated Solder Bump Properties Fabricated by Different Plating and Reflow Conditions
Kim et al. Electrodeposition of ternary near-eutectic SnAgCu solders with an alkaline bath
WO2006028341A1 (en) Method of making bump on semiconductor device
Ruhmer et al. Low cost UBM for lead free solder bumping with C4NP
Datta Paradigm Shifts in Electronics Enabled by Electrochemical Micro/Nano Processing
EP2506690A1 (en) Method to form solder deposits and non-melting bump structures on substrates

Legal Events

Date Code Title Description
AS Assignment

Owner name: NEXX SYSTEMS, INC., MASSACHUSETTS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KEIGLER, ARTHUR;CHIU, JOHANNES;LIU, ZHENQIU;AND OTHERS;REEL/FRAME:026092/0633

Effective date: 20110330

AS Assignment

Owner name: NEXX SYSTEMS, INC., MASSACHUSETTS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KEIGLER, ARTHUR;LIU, ZHENQIU;ZHANG, ZHONGQIN;SIGNING DATES FROM 20111213 TO 20111220;REEL/FRAME:027594/0366

AS Assignment

Owner name: TEL NEXX, INC., MASSACHUSETTS

Free format text: MERGER, CHANGE OF NAME;ASSIGNORS:NEXX SYSTEMS, INC.;SUB NEXX, INC.;REEL/FRAME:028604/0439

Effective date: 20120501

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION