US20110175177A1 - Microelectromechanical system (mems) device and methods for fabricating the same - Google Patents
Microelectromechanical system (mems) device and methods for fabricating the same Download PDFInfo
- Publication number
- US20110175177A1 US20110175177A1 US12/759,845 US75984510A US2011175177A1 US 20110175177 A1 US20110175177 A1 US 20110175177A1 US 75984510 A US75984510 A US 75984510A US 2011175177 A1 US2011175177 A1 US 2011175177A1
- Authority
- US
- United States
- Prior art keywords
- layer
- semiconductor layer
- substrate
- interconnect structure
- trenches
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00222—Integrating an electronic processing unit with a micromechanical structure
- B81C1/00246—Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B2201/00—Specific applications of microelectromechanical systems
- B81B2201/02—Sensors
- B81B2201/0228—Inertial sensors
- B81B2201/0235—Accelerometers
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2203/00—Forming microstructural systems
- B81C2203/01—Packaging MEMS
- B81C2203/0109—Bonding an individual cap on the substrate
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2203/00—Forming microstructural systems
- B81C2203/07—Integrating an electronic processing unit with a micromechanical structure
- B81C2203/0707—Monolithic integration, i.e. the electronic processing unit is formed on or in the same substrate as the micromechanical structure
- B81C2203/0742—Interleave, i.e. simultaneously forming the micromechanical structure and the CMOS circuit
Definitions
- the present invention relates to fabrication of a microelectromechanical system (MEMS) device, and in particularly to a method for fabricating a MEMS device capable of preventing dielectric or metal layers of micromachined structures therein from damages.
- MEMS microelectromechanical system
- Microelectromechanical structures have found applications in inertial measurement, pressure sensing, thermal measurement, micro-fluidics, optics, and radio frequency communications, and the application field for these structures continues to grow.
- Conventional microelectromechanical structures such as accelerometers, pressure sensors, flow sensors, microactuators and the like, typically comprise suspended micromachined structures having a released portion spaced apart from a substrate and one or more posts attached the substrate.
- an uppermost patterned metal layer is used as an etching mask and an adequate etching process is performed to remove films not covered by the patterned metal layer to thereby form the micromachined structure.
- the obtained micromachined structure may not be formed in a desired profile.
- portions of the film layers in the micromachined structure may be partially or entirely removed during the etching process, thereby negatively affecting functionality of the obtained MEMS device.
- a microelectromechanical system (MEMS) device and a method of fabricating the same for ensuring completeness of films in a micromachined structure in the MEMS device are provided to ensure functionality of the MEMS device.
- MEMS microelectromechanical system
- An exemplary method of fabricating a microelectromechanical system (MEMS) device comprises providing a semiconductor substrate comprising a semiconductor layer and an interconnect structure formed over the semiconductor layer.
- a passivation layer and a photoresist layer are sequentially formed over the interconnect structure.
- a plurality of openings is formed in the photoresist layer, wherein the openings expose a portion of the passivation layer.
- a first etching process is performed using the photoresist layer as an etching mask to remove the passivation layer exposed by the openings and the interconnect structure thereunder, and forms a plurality of first trenches exposing a portion of the semiconductor layer.
- the photoresist layer is removed to expose the passivation layer.
- a second etching process is performed using the passivation layer as an etching mask to remove a portion of the semiconductor layer exposed by the first trenches, and forms a plurality of second trenches in the semiconductor layer.
- An upper capping substrate is attached to the passivation layer to form a first composite substrate.
- a third etching process is performed to partially remove the thinned semiconductor layer and to form a third trench therein, wherein the third trench exposes and connects the second trenches, and a suspended micromachined structure is defined in a region between the first trench, the second trenches, and the third trench.
- An exemplary microelectromechanical system device comprises a semiconductor substrate comprising: a semiconductor layer and an interconnect structure formed over the semiconductor layer, wherein the semiconductor layer has opposing first and second sides, and the interconnect structure is formed over a surface of the semiconductor layer from the first side; a passivation layer disposed over the interconnect structure; a plurality of first trenches disposed in a portion of the passivation layer, the interconnect structure, and the semiconductor substrate; an upper capping substrate disposed over the passivation layer; a second trench disposed in a portion of the semiconductor layer from the second side, wherein the second trench exposes and connects with the first trenches, and the first trenches and the second trench defines a suspended micromachined structure therebetween; and a lower capping film attached to a surface of the semiconductor layer from the second side, wherein the upper capping substrate, the semiconductor substrate, and the lower capping substrate form a sealed chamber therebetween.
- FIGS. 1 a - 1 g are cross sections showing a method of fabricating a microelectromechanical device according to an embodiment of the invention.
- FIGS. 1 a - 1 g are cross sections showing an exemplary method for fabricating a microelectromechanical system (MEMS) device capable of ensuing a profile of film layers in micromachined structures therein and functionality of the MEMS device comprising the fabricated micromachined structures.
- MEMS microelectromechanical system
- a semiconductor substrate 10 is first provided.
- the semiconductor substrate 10 is an uncut semiconductor wafer having a plurality of substantially fabricated, but not separated, integrated circuit (IC) regions (not shown) thereover.
- IC integrated circuit
- MEMS microelectromechanical system
- FIG. 1 a the IC region provided over the semiconductor substrate 10 comprises a semiconductor layer 100 and an interconnect structure 101 formed over the semiconductor layer 100 .
- the interconnect structure 101 comprises a dielectric layer 102 , a plurality of conductive layers 104 disposed in various regions in the dielectric layer 102 , and a bond pad 106 disposed in the dielectric layer 102 .
- the conductive layers 104 are stacked over a same region from bottom to top.
- the semiconductor layer 100 can be, for example, a bulk silicon layer, and passive elements, active elements and other elements and/or combinations thereof can be formed at adequate places in or above the semiconductor layer 100 .
- the passive elements can be, for example, resistors, capacitors, inductances and/or fuses
- the active elements can be, for example, p-channel field effect transistors (PFET), n-channel field effect transistors (NFET), metal-oxide-semiconductor field effect transistors (MOSFET), complementary metal oxide transistors (CMOS), high voltage transistors, and/or high frequency transistors.
- the dielectric layer 102 may comprise dielectric materials such as silicon oxide or silicon nitride and may have a thickness of about 8-9 ⁇ m.
- the elements formed in the IC region shown in FIG. 1 a are not illustrated, and only a planar semiconductor layer 100 is illustrated.
- the interconnect structure 101 is illustrated by a structure comprising the conductive layers 104 and the bond pad 106 disposed in the dielectric layer 102 , the invention is not limited thereto.
- Other elements such as a plurality of interconnecting elements made of conductive elements comprising conductive layers and conductive vias can be further disposed in the dielectric layer 102 to electrically connect the conductive layers 104 and the bond pad 106 with the elements disposed in or above the semiconductor layer 100 .
- the above described layers and elements formed in or above the semiconductor layer 100 and the interconnect structure 101 can be fabricated by a standard complementary metal-oxide-semiconductor (CMOS) process, and fabrication thereof is not discussed here in detail, for simplicity.
- CMOS complementary metal-oxide-semiconductor
- the passivation layer 110 may comprise dielectric materials such as silicon oxide and has a thickness of about 0.8-1.0 ⁇ m.
- the passivation layer 110 and the dielectric layer 10 preferably comprise the same materials such that they may have a similar etching selectivity to an etchant.
- the photoresist layer 112 may comprise photoresist materials typically used in fabrication of MEMS devices and may have a thickness of about 5 ⁇ 15 ⁇ m.
- a photolithography process (not shown) is performed to form a plurality of openings 120 in the photoresist layer 112 .
- the openings 120 are respectively located over a portion of the dielectric layer 102 between the conductive layers 104 and partially expose a surface of a portion of the passivation layer 110 .
- an etching process 130 is performed to remove the passivation layer 110 and a portion of the dielectric layer 102 under the passivation layer 110 exposed by the openings 120 , thereby forming a plurality of trenches 132 in the dielectric layer 102 .
- the etching process 130 can be an anisotropic etching process such as a reactive ion etching (RIE) process.
- RIE reactive ion etching
- the etchants used in the etching process 130 not only removes the dielectric layer 102 but also partially removes a portion of the photoresist layer 112 , thereby leaving a thinned photoresist layer 112 ′ over the passivation layer 110 .
- the trenches 132 in the dielectric layer 102 expose a portion of the semiconductor layer 100 , and an included angle ⁇ greater than 85° is provided between the dielectric layer 132 adjacent to the trench 132 and the semiconductor layer 100 to thereby ensure that each of the trenches 132 has a profile substantially perpendicular to the semiconductor layer 100 .
- an etching process (not shown) is performed to remove the thinned photoresist layer 112 ′ over the passivation layer 110 , and an etching process 140 is then performed to remove a portion of the semiconductor layer 100 exposed by the trenches 132 (see FIG. 1 b ), thereby forming a plurality of trenches 142 in the semiconductor layer 100 .
- the passivation layer 110 serves as an etch stop to prevent the dielectric layer 102 covered by the passivation layer 110 from being etched in the etching process 140 .
- the trenches 142 formed in the dielectric layer 102 have a depth Dl of about 20-50 ⁇ m from a top surface of the semiconductor layer 100 .
- the etching process 140 can be as an anisotropic etching process such as a deep reactive ion etching (DRIE) process.
- DRIE deep reactive ion etching
- an adhesive layer 152 is formed over portions over the passivation layer 110 .
- the adhesive layer 152 may comprise adhesive materials such as frit.
- An upper capping substrate 150 is then provided over the semiconductor substrate 10 and then attached to the semiconductor substrate 10 by use of the adhering layers 152 , thereby forming a composite substrate 200 , as shown in FIG. 1 d .
- the upper capping substrate 150 may comprise a silicon or glass wafer.
- the composite substrate 200 shown in FIG. 1 d is inverted.
- a thinning process (not shown), such as a chemical mechanical polishing (CMP) process, is then performed to the surface of the semiconductor layer 100 in areas no trench is formed by holding the upper capping substrate 150 , thereby forming a thinned semiconductor layer 100 ′.
- CMP chemical mechanical polishing
- an etching process 160 is performed to form a wide trench 162 in the thinned semiconductor layer 100 ′.
- the etching process 160 can be an anisotropic etching process such as a deep reactive ion etching (DRIE) process.
- DRIE deep reactive ion etching
- the wide trench 162 substantially exposes and connects the trenches 142 formed in the thinned semiconductor layer 100 ′.
- a suspended micromachined structure is defined and formed in a region 164 .
- the micromachined structure in the region 164 comprises the thinned semiconductor layer 100 ′, the dielectric layer 102 and the conductive layers 104 formed in the dielectric layer 102 .
- the conductive layers 104 in the dielectric layer 102 are arranged in parallel and separated by the dielectric layer 102 , such that the suspended micromachined structure in the region 164 may function as a sensing capacitor.
- Functionality and structure of the suspended micromachined structure in the region 164 is not limited by that shown in FIG. 1 e . To the contrary, the suspended micromachined structure in the region 164 may have other structures and functionalities rather than that shown in FIG. 1 e.
- the structure shown in FIG. 1 e is inverted and a cutting process 170 is performed to expose the bond pad 106 formed in the dielectric layer 102 .
- the cutting process 170 can be, for example, a laser cutting or a mechanical cutting process, and a portion of the upper capping substrate 150 , the passivation layer 110 and the dielectric layer 102 above the bond pad 106 are removed in the cutting process 170 until a surface of the bond pad 106 is exposed.
- a lower capping film 180 is provided and attached to the surface of the thinned semiconductor layer 100 ′ where the wide trench 162 is formed.
- the lower capping film 170 can be, for example, a die attached film (DAF).
- the lower capping film 180 can be a dry film made of insulating materials such as a hot melt adhesive.
- Another composite substrate (not shown) is formed after attachment of the lower capping film 180 to the composite substrate 200 .
- a cutting process such as a wafer cutting process is performed to the composite substrate to separate the composite structure made of the upper capping substrate 150 , the semiconductor substrate 10 , and the lower capping film 180 into a plurality of independent microelectromechanical system (MEMS) device 300 .
- MEMS microelectromechanical system
- FIG. 1 g after formation of the MEMS device 300 , a sealed chamber 182 is provided among the thinned semiconductor layer 110 ′, the upper capping substrate 150 , and the lower capping substrate 180 .
- the sealed chamber 182 is formed with an inner pressure of about 1 atm and thus provides a space for allowing suitable movement of the suspended micromachined structure provided in the region 164 and ensures sensitivity of the micromachined structure.
- the MEMS device 300 shown in FIG. 1 g can be then disposed over a package substrate (not shown) depending on process demands, and a bonding process such as a wire boding process can be performed to form a conductive wire bonding which connects the package substrate (not shown) with the bond pad 106 in the MEMS device 300 , thereby forming electrical connection between the MEMS device 300 and the package substrate.
- an exemplary MEMS device comprising a semiconductor substrate comprising a semiconductor layer (e.g. the thinned semiconductor layer 100 ′) and an interconnect structure (e.g. the interconnect structure) formed over the semiconductor layer, wherein the semiconductor layer has opposing first and second sides, and the interconnect structure is formed over a surface of the semiconductor layer at the first side.
- a passivation layer e.g. the passivation layer 110
- a plurality of first trenches e.g. combination of the trenches 132 and 142
- An upper capping substrate e.g.
- a second trench (e.g. the wide trench 162 shown in FIG. 1 e ) is disposed in a portion of the semiconductor layer at the second side, wherein the second trench exposes and connects with the first trenches, and the first trenches and the second trench defines a suspended micromachined structure (e.g. the suspended micromachined structure in the region 164 ) therebetween.
- a lower capping film (e.g. the lower capping film 180 ) is attached to a surface of the semiconductor layer from the second side, wherein the upper capping substrate, the semiconductor substrate, and the lower capping substrate form a sealed chamber (e.g. the sealed chamber 182 ) therebetween.
- an improved fabrication method is provided by the invention by using an additional passivation layer and a photoresist layer as etching masks for ensuring a profile of films of a micromachined structure in a MEMS device. Reliability of a MEMS device comprising such a micromachined structure fabricated by the improved method can thus be ensured.
- fabricating the exemplary MEMS device can be achieved by wafer level fabrication and packaging processes, the micromachined structure and the integrated circuit elements used in the MEMS device can be simultaneously fabricated and no additional packaging process is needed. Therefore, a majority of the fabricating processes of the MEMS device can be completed in an IC foundry and transported to a packaging company for wafer cutting, such that fabrication costs of an MEMS device can thus be reduced.
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Micromachines (AREA)
Abstract
Description
- This Application claims priority of Taiwan Patent Application No. 99101593, filed on Jan. 21, 2010, the entirety of which is incorporated by reference herein.
- 1. Field of the Invention
- The present invention relates to fabrication of a microelectromechanical system (MEMS) device, and in particularly to a method for fabricating a MEMS device capable of preventing dielectric or metal layers of micromachined structures therein from damages.
- 2. Description of the Related Art
- Microelectromechanical structures (MEMS) have found applications in inertial measurement, pressure sensing, thermal measurement, micro-fluidics, optics, and radio frequency communications, and the application field for these structures continues to grow. Conventional microelectromechanical structures, such as accelerometers, pressure sensors, flow sensors, microactuators and the like, typically comprise suspended micromachined structures having a released portion spaced apart from a substrate and one or more posts attached the substrate.
- Generally, during fabrication of the micromachined structures, an uppermost patterned metal layer is used as an etching mask and an adequate etching process is performed to remove films not covered by the patterned metal layer to thereby form the micromachined structure.
- Nevertheless, in the above etching process, since the patterned metal layers show limited etch resistance during the etching process, the obtained micromachined structure may not be formed in a desired profile. Thus, portions of the film layers in the micromachined structure may be partially or entirely removed during the etching process, thereby negatively affecting functionality of the obtained MEMS device.
- Accordingly, a microelectromechanical system (MEMS) device and a method of fabricating the same for ensuring completeness of films in a micromachined structure in the MEMS device are provided to ensure functionality of the MEMS device.
- An exemplary method of fabricating a microelectromechanical system (MEMS) device comprises providing a semiconductor substrate comprising a semiconductor layer and an interconnect structure formed over the semiconductor layer. A passivation layer and a photoresist layer are sequentially formed over the interconnect structure. A plurality of openings is formed in the photoresist layer, wherein the openings expose a portion of the passivation layer. A first etching process is performed using the photoresist layer as an etching mask to remove the passivation layer exposed by the openings and the interconnect structure thereunder, and forms a plurality of first trenches exposing a portion of the semiconductor layer. The photoresist layer is removed to expose the passivation layer. A second etching process is performed using the passivation layer as an etching mask to remove a portion of the semiconductor layer exposed by the first trenches, and forms a plurality of second trenches in the semiconductor layer. An upper capping substrate is attached to the passivation layer to form a first composite substrate. A surface of the semiconductor layer of the first composite substrate in areas where the second trench is not formed, leaving a thinned semiconductor layer. A third etching process is performed to partially remove the thinned semiconductor layer and to form a third trench therein, wherein the third trench exposes and connects the second trenches, and a suspended micromachined structure is defined in a region between the first trench, the second trenches, and the third trench.
- An exemplary microelectromechanical system device comprises a semiconductor substrate comprising: a semiconductor layer and an interconnect structure formed over the semiconductor layer, wherein the semiconductor layer has opposing first and second sides, and the interconnect structure is formed over a surface of the semiconductor layer from the first side; a passivation layer disposed over the interconnect structure; a plurality of first trenches disposed in a portion of the passivation layer, the interconnect structure, and the semiconductor substrate; an upper capping substrate disposed over the passivation layer; a second trench disposed in a portion of the semiconductor layer from the second side, wherein the second trench exposes and connects with the first trenches, and the first trenches and the second trench defines a suspended micromachined structure therebetween; and a lower capping film attached to a surface of the semiconductor layer from the second side, wherein the upper capping substrate, the semiconductor substrate, and the lower capping substrate form a sealed chamber therebetween.
- A detailed description is given in the following embodiments with reference to the accompanying drawings.
- The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
-
FIGS. 1 a-1 g are cross sections showing a method of fabricating a microelectromechanical device according to an embodiment of the invention. - The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
-
FIGS. 1 a-1 g are cross sections showing an exemplary method for fabricating a microelectromechanical system (MEMS) device capable of ensuing a profile of film layers in micromachined structures therein and functionality of the MEMS device comprising the fabricated micromachined structures. - In
FIG. 1 a, asemiconductor substrate 10 is first provided. As shown inFIG. 1 a, thesemiconductor substrate 10 is an uncut semiconductor wafer having a plurality of substantially fabricated, but not separated, integrated circuit (IC) regions (not shown) thereover. For simplicity, only fabrication of a micromachined structure of a microelectromechanical system (MEMS) device in one of the IC regions is partially illustrated inFIG. 1 a. As shown inFIG. 1 a, the IC region provided over thesemiconductor substrate 10 comprises asemiconductor layer 100 and aninterconnect structure 101 formed over thesemiconductor layer 100. Herein, theinterconnect structure 101 comprises adielectric layer 102, a plurality ofconductive layers 104 disposed in various regions in thedielectric layer 102, and abond pad 106 disposed in thedielectric layer 102. Theconductive layers 104 are stacked over a same region from bottom to top. Thesemiconductor layer 100 can be, for example, a bulk silicon layer, and passive elements, active elements and other elements and/or combinations thereof can be formed at adequate places in or above thesemiconductor layer 100. In one embodiment, the passive elements can be, for example, resistors, capacitors, inductances and/or fuses, and the active elements can be, for example, p-channel field effect transistors (PFET), n-channel field effect transistors (NFET), metal-oxide-semiconductor field effect transistors (MOSFET), complementary metal oxide transistors (CMOS), high voltage transistors, and/or high frequency transistors. Thedielectric layer 102 may comprise dielectric materials such as silicon oxide or silicon nitride and may have a thickness of about 8-9 μm. - For the purpose of simplicity, the elements formed in the IC region shown in
FIG. 1 a are not illustrated, and only aplanar semiconductor layer 100 is illustrated. Although theinterconnect structure 101 is illustrated by a structure comprising theconductive layers 104 and thebond pad 106 disposed in thedielectric layer 102, the invention is not limited thereto. Other elements such as a plurality of interconnecting elements made of conductive elements comprising conductive layers and conductive vias can be further disposed in thedielectric layer 102 to electrically connect theconductive layers 104 and thebond pad 106 with the elements disposed in or above thesemiconductor layer 100. The above described layers and elements formed in or above thesemiconductor layer 100 and theinterconnect structure 101 can be fabricated by a standard complementary metal-oxide-semiconductor (CMOS) process, and fabrication thereof is not discussed here in detail, for simplicity. - Next, a
passivation layer 110 and aphotoresist layer 112 are blanketly formed over thedielectric layer 102. Herein, thepassivation layer 110 may comprise dielectric materials such as silicon oxide and has a thickness of about 0.8-1.0 μm. Thepassivation layer 110 and thedielectric layer 10 preferably comprise the same materials such that they may have a similar etching selectivity to an etchant. In addition, thephotoresist layer 112 may comprise photoresist materials typically used in fabrication of MEMS devices and may have a thickness of about 5˜15 μm. - In
FIG. 1 b, a photolithography process (not shown) is performed to form a plurality ofopenings 120 in thephotoresist layer 112. Theopenings 120, are respectively located over a portion of thedielectric layer 102 between theconductive layers 104 and partially expose a surface of a portion of thepassivation layer 110. Next, anetching process 130 is performed to remove thepassivation layer 110 and a portion of thedielectric layer 102 under thepassivation layer 110 exposed by theopenings 120, thereby forming a plurality oftrenches 132 in thedielectric layer 102. In one embodiment, theetching process 130 can be an anisotropic etching process such as a reactive ion etching (RIE) process. Herein, the etchants used in theetching process 130 not only removes thedielectric layer 102 but also partially removes a portion of thephotoresist layer 112, thereby leaving a thinnedphotoresist layer 112′ over thepassivation layer 110. Thetrenches 132 in thedielectric layer 102 expose a portion of thesemiconductor layer 100, and an included angle θ greater than 85° is provided between thedielectric layer 132 adjacent to thetrench 132 and thesemiconductor layer 100 to thereby ensure that each of thetrenches 132 has a profile substantially perpendicular to thesemiconductor layer 100. - In
FIG. 1 c, an etching process (not shown) is performed to remove the thinnedphotoresist layer 112′ over thepassivation layer 110, and anetching process 140 is then performed to remove a portion of thesemiconductor layer 100 exposed by the trenches 132 (seeFIG. 1 b), thereby forming a plurality oftrenches 142 in thesemiconductor layer 100. In theetching process 140, thepassivation layer 110 serves as an etch stop to prevent thedielectric layer 102 covered by thepassivation layer 110 from being etched in theetching process 140. Thetrenches 142 formed in thedielectric layer 102 have a depth Dl of about 20-50 μm from a top surface of thesemiconductor layer 100. In one embodiment, theetching process 140 can be as an anisotropic etching process such as a deep reactive ion etching (DRIE) process. - In
FIG. 1 d, anadhesive layer 152 is formed over portions over thepassivation layer 110. Theadhesive layer 152 may comprise adhesive materials such as frit. Anupper capping substrate 150 is then provided over thesemiconductor substrate 10 and then attached to thesemiconductor substrate 10 by use of theadhering layers 152, thereby forming acomposite substrate 200, as shown inFIG. 1 d. Herein, theupper capping substrate 150 may comprise a silicon or glass wafer. - In
FIG. 1 e, thecomposite substrate 200 shown inFIG. 1 d is inverted. A thinning process (not shown), such as a chemical mechanical polishing (CMP) process, is then performed to the surface of thesemiconductor layer 100 in areas no trench is formed by holding theupper capping substrate 150, thereby forming a thinnedsemiconductor layer 100′. Next, anetching process 160 is performed to form awide trench 162 in the thinnedsemiconductor layer 100′. In one embodiment, theetching process 160 can be an anisotropic etching process such as a deep reactive ion etching (DRIE) process. As shown inFIG. 1 e, thewide trench 162 substantially exposes and connects thetrenches 142 formed in the thinnedsemiconductor layer 100′. Thus, after formation of thewide trench 162, a suspended micromachined structure is defined and formed in aregion 164. Herein, the micromachined structure in theregion 164 comprises the thinnedsemiconductor layer 100′, thedielectric layer 102 and theconductive layers 104 formed in thedielectric layer 102. Theconductive layers 104 in thedielectric layer 102 are arranged in parallel and separated by thedielectric layer 102, such that the suspended micromachined structure in theregion 164 may function as a sensing capacitor. Functionality and structure of the suspended micromachined structure in theregion 164 is not limited by that shown inFIG. 1 e. To the contrary, the suspended micromachined structure in theregion 164 may have other structures and functionalities rather than that shown inFIG. 1 e. - As shown in
FIG. 1 f, the structure shown inFIG. 1 e is inverted and acutting process 170 is performed to expose thebond pad 106 formed in thedielectric layer 102. Herein, thecutting process 170 can be, for example, a laser cutting or a mechanical cutting process, and a portion of theupper capping substrate 150, thepassivation layer 110 and thedielectric layer 102 above thebond pad 106 are removed in thecutting process 170 until a surface of thebond pad 106 is exposed. - In
FIG. 1 g, alower capping film 180 is provided and attached to the surface of the thinnedsemiconductor layer 100′ where thewide trench 162 is formed. Thelower capping film 170 can be, for example, a die attached film (DAF). Thelower capping film 180 can be a dry film made of insulating materials such as a hot melt adhesive. Another composite substrate (not shown) is formed after attachment of thelower capping film 180 to thecomposite substrate 200. After formation of thelower capping substrate 180, a cutting process (not shown) such as a wafer cutting process is performed to the composite substrate to separate the composite structure made of theupper capping substrate 150, thesemiconductor substrate 10, and thelower capping film 180 into a plurality of independent microelectromechanical system (MEMS)device 300. As shown inFIG. 1 g, after formation of theMEMS device 300, a sealedchamber 182 is provided among the thinnedsemiconductor layer 110′, theupper capping substrate 150, and thelower capping substrate 180. The sealedchamber 182 is formed with an inner pressure of about 1 atm and thus provides a space for allowing suitable movement of the suspended micromachined structure provided in theregion 164 and ensures sensitivity of the micromachined structure. TheMEMS device 300 shown inFIG. 1 g can be then disposed over a package substrate (not shown) depending on process demands, and a bonding process such as a wire boding process can be performed to form a conductive wire bonding which connects the package substrate (not shown) with thebond pad 106 in theMEMS device 300, thereby forming electrical connection between theMEMS device 300 and the package substrate. - As shown in
FIG. 1 g, an exemplary MEMS device is illustrated, comprising a semiconductor substrate comprising a semiconductor layer (e.g. the thinnedsemiconductor layer 100′) and an interconnect structure (e.g. the interconnect structure) formed over the semiconductor layer, wherein the semiconductor layer has opposing first and second sides, and the interconnect structure is formed over a surface of the semiconductor layer at the first side. A passivation layer (e.g. the passivation layer 110) is disposed over the interconnect structure. A plurality of first trenches (e.g. combination of thetrenches 132 and 142) are respectively disposed in a portion of the passivation layer, the interconnect structure, and the semiconductor substrate. An upper capping substrate (e.g. the upper capping substrate 150) is disposed over the passivation layer. A second trench (e.g. thewide trench 162 shown inFIG. 1 e) is disposed in a portion of the semiconductor layer at the second side, wherein the second trench exposes and connects with the first trenches, and the first trenches and the second trench defines a suspended micromachined structure (e.g. the suspended micromachined structure in the region 164) therebetween. A lower capping film (e.g. the lower capping film 180) is attached to a surface of the semiconductor layer from the second side, wherein the upper capping substrate, the semiconductor substrate, and the lower capping substrate form a sealed chamber (e.g. the sealed chamber 182) therebetween. - Based on the exemplary fabrication method illustrated in
FIGS. 1 a-1 g and the exemplary MEMS device shown inFIG. 1 g, an improved fabrication method is provided by the invention by using an additional passivation layer and a photoresist layer as etching masks for ensuring a profile of films of a micromachined structure in a MEMS device. Reliability of a MEMS device comprising such a micromachined structure fabricated by the improved method can thus be ensured. - In addition, since fabrication of the exemplary MEMS device can be achieved by wafer level fabrication and packaging processes, the micromachined structure and the integrated circuit elements used in the MEMS device can be simultaneously fabricated and no additional packaging process is needed. Therefore, a majority of the fabricating processes of the MEMS device can be completed in an IC foundry and transported to a packaging company for wafer cutting, such that fabrication costs of an MEMS device can thus be reduced.
- While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Claims (18)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW99101593 | 2010-01-21 | ||
TW99101593A | 2010-01-21 | ||
TW099101593A TWI392641B (en) | 2010-01-21 | 2010-01-21 | Microelectromechanical system (mems) device and methods for fabricating the same |
Publications (2)
Publication Number | Publication Date |
---|---|
US20110175177A1 true US20110175177A1 (en) | 2011-07-21 |
US8129805B2 US8129805B2 (en) | 2012-03-06 |
Family
ID=44276959
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/759,845 Active 2030-10-29 US8129805B2 (en) | 2010-01-21 | 2010-04-14 | Microelectromechanical system (MEMS) device and methods for fabricating the same |
Country Status (2)
Country | Link |
---|---|
US (1) | US8129805B2 (en) |
TW (1) | TWI392641B (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130091949A1 (en) * | 2011-10-12 | 2013-04-18 | Richwave Technology Corp. | Piezoresistive type z-axis accelerometer |
CN105336686A (en) * | 2015-09-30 | 2016-02-17 | 中国电子科技集团公司第五十五研究所 | Cutting method of composite structure SiC substrate device |
KR20160054415A (en) * | 2014-11-06 | 2016-05-16 | 후지제롯쿠스 가부시끼가이샤 | Method for manufacturing semiconductor piece |
US9589812B2 (en) | 2014-11-06 | 2017-03-07 | Fuji Xerox Co., Ltd. | Fabrication method of semiconductor piece |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2017054861A (en) | 2015-09-07 | 2017-03-16 | 株式会社東芝 | Method of manufacturing semiconductor device |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5316979A (en) * | 1992-01-16 | 1994-05-31 | Cornell Research Foundation, Inc. | RIE process for fabricating submicron, silicon electromechanical structures |
US6712983B2 (en) * | 2001-04-12 | 2004-03-30 | Memsic, Inc. | Method of etching a deep trench in a substrate and method of fabricating on-chip devices and micro-machined structures using the same |
US20100044147A1 (en) * | 2008-08-21 | 2010-02-25 | United Microelectronics Corp. | Microelectromechanical system diaphragm and fabricating method thereof |
US7951636B2 (en) * | 2008-09-22 | 2011-05-31 | Solid State System Co. Ltd. | Method for fabricating micro-electro-mechanical system (MEMS) device |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI334734B (en) * | 2006-06-20 | 2010-12-11 | Ind Tech Res Inst | Miniature acoustic transducer |
TWI490900B (en) * | 2008-02-04 | 2015-07-01 | 微智半導體股份有限公司 | Capacitor compensation structure and a method for an micro electro-mechanical system |
-
2010
- 2010-01-21 TW TW099101593A patent/TWI392641B/en active
- 2010-04-14 US US12/759,845 patent/US8129805B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5316979A (en) * | 1992-01-16 | 1994-05-31 | Cornell Research Foundation, Inc. | RIE process for fabricating submicron, silicon electromechanical structures |
US6712983B2 (en) * | 2001-04-12 | 2004-03-30 | Memsic, Inc. | Method of etching a deep trench in a substrate and method of fabricating on-chip devices and micro-machined structures using the same |
US20100044147A1 (en) * | 2008-08-21 | 2010-02-25 | United Microelectronics Corp. | Microelectromechanical system diaphragm and fabricating method thereof |
US7951636B2 (en) * | 2008-09-22 | 2011-05-31 | Solid State System Co. Ltd. | Method for fabricating micro-electro-mechanical system (MEMS) device |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130091949A1 (en) * | 2011-10-12 | 2013-04-18 | Richwave Technology Corp. | Piezoresistive type z-axis accelerometer |
TWI477780B (en) * | 2011-10-12 | 2015-03-21 | Richwave Technology Corp | Piezoresistive type z-axis accelerometer |
US9052332B2 (en) * | 2011-10-12 | 2015-06-09 | Richwave Technology Corp. | Piezoresistive type Z-axis accelerometer |
KR20160054415A (en) * | 2014-11-06 | 2016-05-16 | 후지제롯쿠스 가부시끼가이샤 | Method for manufacturing semiconductor piece |
US9589812B2 (en) | 2014-11-06 | 2017-03-07 | Fuji Xerox Co., Ltd. | Fabrication method of semiconductor piece |
TWI622096B (en) * | 2014-11-06 | 2018-04-21 | 富士全錄股份有限公司 | Fabrication method of semiconductor piece |
KR102024697B1 (en) * | 2014-11-06 | 2019-09-24 | 후지제롯쿠스 가부시끼가이샤 | Method for manufacturing semiconductor piece |
CN105336686A (en) * | 2015-09-30 | 2016-02-17 | 中国电子科技集团公司第五十五研究所 | Cutting method of composite structure SiC substrate device |
Also Published As
Publication number | Publication date |
---|---|
TW201125807A (en) | 2011-08-01 |
US8129805B2 (en) | 2012-03-06 |
TWI392641B (en) | 2013-04-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10508029B2 (en) | MEMS integrated pressure sensor devices and methods of forming same | |
US8962367B2 (en) | MEMS device with release aperture | |
US9511997B2 (en) | MEMS device with a capping substrate | |
US9187317B2 (en) | MEMS integrated pressure sensor and microphone devices and methods of forming same | |
US8735260B2 (en) | Method to prevent metal pad damage in wafer level package | |
CN109553065B (en) | MEMS device and packaging method of MEMS | |
US8252695B2 (en) | Method for manufacturing a micro-electromechanical structure | |
US20130134599A1 (en) | Method and structure of integrated micro electro-mechanical systems and electronic devices using edge bond pads | |
JP2014523815A (en) | Process for a sealed MEMS device comprising a portion exposed to the environment | |
US9799588B2 (en) | Chip package and manufacturing method thereof | |
TWI770030B (en) | Method and system for mems devices with dual damascene formed electrodes | |
KR20160106754A (en) | Micromechanical pressure sensor and corresponding production method | |
US8129805B2 (en) | Microelectromechanical system (MEMS) device and methods for fabricating the same | |
TW201725170A (en) | MEMS structure and manufacturing method thereof | |
US9064950B2 (en) | Fabrication method for a chip package | |
US8193640B2 (en) | MEMS and a protection structure thereof | |
CN108117034B (en) | MEMS component and manufacturing method thereof | |
US7323355B2 (en) | Method of forming a microelectronic device | |
US20130168784A1 (en) | Semiconductor package and fabrication method thereof | |
CN102145874B (en) | Micro-electro-mechanical device and manufacturing method thereof | |
CN102234098B (en) | Manufacturing method of micro electromechanical structure |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: RICHWAVE TECHNOLOGY CORP., TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LIOU, TSYR-SHYANG;REEL/FRAME:024230/0111 Effective date: 20100406 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YR, SMALL ENTITY (ORIGINAL EVENT CODE: M2552); ENTITY STATUS OF PATENT OWNER: SMALL ENTITY Year of fee payment: 8 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YR, SMALL ENTITY (ORIGINAL EVENT CODE: M2553); ENTITY STATUS OF PATENT OWNER: SMALL ENTITY Year of fee payment: 12 |