US20110147796A1 - Semiconductor device with metal carrier and manufacturing method - Google Patents
Semiconductor device with metal carrier and manufacturing method Download PDFInfo
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- US20110147796A1 US20110147796A1 US12/641,130 US64113009A US2011147796A1 US 20110147796 A1 US20110147796 A1 US 20110147796A1 US 64113009 A US64113009 A US 64113009A US 2011147796 A1 US2011147796 A1 US 2011147796A1
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0626—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a localised breakdown region, e.g. built-in avalanching region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4871—Bases, plates or heatsinks
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- FETs Field Effect Transistors
- HEMTs High Electron Mobility Transistors
- Examples for requirements on these devices are low area specific on-resistance R ON ⁇ A, high breakdown voltage V BR , and high robustness under electrical breakdown conditions.
- Power semiconductor devices based on wide band gap semiconductor materials such as GaN allow for low specific on-resistance. Reduction of the specific on-resistance is accompanied by requirements on improved heat dissipation and improved device robustness.
- FIG. 1A is a cross-sectional view illustrating one embodiment of a semiconductor device including a portion of a nitride semiconductor power device including a carrier substrate made of metal.
- FIG. 1B is a cross-sectional view illustrating one embodiment of a semiconductor device including a portion of a nitride semiconductor power device including a carrier substrate made of metal and source regions electrically coupled to a contact pad arranged on top of an active area of the device.
- FIG. 2 is a cross-sectional view illustrating one embodiment of a semiconductor device including a portion of a nitride semiconductor power device including a carrier substrate made of metal and a doped nitride semiconductor layer for fixing avalanche breakdown.
- FIG. 3 is a cross-sectional view illustrating one embodiment of a semiconductor device including a portion of a nitride semiconductor power device including a doped nitride semiconductor zone for fixing avalanche breakdown.
- FIG. 4 is a cross-sectional view illustrating one embodiment of a semiconductor device including a portion of a nitride semiconductor power device including doped nitride semiconductor zones of same conductivity type for fixing avalanche breakdown.
- FIG. 5 is a cross-sectional view illustrating one embodiment of a semiconductor device including a portion of a nitride semiconductor power device including doped nitride semiconductor zones of different conductivity type for fixing avalanche breakdown.
- FIG. 6 is a cross-sectional view illustrating one embodiment of a semiconductor device including a portion of a nitride semiconductor power device including a doped nitride semiconductor zone and a trench contact for fixing avalanche breakdown.
- FIG. 7 is a simplified flowchart illustrating one embodiment of a method for manufacturing a nitride semiconductor power device according to an embodiment.
- FIGS. 8A to 8E are cross-sectional views illustrating one embodiment of a semiconductor portion during manufacture of a nitride semiconductor power device similar to the one illustrated in FIG. 1A .
- FIGS. 9A to 9C are cross-sectional views illustrating one embodiment of a semiconductor portion during manufacture of the nitride semiconductor power device illustrated in FIG. 2 .
- FIG. 10A to 10D are cross-sectional views illustrating one embodiment of a semiconductor portion during manufacture of a nitride semiconductor power device similar to the ones illustrated in FIGS. 3 to 6 .
- FIG. 1A illustrates one embodiment of a schematic cross-sectional view of a semiconductor device, in one embodiment a portion of a lateral channel HEMT 100 .
- HEMT 100 includes a carrier substrate 105 made of metal, e.g. Cu.
- carrier substrate 105 On carrier substrate 105 , an optional buffer layer 110 such as an MN buffer layer is arranged.
- Source regions 125 a , 125 b and drain region 130 are electrically coupled to the second semiconductor layer 120 .
- Gate regions 135 a . . . 135 d are arranged on the second semiconductor layer 120 .
- the gate regions 135 a . . . 135 d may include metal and/or conductive semiconductor material such as doped polysilicon or p-doped GaN.
- the gate regions 135 a . . . 135 d may also include additional dielectric layers below the conductive gate region, e.g. similar to a MISFET (Metal-Insulator-FET).
- MISFET Metal-Insulator-FET
- Source region 125 a and drain region 130 may be controlled by applying a voltage to the gate regions 135 a . . . 135 d , e.g. gate region 135 b .
- An insulating layer 140 e.g. a Si 3 N 4 or SiO 2 layer, is formed on the second semiconductor layer 120 .
- the drain region 130 which may include one or several conductive parts formed of metal such as Ti/Al or doped semiconductor material, is electrically coupled to the carrier substrate 105 and includes a conductive part extending through the second semiconductor layer 120 , the first semiconductor layer 115 and the buffer layer 110 to the carrier substrate 105 .
- the source regions 125 a , 125 b are electrically coupled to a contact area, e.g. a contact pad, at the front side. This contact pad may also be formed as part of a multi-metal layer system arranged on top of the active area of the device.
- the source regions are electrically coupled to the carrier substrate at a rear side and the drain regions are electrically coupled to a contact area, e.g. a contact pad, at the front side.
- a thickness of the carrier substrate 105 is appropriately chosen to provide mechanical stability to the layer stack arranged thereon.
- the carrier substrate supports dissipation of heat generated in the device arranged thereon in an operation mode of the device.
- the thickness of a carrier substrate 105 made of Cu may be between 15 ⁇ m to 50 ⁇ m, in particular between 30 ⁇ m to 40 ⁇ m.
- a metal layer of a same or different material than carrier substrate 105 may also be formed on the front side opposite to the rear side where the carrier substrate 105 is formed. In this case, each one of the carrier substrate at the rear side and the metal layer at the front side may contribute to the mechanical stability and may each have a thickness between 10 ⁇ m to 40 ⁇ m, in one embodiment between 20 to 30 ⁇ m.
- the metal carrier substrate(s) improve dissipation of heat during operation mode of the power semiconductor device(s) formed thereon. Omitting the buffer layer 110 may improve heat dissipation since this buffer layer which supports growth of GaN layers on initial silicon substrates may decrease heat dissipation due to a high thermal boundary resistance.
- FIG. 1B illustrates a cross-sectional view of one embodiment of a semiconductor device including a portion of a lateral channel HEMT 100 that differs from the embodiment illustrated in FIG. 1A in that the source regions 125 a , 125 b are electrically coupled to a contact area, e.g. a contact pad 155 at the front side.
- the contact pad 155 is formed as part of a multi- or single-metal layer system including metals such as Cu arranged on top of the active area of the device.
- buffer layer 110 illustrated in FIG. 1A is omitted to improve heat dissipation as described above.
- An interlayer dielectric 160 may be provided to electrically insulate conductive regions from each other.
- FIG. 2 is a cross-sectional view illustrating one embodiment of a semiconductor device including a portion of a lateral channel HEMT 200 .
- the third semiconductor layer 245 is in contact with the first semiconductor layer 215 and includes an average concentration of dopants higher than 10 17 cm ⁇ 3 .
- a vertical avalanche breakdown voltage between the second semiconductor layer 220 , the first semiconductor layer 215 and the third semiconductor layer is set smaller than the lateral breakdown voltage between gate, e.g. gate region 235 d , and drain, e.g. drain region 230 .
- gate e.g. gate region 235 d
- drain e.g. drain region 230 .
- a channel region of HEMT 200 located at an interface 250 between the first semiconductor layer 215 and the second semiconductor layer 220 may be prevented from damage due to hot carrier degradation or other electrical stress mechanisms.
- a distance 1 between gate, e.g. gate region 235 b , and drain, e.g. drain region 230 , along a lateral direction 255 may be set larger than a thickness d of the first semiconductor layer 215 along a vertical direction 260 extending perpendicular to the lateral direction 255 .
- the concentration of dopants of the third semiconductor layer 245 may be chosen high enough to provide a beneficial ohmic contact to the carrier substrate 205 , e.g. higher than 10 17 cm ⁇ 3 , higher than 10 18 cm ⁇ 3 or even higher than 10 19 cm ⁇ 3 .
- a conductivity type of the third semiconductor layer 245 may equal the conductivity type of the second semiconductor layer 220 , e.g. both conductivity types being n-type or p-type.
- the conductivity type of the third semiconductor layer 245 may differ from the conductivity type of the second semiconductor layer 220 , e.g. the conductivity type of the third semiconductor layer 245 being p-type and the conductivity type of the second semiconductor layer being n-type.
- FIG. 3 is a cross-sectional view illustrating one embodiment of a semiconductor device including a portion of a lateral channel HEMT 300 .
- HEMT 300 includes a carrier substrate 305 made of metal, e.g. Cu, doped Si such as n + -type Si, SiC or GaN, for example.
- carrier substrate 305 On carrier substrate 305 , a third semiconductor layer 345 is arranged.
- Third semiconductor layer 345 can be similar to third semiconductor layer 245 illustrated in FIG. 2 .
- the carrier substrate 305 and the third semiconductor layer 345 constitute a drain of HEMT 300 .
- first semiconductor layer 315 similar to first semiconductor layers 115 , 215 illustrated in FIGS. 1A and 2 is arranged.
- a second semiconductor layer 320 of Al x2 Ga y2 In z2 N (x2+y2+z2 1, x2>x1, y2 ⁇ 0, z2 ⁇ 0), e.g. AlGaN, is arranged.
- the second semiconductor layer 320 may be in the shape of stripes, columns, rings, hexagons, octagons and complementary structures, for example.
- Gate regions 335 a , 335 b are arranged on the second semiconductor layer 320 .
- the gate regions 335 a , 335 b may include metal and/or conductive semiconductor material such as doped polysilicon.
- the gate regions 335 a , 335 b may be congruent with the second semiconductor layer 320 .
- Source regions 325 a , 325 b are embedded in the first semiconductor layer 315 , the source regions including a concentration of dopants higher than 10 17 cm ⁇ 3 .
- the source regions 325 a , 325 b may be self-aligned to the second semiconductor layer 320 and the gate regions 325 a , 325 b.
- a drift region 365 including a concentration of activated dopants higher than 10 14 cm ⁇ 3 extends through the first semiconductor layer 315 . If the device is turned ON, the drift region provides a conductive path between the third semiconductor layer 345 and a channel region located at an interface 350 between the first semiconductor layer 315 and the second semiconductor layer 320 . If the device is turned OFF, the drift region is partly depleted and contributes to the electrical isolation between source and drain. Shape and doping profile of the drift region may be chosen accordingly.
- the drift region 365 may include one doped semiconductor zone or a plurality of doped semiconductor zones overlapping each other in the vertical direction 360 .
- an average concentration within each of these zones may decrease in a direction from the third semiconductor layer 345 to the second semiconductor layer 320 , for example, such as n ⁇ -type zone 366 and n-type zone 367 illustrated in FIG. 3 .
- the conductivity between source and drain i.e. between source region 325 a and drift region 365 , may be controlled by applying a voltage to the gate, i.e. gate region 335 a .
- An insulating layer 340 e.g. a SiN or SiO 2 layer, is formed on the second semiconductor layer 320 and the source regions 325 a , 325 b .
- Contact plugs 370 a , 370 b are formed within apertures of the insulating layer 340 and electrically couple the source regions 325 a , 325 b to a wiring level 375 , e.g. a metal layer.
- First avalanche regions 380 a , 380 b are formed within the first semiconductor layer 315 , the first avalanche regions 380 a , 380 b being arranged opposite to the source, e.g. source regions 325 a , 325 b .
- the first avalanche regions 380 a , 380 b are in contact with the third semiconductor layer 345 and include an average concentration of activated dopants higher than 10 17 cm ⁇ 3 .
- a vertical avalanche breakdown voltage between source, e.g. source region 325 a , and drain, e.g. third semiconductor layer 345 is set smaller than the lateral breakdown voltage between gate, e.g. gate region 335 b , and the drift zone 365 , e.g. by appropriate choice of dimensions and dopant concentrations of first avalanche regions 380 a , 380 b .
- a channel region of HEMT 300 located at the interface 250 between the first semiconductor layer 315 and the second semiconductor layer 320 may be prevented from damage by hot carrier degradation or other electrical stress mechanisms.
- a distance l 1 between source, e.g. source region 325 a , and an undepleted part of the drift region 365 along a lateral direction 355 may be set larger than a distance l 2 between a top side of the first avalanche regions, e.g. first avalanche region 380 a , and a bottom side of the source, e.g. source region 325 a , along a vertical direction 360 extending perpendicular to the lateral direction 355 .
- a threshold voltage Vth of HEMT 300 may be adjusted by choice of the gate material, the thickness of the second semiconductor layer 320 , the concentration of dopants within the second semiconductor layer 320 and piezo-electric effects, for example.
- HEMT 300 may be a depletion mode transistor (Vth ⁇ 0V) or an enhancement mode transistor (Vth>0V).
- Source regions 325 a , 325 b , drift region 365 and first avalanche regions 380 a , 380 b may be formed by implanting dopants such as Si, Ge or O into the first semiconductor layer 315 , for example. These regions may also be formed by epitaxial regrowth, for example. These regions may also have a same conductivity type, e.g. an n-type.
- HEMT 300 exhibits an improved avalanche robustness.
- both of them may be electrically coupled at a front side and the avalanche regions 380 a , 380 b may be electrically coupled to a contact region at a front side of the semiconductor device via the carrier substrate, a lead frame and a bond wire.
- FIG. 4 is a cross-sectional view illustrating one embodiment of a semiconductor device including a portion of a lateral channel HEMT 400 .
- HEMT 400 differs from HEMT 300 illustrated in FIG. 3 in that second avalanche regions 482 a , 482 b are provided, the second avalanche regions 482 a , 482 b being arranged opposite to the first avalanche regions 480 a , 480 b .
- a conductivity type of the second avalanche regions 482 a , 482 b equals the conductivity type of the first avalanche regions.
- Dimensions and concentration of dopants of the second avalanche regions may be similar to the first avalanche regions 480 a , 480 b.
- a vertical avalanche breakdown voltage between source, e.g. source region 425 a , and drain, e.g. third semiconductor layer 445 is set smaller than the lateral breakdown voltage between gate, e.g. gate region 435 b , and the drift region 465 , e.g. by appropriate choice of dimensions and dopant concentrations of the first and second avalanche regions 480 a , 480 b , 482 a , 482 b .
- a distance l i between source e.g.
- a channel region of HEMT 400 located at the interface 450 between the first semiconductor layer 415 and the second semiconductor layer 420 may be prevented from damage by hot carrier degradation or other electrical stress mechanisms.
- FIG. 5 is a cross-sectional view illustrating one embodiment of a semiconductor device including a portion of a lateral channel HEMT 500 .
- HEMT 500 differs from HEMT 400 illustrated in FIG. 4 in that the second avalanche regions 582 a , 582 b are of opposite conductivity type than the first avalanche regions 580 a , 580 b .
- the second avalanche regions 582 a , 582 b are of p + -type and the first avalanche regions 580 a , 580 b are of n + -type.
- This arrangement is beneficial with regard to efficient discharge of avalanche current flowing into the second avalanche regions 582 a , 582 b , since this avalanche current is a hole current flowing into a p + -type region.
- this avalanche current is a hole current flowing into a p + -type region.
- the hole avalanche current will be injected into these regions and the injected holes will recombine within these regions.
- recombination centers may be formed within the second avalanche regions 582 a , 582 , 482 a , 482 b and/or below a bottom side of these regions to enhance recombination of injected carriers in avalanche breakdown operation.
- FIG. 6 is a cross-sectional view illustrating one embodiment of a semiconductor device including a portion of a lateral channel HEMT 600 .
- HEMT 600 differs from HEMT 400 illustrated in FIG. 4 in that the first avalanche regions 482 a , 482 b are omitted and the contact plugs 670 a , 670 b partly extend into the source regions 625 a , 625 b and the second avalanche regions 682 a , 682 b as trench contacts.
- a vertical avalanche breakdown voltage between source, e.g. source region 625 a , and drain, e.g. third semiconductor layer 645 is set smaller than the lateral breakdown voltage between source, e.g. source region 625 a , and the undepleted part of the drift zone 665 , e.g. by appropriate choice of dimensions and dopant concentrations of the second avalanche regions 682 a , 682 b and the trench contacts.
- a distance l 1 between source e.g.
- drift region 665 along a lateral direction 655 may be set larger than a distance l 2 between the second avalanche regions 682 a , 682 b and the third semiconductor layer 645 along a vertical direction 660 extending perpendicular to the lateral direction 655 .
- FIG. 7 illustrates a simplified flowchart of a method for manufacturing a nitride semiconductor power device according to one embodiment.
- the semiconductor carrier substrate is removed from the rear side.
- a metal substrate carrier is formed on the rear side.
- the metal substrate carrier improves dissipation of heat generated during operation of a nitride semiconductor power device formed thereon.
- FIGS. 8A to 8E are cross-sectional views illustrating one embodiment of a semiconductor device including a semiconductor portion, during one example of manufacture of a nitride semiconductor power device similar to the one illustrated in FIG. 1A .
- Source regions 825 a , 825 b and a drain region 830 are electrically coupled to the second semiconductor layer 820 .
- Gate regions 835 a . . . 835 d are arranged on the second semiconductor layer 820 .
- the gate regions 135 a . . . 135 d may include metal and/or
- An insulating layer 140 e.g. a SiN or SiO 2 layer, is formed on the second semiconductor layer 120 .
- the semiconductor body 800 is attached with its front side to a first carrier 880 , e.g. a glass carrier or a metal carrier. Between the carrier 880 and the semiconductor body 800 , an adhesive 882 may be provided. Then the semiconductor carrier substrate 803 is removed, e.g. by grinding or etching. Removal of the semiconductor carrier substrate 803 may be purely mechanical with a stop on the buffer layer 810 or may start with a mechanical removal process followed by an etching process.
- a first carrier 880 e.g. a glass carrier or a metal carrier.
- an adhesive 882 may be provided.
- the semiconductor carrier substrate 803 is removed, e.g. by grinding or etching. Removal of the semiconductor carrier substrate 803 may be purely mechanical with a stop on the buffer layer 810 or may start with a mechanical removal process followed by an etching process.
- a seed layer 885 such as a Cu seed layer may be formed on the buffer layer 810 at a rear side of the semiconductor body 800 .
- the seed layer 885 may be formed by sputtering, for example, and also covers a bottom side of the drain region 830 extending through an insulating layer 840 , the second semiconductor layer 820 , the first semiconductor layer 815 and the buffer layer 810 .
- a metal is formed on the seed layer 885 , e.g. by plating of Cu, to form a metal carrier substrate 810 .
- the seed layer 885 may also be omitted and the metal, metal alloy or plurality of metal/metal alloys of the metal carrier substrate 810 may be formed on the buffer layer 810 .
- the semiconductor body 800 is attached, e.g. laminated, to a sawing foil 888 and the first carrier 880 as well as the adhesive 882 are released.
- nitride semiconductor power device including a metal substrate carrier for improved dissipation of heat during operation of the nitride semiconductor power device.
- FIGS. 9A to 9C are cross-sectional views of one embodiment of a semiconductor portion during one example of manufacture of the nitride semiconductor power device similar to the one illustrated in FIG. 2 .
- the semiconductor body 900 is attached with its front side to a first carrier 980 , e.g. a glass carrier or a metal carrier. Between the carrier 980 and the semiconductor body 900 , an adhesive 982 may be provided.
- the semiconductor carrier substrate 903 is removed, e.g. by grinding or etching. Removal of the semiconductor carrier substrate 903 may be purely mechanical with a stop on the buffer layer 910 or may start with a mechanical removal process followed by an etching process.
- the buffer layer 910 is removed, e.g. by plasma etching.
- the third semiconductor layer 945 is exposed at a rear side of the semiconductor body 900 .
- a seed layer 985 similar to the seed layer 885 described with reference to FIG. 8C is formed.
- the seed layer may also be a multi-layer metal stack for low ohmic contact purposes.
- the seed layer may be thickened by a metal or metal alloy and further processes may be carried out to end up with to a nitride semiconductor power device as illustrated in FIG. 2 .
- FIG. 10A to 10D are cross-sectional views illustrating one embodiment of a semiconductor device including a semiconductor portion during one example of manufacture of a nitride semiconductor power device similar to the ones illustrated in FIGS. 3 to 6 .
- FIGS. 10A to 10D illustrate one embodiment of formation of a lowermost zone of the doped drift region.
- an aperture 191 is formed within the first semiconductor layer 165 , e.g. by patterning a hard mask 198 on the first semiconductor layer 165 and etching through the first semiconductor layer 165 via the hard mask 198 .
- a lowermost nitride semiconductor zone of the drift region 181 is formed within aperture 191 by selective epitaxy.
- This zone 181 may be doped in-situ to include a concentration of activated dopants higher than the first semiconductor layer 165 .
- a top surface of the lowermost nitride semiconductor zone of the drift region 181 is made planar, e.g. by chemical mechanical polishing (CMP). Thereby the hard mask 198 may be removed.
- a barrier layer 199 may be formed on the surface of the leveled surface.
- a continuous semiconductor region may be formed by a plurality of semiconductor zones in contact with each other, wherein the semiconductor zones may differ with regard to their dopant concentration.
- a desired vertical dopant profile may be achieved, for example.
- a drift region may be formed by a plurality of doped semiconductor zones having different concentrations of dopants such that the concentration of dopants decreases from a rear side, i.e. at an interface with the third semiconductor layer 195 , to the front side, cf. drift region 365 including zone 366 and 367 illustrated in FIG. 3 .
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Abstract
Semiconductor device including a metal carrier substrate. Above the carrier substrate a first semiconductor layer of Alx1Gay1Inz1N (x1+y1+z1=1, x1≧0, y1≧0, z1≧0) is formed. A second semiconductor layer of Alx2Gay2Inz2N (x2+y2+z2=1, x2>x1, y2≧0, z2≧0) is arranged on the first semiconductor layer and a gate region is arranged on the second semiconductor layer. The semiconductor device furthermore includes a source region and a drain region, wherein one of these regions is electrically coupled to the metal carrier substrate and includes a conductive region extending through the first semiconductor layer.
Description
- Power semiconductor devices such as Field Effect Transistors (FETs) and High Electron Mobility Transistors (HEMTs) are widely used for applications such as power switch circuits. Examples for requirements on these devices are low area specific on-resistance RON×A, high breakdown voltage VBR, and high robustness under electrical breakdown conditions.
- Power semiconductor devices based on wide band gap semiconductor materials such as GaN allow for low specific on-resistance. Reduction of the specific on-resistance is accompanied by requirements on improved heat dissipation and improved device robustness.
- A need exists for a nitride semiconductor power device having improved heat dissipation and improved device robustness
- For these and other reasons there is a need for the present invention.
- The accompanying drawings are included to provide a further understanding of embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments and together with the description serve to explain principles of embodiments. Other embodiments and many of the intended advantages of embodiments will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts. The features of the various illustrated embodiments can be combined in any way unless they exclude each other. For differentiation of different layers, a numbering such as first layer, second layer and third layer is used. The numbering only serves to distinguish between these layers and is independent from any sequence of manufacture.
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FIG. 1A is a cross-sectional view illustrating one embodiment of a semiconductor device including a portion of a nitride semiconductor power device including a carrier substrate made of metal. -
FIG. 1B is a cross-sectional view illustrating one embodiment of a semiconductor device including a portion of a nitride semiconductor power device including a carrier substrate made of metal and source regions electrically coupled to a contact pad arranged on top of an active area of the device. -
FIG. 2 is a cross-sectional view illustrating one embodiment of a semiconductor device including a portion of a nitride semiconductor power device including a carrier substrate made of metal and a doped nitride semiconductor layer for fixing avalanche breakdown. -
FIG. 3 is a cross-sectional view illustrating one embodiment of a semiconductor device including a portion of a nitride semiconductor power device including a doped nitride semiconductor zone for fixing avalanche breakdown. -
FIG. 4 is a cross-sectional view illustrating one embodiment of a semiconductor device including a portion of a nitride semiconductor power device including doped nitride semiconductor zones of same conductivity type for fixing avalanche breakdown. -
FIG. 5 is a cross-sectional view illustrating one embodiment of a semiconductor device including a portion of a nitride semiconductor power device including doped nitride semiconductor zones of different conductivity type for fixing avalanche breakdown. -
FIG. 6 is a cross-sectional view illustrating one embodiment of a semiconductor device including a portion of a nitride semiconductor power device including a doped nitride semiconductor zone and a trench contact for fixing avalanche breakdown. -
FIG. 7 is a simplified flowchart illustrating one embodiment of a method for manufacturing a nitride semiconductor power device according to an embodiment. -
FIGS. 8A to 8E are cross-sectional views illustrating one embodiment of a semiconductor portion during manufacture of a nitride semiconductor power device similar to the one illustrated inFIG. 1A . -
FIGS. 9A to 9C are cross-sectional views illustrating one embodiment of a semiconductor portion during manufacture of the nitride semiconductor power device illustrated inFIG. 2 . -
FIG. 10A to 10D are cross-sectional views illustrating one embodiment of a semiconductor portion during manufacture of a nitride semiconductor power device similar to the ones illustrated inFIGS. 3 to 6 . - In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top,” “bottom,” “front,” “back,” “leading,” “trailing,” etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
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FIG. 1A illustrates one embodiment of a schematic cross-sectional view of a semiconductor device, in one embodiment a portion of a lateral channel HEMT 100. HEMT 100 includes acarrier substrate 105 made of metal, e.g. Cu. Oncarrier substrate 105, anoptional buffer layer 110 such as an MN buffer layer is arranged. Onbuffer layer 110, afirst semiconductor layer 115 of Alx1Gay1Inz1N (x1+y1+z1=1, x1≧0, y z1≧0), e.g. intrinsic GaN or GaN including at least one of Fe, C, Mg, in a concentration smaller than 5×1017 cm−3, or smaller 1018 cm−3 or smaller than 5×1018 cm−3 is arranged. On thefirst semiconductor layer 115, asecond semiconductor layer 120 of Alx2Gay2Inz2N (x2+y2+z2=1, x2>x1, y2≧0, z2≧0), e.g. AlGaN or InGaN, is arranged, either doped or undoped, optionally capped with a thin layer of GaN. -
Source regions drain region 130 are electrically coupled to thesecond semiconductor layer 120.Gate regions 135 a . . . 135 d are arranged on thesecond semiconductor layer 120. Thegate regions 135 a . . . 135 d may include metal and/or conductive semiconductor material such as doped polysilicon or p-doped GaN. Thegate regions 135 a . . . 135 d may also include additional dielectric layers below the conductive gate region, e.g. similar to a MISFET (Metal-Insulator-FET). The conductivity between source and drain, e.g. betweensource region 125 a anddrain region 130, may be controlled by applying a voltage to thegate regions 135 a . . . 135 d,e.g. gate region 135 b. Aninsulating layer 140, e.g. a Si3N4 or SiO2 layer, is formed on thesecond semiconductor layer 120. - The
drain region 130, which may include one or several conductive parts formed of metal such as Ti/Al or doped semiconductor material, is electrically coupled to thecarrier substrate 105 and includes a conductive part extending through thesecond semiconductor layer 120, thefirst semiconductor layer 115 and thebuffer layer 110 to thecarrier substrate 105. Thesource regions - A thickness of the
carrier substrate 105 is appropriately chosen to provide mechanical stability to the layer stack arranged thereon. In addition, the carrier substrate supports dissipation of heat generated in the device arranged thereon in an operation mode of the device. As an example, the thickness of acarrier substrate 105 made of Cu may be between 15 μm to 50 μm, in particular between 30 μm to 40 μm. A metal layer of a same or different material thancarrier substrate 105 may also be formed on the front side opposite to the rear side where thecarrier substrate 105 is formed. In this case, each one of the carrier substrate at the rear side and the metal layer at the front side may contribute to the mechanical stability and may each have a thickness between 10 μm to 40 μm, in one embodiment between 20 to 30 μm. The metal carrier substrate(s) improve dissipation of heat during operation mode of the power semiconductor device(s) formed thereon. Omitting thebuffer layer 110 may improve heat dissipation since this buffer layer which supports growth of GaN layers on initial silicon substrates may decrease heat dissipation due to a high thermal boundary resistance. -
FIG. 1B illustrates a cross-sectional view of one embodiment of a semiconductor device including a portion of alateral channel HEMT 100 that differs from the embodiment illustrated inFIG. 1A in that thesource regions contact pad 155 at the front side. Thecontact pad 155 is formed as part of a multi- or single-metal layer system including metals such as Cu arranged on top of the active area of the device. Furthermore,buffer layer 110 illustrated inFIG. 1A is omitted to improve heat dissipation as described above. An interlayer dielectric 160 may be provided to electrically insulate conductive regions from each other. -
FIG. 2 is a cross-sectional view illustrating one embodiment of a semiconductor device including a portion of a lateral channel HEMT 200. HEMT 200 differs fromHEMT 100 illustrated inFIG. 1A in thatbuffer layer 110 is replaced by athird semiconductor layer 245 including Alx3Gay3Inz3N (x3+y3+z3=1, x2>x3, y3≧0, z3≧0). Thethird semiconductor layer 245 is in contact with thefirst semiconductor layer 215 and includes an average concentration of dopants higher than 1017 cm−3. - In an OFF state, a vertical avalanche breakdown voltage between the
second semiconductor layer 220, thefirst semiconductor layer 215 and the third semiconductor layer is set smaller than the lateral breakdown voltage between gate,e.g. gate region 235 d, and drain,e.g. drain region 230. Thus a channel region of HEMT 200 located at aninterface 250 between thefirst semiconductor layer 215 and thesecond semiconductor layer 220 may be prevented from damage due to hot carrier degradation or other electrical stress mechanisms. - As an example, a distance 1 between gate,
e.g. gate region 235 b, and drain,e.g. drain region 230, along alateral direction 255 may be set larger than a thickness d of thefirst semiconductor layer 215 along avertical direction 260 extending perpendicular to thelateral direction 255. - The concentration of dopants of the
third semiconductor layer 245 may be chosen high enough to provide a beneficial ohmic contact to thecarrier substrate 205, e.g. higher than 1017 cm−3, higher than 1018 cm−3 or even higher than 1019 cm−3. A conductivity type of thethird semiconductor layer 245 may equal the conductivity type of thesecond semiconductor layer 220, e.g. both conductivity types being n-type or p-type. In another embodiment, the conductivity type of thethird semiconductor layer 245 may differ from the conductivity type of thesecond semiconductor layer 220, e.g. the conductivity type of thethird semiconductor layer 245 being p-type and the conductivity type of the second semiconductor layer being n-type. -
FIG. 3 is a cross-sectional view illustrating one embodiment of a semiconductor device including a portion of alateral channel HEMT 300.HEMT 300 includes acarrier substrate 305 made of metal, e.g. Cu, doped Si such as n+-type Si, SiC or GaN, for example. Oncarrier substrate 305, athird semiconductor layer 345 is arranged.Third semiconductor layer 345 can be similar tothird semiconductor layer 245 illustrated inFIG. 2 . Thecarrier substrate 305 and thethird semiconductor layer 345 constitute a drain ofHEMT 300. - On
third semiconductor layer 345, afirst semiconductor layer 315 similar to first semiconductor layers 115, 215 illustrated inFIGS. 1A and 2 is arranged. Onfirst semiconductor layer 315, asecond semiconductor layer 320 of Alx2Gay2Inz2N (x2+y2+z2=1, x2>x1, y2≧0, z2≧0), e.g. AlGaN, is arranged. In one or more embodiments, thesecond semiconductor layer 320 may be in the shape of stripes, columns, rings, hexagons, octagons and complementary structures, for example. -
Gate regions second semiconductor layer 320. Thegate regions gate regions second semiconductor layer 320. -
Source regions first semiconductor layer 315, the source regions including a concentration of dopants higher than 1017 cm−3. Thesource regions second semiconductor layer 320 and thegate regions - A
drift region 365 including a concentration of activated dopants higher than 1014 cm−3 extends through thefirst semiconductor layer 315. If the device is turned ON, the drift region provides a conductive path between thethird semiconductor layer 345 and a channel region located at aninterface 350 between thefirst semiconductor layer 315 and thesecond semiconductor layer 320. If the device is turned OFF, the drift region is partly depleted and contributes to the electrical isolation between source and drain. Shape and doping profile of the drift region may be chosen accordingly. Thedrift region 365 may include one doped semiconductor zone or a plurality of doped semiconductor zones overlapping each other in thevertical direction 360. In case of a plurality of doped and overlapping semiconductor zones, an average concentration within each of these zones may decrease in a direction from thethird semiconductor layer 345 to thesecond semiconductor layer 320, for example, such as n−-type zone 366 and n-type zone 367 illustrated inFIG. 3 . - The conductivity between source and drain, i.e. between
source region 325 a and driftregion 365, may be controlled by applying a voltage to the gate, i.e.gate region 335 a. An insulatinglayer 340, e.g. a SiN or SiO2 layer, is formed on thesecond semiconductor layer 320 and thesource regions layer 340 and electrically couple thesource regions wiring level 375, e.g. a metal layer. -
First avalanche regions first semiconductor layer 315, thefirst avalanche regions e.g. source regions first avalanche regions third semiconductor layer 345 and include an average concentration of activated dopants higher than 1017 cm−3. - In an OFF state, a vertical avalanche breakdown voltage between source,
e.g. source region 325 a, and drain, e.g.third semiconductor layer 345, is set smaller than the lateral breakdown voltage between gate,e.g. gate region 335 b, and thedrift zone 365, e.g. by appropriate choice of dimensions and dopant concentrations offirst avalanche regions HEMT 300 located at theinterface 250 between thefirst semiconductor layer 315 and thesecond semiconductor layer 320 may be prevented from damage by hot carrier degradation or other electrical stress mechanisms. - In one embodiment, a distance l1 between source,
e.g. source region 325 a, and an undepleted part of thedrift region 365 along alateral direction 355 may be set larger than a distance l2 between a top side of the first avalanche regions, e.g.first avalanche region 380 a, and a bottom side of the source,e.g. source region 325 a, along avertical direction 360 extending perpendicular to thelateral direction 355. - A threshold voltage Vth of
HEMT 300 may be adjusted by choice of the gate material, the thickness of thesecond semiconductor layer 320, the concentration of dopants within thesecond semiconductor layer 320 and piezo-electric effects, for example.HEMT 300 may be a depletion mode transistor (Vth<0V) or an enhancement mode transistor (Vth>0V). -
Source regions region 365 andfirst avalanche regions first semiconductor layer 315, for example. These regions may also be formed by epitaxial regrowth, for example. These regions may also have a same conductivity type, e.g. an n-type. -
HEMT 300 exhibits an improved avalanche robustness. As a further example of arrangement of source and drain, both of them may be electrically coupled at a front side and theavalanche regions -
FIG. 4 is a cross-sectional view illustrating one embodiment of a semiconductor device including a portion of alateral channel HEMT 400.HEMT 400 differs fromHEMT 300 illustrated inFIG. 3 in thatsecond avalanche regions second avalanche regions first avalanche regions second avalanche regions first avalanche regions - In an OFF state, a vertical avalanche breakdown voltage between source,
e.g. source region 425 a, and drain, e.g.third semiconductor layer 445, is set smaller than the lateral breakdown voltage between gate,e.g. gate region 435 b, and thedrift region 465, e.g. by appropriate choice of dimensions and dopant concentrations of the first andsecond avalanche regions e.g. source region 425 a, and an undepleted part of thedrift region 465 along alateral direction 455 may be set larger than a distance l2 between the first andsecond avalanche regions vertical direction 460 extending perpendicular to thelateral direction 455. Thus a channel region ofHEMT 400 located at theinterface 450 between thefirst semiconductor layer 415 and thesecond semiconductor layer 420 may be prevented from damage by hot carrier degradation or other electrical stress mechanisms. -
FIG. 5 is a cross-sectional view illustrating one embodiment of a semiconductor device including a portion of alateral channel HEMT 500.HEMT 500 differs fromHEMT 400 illustrated inFIG. 4 in that thesecond avalanche regions first avalanche regions FIG. 5 , thesecond avalanche regions first avalanche regions second avalanche regions second avalanche regions second avalanche regions -
FIG. 6 is a cross-sectional view illustrating one embodiment of a semiconductor device including a portion of alateral channel HEMT 600.HEMT 600 differs fromHEMT 400 illustrated inFIG. 4 in that thefirst avalanche regions second avalanche regions - In an OFF state, a vertical avalanche breakdown voltage between source, e.g. source region 625 a, and drain, e.g.
third semiconductor layer 645, is set smaller than the lateral breakdown voltage between source, e.g. source region 625 a, and the undepleted part of thedrift zone 665, e.g. by appropriate choice of dimensions and dopant concentrations of thesecond avalanche regions region 665 along a lateral direction 655 may be set larger than a distance l2 between thesecond avalanche regions third semiconductor layer 645 along a vertical direction 660 extending perpendicular to the lateral direction 655. -
FIG. 7 illustrates a simplified flowchart of a method for manufacturing a nitride semiconductor power device according to one embodiment. - At S100, a front side of a semiconductor body is attached to a first carrier, the semiconductor body including, in a sequence from a rear side to the front side, a semiconductor carrier substrate, a buffer layer including MN, a first semiconductor layer, in one embodiment made of Alx1Gay1Inz1N (x1+y1+z1=1, x1≧0, y1≧0, z1≧0) and a second semiconductor layer in one embodiment made of Alx2Gay2Inz2N (x2+y2+z2=1, x2>x1, y2≧0, z2≧0).
- At S200, the semiconductor carrier substrate is removed from the rear side.
- At S300, a metal substrate carrier is formed on the rear side.
- The metal substrate carrier improves dissipation of heat generated during operation of a nitride semiconductor power device formed thereon.
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FIGS. 8A to 8E are cross-sectional views illustrating one embodiment of a semiconductor device including a semiconductor portion, during one example of manufacture of a nitride semiconductor power device similar to the one illustrated inFIG. 1A . - Referring to the schematic cross-sectional view of
FIG. 8A , asemiconductor body 800 is provided, thesemiconductor body 800 including, in a sequence from a rear side to the front side, asemiconductor carrier substrate 803, e.g. a Si substrate, abuffer layer 810 including MN, afirst semiconductor layer 815 of Alx1Gay1Inz1N (x1+y1+z1=1, x1≧0, y1≧0, z1≧0) and asecond semiconductor layer 820 of Alx2Gay2Inz2N (x2+y2+z2=1, x2>x1, y2≧0, z2≧0).Source regions drain region 830 are electrically coupled to thesecond semiconductor layer 820.Gate regions 835 a . . . 835 d are arranged on thesecond semiconductor layer 820. Thegate regions 135 a . . . 135 d may include metal and/or Aninsulating layer 140, e.g. a SiN or SiO2 layer, is formed on thesecond semiconductor layer 120. - Referring to the schematic cross-sectional view of
FIG. 8B , thesemiconductor body 800 is attached with its front side to afirst carrier 880, e.g. a glass carrier or a metal carrier. Between thecarrier 880 and thesemiconductor body 800, an adhesive 882 may be provided. Then thesemiconductor carrier substrate 803 is removed, e.g. by grinding or etching. Removal of thesemiconductor carrier substrate 803 may be purely mechanical with a stop on thebuffer layer 810 or may start with a mechanical removal process followed by an etching process. - Referring to the schematic cross-sectional view of
FIG. 8C , aseed layer 885 such as a Cu seed layer may be formed on thebuffer layer 810 at a rear side of thesemiconductor body 800. Theseed layer 885 may be formed by sputtering, for example, and also covers a bottom side of thedrain region 830 extending through an insulatinglayer 840, thesecond semiconductor layer 820, thefirst semiconductor layer 815 and thebuffer layer 810. - Referring to the schematic cross-sectional view of
FIG. 8D , a metal is formed on theseed layer 885, e.g. by plating of Cu, to form ametal carrier substrate 810. Theseed layer 885 may also be omitted and the metal, metal alloy or plurality of metal/metal alloys of themetal carrier substrate 810 may be formed on thebuffer layer 810. - Referring to the schematic cross-sectional view of
FIG. 8E , thesemiconductor body 800 is attached, e.g. laminated, to a sawingfoil 888 and thefirst carrier 880 as well as the adhesive 882 are released. - Further processes steps may follow to finalize nitride semiconductor power device including a metal substrate carrier for improved dissipation of heat during operation of the nitride semiconductor power device.
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FIGS. 9A to 9C are cross-sectional views of one embodiment of a semiconductor portion during one example of manufacture of the nitride semiconductor power device similar to the one illustrated inFIG. 2 . - Referring to the schematic cross-sectional view of
FIG. 9A , asemiconductor body 900 is provided, the semiconductor body including a structure similar to the structure ofsemiconductor body 800 illustrated inFIG. 8A except that a third semiconductor layer including Alx3Gay3Inz3N (x3+y3+z3=1, x2>x3, y3≧0, z3≧0) is arranged between thebuffer layer 910 and thefirst semiconductor layer 915. Similar to the process described with reference toFIG. 8B , thesemiconductor body 900 is attached with its front side to afirst carrier 980, e.g. a glass carrier or a metal carrier. Between thecarrier 980 and thesemiconductor body 900, an adhesive 982 may be provided. Then thesemiconductor carrier substrate 903 is removed, e.g. by grinding or etching. Removal of thesemiconductor carrier substrate 903 may be purely mechanical with a stop on thebuffer layer 910 or may start with a mechanical removal process followed by an etching process. - As is illustrated in
FIG. 9B , after removal of thecarrier substrate 903, thebuffer layer 910 is removed, e.g. by plasma etching. Thus thethird semiconductor layer 945 is exposed at a rear side of thesemiconductor body 900. - Then, as illustrated in
FIG. 9C , aseed layer 985 similar to theseed layer 885 described with reference toFIG. 8C is formed. The seed layer may also be a multi-layer metal stack for low ohmic contact purposes. Thereafter, the seed layer may be thickened by a metal or metal alloy and further processes may be carried out to end up with to a nitride semiconductor power device as illustrated inFIG. 2 . -
FIG. 10A to 10D are cross-sectional views illustrating one embodiment of a semiconductor device including a semiconductor portion during one example of manufacture of a nitride semiconductor power device similar to the ones illustrated inFIGS. 3 to 6 . In particularFIGS. 10A to 10D illustrate one embodiment of formation of a lowermost zone of the doped drift region. - Referring to the schematic cross-sectional view illustrated in
FIG. 10A , a doped third semiconductor layer of Alx3Gay3Inz3N (x3+y3+z3=1, x3≧0, y3≧0, z3≧0) and a first semiconductor layer are formed on asemiconductor carrier substrate 155 made of Si, SiC or GaN, for example. - Referring to the schematic cross-sectional view illustrated in
FIG. 10B , anaperture 191 is formed within thefirst semiconductor layer 165, e.g. by patterning ahard mask 198 on thefirst semiconductor layer 165 and etching through thefirst semiconductor layer 165 via thehard mask 198. - Then, as illustrated in the schematic cross-sectional view of
FIG. 10C , a lowermost nitride semiconductor zone of thedrift region 181 is formed withinaperture 191 by selective epitaxy. Thiszone 181 may be doped in-situ to include a concentration of activated dopants higher than thefirst semiconductor layer 165. - Then, as illustrated in the schematic cross-sectional view of
FIG. 10D , a top surface of the lowermost nitride semiconductor zone of thedrift region 181 is made planar, e.g. by chemical mechanical polishing (CMP). Thereby thehard mask 198 may be removed. Abarrier layer 199 may be formed on the surface of the leveled surface. - The sequence of processes described with regard to
FIGS. 10A to 10D may be repeated to form a plurality of doped semiconductor zones, e.g. avalanche regions, source, drain regions. As a further example, by repeating above sequence of processes, a continuous semiconductor region may be formed by a plurality of semiconductor zones in contact with each other, wherein the semiconductor zones may differ with regard to their dopant concentration. Thereby, a desired vertical dopant profile may be achieved, for example. As an example, a drift region may be formed by a plurality of doped semiconductor zones having different concentrations of dopants such that the concentration of dopants decreases from a rear side, i.e. at an interface with thethird semiconductor layer 195, to the front side, cf. driftregion 365 includingzone FIG. 3 . - It is to be understood that the features of the various embodiments described herein may be combined with each other unless specifically noted otherwise.
- Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptions or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.
Claims (25)
1. A semiconductor device, comprising
a carrier substrate including metal;
a first semiconductor layer of Alx1Gay1Inz1N (x1+y1+z1=1, x1≧0, y1≧0, z1≧0) above the carrier substrate;
a second semiconductor layer of Alx2Gay2Inz2N (x2+y2+z2=1, x2>x1, y2≧0, z2≧0) on the first semiconductor layer;
a gate region on the second semiconductor layer; and
a source region and a drain region, wherein one of these regions is electrically coupled to the carrier substrate and includes a conductive region extending through the first semiconductor layer.
2. The semiconductor device of claim 1 , further comprising
a third semiconductor layer including MN between the carrier substrate and the first semiconductor layer.
3. The semiconductor device of claim 1 , further comprising
a third semiconductor layer including Alx3Gay3Inz3N (x3+y3+z3=1, x2>x3, y3≧0, z3≧0) between the carrier substrate and the first semiconductor layer and in contact with the first semiconductor layer, the third semiconductor layer including an average concentration of dopants higher than 1017 cm−3.
4. The semiconductor device of claim 1 , wherein
the carrier substrate is made of Cu.
5. The semiconductor device of claim 1 , wherein
the conductive region includes a metal.
6. The semiconductor device of claim 1 , wherein
a distance between the gate region and the drain region along a lateral direction extending parallel to an interface between the first and second semiconductor layers is larger than a thickness of the first semiconductor layer along a vertical direction extending perpendicular to the interface.
7. The semiconductor device of claim 1 , wherein
both the source region and the drain region include doped semiconductor regions of a same conductivity type within the first semiconductor layer, an average concentration of dopants within each of these regions being higher than 1017 cm−3.
8. The semiconductor device of claim 7 , wherein
the second semiconductor layer is formed on a first part of the first semiconductor layer including the conductive region and is absent on a second part of the first semiconductor layer including the source region.
9. The semiconductor device of claim 7 , further comprising
a doped semiconductor region within the first semiconductor layer, wherein an average concentration of dopants of the doped semiconductor region is higher than 1017 cm−3, the doped semiconductor region being formed at a rear side of the first semiconductor layer and opposite to the source region at the front side of the first semiconductor layer.
10. The semiconductor device of claim 7 , further comprising
a doped semiconductor region within the first semiconductor layer, wherein an average concentration of dopants of the doped semiconductor region is higher than 1017 cm−3, the doped semiconductor region overlapping a bottom side of the source region.
11. The semiconductor device of claim 1 , wherein
the conductive region includes a doped epitaxial layer formed within an aperture of the first semiconductor layer.
12. A semiconductor device, comprising
a carrier substrate;
a first semiconductor layer of Alx1Gay1Inz1N (x1+y1+z1=1, x1≧0, y1≧0, z1≧0) above the carrier substrate;
a second semiconductor layer of Alx2Gay2Inz2N (x2+y2+z2=1, x2>x1, y2≧0, z2≧0) on the first semiconductor layer;
a gate region on the second semiconductor layer;
a source region and a drain region; and
a third semiconductor layer including Alx3Gay3Inz3N (x3+y3+z3=1, x2>x3, y3≧0, z3≧0) between the carrier substrate and the first semiconductor layer and in contact with the first semiconductor layer, the third semiconductor layer including an average concentration of dopants higher than 1017 cm−3.
13. The semiconductor device of claim 12 , wherein
one of the source region and the drain region is electrically coupled to the carrier substrate and includes a conductive region extending through the first semiconductor layer.
14. The semiconductor device of claim 12 , wherein
the carrier substrate at a rear side of the semiconductor device is electrically coupled to a contact region at a front side of the semiconductor device via a lead frame and a bond wire.
15. The semiconductor device of claim 12 , wherein
the carrier substrate includes at least one of doped Si, SiC, GaN, metal.
16. The semiconductor device of claim 12 , further comprising
a doped semiconductor region within the first semiconductor layer, wherein an average concentration of dopants of the doped semiconductor region is higher than 1017 cm−3, the doped semiconductor region being formed at a rear side of the first semiconductor layer opposite to the source region at a front side of the first semiconductor layer.
17. The semiconductor device of claim 12 , further comprising
a doped semiconductor region within the first semiconductor layer, wherein an average concentration of dopants of the doped semiconductor region is higher than 1017 cm−3, the doped semiconductor region overlapping a bottom side of the source region.
18. The semiconductor device of claim 12 , wherein
a distance between the gate region and the drain region along a lateral direction extending parallel to an interface between the first and second semiconductor layers is larger than a thickness of the first semiconductor layer along the vertical direction extending perpendicular to the interface.
19. The semiconductor device of claim 12 , wherein
the conductive region includes a doped epitaxial layer formed within an aperture of the first semiconductor layer.
20. The semiconductor device of claim 12 , wherein
the first semiconductor layer includes at least one of Fe, C, Mg.
21. A method for manufacturing a semiconductor device, comprising:
attaching a front side of a semiconductor body to a first carrier, the semiconductor body including, in a sequence from a rear side to the front side, a semiconductor carrier substrate, a buffer layer including MN, a first semiconductor layer of Alx1Gay1Inz1N (x1+y1+z1=1, x1≧0, y1≧0, z1≧0) and a second semiconductor layer of Alx2Gay2Inz2N (x2+y2+z2=1, x2>x1, y2≧0, z2≧0);
removing the semiconductor carrier substrate from the rear side;
forming a metal substrate carrier on the rear side.
22. The method of claim 21 , wherein
forming the metal substrate carrier includes
forming a seed layer of Cu on the rear side; and
forming Cu on the rear side by galvanic plating.
23. The method of claim 21 , wherein
the semiconductor body comprises a third semiconductor layer including Alx3Gay3Inz3N (x3+y3+z3=1, x2>x3, y3≧0, z3≧0) between the carrier substrate and the first semiconductor layer and in contact with the first semiconductor layer, the third semiconductor layer including an average concentration of dopants higher than 1017 cm−3; the method further comprising
removing the buffer layer after removal of the semiconductor carrier and before formation of the metal substrate carrier.
24. The method of claim 21 , further comprising
forming an aperture at least within the first semiconductor layer; and
forming a conductive material within the aperture.
25. The method of claim 22 , wherein
forming the conductive material within the aperture includes forming a doped epitaxial semiconductor layer within the aperture.
Priority Applications (5)
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US12/641,130 US20110147796A1 (en) | 2009-12-17 | 2009-12-17 | Semiconductor device with metal carrier and manufacturing method |
JP2010278873A JP5611020B2 (en) | 2009-12-17 | 2010-12-15 | Semiconductor device having metal carrier and manufacturing method |
DE102010061295.2A DE102010061295B4 (en) | 2009-12-17 | 2010-12-16 | Semiconductor device with metallic carrier |
CN2010106250765A CN102130157B (en) | 2009-12-17 | 2010-12-17 | Semiconductor device with metal carrier and manufacturing method |
US14/711,198 US9646855B2 (en) | 2009-12-17 | 2015-05-13 | Semiconductor device with metal carrier and manufacturing method |
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US12/641,130 Abandoned US20110147796A1 (en) | 2009-12-17 | 2009-12-17 | Semiconductor device with metal carrier and manufacturing method |
US14/711,198 Active 2030-03-12 US9646855B2 (en) | 2009-12-17 | 2015-05-13 | Semiconductor device with metal carrier and manufacturing method |
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Also Published As
Publication number | Publication date |
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US20150249020A1 (en) | 2015-09-03 |
DE102010061295B4 (en) | 2017-11-23 |
CN102130157A (en) | 2011-07-20 |
DE102010061295A1 (en) | 2011-06-22 |
JP2011129924A (en) | 2011-06-30 |
CN102130157B (en) | 2013-10-16 |
US9646855B2 (en) | 2017-05-09 |
JP5611020B2 (en) | 2014-10-22 |
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