US20110113215A1 - Method and apparatus for dynamic resizing of cache partitions based on the execution phase of tasks - Google Patents

Method and apparatus for dynamic resizing of cache partitions based on the execution phase of tasks Download PDF

Info

Publication number
US20110113215A1
US20110113215A1 US12/281,359 US28135907A US2011113215A1 US 20110113215 A1 US20110113215 A1 US 20110113215A1 US 28135907 A US28135907 A US 28135907A US 2011113215 A1 US2011113215 A1 US 2011113215A1
Authority
US
United States
Prior art keywords
cache
task
application
tasks
execution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US12/281,359
Inventor
Bijo Thomas
Sriram Krishnan
Milind Manohar Kulkarni
Sainath Karlapalem
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Morgan Stanley Senior Funding Inc
Original Assignee
NXP BV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US12/281,359 priority Critical patent/US20110113215A1/en
Application filed by NXP BV filed Critical NXP BV
Assigned to NXP, B.V. reassignment NXP, B.V. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KARLAPALEM, SAINATH, KULKARNI, MILIND MANOHAR, THOMAS, BIJO, KRISHNAN, SRIRAM
Publication of US20110113215A1 publication Critical patent/US20110113215A1/en
Assigned to MORGAN STANLEY SENIOR FUNDING, INC. reassignment MORGAN STANLEY SENIOR FUNDING, INC. SECURITY AGREEMENT SUPPLEMENT Assignors: NXP B.V.
Assigned to MORGAN STANLEY SENIOR FUNDING, INC. reassignment MORGAN STANLEY SENIOR FUNDING, INC. CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Assignors: NXP B.V.
Assigned to MORGAN STANLEY SENIOR FUNDING, INC. reassignment MORGAN STANLEY SENIOR FUNDING, INC. CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Assignors: NXP B.V.
Assigned to MORGAN STANLEY SENIOR FUNDING, INC. reassignment MORGAN STANLEY SENIOR FUNDING, INC. CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Assignors: NXP B.V.
Assigned to NXP B.V. reassignment NXP B.V. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: MORGAN STANLEY SENIOR FUNDING, INC.
Assigned to MORGAN STANLEY SENIOR FUNDING, INC. reassignment MORGAN STANLEY SENIOR FUNDING, INC. CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Assignors: NXP B.V.
Assigned to MORGAN STANLEY SENIOR FUNDING, INC. reassignment MORGAN STANLEY SENIOR FUNDING, INC. CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Assignors: NXP B.V.
Assigned to MORGAN STANLEY SENIOR FUNDING, INC. reassignment MORGAN STANLEY SENIOR FUNDING, INC. CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Assignors: NXP B.V.
Assigned to MORGAN STANLEY SENIOR FUNDING, INC. reassignment MORGAN STANLEY SENIOR FUNDING, INC. CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Assignors: NXP B.V.
Abandoned legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0808Multiuser, multiprocessor or multiprocessing cache systems with cache invalidating means
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0842Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12Replacement control
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60Details of cache memory
    • G06F2212/601Reconfiguration of cache memory

Definitions

  • the present invention relates, in general to a data processing system comprising cache storage, and more specifically relates to dynamic partitioning of the cache storage for application tasks in a multiprocessor.
  • Cache partitioning is a well-known technique in multi-tasking systems for achieving more predictable cache performance by reducing resource interference.
  • the cache storage is shared between multiple processes or tasks.
  • the cache storage is partitioned into different sections for different application tasks. It can be advantageous to partition the cache into sections, where each section is allocated to a respective class of processes, rather than the processes sharing entire cache storage.
  • cache storage is divided into a number of sections, the question arises of how to determine the size of cache partition for different application tasks and when to resize the cache partitions.
  • US Patent application 2002/0002657A1 by Henk Muller et al discloses a method of operating a cache memory in a system, in which a processor is capable of executing a plurality of processes.
  • Such techniques partition the cache into many small partitions instead of using one monolithic data-cache in which accesses to different data objects may interfere.
  • the compiler is aware of the cache architecture and allocates the cache partitions to the tasks.
  • Such techniques reserve the partitioned section of the cache for the tasks during its entire duration of execution.
  • static partitioning techniques often result in either suboptimal usage of cache or insufficient reservations of cache partitions.
  • Dynamic partitioning techniques as proposed by Edward Suh et al in “Analytical Cache Models with applications to cache partitioning” attempt to avoid the above said drawback of static partitioning by dynamically resizing the partition sizes. Such techniques do not consider the program characteristics like phased execution of the individual tasks. For instance, the execution behavior of multimedia applications often falls into repeating behaviors (phases), which may have different cache usage characteristics. Effective cache usage can be achieved by determining the partition sizes at the program phase boundaries.
  • Timothy et al have described that it is possible to accurately identify and predict the phases in program behavior [Ref. 2: “Discovering and exploiting program phases”, Timothy Sherwood et al].
  • the program (task) behavior in these phases has different resource usage characteristics and can be quantified using performance metrics.
  • An example of such a metric is basic block vector [BBV] described in [Ref. 2].
  • the present invention proposes a method and a system for dynamic cache partitioning for each application task in a multiprocessor.
  • An approach for dynamically resizing cache partitions based on the execution phase of the application tasks is provided.
  • Cache partitions are dynamically resized according to the execution phase of the current task such that, unnecessary reservation of the entire cache is avoided and hence an effective utilization of the cache is achieved.
  • partitioning In a multiprocessor, multitasking scenarios with shared cache/memory, partitioning is often conceived as a mechanism to achieve the predictable performance of the memory subsystem.
  • partitioning schemes are available in the literature such as Way Partitioning (Column Caching), Set Partitioning, etc.
  • Streaming applications adopt a pattern of execution that has distinct phases with distinct durations.
  • the objective of the present invention is to exploit the information regarding the distinct phases of execution of the multimedia application tasks and hence adapt the partition size based on the requirements during their executions phases.
  • Execution phases of the application task (program) can be identified in many ways: one example is by monitoring the working set changes and other methods [Ref. 2].
  • the execution phases of application tasks are defined as the set of intervals within the application task's execution that have similar behaviour, and the working set of the application task is defined as the cache partition requirements of the application task at a particular execution phase.
  • One aspect of the present invention provides a method for dynamically resizing cache partitions based on the execution phase of the application tasks.
  • the execution phases of the application tasks are identified and updated in a tabular form.
  • Cache partitions are resized during a particular instance of the execution of tasks such that the necessary and sufficient amount of cache space is allocated to the tasks at any given point of time.
  • the cache partition size is determined according to the working set requirement of the tasks during its execution, which is monitored dynamically or statically.
  • Another aspect of the present invention provides a computer system for dynamically resizing cache partitions for the application tasks in a multiprocessor.
  • the system comprises a task phase monitor for monitoring the working set variations of application tasks which can be either monitored dynamically or the information can be collected statically and stored in the same.
  • the phase information of the tasks is stored in a task phase table.
  • the task phase table contains the phase and the cache partition allocated (which is the working set of the application task at the corresponding phase) at the time of switching of the tasks.
  • the system also comprises of a cache allocation controller for allocating maximum cache size when a new application task interrupts a currently executing task.
  • the cache allocation controller looks at the working set requirements of the new application task and partitions the cache by allocating maximum possible cache size to the new task.
  • the cache storage allocation is done according to the phase of the new application task.
  • One object of the present invention is to devise a method and means for dynamically managing cache partitioning among a plurality of processes executing on a computing system.
  • Another object of the present invention is to improve the cache utilization by avoiding unnecessary reservation of the cache partitions for the executing application tasks during the entire duration of their execution.
  • Another object of the present invention is to increase the probability of having a greater portion of the working set of the interrupting task to be mapped onto the cache. So when a higher priority task or an interrupt occurs, there will be more cache available to be allocated for the interrupting task.
  • FIG. 1 illustrates an embodiment of the method of dynamically resizing cache partitions in a multiprocessor for the application tasks.
  • FIG. 2 is a graphical depiction showing the working set variations for an application task.
  • FIG. 3 presents a block diagram illustrating the architecture of an embodiment of a system for dynamically resizing cache partitions for the application tasks.
  • FIG. 4 illustrates a task phase table for storing information of application tasks.
  • FIG. 5 illustrates a snapshot depicting an example of cache requirements for two application tasks (T1 and T2).
  • FIG. 6 illustrates the cache partitioning scenario for the example shown in FIG. 5 when a new application task, T3, interrupts the currently executing application tasks (T1 and T2).
  • FIG. 1 illustrates an embodiment of the method of dynamically resizing cache partitions in a multiprocessor for the application tasks.
  • basic block vector (BBV) metrics or working set of the application task the execution phases of each of the application task is identified 101 .
  • the phase information and working set of an application task is stored in tabular form 102 . This phase information is then utilized for dynamically configuring the cache partition depending on the execution phase of the application task 103 .
  • BBV basic block vector
  • the cache partitions are resized during a particular instance of the execution of application tasks such that the necessary and sufficient amount of cache space is allocated to the application tasks at any time.
  • the cache partition size is determined according to the working set requirement of the tasks during its execution.
  • the working set requirements of the tasks can be monitored dynamically or statically.
  • FIG. 2 illustrates a graph depicting the working set variations for an application task 201 .
  • Variation of the working set W (t) for an application task during the period of execution ‘T’ of the task is shown in FIG. 2 .
  • the working set of the application task varies during its execution period T. Accordingly there are distinct phases P1, P2 and P3 corresponding to the working sets W1, W2 and W3.
  • the application task can get switched at any of the phases of its execution. If the cache partition allocated to the application tasks is constant (as in prior art) during its period of execution T, this would result in a redundant blocking of the cache partitions.
  • the cache partition allocated to the application task is equal to that of W1 (bytes), and if the application task switches at P3 (corresponding to W3), then the cache space W1-W3 is unnecessarily blocked for the application task.
  • FIG. 3 presents a block diagram illustrating the architecture of an embodiment of a system for dynamically resizing cache partitions for the application tasks.
  • the working set variations of the application tasks is monitored by a task phase monitor 301 .
  • the working set variations can be either monitored dynamically or the information can be collected statically.
  • This phase information is stored in a task phase table 302 .
  • the task phase table 302 contains the phase and the cache partition allocated (which is the working set of the task at the corresponding phase) at the time of switching of the application tasks.
  • the cache allocation controller 303 looks at the working set requirements of the new application task and partitions the cache by allocating maximum possible cache size to the new application task, in observance with the phase of the new application task.
  • FIG. 4 illustrates a task phase table 302 for storing the phase information of application tasks 401 .
  • the task phase table 302 includes a separate task ID for each of the application tasks, the phase information of the application task and cache partition size allocated for each application task at the time of switching of tasks.
  • the phase information of the application task is denoted as P 1 (T1), P 2 (T2) and P 3 (T3) respectively for three successive application tasks, T1, T2 and T3 and P1, P2, P3 are three distinct phases of the three tasks.
  • the cache partition size allocated for each application task at the time of switching of tasks is denoted as W1, W2 and W3.
  • FIG. 5 illustrates a snapshot depicting an example of cache requirements for two application tasks 501 .
  • T1 and T2 As shown in FIG. 5 .
  • the application tasks are running in a multi-tasking mode, switching from one task to the other.
  • T1 in phase P2
  • T2 task T2 in phase P3 (T2).
  • FIG. 6 illustrates the cache partitioning scenario for two cases of examples 601 when a new application task interrupts a currently executing application task.
  • FIG. 5 consider the situation when a new application task T3 (interrupting task) arrives at phase P1 (T3) with a working set requirement of 8 lines.
  • T3 interrupting task
  • the cache size would have been allocated based on maximum cache requirements, i.e., 7 for task T1 and 8 for task T2, over the entire duration of execution. This would have consumed 15 lines until task T1 and task T2 finish their execution.
  • the present invention will find its industrial applications in system on chip (SoC) for audio, video and mobile applications.
  • SoC system on chip
  • the present invention will improve the cache utilization by avoiding unnecessary reservation of the cache partitions for the executing application tasks during the entire duration of their execution. So an effective utilization of the cache storage is achieved.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

The present invention proposes a method and a system for dynamic cache partitioning for application tasks in a multiprocessor. An approach for dynamically resizing cache partitions based on the execution phase of the application tasks is provided. The execution phases of the application tasks are identified and updated in a tabular form. Cache partitions are resized during a particular instance of the execution of application tasks such that the necessary and sufficient amount of cache space is allocated to the application tasks at any given point of time. The cache partition size is determined according to the working set requirement of the tasks during its execution, which is monitored dynamically or statically. Cache partitions are resized according to the execution phase of the task dynamically such that unnecessary reservation of the entire cache is avoided and hence an effective utilization of the cache is achieved.

Description

  • The present invention relates, in general to a data processing system comprising cache storage, and more specifically relates to dynamic partitioning of the cache storage for application tasks in a multiprocessor.
  • Cache partitioning is a well-known technique in multi-tasking systems for achieving more predictable cache performance by reducing resource interference. In a data processing system comprising of multiprocessors, the cache storage is shared between multiple processes or tasks. The cache storage is partitioned into different sections for different application tasks. It can be advantageous to partition the cache into sections, where each section is allocated to a respective class of processes, rather than the processes sharing entire cache storage. When cache storage is divided into a number of sections, the question arises of how to determine the size of cache partition for different application tasks and when to resize the cache partitions.
  • US Patent application 2002/0002657A1 by Henk Muller et al discloses a method of operating a cache memory in a system, in which a processor is capable of executing a plurality of processes. Such techniques partition the cache into many small partitions instead of using one monolithic data-cache in which accesses to different data objects may interfere. In such cases, typically the compiler is aware of the cache architecture and allocates the cache partitions to the tasks. Such techniques reserve the partitioned section of the cache for the tasks during its entire duration of execution. Hence, static partitioning techniques often result in either suboptimal usage of cache or insufficient reservations of cache partitions.
  • Dynamic partitioning techniques as proposed by Edward Suh et al in “Analytical Cache Models with applications to cache partitioning” attempt to avoid the above said drawback of static partitioning by dynamically resizing the partition sizes. Such techniques do not consider the program characteristics like phased execution of the individual tasks. For instance, the execution behavior of multimedia applications often falls into repeating behaviors (phases), which may have different cache usage characteristics. Effective cache usage can be achieved by determining the partition sizes at the program phase boundaries.
  • Timothy et al have described that it is possible to accurately identify and predict the phases in program behavior [Ref. 2: “Discovering and exploiting program phases”, Timothy Sherwood et al]. The program (task) behavior in these phases has different resource usage characteristics and can be quantified using performance metrics. An example of such a metric is basic block vector [BBV] described in [Ref. 2].
  • Current cache partitioning techniques reserve the partitioned section of the cache storage for the application tasks for their entire duration of execution. But media processing tasks have distinct phases of execution and the cache requirements vary in each of these phases. In multi-tasking real-time systems, application task switches due to arrival of high priority application tasks. Switching of application tasks due to interrupts is also common These task switches could occur at different execution phases of the currently executing task. Current cache partitioning techniques do not address this varying demand for cache.
  • Hence, there exists an unsatisfied need for dynamic resizing of cache partition assigned for each task in a multiprocessor according to the execution phase so that only minimal amount of cache space is allocated at any given time. The solution for this problem will ensure that sufficient (or more optimal) cache space is available for the incoming task (interrupting task or high priority task that is switched in).
  • The present invention proposes a method and a system for dynamic cache partitioning for each application task in a multiprocessor. An approach for dynamically resizing cache partitions based on the execution phase of the application tasks is provided. Cache partitions are dynamically resized according to the execution phase of the current task such that, unnecessary reservation of the entire cache is avoided and hence an effective utilization of the cache is achieved.
  • In a multiprocessor, multitasking scenarios with shared cache/memory, partitioning is often conceived as a mechanism to achieve the predictable performance of the memory subsystem. Several partitioning schemes are available in the literature such as Way Partitioning (Column Caching), Set Partitioning, etc. Streaming applications adopt a pattern of execution that has distinct phases with distinct durations. The objective of the present invention is to exploit the information regarding the distinct phases of execution of the multimedia application tasks and hence adapt the partition size based on the requirements during their executions phases. Execution phases of the application task (program) can be identified in many ways: one example is by monitoring the working set changes and other methods [Ref. 2]. The execution phases of application tasks are defined as the set of intervals within the application task's execution that have similar behaviour, and the working set of the application task is defined as the cache partition requirements of the application task at a particular execution phase.
  • One aspect of the present invention provides a method for dynamically resizing cache partitions based on the execution phase of the application tasks. The execution phases of the application tasks are identified and updated in a tabular form. Cache partitions are resized during a particular instance of the execution of tasks such that the necessary and sufficient amount of cache space is allocated to the tasks at any given point of time. The cache partition size is determined according to the working set requirement of the tasks during its execution, which is monitored dynamically or statically.
  • Another aspect of the present invention provides a computer system for dynamically resizing cache partitions for the application tasks in a multiprocessor. The system comprises a task phase monitor for monitoring the working set variations of application tasks which can be either monitored dynamically or the information can be collected statically and stored in the same. The phase information of the tasks is stored in a task phase table. The task phase table contains the phase and the cache partition allocated (which is the working set of the application task at the corresponding phase) at the time of switching of the tasks.
  • The system also comprises of a cache allocation controller for allocating maximum cache size when a new application task interrupts a currently executing task. When a new application task interrupts the currently executing task, the cache allocation controller looks at the working set requirements of the new application task and partitions the cache by allocating maximum possible cache size to the new task. The cache storage allocation is done according to the phase of the new application task.
  • One object of the present invention is to devise a method and means for dynamically managing cache partitioning among a plurality of processes executing on a computing system.
  • Another object of the present invention is to improve the cache utilization by avoiding unnecessary reservation of the cache partitions for the executing application tasks during the entire duration of their execution.
  • Another object of the present invention is to increase the probability of having a greater portion of the working set of the interrupting task to be mapped onto the cache. So when a higher priority task or an interrupt occurs, there will be more cache available to be allocated for the interrupting task.
  • The above summary of the present invention is not intended to describe each disclosed embodiment of the present invention. The figures and detailed description that follow provide additional aspects of the present invention.
  • FIG. 1 illustrates an embodiment of the method of dynamically resizing cache partitions in a multiprocessor for the application tasks.
  • FIG. 2 is a graphical depiction showing the working set variations for an application task.
  • FIG. 3 presents a block diagram illustrating the architecture of an embodiment of a system for dynamically resizing cache partitions for the application tasks.
  • FIG. 4 illustrates a task phase table for storing information of application tasks.
  • FIG. 5 illustrates a snapshot depicting an example of cache requirements for two application tasks (T1 and T2).
  • FIG. 6 illustrates the cache partitioning scenario for the example shown in FIG. 5 when a new application task, T3, interrupts the currently executing application tasks (T1 and T2).
  • The foregoing and other features, aspects and advantages of the present invention are described in detail below in connection with the accompanying drawings. The drawings comprise of 6 figures.
  • FIG. 1 illustrates an embodiment of the method of dynamically resizing cache partitions in a multiprocessor for the application tasks. Using basic block vector (BBV) metrics or working set of the application task, the execution phases of each of the application task is identified 101. The phase information and working set of an application task is stored in tabular form 102. This phase information is then utilized for dynamically configuring the cache partition depending on the execution phase of the application task 103.
  • According to the proposed invention, the cache partitions are resized during a particular instance of the execution of application tasks such that the necessary and sufficient amount of cache space is allocated to the application tasks at any time. The cache partition size is determined according to the working set requirement of the tasks during its execution. The working set requirements of the tasks can be monitored dynamically or statically. By avoiding redundant reservation of the cache partitions for the application tasks for the entire duration of their execution, the overall cache utilization is improved.
  • FIG. 2 illustrates a graph depicting the working set variations for an application task 201. Variation of the working set W (t) for an application task during the period of execution ‘T’ of the task is shown in FIG. 2. The working set of the application task varies during its execution period T. Accordingly there are distinct phases P1, P2 and P3 corresponding to the working sets W1, W2 and W3. Depending on the system conditions like schedule quantum, interrupts, data/space availability of the input/output buffers, etc, the application task can get switched at any of the phases of its execution. If the cache partition allocated to the application tasks is constant (as in prior art) during its period of execution T, this would result in a redundant blocking of the cache partitions.
  • For example, if the cache partition allocated to the application task is equal to that of W1 (bytes), and if the application task switches at P3 (corresponding to W3), then the cache space W1-W3 is unnecessarily blocked for the application task.
  • FIG. 3 presents a block diagram illustrating the architecture of an embodiment of a system for dynamically resizing cache partitions for the application tasks. The working set variations of the application tasks is monitored by a task phase monitor 301. The working set variations can be either monitored dynamically or the information can be collected statically. This phase information is stored in a task phase table 302. The task phase table 302 contains the phase and the cache partition allocated (which is the working set of the task at the corresponding phase) at the time of switching of the application tasks.
  • When a new application task interrupts a currently executing application task, the cache allocation controller 303 looks at the working set requirements of the new application task and partitions the cache by allocating maximum possible cache size to the new application task, in observance with the phase of the new application task.
  • FIG. 4 illustrates a task phase table 302 for storing the phase information of application tasks 401. The task phase table 302 includes a separate task ID for each of the application tasks, the phase information of the application task and cache partition size allocated for each application task at the time of switching of tasks. The phase information of the application task is denoted as P1 (T1), P2 (T2) and P3 (T3) respectively for three successive application tasks, T1, T2 and T3 and P1, P2, P3 are three distinct phases of the three tasks. Also, the cache partition size allocated for each application task at the time of switching of tasks is denoted as W1, W2 and W3.
  • FIG. 5 illustrates a snapshot depicting an example of cache requirements for two application tasks 501. Consider the snapshot of cache requirements of two application tasks T1 and T2 as shown in FIG. 5. Assume that the total cache size is 20 lines. The application tasks are running in a multi-tasking mode, switching from one task to the other. After a period of time assume that the execution has resulted in the cache having task T1 in phase P2 (T1) and task T2 in phase P3 (T2). The total cache that has been taken up is 7+4=11 lines, leaving 9 lines free.
  • FIG. 6 illustrates the cache partitioning scenario for two cases of examples 601 when a new application task interrupts a currently executing application task. In FIG. 5, consider the situation when a new application task T3 (interrupting task) arrives at phase P1 (T3) with a working set requirement of 8 lines. In the conventional mode of cache partition which is shown in Casel 602, the cache size would have been allocated based on maximum cache requirements, i.e., 7 for task T1 and 8 for task T2, over the entire duration of execution. This would have consumed 15 lines until task T1 and task T2 finish their execution.
  • In Case 2 603, task T3 could be allocated leaving 1 line free. If the tasks T1, T2 were in some other phases of their execution, the allocation in Case 1, 601 and Case 2, 602 would be more dramatic. For instance if task T1 and T2 were in phase P1 (T1) and P1 (T2) respectively, when task T3 arrived, there would have been 20−(2+4)=14 lines available for T3. Thus with the case 2 even if the working set for task T3 was more (maximum 14), there will be free lines available for the interrupting application task.
  • The present invention will find its industrial applications in system on chip (SoC) for audio, video and mobile applications. The present invention will improve the cache utilization by avoiding unnecessary reservation of the cache partitions for the executing application tasks during the entire duration of their execution. So an effective utilization of the cache storage is achieved.

Claims (13)

1. A method of dynamically resizing cache partitions in a multiprocessor for a plurality of application tasks wherein, said multiprocessor being capable of executing said plurality of application tasks, comprising of a main memory and a cache memory wherein, said cache memory comprises a set of cache partitions, the method comprising the steps of:
identifying and monitoring execution phases of the plurality of application tasks;
maintaining and updating information regarding said execution phases and working set of a current application task; and
configuring said cache partitions dynamically depending on the execution phases of said current application task whereby, avoiding redundant reservation of the cache partitions for the execution tasks for the entire duration of their execution.
2. The method of claim 1 wherein, the application tasks comprises a sequence of instructions.
3. The method of claim 1 wherein, the execution phases of the application tasks comprises a set of intervals within the application task's execution that have similar behaviour.
4. The method of claim 1 wherein, said working set of the application tasks comprises the cache partition requirements of the application tasks at a particular execution phase.
5. The method of claim 1 wherein, monitoring execution phases of said execution tasks is implemented statically and cache partition size is determined according to the working set requirements of the application tasks during execution.
6. The method of claim 1 wherein, monitoring execution phases of said execution tasks is implemented dynamically and cache partition size is determined according to the working set requirements of the application tasks during execution.
7. The method of claim 1 wherein, when a higher priority task occurs, adequate cache partition is available to be allocated to said higher priority task whereby, sufficient portion of the working set of the higher priority task is mapped onto the cache.
8. The method of claim 1 wherein, cache partitions assigned for each application task is varied according to the execution phase whereby, only the optimal amount of cache space is allocated at any given time.
9. A system for dynamically resizing cache partitions in a multiprocessor for a plurality of application tasks wherein, said multiprocessor being capable of executing said plurality of application tasks, comprising of a main memory and a cache memory wherein, said cache memory comprises a set of cache partitions, comprising of:
a task phase monitor for monitoring working set variations of application tasks;
a storage for storing phase information regarding application tasks from said task phase monitor; and
a cache allocation controller for allocating maximum cache size when a new application task interrupts a currently executing application task.
10. The system as in claim 9 wherein, said storage comprises a task phase table further comprising of the phase information of application tasks and cache partition size allocated for each application task at the time of switching of tasks wherein, cache partition size allocated for each application task comprises the working set of the task at the corresponding phase.
11. The system as in claim 9 wherein, said task phase monitor monitors said working set variations statically and stored in task phase table.
12. The system as in claim 9 wherein, the task phase monitor monitors working set variations dynamically and stored in the storage.
13. The method of claim 9 wherein, the application tasks comprises a sequence of instructions.
US12/281,359 2006-03-02 2007-02-24 Method and apparatus for dynamic resizing of cache partitions based on the execution phase of tasks Abandoned US20110113215A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US12/281,359 US20110113215A1 (en) 2006-03-02 2007-02-24 Method and apparatus for dynamic resizing of cache partitions based on the execution phase of tasks

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US77927106P 2006-03-02 2006-03-02
IBPCT/IB2007/050593 2007-02-24
US12/281,359 US20110113215A1 (en) 2006-03-02 2007-02-24 Method and apparatus for dynamic resizing of cache partitions based on the execution phase of tasks
PCT/IB2007/050593 WO2007099483A2 (en) 2006-03-02 2007-02-24 Method and apparatus for dynamic resizing of cache partitions based on the execution phase of tasks

Publications (1)

Publication Number Publication Date
US20110113215A1 true US20110113215A1 (en) 2011-05-12

Family

ID=38459415

Family Applications (1)

Application Number Title Priority Date Filing Date
US12/281,359 Abandoned US20110113215A1 (en) 2006-03-02 2007-02-24 Method and apparatus for dynamic resizing of cache partitions based on the execution phase of tasks

Country Status (5)

Country Link
US (1) US20110113215A1 (en)
EP (1) EP1999596A2 (en)
JP (1) JP2009528610A (en)
CN (1) CN101395586A (en)
WO (1) WO2007099483A2 (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120278586A1 (en) * 2011-04-26 2012-11-01 International Business Machines Corporation Dynamic Data Partitioning For Optimal Resource Utilization In A Parallel Data Processing System
US20130346705A1 (en) * 2012-06-26 2013-12-26 Qualcomm Incrorporated Cache Memory with Write Through, No Allocate Mode
US8621070B1 (en) * 2010-12-17 2013-12-31 Netapp Inc. Statistical profiling of cluster tasks
US20140032818A1 (en) * 2012-07-30 2014-01-30 Jichuan Chang Providing a hybrid memory
US20150006935A1 (en) * 2013-06-26 2015-01-01 Electronics And Telecommunications Research Institute Method for controlling cache memory and apparatus for the same
US20150161047A1 (en) * 2013-12-10 2015-06-11 Samsung Electronics Co., Ltd. Multi-core cpu system for adjusting l2 cache character, method thereof, and devices having the same
US20210255972A1 (en) * 2019-02-13 2021-08-19 Google Llc Way partitioning for a system-level cache
US11520700B2 (en) 2018-06-29 2022-12-06 Intel Corporation Techniques to support a holistic view of cache class of service for a processor cache

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8250305B2 (en) 2008-03-19 2012-08-21 International Business Machines Corporation Method, system and computer program product for data buffers partitioned from a cache array
JP5239890B2 (en) * 2009-01-21 2013-07-17 トヨタ自動車株式会社 Control device
CN101894048B (en) * 2010-05-07 2012-11-14 中国科学院计算技术研究所 Phase analysis-based cache dynamic partitioning method and system
US9104583B2 (en) 2010-06-24 2015-08-11 International Business Machines Corporation On demand allocation of cache buffer slots
CN102681792B (en) * 2012-04-16 2015-03-04 华中科技大学 Solid-state disk memory partition method
JP6042170B2 (en) * 2012-10-19 2016-12-14 ルネサスエレクトロニクス株式会社 Cache control device and cache control method
JP6248808B2 (en) * 2014-05-22 2017-12-20 富士通株式会社 Information processing apparatus, information processing system, information processing apparatus control method, and information processing apparatus control program
US10089238B2 (en) * 2014-07-17 2018-10-02 Qualcomm Incorporated Method and apparatus for a shared cache with dynamic partitioning
CN105512185B (en) * 2015-11-24 2019-03-26 无锡江南计算技术研究所 A method of it is shared based on operation timing caching
JP2019168733A (en) * 2016-07-08 2019-10-03 日本電気株式会社 Information processing system, cache capacity distribution method, storage control apparatus, and method and program thereof
CN107329911B (en) * 2017-07-04 2020-07-28 国网浙江省电力公司信息通信分公司 Cache replacement method based on CP-ABE attribute access mechanism
CN110058814B (en) * 2019-03-25 2022-09-06 中国航空无线电电子研究所 System for safely obtaining memory snapshot of inactive partition in partition operating system
WO2021019652A1 (en) * 2019-07-29 2021-02-04 日本電信電話株式会社 Cache tuning device, cache tuning method and cache tuning program
CN111355962A (en) * 2020-03-10 2020-06-30 珠海全志科技股份有限公司 Video decoding caching method suitable for multiple reference frames, computer device and computer readable storage medium

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020002657A1 (en) * 1997-01-30 2002-01-03 Sgs-Thomson Microelectronics Limited Cache system for concurrent processes
US6493800B1 (en) * 1999-03-31 2002-12-10 International Business Machines Corporation Method and system for dynamically partitioning a shared cache

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0799508B2 (en) * 1990-10-15 1995-10-25 インターナショナル・ビジネス・マシーンズ・コーポレイション Method and system for dynamically partitioning cache storage
JP2001282617A (en) * 2000-03-27 2001-10-12 Internatl Business Mach Corp <Ibm> Method and system for dynamically sectioning shared cache

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020002657A1 (en) * 1997-01-30 2002-01-03 Sgs-Thomson Microelectronics Limited Cache system for concurrent processes
US6493800B1 (en) * 1999-03-31 2002-12-10 International Business Machines Corporation Method and system for dynamically partitioning a shared cache

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8621070B1 (en) * 2010-12-17 2013-12-31 Netapp Inc. Statistical profiling of cluster tasks
US20140136698A1 (en) * 2010-12-17 2014-05-15 Netapp Inc. Statistical profiling of cluster tasks
US20120278586A1 (en) * 2011-04-26 2012-11-01 International Business Machines Corporation Dynamic Data Partitioning For Optimal Resource Utilization In A Parallel Data Processing System
US20120278587A1 (en) * 2011-04-26 2012-11-01 International Business Machines Corporation Dynamic Data Partitioning For Optimal Resource Utilization In A Parallel Data Processing System
US9811384B2 (en) * 2011-04-26 2017-11-07 International Business Machines Corporation Dynamic data partitioning for optimal resource utilization in a parallel data processing system
US9817700B2 (en) * 2011-04-26 2017-11-14 International Business Machines Corporation Dynamic data partitioning for optimal resource utilization in a parallel data processing system
US20130346705A1 (en) * 2012-06-26 2013-12-26 Qualcomm Incrorporated Cache Memory with Write Through, No Allocate Mode
US9141544B2 (en) * 2012-06-26 2015-09-22 Qualcomm Incorporated Cache memory with write through, no allocate mode
US9128845B2 (en) * 2012-07-30 2015-09-08 Hewlett-Packard Development Company, L.P. Dynamically partition a volatile memory for a cache and a memory partition
US20140032818A1 (en) * 2012-07-30 2014-01-30 Jichuan Chang Providing a hybrid memory
KR20150001218A (en) * 2013-06-26 2015-01-06 한국전자통신연구원 Method for controlling cache memory and apparatus thereof
US20150006935A1 (en) * 2013-06-26 2015-01-01 Electronics And Telecommunications Research Institute Method for controlling cache memory and apparatus for the same
KR102027573B1 (en) 2013-06-26 2019-11-04 한국전자통신연구원 Method for controlling cache memory and apparatus thereof
US20150161047A1 (en) * 2013-12-10 2015-06-11 Samsung Electronics Co., Ltd. Multi-core cpu system for adjusting l2 cache character, method thereof, and devices having the same
US9817759B2 (en) * 2013-12-10 2017-11-14 Samsung Electronics Co., Ltd. Multi-core CPU system for adjusting L2 cache character, method thereof, and devices having the same
US11520700B2 (en) 2018-06-29 2022-12-06 Intel Corporation Techniques to support a holistic view of cache class of service for a processor cache
US20210255972A1 (en) * 2019-02-13 2021-08-19 Google Llc Way partitioning for a system-level cache
US11620243B2 (en) * 2019-02-13 2023-04-04 Google Llc Way partitioning for a system-level cache

Also Published As

Publication number Publication date
WO2007099483A2 (en) 2007-09-07
WO2007099483A3 (en) 2008-01-03
JP2009528610A (en) 2009-08-06
EP1999596A2 (en) 2008-12-10
CN101395586A (en) 2009-03-25

Similar Documents

Publication Publication Date Title
US20110113215A1 (en) Method and apparatus for dynamic resizing of cache partitions based on the execution phase of tasks
JP5040773B2 (en) Memory buffer allocation device and program
US7840775B2 (en) Storage system in which resources are dynamically allocated to logical partition, and logical division method for storage system
JP4838240B2 (en) Power control apparatus in information processing apparatus
US20110010503A1 (en) Cache memory
US20060288159A1 (en) Method of controlling cache allocation
US9063794B2 (en) Multi-threaded processor context switching with multi-level cache
US9507633B2 (en) Scheduling method and system
US20120079494A1 (en) System And Method For Maximizing Data Processing Throughput Via Application Load Adaptive Scheduling And Content Switching
US10768684B2 (en) Reducing power by vacating subsets of CPUs and memory
JPWO2009150815A1 (en) Multiprocessor system
US8769201B2 (en) Technique for controlling computing resources
US20080244118A1 (en) Method and apparatus for sharing buffers
KR20030020397A (en) A method for scalable memory efficient thread-local object allocation
CN111625339A (en) Cluster resource scheduling method, device, medium and computing equipment
CN102193828B (en) Decoupling the number of logical threads from the number of simultaneous physical threads in a processor
CN112783652A (en) Method, device and equipment for acquiring running state of current task and storage medium
CN101847128A (en) TLB management method and device
US11294724B2 (en) Shared resource allocation in a multi-threaded microprocessor
US8607245B2 (en) Dynamic processor-set management
WO2008026142A1 (en) Dynamic cache partitioning
US20060100986A1 (en) Task switching
Sudarsan et al. Dynamic resizing of parallel scientific simulations: A case study using LAMMPS
KR20150136811A (en) Apparatus and Method for managing memory in an embedded system
KR20230143025A (en) Resource-aware device allocation of multiple gpgpu applications on multi-accelerator system

Legal Events

Date Code Title Description
AS Assignment

Owner name: NXP, B.V., NETHERLANDS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:THOMAS, BIJO;KRISHNAN, SRIRAM;KULKARNI, MILIND MANOHAR;AND OTHERS;SIGNING DATES FROM 20080821 TO 20080901;REEL/FRAME:021575/0312

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION

AS Assignment

Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND

Free format text: SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:038017/0058

Effective date: 20160218

AS Assignment

Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND

Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:039361/0212

Effective date: 20160218

AS Assignment

Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND

Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:042762/0145

Effective date: 20160218

Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND

Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:042985/0001

Effective date: 20160218

AS Assignment

Owner name: NXP B.V., NETHERLANDS

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:050745/0001

Effective date: 20190903

AS Assignment

Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND

Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:051145/0184

Effective date: 20160218

Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND

Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:051029/0387

Effective date: 20160218

Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND

Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:051029/0001

Effective date: 20160218

Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND

Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:051029/0001

Effective date: 20160218

Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND

Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:051030/0001

Effective date: 20160218

Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND

Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:051029/0387

Effective date: 20160218

Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND

Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:051145/0184

Effective date: 20160218