US20110101439A1 - Interconnection structures for semicondcutor devices - Google Patents
Interconnection structures for semicondcutor devices Download PDFInfo
- Publication number
- US20110101439A1 US20110101439A1 US12/987,440 US98744011A US2011101439A1 US 20110101439 A1 US20110101439 A1 US 20110101439A1 US 98744011 A US98744011 A US 98744011A US 2011101439 A1 US2011101439 A1 US 2011101439A1
- Authority
- US
- United States
- Prior art keywords
- impurity regions
- layer
- insulation layer
- cell
- inter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 229910052751 metal Inorganic materials 0.000 claims abstract description 143
- 239000002184 metal Substances 0.000 claims abstract description 143
- 238000009413 insulation Methods 0.000 claims abstract description 90
- 238000010276 construction Methods 0.000 claims abstract description 55
- 239000004065 semiconductor Substances 0.000 claims abstract description 41
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 239000012535 impurity Substances 0.000 claims description 80
- 230000004888 barrier function Effects 0.000 claims description 36
- 239000010949 copper Substances 0.000 claims description 18
- 239000012560 cell impurity Substances 0.000 claims description 17
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 17
- 229910052721 tungsten Inorganic materials 0.000 claims description 17
- 239000010937 tungsten Substances 0.000 claims description 17
- 239000010936 titanium Substances 0.000 claims description 16
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 12
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 12
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 12
- 229910052782 aluminium Inorganic materials 0.000 claims description 12
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 12
- 229910052802 copper Inorganic materials 0.000 claims description 12
- 229910052719 titanium Inorganic materials 0.000 claims description 12
- 238000007667 floating Methods 0.000 claims description 10
- 229910052715 tantalum Inorganic materials 0.000 claims description 10
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 10
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- -1 tungsten-nitride Chemical compound 0.000 claims description 6
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 238000000034 method Methods 0.000 description 33
- 238000005530 etching Methods 0.000 description 15
- 229910052581 Si3N4 Inorganic materials 0.000 description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 12
- 230000002093 peripheral effect Effects 0.000 description 11
- 238000004519 manufacturing process Methods 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 229910052814 silicon oxide Inorganic materials 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 238000000059 patterning Methods 0.000 description 7
- 238000002955 isolation Methods 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- IVHJCRXBQPGLOV-UHFFFAOYSA-N azanylidynetungsten Chemical compound [W]#N IVHJCRXBQPGLOV-UHFFFAOYSA-N 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000000465 moulding Methods 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000011295 pitch Substances 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000012774 insulation material Substances 0.000 description 2
- 238000007493 shaping process Methods 0.000 description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
Definitions
- the present invention relates generally to integrated circuit devices and methods of forming the same and, more particularly, to interconnection structures for integrated circuit devices and methods of forming the same.
- Operating frequencies and integration densities are technical factors that may influence the cost of semiconductor devices. Device manufacturers are generally concerned with enhancing device performance and factors that affect the commercial value of the devices. As the operating frequency (or speed) is mostly affected by the resistance of interconnections connecting electrodes of transistors to each other in circuit patterns, it may be desirable to reduce the resistance of interconnections and to use techniques to improve operation and/or integration characteristics. Considering that the resistance of interconnections is dependent on the resistivity and sectional area of a material used for the interconnections, there has been proposed a technique for forming interconnections using a low-resistivity material, such as aluminum (Al) or copper (Cu). The Cu damascene process is a typical technique used to reduce interconnection resistance.
- Al aluminum
- Cu copper
- a shrink-down of pitches on conductive patterns, including interconnections may be used to enhance the integration density of a semiconductor device.
- a shrink-down in pitches of interconnections may cause the sheet resistance of the interconnections to increase.
- Such interconnections may use barrier metal layers to reduce the likelihood of an abnormal reaction and a diffusion of impurities.
- FIG. 1 is a cross-section diagram that illustrates a conventional process for forming a semiconductor device that includes interconnection structures.
- a domain C 1 depicts a partial section of a cell array region taken along a first direction
- a domain C 2 depicts a vertical section of the domain C 1 taken on a plane a.
- a field isolation layer 20 is formed in predetermined regions of a semiconductor substrate 10 to define active regions.
- the semiconductor substrate 10 may be divided into a cell array region and a peripheral region.
- a gate insulation layer 32 and a gate conductive layer 34 are patterned to form a gate pattern 30 .
- impurity regions 40 are provided in the active regions.
- an inter-level insulation layer 50 is deposited.
- the inter-level insulation layer 50 is patterned to form a first contact hole 55 partially opening the impurity regions of the cell array region.
- the impurity regions 50 exposed by the first contact hole 55 will be connected to a bitline formed by the subsequent process.
- the plug conductive layer is etched away until the top surface of the inter-level insulation layer 50 is exposed.
- a contact plug 60 is formed that is connected to the impurity region 40 through the first contact hole 55 .
- the contact plug 60 may be made of polycrystalline silicon.
- a barrier metal layer 92 and a metal layer 94 are deposited on the inter-level insulation layer 50 in sequence.
- the metal layer 94 and the barrier metal layer 92 are patterned to form interconnecting constructions 90 connected to the contact plugs 60 .
- the patterning process for the interconnecting constructions 90 is carried out with an over-etching technique. As a result of the over-etching, the inter-level insulation layer 50 around the interconnecting construction 90 becomes lower than the bottom of the barrier metal layer 92 .
- the contact plug 60 may not be etched anisotropically or removed faster than the inter-level insulation layer 50 .
- the top sides of the contact plug 60 may be etched away to result in a narrower section thereof, which causes the contact plug 60 not to be connected to the bitline 90 or to remain with high resistance.
- the metal layer 94 is usually formed of aluminum, tungsten, or copper for high conductivity. But, when the metal layer 94 directly contacts the impurity regions 40 or the contact plug 60 that contains silicon, it may cause the degradation of quality due to impurity diffusion and abnormal reactions between the metal and the silicon.
- the barrier metal layer 92 is provided over a critical thickness t c to reduce the likelihood of such problems arising from contact between the metal and the silicon.
- the necessity for the critical thickness of the barrier metal layer 92 may reduce the ratio of an effective sectional area of the metal in the interconnecting construction 90 , which may cause an abrupt increase of the sheet resistance in the interconnecting construction 90 .
- the minimum pitch of the interconnecting construction 90 is reduced to less than 0.1 ⁇ m, then the increase of the sheet resistance may be an important issue to address in fabricating high-frequency semiconductor devices.
- an interconnection structure for a semiconductor device includes an inter-level insulation layer disposed on a semiconductor substrate.
- First contact constructions penetrate the inter-level insulation layer.
- Second contact constructions penetrate the inter-level insulation layer.
- Metal interconnections connect the first contact constructions to the second contact constructions on the inter-level insulation layer.
- the first contact constructions include first and second plugs stacked in sequence and the second contact constructions include the second plug.
- gate layers are interposed between the inter-level insulation layer and the semiconductor substrate, the gate layers being connected to the metal interconnections by the second contact constructions.
- the first plug comprises polycrystalline silicon.
- the second plug comprises a first barrier metal layer and a first metal layer, the first barrier metal layer comprising titanium, titanium-nitride, tungsten-nitride, tantalum, and/or tantalum-nitride, the first metal layer comprising tungsten, aluminum, and/or copper.
- the metal interconnections comprise a second barrier metal layer and a second metal layer, the second barrier metal layer comprising titanium, titanium-nitride, tungsten-nitride, tantalum, and/or tantalum-nitride, the second metal layer comprising tungsten, aluminum, and/or copper.
- the semiconductor substrate comprises a cell array region where cell transistors are arranged with cell impurity regions and cell gate layers, a low voltage region where low voltage transistors are arranged with low voltage impurity regions and low voltage gate layers, and a high voltage region where high voltage transistors are arranged with high voltage impurity regions and high voltage gate layers.
- the cell impurity regions are partially connected to the metal interconnections by the first contact constructions, and the cell gate layers, the low voltage gate layers, and the high voltage gate layers are connected to the metal interconnections by the second contact constructions.
- the low voltage impurity regions are connected to the metal interconnections by the first contact constructions and the high voltage impurity regions are connected to the metal interconnections by the second contact constructions.
- the high voltage impurity regions are connected to the metal interconnections by the first contact constructions and the low voltage impurity regions are connected to the metal interconnections by the second contact constructions.
- the high voltage and low voltage impurity regions are connected to the metal interconnections by the first contact constructions.
- the high voltage and low voltage impurity regions are connected to the metal interconnections by the second contact constructions.
- the cell gate layers comprise a floating gate electrode layer, a gate inter-level insulation layer, and a control gate layer, and the cell transistors and the metal interconnections form a cell array architecture of a NAND flash memory.
- an interconnection structure for a semiconductor device includes a semiconductor substrate comprising a cell array region, a low voltage region, and a high voltage region.
- Cell transistors are disposed in the cell array region, which comprises cell impurity regions and cell gate layers.
- Low voltage transistors are disposed in the low voltage region, which comprises low voltage impurity regions and low voltage gate layers.
- High voltage transistors are disposed in the high voltage region, which comprises high voltage impurity regions and high voltage gate layers.
- Metal interconnections are disposed on the semiconductor substrate.
- First contact constructions connect the cell impurity regions to the metal interconnections.
- Second contact constructions connect the metal interconnections to the cell gate layers, the low voltage gate layers, and the high voltage gate layers.
- the first contact constructions comprise first and second plugs stacked in sequence and the second contact constructions comprise the second plugs.
- an interconnection structure for a semiconductor device is formed by forming an inter-level insulation layer on a semiconductor substrate.
- First contact holes are formed that penetrate the inter-level insulation layer.
- First plugs are formed in the first contact holes.
- Second contact holes are formed that penetrate the inter-level insulation layer.
- Second plugs are formed that fill the first contact holes and the second contact holes.
- Metal interconnections are formed that are connected to the second plugs on the inter-level insulation layer.
- an interconnection structure for a semiconductor device is formed by forming cell transistors in cell impurity regions and cell gate layers in a cell array region of a semiconductor substrate, low voltage transistors in low voltage impurity regions and low voltage gate layers in a low voltage region of the semiconductor substrate, and high voltage transistors in high voltage impurity regions and high voltage gate layers in a high voltage region of the semiconductor substrate.
- An inter-level insulation layer is formed on the resultant structure comprising the transistors.
- the inter-level insulation layer is patterned to form first contact holes partially exposing the cell impurity regions.
- First plugs are formed in the first contact holes.
- the inter-level insulation layer is patterned to form second contact holes partially exposing the cell gate layers, the low voltage gate layers, and the high voltage gate layers. Second plugs are formed to fill the second contact holes and the first contact holes. Interconnections are formed that are connected to the second plugs on the inter-level insulation layer.
- FIG. 1 is a cross-section diagram that illustrates a conventional process for forming a semiconductor device that includes interconnection structures
- FIGS. 2A through 6B are cross-section diagrams that illustrate a processing flow for manufacturing a semiconductor device according to some embodiments of the present invention
- FIGS. 7A and 7B are cross-section diagrams that illustrate a processing flow for manufacturing a semiconductor device according to further embodiments of the present invention.
- FIGS. 8 through 11 , FIG. 12 , FIGS. 13 through 15 , and FIG. 16 are cross-section diagrams that illustrate processing flows for manufacturing a semiconductor device according to various other embodiments of the invention, respectively.
- first and second are used herein to describe various regions, layers and/or sections, these regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one region, layer or section from another region, layer or section. Thus, a first region, layer or section discussed below could be termed a second region, layer or section, and similarly, a second region, layer or section may be termed a first region, layer or section without departing from the teachings of the present invention.
- relative terms such as “lower” or “bottom” and “upper” or “top” may be used herein to describe one element's relationship to another element as illustrated in the figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as being on the “lower” side of other elements would then be oriented on “upper” sides of the other elements. The exemplary term “lower” can, therefore, encompass both an orientation of “lower” and “upper,” depending of the particular orientation of the figure.
- Embodiments of the present invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments of the present invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region.
- a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place.
- the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the present invention.
- FIGS. 2A through 6B are cross-section diagrams that illustrate a processing flow for manufacturing a semiconductor device according to some embodiments of the present invention.
- FIGS. 7A and 7B are cross-section diagrams that illustrate a processing flow for manufacturing a semiconductor device according to further embodiments of the present invention.
- FIGS. 8 through 11 , FIG. 12 , FIGS. 13 through 15 , and FIG. 16 are cross-section diagrams that illustrate processing flows for manufacturing a semiconductor device according to various other embodiments of the invention, respectively.
- domains I, II, and III denote a common source region, a drain contact region, and a gate contact region, of a cell array region, respectively.
- FIGS. 2B , 3 B, 4 B, 5 B, 6 B, and 7 B, and in FIGS. 8 through 16 domains IV and V denote high and low voltage fields of a peripheral region, respectively.
- a field isolation region 110 is formed to define active regions in predetermined positions in the semiconductor substrate 100 .
- the cell array region comprises the common source region I, the drain contact region II, and the gate contact region III, while the peripheral region comprises the low voltage field IV and the high voltage field V.
- a gate insulation layer, a cell gate insulation layer 120 c , a low-voltage (LV) gate insulation layer 1201 , and a high-voltage (HV) gate insulation layer 120 h are formed on the active regions of the cell array region, the low voltage field IV, and the high voltage field V, respectively.
- the HV gate insulation layer 120 h may be thicker than the cell gate insulation layer 120 c and the LV gate insulation layer 1201 .
- a gate patterning process forms cell gate layers 130 c , LV gate layers 1301 , and HV gate layers 130 h that cross over the active regions and the field isolation layer 110 in the LV field IV and the HV field V.
- the cell gate layer 130 c comprises a floating gate electrode layer 132 , a gate inter-level insulation layer 134 , and a control gate electrode layer ( 136 , 138 ) that are stacked in sequence.
- the control gate electrode layer comprises a lower control gate electrode layer 136 and a higher control gate electrode layer 138 .
- the floating gate electrode layer 132 and the lower control gate electrode layer 136 may comprise polycrystalline silicon, while the gate inter-level insulation layer 134 may comprise a compound of silicon, silicon-nitride, and silicon-oxide.
- the higher control gate electrode layer 138 comprises a low-resistance conductive material, such as tungsten-silicide or tungsten.
- the gate inter-level insulation layer 134 is removed in the LV and HV fields IV and V.
- the LV and HV gate layers, 1301 and 130 h are each formed of the floating gate electrode layer 132 , the lower control gate electrode layer 136 , and the higher control gate layer 138 .
- the gate inter-level insulation layer 134 may be partially removed at predetermined positions in the cell array region. As a result, in the predetermined positions of the cell array region, a selection gate layer 130 s contacts the lower control gate electrode layer 136 directly with the floating gate electrode layer 132 .
- the cell impurity region 140 c includes source impurity regions 140 s and drain impurity regions 140 d in the active regions between the patterns of the selection gate layers 130 s .
- the ion implantation process may be carried out with a mask using the pattern of the gate layers 130 or the pattern of gate spacers 150 formed on both side walls of the gate layers 130 . Therefore, the impurity regions 140 may have different positions with respect to each other in the cell array region.
- a lower insulation layer 160 is deposited.
- the lower insulation layer 160 may comprise a silicon-oxide.
- the lower insulation layer 160 is patterned to form common source trenches 165 that expose the source impurity regions 140 s .
- the common source trenches 165 are filled with a common source line layer 170 that connects the common source regions 140 s .
- the common source line layer 170 may comprise tungsten.
- a higher insulation layer 180 is formed in the resultant structure with the common source line layer 170 .
- the higher and lower insulation layers, 180 and 160 constitute an inter-level insulation layer.
- the higher insulation layer 180 may comprise silicon-oxide, silicon-nitride, silicon-oxynitride, and/or porous insulation materials.
- the higher and lower insulation layers, 180 and 160 are sequentially patterned to form first contact holes 181 that expose the drain impurity regions 140 d and the HV impurity regions 140 h .
- the process for providing the first contact holes 181 may be implemented using an anisotropic etching technique incorporating an etch recipe having an etch selectivity against silicon.
- the lower insulation layer 160 may comprise silicon-nitride and silicon-oxide that are deposited in sequence, where the silicon-nitride is used as an etch stop layer for shaping the first contact holes 181 .
- the first contact holes 181 expose the drain impurity regions 140 d , the HV impurity regions 140 h , and the low voltage impurity regions 1401 (refer to FIGS. 3A and 8 ).
- the first contact holes 181 are confined within the cell array region. In other words, the first contact holes 181 expose only the drain impurity regions 140 d , without being formed in the peripheral region (see FIGS. 3A and 13 ).
- a first conductive layer is deposited on the higher insulation layer 180 filling the first contact holes 181 .
- the first conductive material may comprise polycrystalline silicon.
- the first conductive layer is then etched away to expose the top surface of the higher insulation layer 180 .
- the first conductive layer may be etched by means of a chemical and mechanical polishing (CMP) process.
- CMP chemical and mechanical polishing
- the first contact holes 181 are filled with the first contact layer on the same level of the higher insulation layer 180 .
- the top surface of the first conductive layer is further etched away to be lower than that of the higher insulation layer 180 .
- first plugs 190 fill the first contact holes 181 but are at a lower level than the higher insulation layer 180 .
- the top surfaces of the first plugs 190 may be leveled higher than that of the lower insulation layer 160 .
- the first plugs 190 are connected to the drain impurity regions 140 d and the HV impurity regions 140 h . In other embodiments of the invention, the first plugs 190 are connected to the drain impurity regions 140 d , the HV impurity regions 140 h , and the LV impurity regions 1401 (see FIGS. 4A and 9 ). In still other embodiments of the invention, the first plugs 190 are connected only to the drain impurity regions 140 d.
- the higher and lower insulation layers 180 and 160 are subsequently patterned to form second contact holes 182 partially exposing the top surfaces of the cell gate layers 130 c , the LV gate layers 1301 , and the HV gate layers 130 h.
- the process of forming the second contact holes 182 is carried out by anisotropically etching the higher and lower insulation layers, 180 and 160 , in sequence with an etch mask pattern (not shown) laid on the higher insulation layer 180 .
- the anisotropic etching process for the second contact holes 182 may include a first operation that includes an etch recipe capable of etching a silicon-oxide with the etch selectivity against silicon-nitride, and a second operation that involves the use of an etch recipe capable of etching a silicon-nitride with the etch selectivity against the higher control gate electrode layer 138 .
- the silicon-nitride forming the lower insulation layer 160 acts as an etch stop in the first operation of the anisotropic etching process for the second contact holes 182 .
- the etch mask pattern has openings that expose the higher insulation layer 180 over the cell gate layers 130 c , the LV gate layers 1301 , and the HV gate layers 130 h .
- the mask pattern exposes the top surface of the higher insulation layer 180 over the LV impurity regions 1401 , which makes the second contact holes open over the top surfaces of the LV impurity regions 1401 as shown in FIG. 5B .
- the process for shaping the second contact holes 182 may expose the LV impurity regions 1401 while reducing the technical difficulty due to the difference of heights between the gate layer and the active region.
- the etching operation may be carried out by means of an etch recipe capable of removing the silicon-nitride with the etch selectivity against silicon.
- a second conductive layer is deposited on the resultant structure in which the second contact holes 182 are settled.
- the second conductive layer fills up the tops of the first contact holes 181 as well as the second contact holes 182 .
- the second conductive layer is then planarized by etching until the top of the higher insulation layer 180 is exposed, resulting in second plugs 200 .
- the second plugs 200 fill up the tops of the first contact holes 181 as well as the second contact holes 182 .
- the first contact holes 181 are filled with the first and second plugs, 190 and 200 , deposited in sequence, while the second contact holes 182 are filled only with the second plugs 200 .
- the second conductive layer comprises a first barrier metal layer 202 and a first metal layer 204 that are stacked in sequence.
- the first barrier metal layer 202 comprises titanium (Ti), titanium-nitride (TiN), tungsten-nitride (WN), tantalum (Ta), and/or tantalum-nitride (TaN), while the first metal layer 204 comprises tungsten (W), aluminum (Al), and/or copper (Cu).
- the first barrier metal layer 202 may comprise layers of titanium and titanium-nitride deposited in sequence, and the first metal layer 204 may comprise tungsten.
- the first barrier metal layer 202 prevents the first metal layer 204 from directly contacting the first plugs 190 .
- the second contact holes 182 do not expose the impurity regions 1401 and 140 h located in the peripheral region.
- the second plugs 200 are connected directly to the tops of the cell gate layers 130 c , the LV gate layers 1301 , and the HV gate layers 130 h , and connected to the LV and HV impurity regions, 1401 and 140 h , through the first plugs 190 (see FIGS. 5A and 10 ). Normally, the second plugs 200 connected to the gate layers 130 c , 1301 , and 130 h are disposed over the filed isolation layers 110 .
- the second contact holes 182 expose all of the impurity regions 1401 and 140 h in the peripheral region.
- the second plugs 200 are connected directly to the tops of the gate layers 130 c , 1301 , and 130 h , the LV impurity region 1401 , and the HV impurity region 140 h (see FIGS. 14 and 10 ).
- a third conductive layer is deposited and patterned to form metal interconnections 220 connected to the tops of the second plugs 200 .
- An inter-metal insulation layer 230 is deposited on the structure having the metal interconnections 220 .
- the third conductive layer may comprise a second barrier metal layer 222 and a second metal layer 224 that are stacked in sequence.
- the second barrier metal layer 222 comprises titanium (Ti), titanium-nitride (TiN), tungsten-nitride (WN), tantalum (Ta), and/or tantalum-nitride (TaN), while the second metal layer 224 comprises tungsten (W), aluminum (Al), and/or copper (Cu).
- the second barrier metal layer 222 may comprise layers of titanium and titanium-nitride deposited in sequence, and the second metal layer 224 may comprise tungsten.
- the metal interconnections 220 may comprise the second metal layer 224 without the second barrier metal layer 220 .
- the metal interconnections 220 form bitlines that are each connected to the drain impurity regions 140 d in the cell array region.
- the cell impurity regions 140 c are each disposed between the drain impurity regions 140 d connected to the bitlines and the source impurity regions 140 s connected to the common source line layer 170 .
- the patterns of the cell gate layers 130 c are arranged between the cell impurity regions 140 c .
- the selection gate layers 130 s are disposed adjacent to the source impurity regions 140 s and the drain impurity regions 140 d.
- the process of patterning the third conductive layer is carried out through anisotropic etching by means of an etch mask pattern that defines the metal interconnections 220 on the third conductive layer.
- Some embodiments of the invention include the process of forming the metal interconnections 220 with the patterning process (see FIGS. 6A , 6 B, 11 , and 15 ).
- the patterning process may also include an over-etching effect to prevent a short circuit between the adjacent interconnections.
- the contact plug 60 of FIG. 1
- the contact plug results in a narrow section because the top sides are excessively over-etched.
- the second plugs 200 of metal are disposed under the metal interconnections 220
- the second plugs 200 are etched in an anisotropic etch mode while prosecuting the over-etch process for the metal interconnections 220 .
- problems with the conventional technique e.g., the narrow section of the contact plug may be reduced and/or overcome.
- the metal interconnections 220 may be formed by means of a damascene process (refer to FIGS. 7A , 7 B, 12 , and 16 ).
- the damascene process is carried out by forming interconnection grooves 235 to expose the tops of the second plugs 200 after deposing and patterning a molding layer 230 ′ on the structure having the second plugs 200 .
- the third conductive layer is deposited thereon to fill the interconnection grooves 235 and is planarized by etching until the top of the molding layer 230 ′ is exposed.
- the third conductive layer may comprise the second barrier metal layer 222 and the second metal layer 224 that are stacked in sequence.
- the thickness of the second metal layer 224 may be thinner than the critical thickness t c of the conventional case.
- some embodiments of the present invention may not include the second barrier metal layer 222 if the second metal layer 224 is made of the same material as the first metal layer 204 , or is not involved in the technical problems due to the impurities.
- the field isolation layer 110 is disposed at predetermined regions of the semiconductor substrate 100 .
- the semiconductor substrate 100 comprises the cell array region and the peripheral regions.
- the cell array region comprises the common source region I, the drain contact region II, and the gate contact region IV, while the peripheral region comprises the LV region IV and the HV region V.
- the cell gate insulation layer 120 c , the LV gate insulation layer 1201 , and the HV gate insulation layer 120 h are formed on the LV and HV regions IV and V.
- the HV gate insulation layer 120 h is usually thicker than the cell gate insulation layer 120 c and the LV gate insulation layer 1201 .
- the patterns of the cell gate layers 130 c , the LV gate layers 1301 , and the HV gate layers 130 h are arranged so as to cross the tops of the active regions and the field isolation layer 110 .
- the cell gate layer 130 c comprises the floating gate electrode layer 132 , the gate inter-level insulation layer 134 , and the control gate electrode layer that are stacked in sequence.
- the control gate electrode layer comprises the lower and higher control gate electrode layers, 136 and 138 , which are deposited in sequence.
- the floating gate electrode layer 132 and the lower control gate electrode layer 136 comprise polycrystalline silicon and the gate inter-level insulation layer 134 may comprise silicon-oxide, silicon-nitride, and/or silicon-oxide.
- the higher control gate electrode layer 138 comprises a low-resistance conductive material (e.g., tungsten-silicide or tungsten).
- the gate inter-level insulation layer 134 is partially removed to form patterns of the selection gate layers 130 s in which the lower control gate electrode layer 136 directly contacts the floating gate layer 132 .
- the LV and HV gate layers, 1301 and 130 h each comprise the floating gate electrode layer 132 , the lower control gate electrode layer 136 , and the higher control gate electrode layer 138 .
- the cell impurity regions 140 c , the LV impurity regions 1401 , and the HV impurity regions 140 h are each disposed in the cell array region, the LV region IV, and the HV region V.
- the cell impurity regions 140 c comprise the source and drain impurity regions, 140 s and 140 d , in the active regions between the patterns of the selection gate layers 130 s .
- the impurity regions may be formed in different patterns in accordance with locations.
- an inter-level insulation layer 140 is formed that comprises lower and higher insulation layers 160 and 180 .
- the lower insulation layer 160 comprises silicon-nitride and silicon-oxide stacked in sequence, while the higher insulation layer 180 comprises a silicon-oxide, a silicon-nitride, a silicon-oxynitride, and/or a porous insulation material.
- the lower insulation layer 160 comprises the common source line layer 170 connecting the source impurity regions 140 s .
- the common source line layer 179 may comprise tungsten (W).
- the metal interconnections 220 are laid on the higher insulation layer 180 . A part of the metal interconnections 220 is connected to the drain impurity regions 140 d by the first and second plugs 190 and 200 penetrating though the inter-level insulation layer.
- the first plug 190 may comprise polycrystalline silicon and the second plug may comprise the first barrier metal layer 202 and the first metal layer 204 stacked in sequence.
- the first barrier metal layer 202 comprises titanium (Ti), titanium-nitride (TiN), tungsten-nitride (WN), tantalum (Ta), and/or tantalum-nitride (TaN), while the first metal layer 204 comprises tungsten (W), aluminum (Al), and/or copper (Cu).
- the cell gate layers 130 c , the LV gate layers 1301 , and the HV gate layers 130 h are connected to the metal interconnections through the second plugs 200 without the first plugs 190 .
- the drain impurity regions 140 d are connected to the metal interconnections 220 through the first and second plugs 190 and 200 .
- the LV and HV impurity regions, 1401 and 140 h may also be connected with the metal interconnections 220 in various features.
- the HV impurity regions 140 h are connected to the metal interconnections 220 through the first and second plugs, 190 and 200 , which are stacked in sequence, while the LV impurity regions 1401 are connected to the metal interconnections 220 through the second plugs 200 (see FIGS. 6A , 6 B, 7 A, and 7 B).
- both the LV and HV impurity regions, 1401 and 140 h are connected to the metal interconnections 220 through the first and second plugs, 190 and 200 , which are stacked in sequence (see FIG. 6A , 7 A, 11 , and 12 ).
- both the LV and HV impurity regions, 1401 and 140 h are connected to the metal interconnections 220 just through the second plug 200 (see FIG. 6A , 7 A, 15 , and 16 ).
- the metal interconnections 220 may comprise the second barrier metal layer 222 and the second metal layer 224 that are stacked in sequence.
- the second barrier metal layer 222 comprises titanium (Ti), titanium-nitride (TiN), tungsten-nitride (WN), tantalum (Ta), and/or tantalum-nitride (TaN), while the second metal layer 224 comprises tungsten (W), aluminum (Al), and/or copper (Cu).
- the metal interconnections 220 are covered by the inter-metal insulation layer 230 .
- the molding layer 230 ′ is disposed between the metal interconnections 222 , and the second barrier metal layer 222 is interposed between the molding layer 230 ′ and the second metal layer 224 .
- the metal interconnections 220 may be formed of the second metal layer 224 without the second barrier metal layer 222 .
- the cell impurity regions and the cell gate layers form cell transistors in the cell array region.
- the cell transistors may be arranged in the cell array region of a NAND flash memory device.
- the LV impurity regions and the LV gate layers form LV transistors in the LV region.
- the HV impurity regions and the HV gate layers form HV transistors in the HV1 region.
- the LV and HV transistors may be arranged in the peripheral region including the LV and HV regions.
- the metal interconnections directly contact the second plugs made of a metallic material, without contacting the first plugs. Therefore, the barrier metal layer may have a thickness less than the critical thickness or the metal interconnections may be formed without the barrier metal layer. As a result, some embodiments of the present invention may be useful for manufacturing a high-frequency semiconductor device because they inhibit increases in the sheet resistance of the metal interconnections.
- the manufacturing processes of the invention are applicable without additional photolithographic steps relative to the conventional methods, improved devices may be obtained without increasing costs.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Non-Volatile Memory (AREA)
Abstract
An interconnection structure for a semiconductor device includes an inter-level insulation layer disposed on a semiconductor substrate. First contact constructions penetrate the inter-level insulation layer. Second contact constructions penetrate the inter-level insulation layer. Metal interconnections connect the first contact constructions to the second contact constructions on the inter-level insulation layer. The first contact constructions include first and second plugs stacked in sequence and the second contact constructions include the second plug.
Description
- This application claims priority under 35 U.S.C. §120 as a divisional application of U.S. patent application Ser. No. 11/022,240, filed Dec. 22, 2004, which in turn claims priority to Korean Patent Application No. 10-2004-0048119 filed Jun. 25, 2004, the disclosures of which are hereby incorporated herein by reference.
- The present invention relates generally to integrated circuit devices and methods of forming the same and, more particularly, to interconnection structures for integrated circuit devices and methods of forming the same.
- Operating frequencies and integration densities are technical factors that may influence the cost of semiconductor devices. Device manufacturers are generally concerned with enhancing device performance and factors that affect the commercial value of the devices. As the operating frequency (or speed) is mostly affected by the resistance of interconnections connecting electrodes of transistors to each other in circuit patterns, it may be desirable to reduce the resistance of interconnections and to use techniques to improve operation and/or integration characteristics. Considering that the resistance of interconnections is dependent on the resistivity and sectional area of a material used for the interconnections, there has been proposed a technique for forming interconnections using a low-resistivity material, such as aluminum (Al) or copper (Cu). The Cu damascene process is a typical technique used to reduce interconnection resistance.
- On the other hand, a shrink-down of pitches on conductive patterns, including interconnections, may be used to enhance the integration density of a semiconductor device. However, such a shrink-down in pitches of interconnections may cause the sheet resistance of the interconnections to increase. Such interconnections may use barrier metal layers to reduce the likelihood of an abnormal reaction and a diffusion of impurities.
-
FIG. 1 is a cross-section diagram that illustrates a conventional process for forming a semiconductor device that includes interconnection structures. InFIG. 1 , a domain C1 depicts a partial section of a cell array region taken along a first direction, while a domain C2 depicts a vertical section of the domain C1 taken on a plane a. - Referring to
FIG. 1 , afield isolation layer 20 is formed in predetermined regions of asemiconductor substrate 10 to define active regions. Thesemiconductor substrate 10 may be divided into a cell array region and a peripheral region. After depositing agate insulation layer 32 and a gateconductive layer 34 in sequence on the active regions, thoselayers gate pattern 30. From an ion implantation process with thegate pattern 30 as a mask,impurity regions 40 are provided in the active regions. - On the resultant structure where the
impurity regions 40 are formed, aninter-level insulation layer 50 is deposited. Theinter-level insulation layer 50 is patterned to form afirst contact hole 55 partially opening the impurity regions of the cell array region. Theimpurity regions 50 exposed by thefirst contact hole 55 will be connected to a bitline formed by the subsequent process. After depositing a plug conductive layer on the inter-level insulation layer and filling thefirst contact hole 55, the plug conductive layer is etched away until the top surface of theinter-level insulation layer 50 is exposed. As a result, acontact plug 60 is formed that is connected to theimpurity region 40 through thefirst contact hole 55. Thecontact plug 60 may be made of polycrystalline silicon. - A
barrier metal layer 92 and ametal layer 94 are deposited on theinter-level insulation layer 50 in sequence. Themetal layer 94 and thebarrier metal layer 92 are patterned to forminterconnecting constructions 90 connected to thecontact plugs 60. During this, to prevent short circuits among theinterconnecting constructions 90, the patterning process for theinterconnecting constructions 90 is carried out with an over-etching technique. As a result of the over-etching, theinter-level insulation layer 50 around the interconnectingconstruction 90 becomes lower than the bottom of thebarrier metal layer 92. - During the over-etching process, the
contact plug 60 may not be etched anisotropically or removed faster than theinter-level insulation layer 50. As a result, as shown inFIG. 1 , the top sides of thecontact plug 60 may be etched away to result in a narrower section thereof, which causes thecontact plug 60 not to be connected to thebitline 90 or to remain with high resistance. - In addition, the
metal layer 94 is usually formed of aluminum, tungsten, or copper for high conductivity. But, when themetal layer 94 directly contacts theimpurity regions 40 or thecontact plug 60 that contains silicon, it may cause the degradation of quality due to impurity diffusion and abnormal reactions between the metal and the silicon. Thebarrier metal layer 92 is provided over a critical thickness tc to reduce the likelihood of such problems arising from contact between the metal and the silicon. However, the necessity for the critical thickness of thebarrier metal layer 92 may reduce the ratio of an effective sectional area of the metal in the interconnectingconstruction 90, which may cause an abrupt increase of the sheet resistance in the interconnectingconstruction 90. Especially, if the minimum pitch of the interconnectingconstruction 90 is reduced to less than 0.1 μm, then the increase of the sheet resistance may be an important issue to address in fabricating high-frequency semiconductor devices. - According to some embodiments of the present invention, an interconnection structure for a semiconductor device includes an inter-level insulation layer disposed on a semiconductor substrate. First contact constructions penetrate the inter-level insulation layer. Second contact constructions penetrate the inter-level insulation layer. Metal interconnections connect the first contact constructions to the second contact constructions on the inter-level insulation layer. The first contact constructions include first and second plugs stacked in sequence and the second contact constructions include the second plug.
- In other embodiments of the present invention, gate layers are interposed between the inter-level insulation layer and the semiconductor substrate, the gate layers being connected to the metal interconnections by the second contact constructions.
- In still other embodiments of the present invention, the first plug comprises polycrystalline silicon. The second plug comprises a first barrier metal layer and a first metal layer, the first barrier metal layer comprising titanium, titanium-nitride, tungsten-nitride, tantalum, and/or tantalum-nitride, the first metal layer comprising tungsten, aluminum, and/or copper. The metal interconnections comprise a second barrier metal layer and a second metal layer, the second barrier metal layer comprising titanium, titanium-nitride, tungsten-nitride, tantalum, and/or tantalum-nitride, the second metal layer comprising tungsten, aluminum, and/or copper.
- In still other embodiments of the present invention, the semiconductor substrate comprises a cell array region where cell transistors are arranged with cell impurity regions and cell gate layers, a low voltage region where low voltage transistors are arranged with low voltage impurity regions and low voltage gate layers, and a high voltage region where high voltage transistors are arranged with high voltage impurity regions and high voltage gate layers. The cell impurity regions are partially connected to the metal interconnections by the first contact constructions, and the cell gate layers, the low voltage gate layers, and the high voltage gate layers are connected to the metal interconnections by the second contact constructions.
- In still other embodiments of the present invention, the low voltage impurity regions are connected to the metal interconnections by the first contact constructions and the high voltage impurity regions are connected to the metal interconnections by the second contact constructions.
- In still other embodiments of the present invention, the high voltage impurity regions are connected to the metal interconnections by the first contact constructions and the low voltage impurity regions are connected to the metal interconnections by the second contact constructions.
- In still other embodiments of the present invention, the high voltage and low voltage impurity regions are connected to the metal interconnections by the first contact constructions.
- In still other embodiments of the present invention, the high voltage and low voltage impurity regions are connected to the metal interconnections by the second contact constructions.
- In still other embodiments of the present invention, the cell gate layers comprise a floating gate electrode layer, a gate inter-level insulation layer, and a control gate layer, and the cell transistors and the metal interconnections form a cell array architecture of a NAND flash memory.
- In further embodiments of the present invention, an interconnection structure for a semiconductor device includes a semiconductor substrate comprising a cell array region, a low voltage region, and a high voltage region. Cell transistors are disposed in the cell array region, which comprises cell impurity regions and cell gate layers. Low voltage transistors are disposed in the low voltage region, which comprises low voltage impurity regions and low voltage gate layers. High voltage transistors are disposed in the high voltage region, which comprises high voltage impurity regions and high voltage gate layers. Metal interconnections are disposed on the semiconductor substrate. First contact constructions connect the cell impurity regions to the metal interconnections. Second contact constructions connect the metal interconnections to the cell gate layers, the low voltage gate layers, and the high voltage gate layers. The first contact constructions comprise first and second plugs stacked in sequence and the second contact constructions comprise the second plugs.
- In other embodiments of the present invention, an interconnection structure for a semiconductor device is formed by forming an inter-level insulation layer on a semiconductor substrate. First contact holes are formed that penetrate the inter-level insulation layer. First plugs are formed in the first contact holes. Second contact holes are formed that penetrate the inter-level insulation layer. Second plugs are formed that fill the first contact holes and the second contact holes. Metal interconnections are formed that are connected to the second plugs on the inter-level insulation layer.
- In further embodiments of the present invention, an interconnection structure for a semiconductor device is formed by forming cell transistors in cell impurity regions and cell gate layers in a cell array region of a semiconductor substrate, low voltage transistors in low voltage impurity regions and low voltage gate layers in a low voltage region of the semiconductor substrate, and high voltage transistors in high voltage impurity regions and high voltage gate layers in a high voltage region of the semiconductor substrate. An inter-level insulation layer is formed on the resultant structure comprising the transistors. The inter-level insulation layer is patterned to form first contact holes partially exposing the cell impurity regions. First plugs are formed in the first contact holes. The inter-level insulation layer is patterned to form second contact holes partially exposing the cell gate layers, the low voltage gate layers, and the high voltage gate layers. Second plugs are formed to fill the second contact holes and the first contact holes. Interconnections are formed that are connected to the second plugs on the inter-level insulation layer.
- Other features of the present invention will be more readily understood from the following detailed description of specific embodiments thereof when read in conjunction with the accompanying drawings, in which:
-
FIG. 1 is a cross-section diagram that illustrates a conventional process for forming a semiconductor device that includes interconnection structures; -
FIGS. 2A through 6B are cross-section diagrams that illustrate a processing flow for manufacturing a semiconductor device according to some embodiments of the present invention; -
FIGS. 7A and 7B are cross-section diagrams that illustrate a processing flow for manufacturing a semiconductor device according to further embodiments of the present invention; and -
FIGS. 8 through 11 ,FIG. 12 ,FIGS. 13 through 15 , andFIG. 16 are cross-section diagrams that illustrate processing flows for manufacturing a semiconductor device according to various other embodiments of the invention, respectively. - While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that there is no intent to limit the invention to the particular foal's disclosed, but on the contrary, the invention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the claims. Like reference numbers signify like elements throughout the description of the figures.
- It will be understood that when an element or layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, it can be directly on, connected, or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers present. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Like numbers refer to like elements throughout the description.
- It will be understood that although the terms first and second are used herein to describe various regions, layers and/or sections, these regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one region, layer or section from another region, layer or section. Thus, a first region, layer or section discussed below could be termed a second region, layer or section, and similarly, a second region, layer or section may be termed a first region, layer or section without departing from the teachings of the present invention.
- Furthermore, relative terms, such as “lower” or “bottom” and “upper” or “top” may be used herein to describe one element's relationship to another element as illustrated in the figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as being on the “lower” side of other elements would then be oriented on “upper” sides of the other elements. The exemplary term “lower” can, therefore, encompass both an orientation of “lower” and “upper,” depending of the particular orientation of the figure. Similarly, if the device in one of the figures is turned over, elements described as “below” or “beneath” other elements would then be oriented “above” the other elements. The exemplary terms “below” or “beneath” can, therefore, encompass both an orientation of above and below.
- Embodiments of the present invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments of the present invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the present invention.
- The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
- Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
-
FIGS. 2A through 6B are cross-section diagrams that illustrate a processing flow for manufacturing a semiconductor device according to some embodiments of the present invention.FIGS. 7A and 7B are cross-section diagrams that illustrate a processing flow for manufacturing a semiconductor device according to further embodiments of the present invention.FIGS. 8 through 11 ,FIG. 12 ,FIGS. 13 through 15 , andFIG. 16 are cross-section diagrams that illustrate processing flows for manufacturing a semiconductor device according to various other embodiments of the invention, respectively. InFIGS. 2A , 3A, 4A, 5A, 6A, and 7A, domains I, II, and III denote a common source region, a drain contact region, and a gate contact region, of a cell array region, respectively. InFIGS. 2B , 3B, 4B, 5B, 6B, and 7B, and inFIGS. 8 through 16 , domains IV and V denote high and low voltage fields of a peripheral region, respectively. - Referring to
FIGS. 2A and 2B , after preparing asemiconductor substrate 100 comprising a cell array region and a peripheral region, afield isolation region 110 is formed to define active regions in predetermined positions in thesemiconductor substrate 100. The cell array region comprises the common source region I, the drain contact region II, and the gate contact region III, while the peripheral region comprises the low voltage field IV and the high voltage field V. Subsequently, a gate insulation layer, a cellgate insulation layer 120 c, a low-voltage (LV)gate insulation layer 1201, and a high-voltage (HV)gate insulation layer 120 h are formed on the active regions of the cell array region, the low voltage field IV, and the high voltage field V, respectively. The HVgate insulation layer 120 h may be thicker than the cellgate insulation layer 120 c and the LVgate insulation layer 1201. - A gate patterning process forms cell gate layers 130 c, LV gate layers 1301, and HV gate layers 130 h that cross over the active regions and the
field isolation layer 110 in the LV field IV and the HV field V. Thecell gate layer 130 c comprises a floatinggate electrode layer 132, a gateinter-level insulation layer 134, and a control gate electrode layer (136, 138) that are stacked in sequence. The control gate electrode layer comprises a lower controlgate electrode layer 136 and a higher controlgate electrode layer 138. The floatinggate electrode layer 132 and the lower controlgate electrode layer 136 may comprise polycrystalline silicon, while the gateinter-level insulation layer 134 may comprise a compound of silicon, silicon-nitride, and silicon-oxide. The higher controlgate electrode layer 138 comprises a low-resistance conductive material, such as tungsten-silicide or tungsten. - During formation of the
cell gate layer 130 c, the gateinter-level insulation layer 134 is removed in the LV and HV fields IV and V. Thus, the LV and HV gate layers, 1301 and 130 h, are each formed of the floatinggate electrode layer 132, the lower controlgate electrode layer 136, and the highercontrol gate layer 138. The gateinter-level insulation layer 134 may be partially removed at predetermined positions in the cell array region. As a result, in the predetermined positions of the cell array region, aselection gate layer 130 s contacts the lower controlgate electrode layer 136 directly with the floatinggate electrode layer 132. - Next, an ion implantation process is carried out to form
cell impurity regions 140 c,LV impurity regions 1401, andHV impurity regions 140 h in the active regions of the LV and HV fields IV and V. Thecell impurity region 140 c includessource impurity regions 140 s and drainimpurity regions 140 d in the active regions between the patterns of the selection gate layers 130 s. The ion implantation process may be carried out with a mask using the pattern of the gate layers 130 or the pattern ofgate spacers 150 formed on both side walls of the gate layers 130. Therefore, the impurity regions 140 may have different positions with respect to each other in the cell array region. - On the resultant structure in which the impurity regions 140 are completed, a
lower insulation layer 160 is deposited. Thelower insulation layer 160 may comprise a silicon-oxide. Thelower insulation layer 160 is patterned to formcommon source trenches 165 that expose thesource impurity regions 140 s. Thecommon source trenches 165 are filled with a commonsource line layer 170 that connects thecommon source regions 140 s. The commonsource line layer 170 may comprise tungsten. - Referring to
FIGS. 3A and 3B , ahigher insulation layer 180 is formed in the resultant structure with the commonsource line layer 170. The higher and lower insulation layers, 180 and 160, constitute an inter-level insulation layer. Thehigher insulation layer 180 may comprise silicon-oxide, silicon-nitride, silicon-oxynitride, and/or porous insulation materials. - In some embodiments of the invention, the higher and lower insulation layers, 180 and 160, are sequentially patterned to form first contact holes 181 that expose the
drain impurity regions 140 d and theHV impurity regions 140 h. The process for providing the first contact holes 181 may be implemented using an anisotropic etching technique incorporating an etch recipe having an etch selectivity against silicon. Thelower insulation layer 160 may comprise silicon-nitride and silicon-oxide that are deposited in sequence, where the silicon-nitride is used as an etch stop layer for shaping the first contact holes 181. - In other embodiments of the invention, the first contact holes 181 expose the
drain impurity regions 140 d, theHV impurity regions 140 h, and the low voltage impurity regions 1401 (refer toFIGS. 3A and 8 ). - In still other embodiments of the invention, the first contact holes 181 are confined within the cell array region. In other words, the first contact holes 181 expose only the
drain impurity regions 140 d, without being formed in the peripheral region (seeFIGS. 3A and 13 ). - Referring to
FIGS. 4A and 4B , a first conductive layer is deposited on thehigher insulation layer 180 filling the first contact holes 181. The first conductive material may comprise polycrystalline silicon. The first conductive layer is then etched away to expose the top surface of thehigher insulation layer 180. The first conductive layer may be etched by means of a chemical and mechanical polishing (CMP) process. As a result, the first contact holes 181 are filled with the first contact layer on the same level of thehigher insulation layer 180. Next, the top surface of the first conductive layer is further etched away to be lower than that of thehigher insulation layer 180. As a result,first plugs 190 fill the first contact holes 181 but are at a lower level than thehigher insulation layer 180. The top surfaces of thefirst plugs 190 may be leveled higher than that of thelower insulation layer 160. - In some embodiments of the invention, the
first plugs 190 are connected to thedrain impurity regions 140 d and theHV impurity regions 140 h. In other embodiments of the invention, thefirst plugs 190 are connected to thedrain impurity regions 140 d, theHV impurity regions 140 h, and the LV impurity regions 1401 (seeFIGS. 4A and 9 ). In still other embodiments of the invention, thefirst plugs 190 are connected only to thedrain impurity regions 140 d. - Referring to
FIGS. 5A and 5B , the higher andlower insulation layers - The process of forming the second contact holes 182 is carried out by anisotropically etching the higher and lower insulation layers, 180 and 160, in sequence with an etch mask pattern (not shown) laid on the
higher insulation layer 180. The anisotropic etching process for the second contact holes 182 may include a first operation that includes an etch recipe capable of etching a silicon-oxide with the etch selectivity against silicon-nitride, and a second operation that involves the use of an etch recipe capable of etching a silicon-nitride with the etch selectivity against the higher controlgate electrode layer 138. During this, the silicon-nitride forming thelower insulation layer 160 acts as an etch stop in the first operation of the anisotropic etching process for the second contact holes 182. - The etch mask pattern has openings that expose the
higher insulation layer 180 over the cell gate layers 130 c, the LV gate layers 1301, and the HV gate layers 130 h. In some embodiments of the invention, the mask pattern exposes the top surface of thehigher insulation layer 180 over theLV impurity regions 1401, which makes the second contact holes open over the top surfaces of theLV impurity regions 1401 as shown inFIG. 5B . As discussed above, when the silicon-nitride of thelower insulation layer 160 acts as the etch stop layer, the process for shaping the second contact holes 182 may expose theLV impurity regions 1401 while reducing the technical difficulty due to the difference of heights between the gate layer and the active region. The etching operation may be carried out by means of an etch recipe capable of removing the silicon-nitride with the etch selectivity against silicon. - A second conductive layer is deposited on the resultant structure in which the second contact holes 182 are settled. The second conductive layer fills up the tops of the first contact holes 181 as well as the second contact holes 182. The second conductive layer is then planarized by etching until the top of the
higher insulation layer 180 is exposed, resulting in second plugs 200. The second plugs 200 fill up the tops of the first contact holes 181 as well as the second contact holes 182. As a result, the first contact holes 181 are filled with the first and second plugs, 190 and 200, deposited in sequence, while the second contact holes 182 are filled only with the second plugs 200. - According to some embodiments of the invention, the second conductive layer comprises a first
barrier metal layer 202 and afirst metal layer 204 that are stacked in sequence. The firstbarrier metal layer 202 comprises titanium (Ti), titanium-nitride (TiN), tungsten-nitride (WN), tantalum (Ta), and/or tantalum-nitride (TaN), while thefirst metal layer 204 comprises tungsten (W), aluminum (Al), and/or copper (Cu). The firstbarrier metal layer 202 may comprise layers of titanium and titanium-nitride deposited in sequence, and thefirst metal layer 204 may comprise tungsten. The firstbarrier metal layer 202 prevents thefirst metal layer 204 from directly contacting the first plugs 190. - In further embodiments of the invention, the second contact holes 182 do not expose the
impurity regions second plugs 200 are connected directly to the tops of the cell gate layers 130 c, the LV gate layers 1301, and the HV gate layers 130 h, and connected to the LV and HV impurity regions, 1401 and 140 h, through the first plugs 190 (seeFIGS. 5A and 10 ). Normally, thesecond plugs 200 connected to the gate layers 130 c, 1301, and 130 h are disposed over the filed isolation layers 110. - In still further embodiments of the invention, the second contact holes 182 expose all of the
impurity regions second plugs 200 are connected directly to the tops of the gate layers 130 c, 1301, and 130 h, theLV impurity region 1401, and theHV impurity region 140 h (seeFIGS. 14 and 10 ). - Referring to
FIGS. 6A and 6B , on the resultant structure where thesecond plugs 200 are constructed, a third conductive layer is deposited and patterned to formmetal interconnections 220 connected to the tops of the second plugs 200. Aninter-metal insulation layer 230 is deposited on the structure having themetal interconnections 220. - The third conductive layer may comprise a second
barrier metal layer 222 and asecond metal layer 224 that are stacked in sequence. The secondbarrier metal layer 222 comprises titanium (Ti), titanium-nitride (TiN), tungsten-nitride (WN), tantalum (Ta), and/or tantalum-nitride (TaN), while thesecond metal layer 224 comprises tungsten (W), aluminum (Al), and/or copper (Cu). The secondbarrier metal layer 222 may comprise layers of titanium and titanium-nitride deposited in sequence, and thesecond metal layer 224 may comprise tungsten. Themetal interconnections 220 may comprise thesecond metal layer 224 without the secondbarrier metal layer 220. - As a result, the
metal interconnections 220 form bitlines that are each connected to thedrain impurity regions 140 d in the cell array region. Thecell impurity regions 140 c are each disposed between thedrain impurity regions 140 d connected to the bitlines and thesource impurity regions 140 s connected to the commonsource line layer 170. The patterns of the cell gate layers 130 c are arranged between thecell impurity regions 140 c. The selection gate layers 130 s are disposed adjacent to thesource impurity regions 140 s and thedrain impurity regions 140 d. - The process of patterning the third conductive layer is carried out through anisotropic etching by means of an etch mask pattern that defines the
metal interconnections 220 on the third conductive layer. Some embodiments of the invention include the process of forming themetal interconnections 220 with the patterning process (seeFIGS. 6A , 6B, 11, and 15). - As stated above, the patterning process may also include an over-etching effect to prevent a short circuit between the adjacent interconnections. In the conventional case, the contact plug (60 of
FIG. 1 ) results in a narrow section because the top sides are excessively over-etched. According to some embodiments of the invention, however, as thesecond plugs 200 of metal are disposed under themetal interconnections 220, thesecond plugs 200 are etched in an anisotropic etch mode while prosecuting the over-etch process for themetal interconnections 220. As result, problems with the conventional technique, e.g., the narrow section of the contact plug may be reduced and/or overcome. - In some embodiments of the invention, the
metal interconnections 220 may be formed by means of a damascene process (refer toFIGS. 7A , 7B, 12, and 16). The damascene process is carried out by forming interconnection grooves 235 to expose the tops of thesecond plugs 200 after deposing and patterning amolding layer 230′ on the structure having the second plugs 200. Afterwards, the third conductive layer is deposited thereon to fill the interconnection grooves 235 and is planarized by etching until the top of themolding layer 230′ is exposed. - In the embodiments using such a damascene process, the third conductive layer may comprise the second
barrier metal layer 222 and thesecond metal layer 224 that are stacked in sequence. However, according to some embodiments of the invention, because thesecond metal layer 224 indirectly contacts thefirst plugs 190, the thickness of thesecond metal layer 224 may be thinner than the critical thickness tc of the conventional case. - In addition, some embodiments of the present invention may not include the second
barrier metal layer 222 if thesecond metal layer 224 is made of the same material as thefirst metal layer 204, or is not involved in the technical problems due to the impurities. - Returning to
FIGS. 6A and 6B , thefield isolation layer 110 is disposed at predetermined regions of thesemiconductor substrate 100. Thesemiconductor substrate 100 comprises the cell array region and the peripheral regions. The cell array region comprises the common source region I, the drain contact region II, and the gate contact region IV, while the peripheral region comprises the LV region IV and the HV region V. - The cell
gate insulation layer 120 c, the LVgate insulation layer 1201, and the HVgate insulation layer 120 h are formed on the LV and HV regions IV and V. The HVgate insulation layer 120 h is usually thicker than the cellgate insulation layer 120 c and the LVgate insulation layer 1201. - Further, in the cell array region, the LV region IV, and the HV region V, the patterns of the cell gate layers 130 c, the LV gate layers 1301, and the HV gate layers 130 h are arranged so as to cross the tops of the active regions and the
field isolation layer 110. - The
cell gate layer 130 c comprises the floatinggate electrode layer 132, the gateinter-level insulation layer 134, and the control gate electrode layer that are stacked in sequence. The control gate electrode layer comprises the lower and higher control gate electrode layers, 136 and 138, which are deposited in sequence. The floatinggate electrode layer 132 and the lower controlgate electrode layer 136 comprise polycrystalline silicon and the gateinter-level insulation layer 134 may comprise silicon-oxide, silicon-nitride, and/or silicon-oxide. The higher controlgate electrode layer 138 comprises a low-resistance conductive material (e.g., tungsten-silicide or tungsten). - On the other hand, at predetermined places in the peripheral region, the gate
inter-level insulation layer 134 is partially removed to form patterns of the selection gate layers 130 s in which the lower controlgate electrode layer 136 directly contacts the floatinggate layer 132. The LV and HV gate layers, 1301 and 130 h, each comprise the floatinggate electrode layer 132, the lower controlgate electrode layer 136, and the higher controlgate electrode layer 138. - The
cell impurity regions 140 c, theLV impurity regions 1401, and theHV impurity regions 140 h are each disposed in the cell array region, the LV region IV, and the HV region V. Thecell impurity regions 140 c comprise the source and drain impurity regions, 140 s and 140 d, in the active regions between the patterns of the selection gate layers 130 s. The impurity regions may be formed in different patterns in accordance with locations. - On the
semiconductor substrate 100 having the impurity regions 140, an inter-level insulation layer 140 is formed that comprises lower andhigher insulation layers lower insulation layer 160 comprises silicon-nitride and silicon-oxide stacked in sequence, while thehigher insulation layer 180 comprises a silicon-oxide, a silicon-nitride, a silicon-oxynitride, and/or a porous insulation material. Thelower insulation layer 160 comprises the commonsource line layer 170 connecting thesource impurity regions 140 s. The common source line layer 179 may comprise tungsten (W). - The
metal interconnections 220 are laid on thehigher insulation layer 180. A part of themetal interconnections 220 is connected to thedrain impurity regions 140 d by the first andsecond plugs first plug 190 may comprise polycrystalline silicon and the second plug may comprise the firstbarrier metal layer 202 and thefirst metal layer 204 stacked in sequence. According to some embodiments of the invention, the firstbarrier metal layer 202 comprises titanium (Ti), titanium-nitride (TiN), tungsten-nitride (WN), tantalum (Ta), and/or tantalum-nitride (TaN), while thefirst metal layer 204 comprises tungsten (W), aluminum (Al), and/or copper (Cu). - According to some embodiments of the invention, the cell gate layers 130 c, the LV gate layers 1301, and the HV gate layers 130 h are connected to the metal interconnections through the
second plugs 200 without the first plugs 190. Thedrain impurity regions 140 d are connected to themetal interconnections 220 through the first andsecond plugs - The LV and HV impurity regions, 1401 and 140 h, may also be connected with the
metal interconnections 220 in various features. In some embodiments of the invention, theHV impurity regions 140 h are connected to themetal interconnections 220 through the first and second plugs, 190 and 200, which are stacked in sequence, while theLV impurity regions 1401 are connected to themetal interconnections 220 through the second plugs 200 (seeFIGS. 6A , 6B, 7A, and 7B). - In further embodiments of the invention, both the LV and HV impurity regions, 1401 and 140 h, are connected to the
metal interconnections 220 through the first and second plugs, 190 and 200, which are stacked in sequence (seeFIG. 6A , 7A, 11, and 12). In still further embodiments of the invention, both the LV and HV impurity regions, 1401 and 140 h, are connected to themetal interconnections 220 just through the second plug 200 (seeFIG. 6A , 7A, 15, and 16). - Further, in other embodiments of the present invention, the
metal interconnections 220 may comprise the secondbarrier metal layer 222 and thesecond metal layer 224 that are stacked in sequence. The secondbarrier metal layer 222 comprises titanium (Ti), titanium-nitride (TiN), tungsten-nitride (WN), tantalum (Ta), and/or tantalum-nitride (TaN), while thesecond metal layer 224 comprises tungsten (W), aluminum (Al), and/or copper (Cu). In these embodiments, themetal interconnections 220 are covered by theinter-metal insulation layer 230. According to some embodiments of the invention, themolding layer 230′ is disposed between themetal interconnections 222, and the secondbarrier metal layer 222 is interposed between themolding layer 230′ and thesecond metal layer 224. In addition, themetal interconnections 220 may be formed of thesecond metal layer 224 without the secondbarrier metal layer 222. - In the aforementioned embodiments, the cell impurity regions and the cell gate layers form cell transistors in the cell array region. The cell transistors may be arranged in the cell array region of a NAND flash memory device. The LV impurity regions and the LV gate layers form LV transistors in the LV region. The HV impurity regions and the HV gate layers form HV transistors in the HV1 region. The LV and HV transistors may be arranged in the peripheral region including the LV and HV regions.
- From the embodiments of the present invention described above, it can be seen that the metal interconnections directly contact the second plugs made of a metallic material, without contacting the first plugs. Therefore, the barrier metal layer may have a thickness less than the critical thickness or the metal interconnections may be formed without the barrier metal layer. As a result, some embodiments of the present invention may be useful for manufacturing a high-frequency semiconductor device because they inhibit increases in the sheet resistance of the metal interconnections.
- In addition, even when the metal connections are shaped by patterning with an anisotropic etching process, the second plugs of metal can be etched together. Thus, the conventional problems, such as short circuits between plugs and interconnections or an increase of resistance therein, can be reduced. Because the manufacturing processes of the invention are applicable without additional photolithographic steps relative to the conventional methods, improved devices may be obtained without increasing costs.
- In concluding the detailed description, it should be noted that many variations and modifications can be made to the preferred embodiments without substantially departing from the principles of the present invention. All such variations and modifications are intended to be included herein within the scope of the present invention, as set forth in the following claims.
Claims (16)
1. An interconnection structure for a semiconductor device, comprising:
an inter-level insulation layer disposed on a semiconductor substrate;
first contact constructions penetrating the inter-level insulation layer;
second contact constructions penetrating the inter-level insulation layer; and
metal interconnections connecting the first contact constructions to the second contact constructions on the inter-level insulation layer;
wherein the first contact constructions comprise first and second plugs stacked in sequence and the second contact constructions comprise the second plug.
2. The interconnection structure as set forth in claim 1 , wherein a minimum pitch of the metal interconnections is less than about 0.1 μm.
3. The interconnection structure as set forth in claim 1 , further comprising:
gate layers interposed between the inter-level insulation layer and the semiconductor substrate, the gate layers being connected to the metal interconnections by the second contact constructions.
4. The interconnection structure as set forth in claim 1 , wherein the first plug comprises polycrystalline silicon;
wherein the second plug comprises a first barrier metal layer and a first metal layer, the first barrier metal layer comprising titanium, titanium-nitride, tungsten-nitride, tantalum, and/or tantalum-nitride, the first metal layer comprising tungsten, aluminum, and/or copper; and
wherein the metal interconnections comprise a second barrier metal layer and a second metal layer, the second barrier metal layer comprising titanium, titanium-nitride, tungsten-nitride, tantalum, and/or tantalum-nitride, the second metal layer comprising tungsten, aluminum, and/or copper.
5. The interconnection structure as set forth in claim 1 , wherein the semiconductor substrate comprises a cell array region where cell transistors are arranged with cell impurity regions and cell gate layers, a low voltage region where low voltage transistors are arranged with low voltage impurity regions and low voltage gate layers, and a high voltage region where high voltage transistors are arranged with high voltage impurity regions and high voltage gate layers; and
wherein the cell impurity regions are partially connected to the metal interconnections by the first contact constructions, and the cell gate layers, the low voltage gate layers, and the high voltage gate layers are connected to the metal interconnections by the second contact constructions.
6. The interconnection structure as set forth in claim 5 , wherein the low voltage impurity regions are connected to the metal interconnections by the first contact constructions and the high voltage impurity regions are connected to the metal interconnections by the second contact constructions.
7. The interconnection structure as set forth in claim 5 , wherein the high voltage impurity regions are connected to the metal interconnections by the first contact constructions and the low voltage impurity regions are connected to the metal interconnections by the second contact constructions.
8. The interconnection structure as set forth in claim 5 , wherein the high voltage and low voltage impurity regions are connected to the metal interconnections by the first contact constructions.
9. The interconnection structure as set forth in claim 5 , wherein the high voltage and low voltage impurity regions are connected to the metal interconnections by the second contact constructions.
10. The interconnection structure as set forth in claim 5 , wherein the cell gate layers comprise a floating gate electrode layer, a gate inter-level insulation layer, and a control gate layer, and the cell transistors and the metal interconnections form a cell array architecture of a NAND flash memory.
11. The interconnection structure as set forth in claim 1 , wherein the inter-level insulation layer has a top surface, wherein the first contact constructions penetrate the inter-level insulation layer while exposing the top surface of the inter-level insulation layer, wherein the second contact constructions penetrate the inter-level insulation layer while exposing the top surface of the inter-level insulation layer, and wherein the metal interconnections are disposed directly on the top surface of the inter-level insulation layer.
12. An interconnection structure for a semiconductor device, comprising:
a semiconductor substrate comprising a cell array region, a low voltage region, and a high voltage region;
cell transistors disposed in the cell array region, which comprises cell impurity regions and cell gate layers;
low voltage transistors disposed in the low voltage region, which comprises low voltage impurity regions and low voltage gate layers;
high voltage transistors disposed in the high voltage region, which comprises high voltage impurity regions and high voltage gate layers;
metal interconnections disposed on the semiconductor substrate;
first contact constructions connecting the cell impurity regions to the metal interconnections; and
second contact constructions connecting the metal interconnections to the cell gate layers, the low voltage gate layers, and the high voltage gate layers;
wherein the first contact constructions comprise first and second plugs stacked in sequence and the second contact constructions comprise the second plugs.
13. The interconnection structure as set forth in claim 12 , wherein the first plug comprises polycrystalline silicon;
wherein the second plug comprises a first barrier metal layer and a first metal layer, the first barrier metal layer comprising titanium, titanium-nitride, tungsten-nitride, tantalum, and/or tantalum-nitride, the first metal layer comprising tungsten, aluminum, and/or copper; and
wherein the metal interconnection comprises a second barrier metal layer and a second metal layer, the second barrier metal layer comprising titanium, titanium-nitride, tungsten-nitride, tantalum, and/or tantalum-nitride, the second metal layer comprising tungsten, aluminum, and/or copper.
14. The interconnection structure as set forth in claim 12 , wherein the low voltage impurity regions are connected to the metal interconnections by one of the first and second contact constructions and the high voltage impurity regions are connected to the metal interconnections by the other one of the first and second contact constructions.
15. The interconnection structure as set forth in claim 12 , wherein the cell transistors and the metal interconnections comprise a cell array architecture of a NAND flash memory.
16. The interconnection structure as set forth in claim 12 , wherein a minimum pitch of the metal interconnections is less than about 0.1 μm.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/987,440 US20110101439A1 (en) | 2004-06-25 | 2011-01-10 | Interconnection structures for semicondcutor devices |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020040048119A KR100626378B1 (en) | 2004-06-25 | 2004-06-25 | Interconnection Structure Of Semiconductor Device And Method Of Forming The Same |
KR2004-0048119 | 2004-06-25 | ||
US11/022,240 US7871921B2 (en) | 2004-06-25 | 2004-12-22 | Methods of forming interconnection structures for semiconductor devices |
US12/987,440 US20110101439A1 (en) | 2004-06-25 | 2011-01-10 | Interconnection structures for semicondcutor devices |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/022,240 Division US7871921B2 (en) | 2004-06-25 | 2004-12-22 | Methods of forming interconnection structures for semiconductor devices |
Publications (1)
Publication Number | Publication Date |
---|---|
US20110101439A1 true US20110101439A1 (en) | 2011-05-05 |
Family
ID=35239967
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/022,240 Active 2025-12-03 US7871921B2 (en) | 2004-06-25 | 2004-12-22 | Methods of forming interconnection structures for semiconductor devices |
US12/987,440 Abandoned US20110101439A1 (en) | 2004-06-25 | 2011-01-10 | Interconnection structures for semicondcutor devices |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/022,240 Active 2025-12-03 US7871921B2 (en) | 2004-06-25 | 2004-12-22 | Methods of forming interconnection structures for semiconductor devices |
Country Status (5)
Country | Link |
---|---|
US (2) | US7871921B2 (en) |
JP (1) | JP5037794B2 (en) |
KR (1) | KR100626378B1 (en) |
CN (1) | CN100521185C (en) |
DE (1) | DE102005027234B4 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20150076625A1 (en) * | 2013-09-17 | 2015-03-19 | Kabushiki Kaisha Toshiba | Semiconductor device |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100784074B1 (en) * | 2005-07-07 | 2007-12-10 | 주식회사 하이닉스반도체 | Method of manufacturing bit line in a semiconductor device |
KR100741882B1 (en) * | 2005-12-29 | 2007-07-23 | 동부일렉트로닉스 주식회사 | Highvoltage device and Method for fabricating of the same |
US7365627B2 (en) * | 2006-03-14 | 2008-04-29 | United Microelectronics Corp. | Metal-insulator-metal transformer and method for manufacturing the same |
KR100854498B1 (en) | 2006-09-04 | 2008-08-26 | 삼성전자주식회사 | NAND-type flash memory device including selection transistors with an anti-punchthrough impurity region and methods of fabricating the same |
KR100766211B1 (en) * | 2006-09-29 | 2007-10-10 | 주식회사 하이닉스반도체 | Method for fabricating contact of flash memory |
KR100822806B1 (en) * | 2006-10-20 | 2008-04-18 | 삼성전자주식회사 | Nonvolatile memory device and method for forming thereor |
KR101099958B1 (en) | 2007-11-20 | 2011-12-28 | 주식회사 하이닉스반도체 | Method of forming metal line of semiconductor devices |
US8329545B1 (en) * | 2008-12-30 | 2012-12-11 | Micron Technology, Inc. | Method of fabricating a charge trap NAND flash memory |
WO2010082328A1 (en) * | 2009-01-15 | 2010-07-22 | ルネサスエレクトロニクス株式会社 | Semiconductor device, and method for manufacturing the same |
KR101068387B1 (en) * | 2009-08-05 | 2011-09-28 | 주식회사 하이닉스반도체 | Metal line of semiconductor device and manufacturing method therefor |
CN104752329B (en) * | 2013-12-30 | 2017-12-01 | 中芯国际集成电路制造(上海)有限公司 | The forming method of interconnection structure |
CN107591335A (en) * | 2016-07-08 | 2018-01-16 | 北大方正集团有限公司 | The preparation method and IC chip of electric connection structure |
CN108231596A (en) * | 2018-01-24 | 2018-06-29 | 德淮半导体有限公司 | Semiconductor structure and forming method thereof |
CN109960438B (en) * | 2019-03-19 | 2021-04-23 | 京东方科技集团股份有限公司 | Substrate, manufacturing method thereof and touch display device |
KR102622026B1 (en) * | 2019-09-23 | 2024-01-08 | 삼성전자 주식회사 | Electronic device for matching antenna impedance and operating method thereof |
CN112968056B (en) * | 2021-02-23 | 2023-11-03 | 长江存储科技有限责任公司 | Semiconductor structure and manufacturing method thereof |
CN115706063A (en) * | 2021-08-09 | 2023-02-17 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method thereof |
Citations (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5674781A (en) * | 1995-06-06 | 1997-10-07 | Advanced Micro Devices, Inc. | Landing pad technology doubled up as a local interconnect and borderless contact for deep sub-half micrometer IC application |
US5712178A (en) * | 1992-08-18 | 1998-01-27 | Samsung Eletronics Co., Ltd. | Non-volatile semiconductor memory device and method for manufacturing the same |
US6020255A (en) * | 1998-07-13 | 2000-02-01 | Taiwan Semiconductor Manufacturing Company | Dual damascene interconnect process with borderless contact |
US6083824A (en) * | 1998-07-13 | 2000-07-04 | Taiwan Semiconductor Manufacturing Company | Borderless contact |
US6258649B1 (en) * | 1998-09-03 | 2001-07-10 | Hitachi, Ltd | Semiconductor integrated circuit device and method of manufacturing the same |
US6291335B1 (en) * | 1999-10-04 | 2001-09-18 | Infineon Technologies Ag | Locally folded split level bitline wiring |
US6342416B1 (en) * | 2000-09-20 | 2002-01-29 | Samsung Electronics Co., Ltd. | Method of manufacturing a semiconductor memory device |
US6352916B1 (en) * | 1999-11-02 | 2002-03-05 | Micron Technology, Inc. | Method of forming plugs in multi-level interconnect structures by partially removing conductive material from a trench |
US6399438B2 (en) * | 1998-01-26 | 2002-06-04 | Hitachi, Ltd. | Method of manufacturing semiconductor integrated circuit device having a capacitor |
US6406968B1 (en) * | 2001-01-23 | 2002-06-18 | United Microelectronics Corp. | Method of forming dynamic random access memory |
US6461911B2 (en) * | 2000-05-26 | 2002-10-08 | Samsung Electronics Co., Ltd. | Semiconductor memory device and fabricating method thereof |
US20020149044A1 (en) * | 1997-10-14 | 2002-10-17 | Naruhiko Nakanishi | Semiconductor integrated circuit device and method of manufacturing the same |
US6479341B1 (en) * | 1998-03-02 | 2002-11-12 | Vanguard International Semiconductor Corporation | Capacitor over metal DRAM structure |
US6479853B2 (en) * | 1997-09-22 | 2002-11-12 | Nec Corporation | Semiconductor device and manufacturing method thereof |
US20030052384A1 (en) * | 2001-09-20 | 2003-03-20 | Kabushiki Kaisha Toshiba | Manufacturing method of semiconductor device with filling insulating film into trench |
US20030087499A1 (en) * | 2001-11-07 | 2003-05-08 | Lane Richard H | Process for forming metallized contacts to periphery transistors |
US6569742B1 (en) * | 1998-12-25 | 2003-05-27 | Hitachi, Ltd. | Method of manufacturing semiconductor integrated circuit device having silicide layers |
US6576509B1 (en) * | 1999-08-18 | 2003-06-10 | Hitachi Ltd. | Semiconductor integrated circuit device and method of manufacturing the same |
US6677230B2 (en) * | 2001-03-05 | 2004-01-13 | Renesas Technology Corporation | Method of manufacturing semiconductor device |
US6716764B1 (en) * | 1999-05-20 | 2004-04-06 | International Business Machines Corporation | Method of forming first level of metallization in DRAM chips |
US6734065B2 (en) * | 2001-03-17 | 2004-05-11 | Samsung Electronics Co., Ltd. | Method of forming a non-volatile memory device having a metal-oxide-nitride-oxide-semiconductor gate structure |
US6780707B2 (en) * | 2001-01-12 | 2004-08-24 | Samsung Electronics Co., Ltd. | Method of forming semiconductor device having contact pad on source/drain region in peripheral circuit area |
US20040169250A1 (en) * | 2000-05-26 | 2004-09-02 | Takashi Kobayashi | Nonvolatile semiconductor memory device with improved gate oxide film arrangement |
US20050023600A1 (en) * | 2000-01-17 | 2005-02-03 | Samsung Electronics, Co. Ltd | NAND-type flash memory devices and methods of fabricating the same |
US7326993B2 (en) * | 2003-07-15 | 2008-02-05 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory and method for fabricating the same |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1154724A (en) | 1997-08-06 | 1999-02-26 | Sony Corp | Manufacture of semiconductor device |
KR100292943B1 (en) | 1998-03-25 | 2001-09-17 | 윤종용 | Fabrication method of dynamic random access memory device |
JP4047500B2 (en) * | 1999-09-27 | 2008-02-13 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
KR20010075778A (en) | 2000-01-18 | 2001-08-11 | 윤종용 | Recessed bit line contact pad in semiconductor device and a manufacturing method thereof |
DE10042235A1 (en) | 2000-08-28 | 2002-04-18 | Infineon Technologies Ag | Process for producing an electrically conductive connection |
KR20020041190A (en) * | 2000-11-27 | 2002-06-01 | 박종섭 | Method for Fabricating of Semiconductor Device |
JP4639524B2 (en) * | 2001-05-24 | 2011-02-23 | ソニー株式会社 | Manufacturing method of semiconductor device |
KR20030032650A (en) | 2001-10-19 | 2003-04-26 | 주식회사 하이닉스반도체 | Method of forming memory device within multi nitride spacer |
KR20040076300A (en) * | 2003-02-25 | 2004-09-01 | 주식회사 하이닉스반도체 | Method of forming a metal wiring in a semiconductor device |
KR100604920B1 (en) | 2004-12-07 | 2006-07-28 | 삼성전자주식회사 | Method for manufacturing semiconductor device having dual plug |
-
2004
- 2004-06-25 KR KR1020040048119A patent/KR100626378B1/en active IP Right Grant
- 2004-12-22 US US11/022,240 patent/US7871921B2/en active Active
-
2005
- 2005-03-14 JP JP2005071421A patent/JP5037794B2/en active Active
- 2005-06-13 DE DE102005027234A patent/DE102005027234B4/en active Active
- 2005-06-23 CN CNB2005100788415A patent/CN100521185C/en active Active
-
2011
- 2011-01-10 US US12/987,440 patent/US20110101439A1/en not_active Abandoned
Patent Citations (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5712178A (en) * | 1992-08-18 | 1998-01-27 | Samsung Eletronics Co., Ltd. | Non-volatile semiconductor memory device and method for manufacturing the same |
US5674781A (en) * | 1995-06-06 | 1997-10-07 | Advanced Micro Devices, Inc. | Landing pad technology doubled up as a local interconnect and borderless contact for deep sub-half micrometer IC application |
US6479853B2 (en) * | 1997-09-22 | 2002-11-12 | Nec Corporation | Semiconductor device and manufacturing method thereof |
US20020149044A1 (en) * | 1997-10-14 | 2002-10-17 | Naruhiko Nakanishi | Semiconductor integrated circuit device and method of manufacturing the same |
US6399438B2 (en) * | 1998-01-26 | 2002-06-04 | Hitachi, Ltd. | Method of manufacturing semiconductor integrated circuit device having a capacitor |
US6479341B1 (en) * | 1998-03-02 | 2002-11-12 | Vanguard International Semiconductor Corporation | Capacitor over metal DRAM structure |
US6083824A (en) * | 1998-07-13 | 2000-07-04 | Taiwan Semiconductor Manufacturing Company | Borderless contact |
US6020255A (en) * | 1998-07-13 | 2000-02-01 | Taiwan Semiconductor Manufacturing Company | Dual damascene interconnect process with borderless contact |
US6258649B1 (en) * | 1998-09-03 | 2001-07-10 | Hitachi, Ltd | Semiconductor integrated circuit device and method of manufacturing the same |
US6569742B1 (en) * | 1998-12-25 | 2003-05-27 | Hitachi, Ltd. | Method of manufacturing semiconductor integrated circuit device having silicide layers |
US6716764B1 (en) * | 1999-05-20 | 2004-04-06 | International Business Machines Corporation | Method of forming first level of metallization in DRAM chips |
US6576509B1 (en) * | 1999-08-18 | 2003-06-10 | Hitachi Ltd. | Semiconductor integrated circuit device and method of manufacturing the same |
US6291335B1 (en) * | 1999-10-04 | 2001-09-18 | Infineon Technologies Ag | Locally folded split level bitline wiring |
US6352916B1 (en) * | 1999-11-02 | 2002-03-05 | Micron Technology, Inc. | Method of forming plugs in multi-level interconnect structures by partially removing conductive material from a trench |
US20050023600A1 (en) * | 2000-01-17 | 2005-02-03 | Samsung Electronics, Co. Ltd | NAND-type flash memory devices and methods of fabricating the same |
US6461911B2 (en) * | 2000-05-26 | 2002-10-08 | Samsung Electronics Co., Ltd. | Semiconductor memory device and fabricating method thereof |
US20040169250A1 (en) * | 2000-05-26 | 2004-09-02 | Takashi Kobayashi | Nonvolatile semiconductor memory device with improved gate oxide film arrangement |
US6342416B1 (en) * | 2000-09-20 | 2002-01-29 | Samsung Electronics Co., Ltd. | Method of manufacturing a semiconductor memory device |
US6780707B2 (en) * | 2001-01-12 | 2004-08-24 | Samsung Electronics Co., Ltd. | Method of forming semiconductor device having contact pad on source/drain region in peripheral circuit area |
US6406968B1 (en) * | 2001-01-23 | 2002-06-18 | United Microelectronics Corp. | Method of forming dynamic random access memory |
US6677230B2 (en) * | 2001-03-05 | 2004-01-13 | Renesas Technology Corporation | Method of manufacturing semiconductor device |
US6734065B2 (en) * | 2001-03-17 | 2004-05-11 | Samsung Electronics Co., Ltd. | Method of forming a non-volatile memory device having a metal-oxide-nitride-oxide-semiconductor gate structure |
US20030052384A1 (en) * | 2001-09-20 | 2003-03-20 | Kabushiki Kaisha Toshiba | Manufacturing method of semiconductor device with filling insulating film into trench |
US20030087499A1 (en) * | 2001-11-07 | 2003-05-08 | Lane Richard H | Process for forming metallized contacts to periphery transistors |
US7326993B2 (en) * | 2003-07-15 | 2008-02-05 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory and method for fabricating the same |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20150076625A1 (en) * | 2013-09-17 | 2015-03-19 | Kabushiki Kaisha Toshiba | Semiconductor device |
US9105618B2 (en) * | 2013-09-17 | 2015-08-11 | Kabushiki Kaisha Toshiba | Semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JP2006013431A (en) | 2006-01-12 |
US7871921B2 (en) | 2011-01-18 |
CN1722427A (en) | 2006-01-18 |
KR100626378B1 (en) | 2006-09-20 |
CN100521185C (en) | 2009-07-29 |
KR20050123454A (en) | 2005-12-29 |
DE102005027234A1 (en) | 2006-01-19 |
US20050250307A1 (en) | 2005-11-10 |
JP5037794B2 (en) | 2012-10-03 |
DE102005027234B4 (en) | 2009-11-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20110101439A1 (en) | Interconnection structures for semicondcutor devices | |
US7772108B2 (en) | Interconnection structures for semiconductor devices and methods of forming the same | |
US8263454B2 (en) | Embedded semiconductor device including planarization resistance patterns and method of manufacturing the same | |
US6949429B2 (en) | Semiconductor memory device and method for manufacturing the same | |
US6251790B1 (en) | Method for fabricating contacts in a semiconductor device | |
US20080251881A1 (en) | Semiconductor device with double barrier film | |
US20070114591A1 (en) | Integrated circuit devices having a resistor pattern and plug pattern that are made from a same material | |
JPH08204014A (en) | Semiconductor device and its production | |
US20040188806A1 (en) | Sidewall spacer structure for self-aligned contact and method for forming the same | |
US6018195A (en) | MOS gate structure semiconductor device | |
US7601630B2 (en) | Semiconductor device and method for fabricating the same | |
US7928494B2 (en) | Semiconductor device | |
US20010001742A1 (en) | Method of fabricating a dual -damascene structure in an integrated cirtcuit with multilevel-interconnect strcture | |
US20220352012A1 (en) | Via structure and methods for forming the same | |
US20040232558A1 (en) | Semiconductor device and method of manufacturing the same | |
US7189613B2 (en) | Method and structure for metal-insulator-metal capacitor based memory device | |
US7825497B2 (en) | Method of manufacture of contact plug and interconnection layer of semiconductor device | |
US5420462A (en) | Semiconductor device with conductors on stepped substrate having planar upper surfaces | |
US6372571B2 (en) | Method of manufacturing semiconductor device | |
US6218291B1 (en) | Method for forming contact plugs and simultaneously planarizing a substrate surface in integrated circuits | |
US20090227101A1 (en) | Method of forming wiring layer of semiconductor device | |
GB2400237A (en) | Sidewall spacer structure for self-aligned contact | |
US20020153544A1 (en) | Semiconductor device and its manufacturing method | |
KR100660552B1 (en) | Interconnection structure of semiconductor device and method of forming the same | |
US20040018754A1 (en) | Conductive contact structure and process |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |