US20090237279A1 - System and method for signaling on a bus using forbidden pattern free codes - Google Patents
System and method for signaling on a bus using forbidden pattern free codes Download PDFInfo
- Publication number
- US20090237279A1 US20090237279A1 US12/051,192 US5119208A US2009237279A1 US 20090237279 A1 US20090237279 A1 US 20090237279A1 US 5119208 A US5119208 A US 5119208A US 2009237279 A1 US2009237279 A1 US 2009237279A1
- Authority
- US
- United States
- Prior art keywords
- stage
- fpf
- codeword
- bus
- fibonacci
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M5/00—Conversion of the form of the representation of individual digits
- H03M5/02—Conversion to or from representation by pulses
- H03M5/04—Conversion to or from representation by pulses the pulses having two levels
- H03M5/14—Code representation, e.g. transition, for a given bit cell depending on the information in one or more adjacent bit cells, e.g. delay modulation code, double density code
Definitions
- This invention relates generally to signaling on a bus, and more particularly to encoders and decoders (CODECs) and a system and method for encoding and decoding using forbidden pattern free codes.
- CDECs encoders and decoders
- DSM Deep Sub-Micron
- VLSI very large scale integration
- the capacitive crosstalk i.e., the crosstalk due to the coupling capacitance between adjacent wires in the bus, induces additional energy consumption and signal delay.
- the crosstalk limits the maximum bus speed and raises the total power consumption.
- FIG. 2 shows an example on-chip bus subject to crosstalk.
- C L is a load capacitance seen by a driver of the j th bit, which includes receiver gate capacitance and wire-to-substrate parasitic capacitance.
- C l is the inter-wire coupling capacitance between the j th line and adjacent signal lines, i.e.,
- the delay ⁇ j of the j th line in the bus is:
- ⁇ j abs ( k ⁇ C L ⁇ V j +k ⁇ C l ⁇ V j ⁇ 1 +k ⁇ C l ⁇ V j+1 ), (1)
- ⁇ V j the voltage change on the j th wire
- Equation (1) can be written as:
- ⁇ j k ⁇ C L ⁇ V dd ⁇ abs ( ⁇ j + ⁇ j,j ⁇ 1 + ⁇ j,j+1 ), (2)
- ⁇ j,j ⁇ 1 ⁇ 0, ⁇ 1, ⁇ 2 ⁇ is the normalized relative voltage change on j th line for the (j+1) th or for the (j ⁇ 1) th line.
- the ⁇ j term corresponds to the intrinsic delay and the ⁇ j,j ⁇ 1 term corresponds to the crosstalk induced delay. Because ⁇ >>1, the ⁇ j has negligible contribution to the delay.
- C eff,j is defined as the effective total capacitance of the driver of j th line
- Equation (2) can be rewritten as
- Crosstalk patterns are classified as 0C, 1C, 2C, 3C and 4C patterns respectively as shown in the first column of Table I.
- the middle column is C eff
- the last column in Table I describes example transition patterns on three adjacent bits b j+1 , b j , b j ⁇ 1 of the bus.
- the speed of the data bus is determined by max ⁇ C eff,j ⁇ over all lines or bits of a bus j.
- max ⁇ C eff,j ⁇ By eliminating the 4C class of crosstalk on all lines of the bus, the maximum speed of the bus is increased by ⁇ 33%.
- the maximum speed of the bus is increased by ⁇ 100%.
- a passive shielding method for reducing crosstalk inserts passive shield, e.g., grounded wires, between adjacent active data wires. This method can reduce crosstalk-induced bus delay by nearly 50% and consequently boost the bus speed by nearly 100%. However, the passive shielding increases the size of the circuit.
- An active shielding method inserts shielding wires between data wires.
- the shielding wires transition in the same direction as the data wire being shielded.
- each data bit is transmitted on three wires.
- On the receiver side only the wire in the middle is used to recover the data.
- the other two wires are used as shielding wires.
- Active shielding is a more aggressive and reduces the bus delay by up to 75%, however, it also increases the size of the circuit.
- the crosstalk can also be reduced by adjusting the dimensions of the bus, including the wire width, depth and spacing between wires. Such method incurs a large overhead and is susceptible to process variation.
- Intentional data skewing reduces crosstalk by intentionally introducing time offset on transitions of the data bits in a bus. Such method requires very tedious physical layout manipulation and is also susceptible to process variation.
- CACs Crosstalk Avoidance Codes
- Bus encoding methods encode the original datawords to CAC codewords and then transmit them on the bus. Those methods can achieve the same degree of bus delay reduction as the passive shielding methods with lower area overhead.
- CACs can be memory-less or memory-based.
- the memory-based CACs use a codeword based on a previously transmitted codeword and the current transmitted codeword. On the receiver side, the codeword recovery is based on the current and previous codewords.
- the memory-less CACs use a fixed codebook to generate a codeword to transmit solely based on input data. The receiver uses the current codeword as the only input to recover the input data.
- a CODEC is a device or program capable of performing encoding and decoding on a digital data stream or signal.
- the area overhead for memory-based CACs can be lower compared to memory-less CACs.
- the CODEC for the memory-based CACs are much more complex than the memory-less CACs.
- a forbidden pattern free code is a memory-less code and can be used for crosstalk avoidance in bus interconnects. It offers the same amount of delay reduction as the passive shielding methods with less area overhead.
- the conventional CODECs are based on bus partitioning and brute-force logic optimization, which partitions a wide bus into a number of small groups (lanes) and applies CAC coding on each group independently. Those methods deal with the crosstalk across the group boundaries.
- the embodiments of the invention provide encoding data on busses using forbidden pattern free (FPF) code.
- the design is based on the Fibonacci numeral system (FNS).
- FNS Fibonacci numeral system
- the embodiments of the invention enable constructing CODECs with large buses as a simple extension of CODECs with small buses.
- the CODEC with the busses according to the embodiments of the invention offer an optimal or near-optimal area overhead performance and high efficiency in both circuit complexity and speed.
- the CODEC also allow an efficient and high speed implementation and therefore enable the FPF code to be used for on-chip bus crosstalk avoidance, and bus speed improvement and energy consumption reduction.
- FIG. 1 is a block diagram of a method and a system for reducing crosstalk on busses according to the embodiments of our invention
- FIG. 2 is a schematic of on-chip bus with crosstalk
- FIG. 3 is pseudo code for the near-optimal FPF-CAC coding method that encodes a binary vector to an FPF Fibonacci vector according to the embodiments of the invention
- FIG. 4A is a block diagram for an encoder implementation based on the pseudo code of FIG. 3 ;
- FIG. 4B is a block diagram of the decoder implementation for the near-optimal FPF code decoding operation according to the embodiments of the invention.
- FIG. 5 is a block diagram of an implementation of one stage of the encoder operation according to the embodiments of the invention.
- FIG. 6 is a block diagram of a modified CODEC with the simplified MSB stage according to the embodiments of the invention.
- FIG. 7 is a block diagram of the CODEC for a partitioned into two groups input bus according to the embodiments of the inventions.
- FIG. 1 shows a method and a system 100 for reducing crosstalk in on-chip busses.
- the bus of the preferred embodiment of the invention is describe for a CODEC. However, it is understood that the invention can be used with any high-speed bus.
- a CODEC encodes 30 a current dataword 20 of a sequence of datawords 10 into Fibonacci-based forbidden patterns based crosstalk avoidance code (FPF-CAC) codeword 40 .
- the codeword is transmitted over a bus 50 .
- the codeword 40 is decoded 60 to recover the dataword 20 .
- the dataword 20 is an input and an output of the method and the system 100 . As described below, there is at least one m-bit Fibonacci “forbidden pattern” free codeword 40 that represents the dataword 20 .
- Forbidden patterns are defined as two three-bit binary patterns: “101” and “010”.
- An m-bit code is forbidden pattern free if none of the three consecutive bits in the code has a forbidden pattern.
- Such a code is defined as forbidden pattern free (FPF) code.
- FPF forbidden pattern free
- 011000 is a 7-bit FPF code while 010000 and 011101 are not FPF codes.
- T g (m) The maximum cardinality of the m-bit FPF-CAC Code
- f m is the m th element in the Fibonacci sequence.
- the Fibonacci sequence f m is defined as
- Equation (8) the minimum number of bits needed, m opt , is the smallest integer m that satisfies Equation (8).
- OH(n) the lower bound of the area overhead
- a numeral system is “a framework where numbers are represented by numerals in a consistent manner.”
- a commonly used numeral system in digital circuits is the binary numeral system, which uses powers of two as a base.
- a binary numeral system is defined by Equation (11). The binary numeral system is complete and unambiguous, which means that each number v has one and only one representation in this binary numeral system.
- k is the bit position and b k is a binary value of the k th bit.
- the Fibonacci-based numeral system N(F m , ⁇ 0, 1 ⁇ ) is the numeral system that uses Fibonacci sequence as the base.
- a number v is represented as the summation of some Fibonacci numbers and no Fibonacci number is in the summation more that once as defined in Equation (12).
- the Fibonacci-based numeral system is complete but ambiguous. For example, there are six 7-digit vectors in the Fibonacci numeral system for the decimal number 19:
- a vector in the binary numeral system is a binary vector or binary code
- a vector in the Fibonacci numeral system is a Fibonacci vector, Fibonacci codeword or Fibonacci code. All the Fibonacci vectors that represent the same number are equivalent vectors.
- the total number of distinct values can be represented using m-bit Fibonacci vector is
- the embodiments of our invention describe coding methods for encoding data to the FPF code.
- the coding methods enable systematical design of the FPF CODECs for busses of arbitrary sizes, such that the CODEC with a wide bus can be derived from the CODEC of a narrow bus.
- the relationship between number of gates and the bus increase is quadratic in the CODEC implementation according to the embodiments of our invention. For comparison, in the conventional coding methods this relationship is exponential.
- the coding methods of our invention are based on the Fibonacci numeral system.
- the embodiments of our invention describe the coding method that converts an input dataword to a FPF Fibonacci code.
- the Fibonacci code is near-optimal because the required overhead is no more than one bit greater than the theoretical lower bound described in Equation (10).
- the encoder converts an input dataword value represented in the numeral system to the Fibonacci numeral system representation.
- the output of the encoder is guaranteed to be a valid FPF codeword.
- FIG. 3 shows the pseudo code 300 for the near-optimal FPF-CAC coding method that encodes a number v to an FPF Fibonacci vector (code).
- FIG. 4A shows an implementation of the encoder 30 based on the near-optimal FPF-CAC pseudo code 300 according to one embodiment of our invention.
- the logical structure of the encoder 30 can be described as:
- FIG. 5 shows an implementation of the k th stage of the encoder, where k ⁇ m.
- FIG. 4B shows a decoder 60 for the near-optimal FPF code decoding operation.
- the decoder 60 converts codeword 420 transmitted on the bus 50 in Fibonacci numeral system back to the dataword 410 in original numeral system, e.g., in the binary format.
- the decoding process is based on Equation (12).
- Table III shows the complete 6-bit codewords generated using the near-optimal FPF-CAC pseudo code in column CODE-1.
- the MSB stage is different from other stages because there is no preceding bit.
- d m ⁇ 1 can be coded to be either value.
- the MSB (d m ) we arbitrarily choose to code the MSB (d m ) to be 0 when the input value is in the gray zone of the m th stage, where gray zone of the k th stage is defined as the region of [f k ⁇ 1 f k ).
- Equation (14) we determine that the total numbers of codewords in both CODE-1 and CODE-2 are f m+2 , which is slightly smaller than the maximum cardinality of 2f m+1 of Equation (5).
- Table IV shows the number of bits needed to encode the binary data from 3 to 32 bits: n denotes the number of bits for the input binary bus; m opt the number of bits required for the optimal code; m no the number of bits needed for the CODEC and ⁇ (m) the difference between the two.
- Optimal CODEC The described above mapping scheme for the near-optimal CODEC can be modified to achieve optimal overhead performance.
- Such a CODEC is referred herein as the ‘Optimal CODEC’.
- Table III shows that there are a total of (f m+1 ⁇ f m ) codewords in CODE-2 that are not included in CODE-1. We define the region where duplicated FPF Fibonacci vectors exist as gray region. The total number of distinct codewords in both CODE-1 and CODE-2 is:
- the decoder is modified accordingly:
- Table V shows the codewords based on the optimal CODEC corresponding dataword value for each codeword. This mapping scheme can also be interpreted as the codewords having an extra bit as shown in the second column (XB) in the table V. This bit is not transmitted on the bus because its value can be recovered by the decoder based on the values of d m and d m ⁇ 1 .
- the modified mapping can be expressed as
- This modification allows the encoder to directly output the input MSB bit as the output MSB bit.
- the outputs are still guaranteed to be the FPF codes for the following reasons: because to code a n-bit binary code to an m-bit Fibonacci code, n and m satisfies: 2 n ⁇ f m+2 and we have 2 n ⁇ f m+2 ⁇ 2 ⁇ f m+1 , hence
- Equation (19) indicates that the n bit input binary data can be partitioned into the MSB bit and a (n ⁇ 1) bit vector.
- the MSB bit is transmitted without coding and the n ⁇ 1 bit vector is encoded into a m ⁇ 1 bit bus.
- FIG. 6 shows a block diagram of the modified CODEC with the simplified MSB stage.
- the MSB of the input b n 640 is mapped directly to the MSB of the output d m 650 .
- the remainder of the input vector b n ⁇ 1 b n ⁇ 2 . . . b 1 becomes the input of the (m ⁇ 1) th stage.
- the decoder 660 for the modified coding scheme is implemented according to Equation (18), similar to the decoder 60 shown on FIG. 4B .
- Embodiments of our invention can be used in combination with bus partitioning to further reduce the overall complexity of the encoder and increase the speed of the encoder. Reducing partition by half can increase the bus speed by approximately a factor of four. Similarly, the total area of the CODEC circuit has the quadratic relation with respect to the number of input bits, and therefore partitioning the bus reduces the area by ⁇ 50%.
- the structure of the decoder is simpler than the structure of the encoder and has no delay rippling effect. However, as the bus width increases, the size of the summation stage also increases, and an increased delay is experienced. In some embodiments of our invention, there are no multiplication and logical AND operations. Because f k is a constant, the case of connecting d k to the non-zero bit positions of f k is simplified.
- a n-bit input bus wherein n is an even number, is partitioned into two n/2-bit groups: b n/2 . . . b 1 (group A) 730 and b n . . . b n/2+1 (group B) 720 . b n/2 . . . b 1 730 and b n . . . b n/2+1 720 are encoded 740 and 741 into two k-bit FPF busses, da k . . . da 1 and db k . . . db 1 , where k satisfies 2f k+1 >2 n/2 .
- Encoders for both group ENC-A 741 and ENC-B 740 are n/2-bit to k-bit encoders. Two k-bit to n/2-bit decoders DEC-A 751 and DEC-B 750 are used on the receiver side. That is, the encoding is performed independently for each group of lines.
- the maximum delay of the encoders and decoders are ⁇ enc (n/2) and ⁇ dec (n/2), respectively, instead of ⁇ enc (n) and ⁇ dec (n).
- the gate count of the CODEC is reduced from GC(n) to 2 ⁇ GC(n/2).
- additional wires 710 are need on the bus.
- da k and db 1 are duplicated so the bits in the bus at the group boundary are . . . db 1 db 1 da k da k da k ⁇ 1 . . . .
- the embodiments of the invention provide CODEC designs for forbidden-pattern-free crosstalk avoidance code (FPF-CAC).
- FPF-CAC forbidden-pattern-free crosstalk avoidance code
- the mapping schemes are based on the representation of numbers in Fibonacci numeral system.
- One embodiment of the invention offers near-optimal area overhead performance. Another embodiment of the invention offers an improved area overhead that reaches theoretical lower bound.
- the described systems and methods enable CODECs for arbitrary bus sizes to be designed in a systematic fashion. With such a deterministic and systematic mapping, the construction of a CODEC with a wider bus is a simple extension of the CODEC for a smaller bus.
- the invented encoders have modularly structure, which allows the modules to be reusable.
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Dc Digital Transmission (AREA)
- Error Detection And Correction (AREA)
Abstract
Embodiments of our invention describe the method for producing forbidden pattern free (FPF) codewords using an encoder-decoder (CODEC). First, the method encodes a dataword to produce a FPF codeword by mapping dataword to a Fibonacci Numeral System space. Further, the FPF codeword is transmitted via adjacent lines of a bus and decoded when received from the bus to recover the dataword to eliminate all crosstalk on the bus.
Description
- This invention relates generally to signaling on a bus, and more particularly to encoders and decoders (CODECs) and a system and method for encoding and decoding using forbidden pattern free codes.
- Crosstalk in Busses
- In circuits with long and wide global busses, interconnect delays often dominate signal delays. For example, in a Deep Sub-Micron (DSM) chip with very large scale integration (VLSI) processes, the performance of the bus based interconnect has become a bottleneck to the overall system performance.
- The capacitive crosstalk, i.e., the crosstalk due to the coupling capacitance between adjacent wires in the bus, induces additional energy consumption and signal delay. Thus, the crosstalk limits the maximum bus speed and raises the total power consumption.
- Crosstalk Classification
-
FIG. 2 shows an example on-chip bus subject to crosstalk. CL is a load capacitance seen by a driver of the jth bit, which includes receiver gate capacitance and wire-to-substrate parasitic capacitance. Cl is the inter-wire coupling capacitance between the jth line and adjacent signal lines, i.e., - (j−1)th and (j+1)th lines of the bus in
FIG. 2 . - The delay τj of the jth line in the bus is:
-
τj =abs(k·C L ·ΔV j +k·C l ·ΔV j−1 +k·C l ·ΔV j+1), (1) - where k is a constant determined by the driver strength and line resistance, ΔVj is the voltage change on the jth wire and ΔVj,k=ΔVj−ΔVk is a relative voltage change between the jth and the kth line.
- Usually on-chip busses are full-swing binary busses, therefore the two output voltage levels are Vdd and 0V, and hence
-
ΔVjε{0,±Vdd} and ΔVj,kε{0,±Vdd,±2·Vdd}. 1. - Equation (1) can be written as:
-
τj =k·C L ·V dd ·abs(δj+λ·δj,j−1+λ·δj,j+1), (2) - where
-
- is the normalized voltage change on jth line; δj,j±1ε{0, ±1, ±2} is the normalized relative voltage change on jth line for the (j+1)th or for the (j−1)th line. The δj term corresponds to the intrinsic delay and the δj,j±1 term corresponds to the crosstalk induced delay. Because λ>>1, the δj has negligible contribution to the delay.
- Ceff,j is defined as the effective total capacitance of the driver of jth line
-
C eff,j =C L ·abs(δj+λ·δj,j−1+λ·δj,j+1), (3) - Equation (2) can be rewritten as
-
τj =k·V dd ·C eff,j (4) - Equation (3) demonstrates that min(Ceff,j)=CL and max(Ceff,j)=(1+4·λ))CL.
- Crosstalk patterns are classified as 0C, 1C, 2C, 3C and 4C patterns respectively as shown in the first column of Table I. The middle column is Ceff, and the last column in Table I describes example transition patterns on three adjacent bits bj+1, bj, bj−1 of the bus.
-
TABLE I class Ceff transition patterns 0C CL 000 → 111 1C CL(1 + λ) 011 → 000 2C CL(1 + 2λ) 010 → 000 3C CL(1 + 3λ) 010 → 100 4C CL(1 + 4λ) 010 → 101 - The speed of the data bus is determined by max{Ceff,j} over all lines or bits of a bus j. By eliminating the 4C class of crosstalk on all lines of the bus, the maximum speed of the bus is increased by ˜33%. By eliminating the transition patterns for the 3C and 4C classes, the maximum speed of the bus is increased by ˜100%.
- Conventional Methods for Reducing Crosstalk
- There are number of conventional methods for reducing the crosstalk.
- Passive Shielding
- A passive shielding method for reducing crosstalk inserts passive shield, e.g., grounded wires, between adjacent active data wires. This method can reduce crosstalk-induced bus delay by nearly 50% and consequently boost the bus speed by nearly 100%. However, the passive shielding increases the size of the circuit.
- Active Shielding
- An active shielding method inserts shielding wires between data wires. The shielding wires, transition in the same direction as the data wire being shielded. In a simple case of active shielding, each data bit is transmitted on three wires. On the receiver side, only the wire in the middle is used to recover the data. The other two wires are used as shielding wires. Active shielding is a more aggressive and reduces the bus delay by up to 75%, however, it also increases the size of the circuit.
- Physical Layout
- The crosstalk can also be reduced by adjusting the dimensions of the bus, including the wire width, depth and spacing between wires. Such method incurs a large overhead and is susceptible to process variation.
- Intentional Data Skewing
- Intentional data skewing reduces crosstalk by intentionally introducing time offset on transitions of the data bits in a bus. Such method requires very tedious physical layout manipulation and is also susceptible to process variation.
- Crosstalk Avoidance Codes
- When special type of codes or codewords transmitted on the bus, certain classes of crosstalk are eliminated. Those codes are commonly referred to as Crosstalk Avoidance Codes (CACs).
- Bus encoding methods encode the original datawords to CAC codewords and then transmit them on the bus. Those methods can achieve the same degree of bus delay reduction as the passive shielding methods with lower area overhead.
- CACs can be memory-less or memory-based. The memory-based CACs use a codeword based on a previously transmitted codeword and the current transmitted codeword. On the receiver side, the codeword recovery is based on the current and previous codewords. The memory-less CACs use a fixed codebook to generate a codeword to transmit solely based on input data. The receiver uses the current codeword as the only input to recover the input data.
- A CODEC is a device or program capable of performing encoding and decoding on a digital data stream or signal. The area overhead for memory-based CACs can be lower compared to memory-less CACs. However, the CODEC for the memory-based CACs are much more complex than the memory-less CACs.
- Forbidden Pattern Free Code
- A forbidden pattern free code is a memory-less code and can be used for crosstalk avoidance in bus interconnects. It offers the same amount of delay reduction as the passive shielding methods with less area overhead. The conventional CODECs are based on bus partitioning and brute-force logic optimization, which partitions a wide bus into a number of small groups (lanes) and applies CAC coding on each group independently. Those methods deal with the crosstalk across the group boundaries.
- In all those methods, more than the required minimal number of wires is needed in the bus, and therefore the overall area overhead is higher than the theoretical lower bound. That leads to non-optimal area overhead and overall power consumption. It is desired to have a CODEC that can be implemented efficiently and operate at high data transfer speed.
- The embodiments of the invention provide encoding data on busses using forbidden pattern free (FPF) code. The design is based on the Fibonacci numeral system (FNS). The embodiments of the invention enable constructing CODECs with large buses as a simple extension of CODECs with small buses.
- The CODEC with the busses according to the embodiments of the invention offer an optimal or near-optimal area overhead performance and high efficiency in both circuit complexity and speed. The CODEC also allow an efficient and high speed implementation and therefore enable the FPF code to be used for on-chip bus crosstalk avoidance, and bus speed improvement and energy consumption reduction.
- Although the embodiments of the invention are described for CODEC busses, it should be understood that the invention can be used for any high-speed, on-chip bus.
-
FIG. 1 is a block diagram of a method and a system for reducing crosstalk on busses according to the embodiments of our invention; -
FIG. 2 is a schematic of on-chip bus with crosstalk; -
FIG. 3 is pseudo code for the near-optimal FPF-CAC coding method that encodes a binary vector to an FPF Fibonacci vector according to the embodiments of the invention; -
FIG. 4A is a block diagram for an encoder implementation based on the pseudo code ofFIG. 3 ; -
FIG. 4B is a block diagram of the decoder implementation for the near-optimal FPF code decoding operation according to the embodiments of the invention; -
FIG. 5 is a block diagram of an implementation of one stage of the encoder operation according to the embodiments of the invention; -
FIG. 6 is a block diagram of a modified CODEC with the simplified MSB stage according to the embodiments of the invention; and -
FIG. 7 is a block diagram of the CODEC for a partitioned into two groups input bus according to the embodiments of the inventions. - System Overview
-
FIG. 1 shows a method and asystem 100 for reducing crosstalk in on-chip busses. The bus of the preferred embodiment of the invention is describe for a CODEC. However, it is understood that the invention can be used with any high-speed bus. A CODEC encodes 30 acurrent dataword 20 of a sequence ofdatawords 10 into Fibonacci-based forbidden patterns based crosstalk avoidance code (FPF-CAC)codeword 40. The codeword is transmitted over abus 50. Thecodeword 40 is decoded 60 to recover thedataword 20. Thedataword 20 is an input and an output of the method and thesystem 100. As described below, there is at least one m-bit Fibonacci “forbidden pattern”free codeword 40 that represents thedataword 20. - Forbidden Pattern Free (FPF) Code
- Forbidden patterns are defined as two three-bit binary patterns: “101” and “010”. An m-bit code is forbidden pattern free if none of the three consecutive bits in the code has a forbidden pattern. Such a code is defined as forbidden pattern free (FPF) code. As an example, 011000 is a 7-bit FPF code while 010000 and 011101 are not FPF codes.
- When only FPF codewords are transmitted on a bus, the maximum crosstalk on any wire at any transition time is reduced by about half. Therefore, by encoding the datawords to FPF codewords, our invention speeds up the bus by ˜100%. This type of code is referred herein as forbidden pattern free crosstalk avoidance code (FPF-CAC), see C. Duan et al. “Analysis and Avoidance of Crosstalk in On-chip Bus,” Hot-Interconnects, 2001, pp 133-138, incorporated herein by reference.
- Fibonacci Sequence
- The maximum cardinality of the m-bit FPF-CAC Code, Tg(m), is
-
T g(m)=2f m+1 (5) - where fm is the mth element in the Fibonacci sequence. The Fibonacci sequence fm is defined as
-
- Another identity of the Fibonacci sequence is
-
- To encode an n-bit binary bus into FPF-CAC code, the minimum number of bits needed, mopt, is the smallest integer m that satisfies Equation (8). We compute the lower bound of the area overhead OH(n), which is defined as a ratio between the additional area required for the coded bus and the area of uncoded bus.
-
- The golden ratio,
-
- is an asymptotic ratio of two consecutive elements of the Fibonacci sequence. Hence,
-
- where c is a constant. Therefore, for wide busses, the lower bound of the overhead is:
-
- Fibonacci-Based Numeral System
- A numeral system is “a framework where numbers are represented by numerals in a consistent manner.” A commonly used numeral system in digital circuits is the binary numeral system, which uses powers of two as a base. A binary numeral system is defined by Equation (11). The binary numeral system is complete and unambiguous, which means that each number v has one and only one representation in this binary numeral system.
-
- where k is the bit position and bk is a binary value of the kth bit.
- The Fibonacci-based numeral system N(Fm, {0, 1}) is the numeral system that uses Fibonacci sequence as the base. A number v is represented as the summation of some Fibonacci numbers and no Fibonacci number is in the summation more that once as defined in Equation (12).
-
- The Fibonacci-based numeral system is complete but ambiguous. For example, there are six 7-digit vectors in the Fibonacci numeral system for the decimal number 19:
-
- {0111101, 0111110, 10001101, 1001110, 10100001, 1010010}.
- As defined herein, a vector in the binary numeral system is a binary vector or binary code; and a vector in the Fibonacci numeral system is a Fibonacci vector, Fibonacci codeword or Fibonacci code. All the Fibonacci vectors that represent the same number are equivalent vectors.
- From Equation (7), we derive the range of m-bit Fibonacci vector as:
-
vε[0fm+2). (13) - The total number of distinct values can be represented using m-bit Fibonacci vector is
-
T gN(m)=f m+2 (14) - CODEC with Forbidden Pattern Free Codes
- The embodiments of our invention describe coding methods for encoding data to the FPF code. The coding methods enable systematical design of the FPF CODECs for busses of arbitrary sizes, such that the CODEC with a wide bus can be derived from the CODEC of a narrow bus. The relationship between number of gates and the bus increase is quadratic in the CODEC implementation according to the embodiments of our invention. For comparison, in the conventional coding methods this relationship is exponential. The coding methods of our invention are based on the Fibonacci numeral system.
- Mapping
- Theorem 1: ∃dmdm−1 . . . d2d1=v, dmdm−1 . . . d2d1εN(Fm, {0, 1}) and is FPF,
-
∀vε[0,fm+2−1] -
Theorem 1 states that for any number vε[0,fm+2−1], there exists at least one m-bit Fibonacci vector dmdm−1 . . . d2d1=v that represents this number and is forbidden pattern free. The proof is described in the Appendix. - According to
Theorem 1, we can design a CODEC that maps an input to its FPF Fibonacci vector. - Near Optimal FPF CODEC
- The embodiments of our invention describe the coding method that converts an input dataword to a FPF Fibonacci code. The Fibonacci code is near-optimal because the required overhead is no more than one bit greater than the theoretical lower bound described in Equation (10).
- In a preferred embodiment of our invention, the encoder converts an input dataword value represented in the numeral system to the Fibonacci numeral system representation. The output of the encoder is guaranteed to be a valid FPF codeword.
- Encoding
-
FIG. 3 shows thepseudo code 300 for the near-optimal FPF-CAC coding method that encodes a number v to an FPF Fibonacci vector (code).FIG. 4A shows an implementation of theencoder 30 based on the near-optimal FPF-CACpseudo code 300 according to one embodiment of our invention. Theencoder 30 converts a n-bit binary vector 410 v=bn−1 . . . b0 to an m-bit FPF Fibonacci vector 420 dm−1dm−2 . . . d0. The logical structure of theencoder 30 can be described as: -
- 1. The encoder comprises m−1 stages;
- 2. Each stage of the encoder produces one coded bit, e.g., the kth stage produces dk 430;
- 3. Each stage generates a
remainder r k 440; - 4. The
remainder r k 440 of a stage is the input to the following stage k−1, i.e., for the kth stage, the inputs are dk+1 and rk+1 and the outputs are dk and rk, wherein dk is one bit of theoutput Fibonacci vector 520 and rk is the remainder ofinput vector v 510 that is the input to the following stage. - 5. In each stage k, i.e., any stage except the most significant bit (MSB) stage, the input rk+1 is compared 450 to two corresponding consecutive elements of the Fibonacci sequence fk+1 and fk. If rk+1≧fk+1, dk=1; If rk+1<fk, dk=0; otherwise, dk=dk+1;
- 6. The input of the MSB stage is the input to the CODEC, v=bn bn−1 . . . b1;
- 7. The logic of the MSB stage can be either
- If v≧fk+1, dk=1; otherwise dk=0; or
- If v<fk, dk−0; otherwise dk−1;
-
FIG. 5 shows an implementation of the kth stage of the encoder, where k<m. There is onecomparator 510 forcomparison operation 450, onesubtractor 520 and a 2-to-1selector 530 that selects accordingselect line 531. - Decoding
-
FIG. 4B shows adecoder 60 for the near-optimal FPF code decoding operation. Thedecoder 60 converts codeword 420 transmitted on thebus 50 in Fibonacci numeral system back to thedataword 410 in original numeral system, e.g., in the binary format. In an embodiment of our invention, the decoding process is based on Equation (12). - Table III shows the complete 6-bit codewords generated using the near-optimal FPF-CAC pseudo code in column CODE-1.
- As described above, the MSB stage is different from other stages because there is no preceding bit. For the values in the gray region, i.e., the region where duplicated FPF Fibonacci vectors exist, dm−1 can be coded to be either value. In the near-optimal FPF-CAC pseudo code, we arbitrarily choose to code the MSB (dm) to be 0 when the input value is in the gray zone of the mth stage, where gray zone of the kth stage is defined as the region of [fk−1fk).
- If we code dm to be 1 for all values in the gray zone, then a different set of codewords is listed in CODE-2 column of the Table III. All codewords in both CODE-1 and CODE-2 columns of Table III are FPF. For clarity, we only list codewords in CODE-2 that are different from codewords in CODE-1.
-
TABLE III Input CODE-1 CODE-2 Decimal f6 f5 f4 f3 f2 f1 f6 f5 f4 f3 f2 f1 value 8 5 3 2 1 1 8 5 3 2 1 1 20* 1 1 1 1 1 1 19* 1 1 1 1 1 0 18* 1 1 1 1 0 0 17* 1 1 1 0 0 1 16* 1 1 1 0 0 0 15 1 1 0 0 1 1 14 1 1 0 0 0 1 13 1 1 0 0 0 0 12 0 1 1 1 1 1 1 0 0 1 1 1 11 0 1 1 1 1 0 1 0 0 1 1 0 10 0 1 1 1 0 0 1 0 0 0 1 1 9 0 1 1 0 0 1 1 0 0 0 0 1 8 0 1 1 0 0 0 1 0 0 0 0 0 7 0 0 1 1 1 1 6 0 0 1 1 1 0 5 0 0 1 1 0 0 4 0 0 0 1 1 1 3 0 0 0 1 1 0 2 0 0 0 0 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 - Based on Equation (14), we determine that the total numbers of codewords in both CODE-1 and CODE-2 are fm+2, which is slightly smaller than the maximum cardinality of 2fm+1 of Equation (5). The coding methods described above require that the number of bits needed for the CODEC is no more than 1 bit greater than the minimum required number of bits mopt. This is because TgN(m)=fm+2, Tg(m)=2fm+1, TgN(m+1)=fm+3 and fm+2<2·fm+1<fm+3.
- Table IV shows the number of bits needed to encode the binary data from 3 to 32 bits: n denotes the number of bits for the input binary bus; mopt the number of bits required for the optimal code; mno the number of bits needed for the CODEC and Δ(m) the difference between the two.
-
TABLE IV nin mopt mno Δ(m) 3 4 4 0 4 5 6 1 5 7 7 0 6 8 9 1 7 10 10 0 8 11 12 1 9 13 13 0 10 14 15 1 11 16 16 0 12 17 17 0 13 18 19 1 14 20 20 0 15 21 22 1 16 23 23 0 17 23 23 1 18 26 26 0 19 27 28 1 20 29 29 0 21 30 30 0 22 31 32 1 23 33 33 0 24 34 35 1 25 36 36 0 26 37 38 1 27 39 39 0 28 40 41 1 29 42 42 0 30 43 43 0 31 44 45 1 32 46 46 0 - Optimal CODEC
- The described above mapping scheme for the near-optimal CODEC can be modified to achieve optimal overhead performance. Such a CODEC is referred herein as the ‘Optimal CODEC’.
- Table III shows that there are a total of (fm+1−fm) codewords in CODE-2 that are not included in CODE-1. We define the region where duplicated FPF Fibonacci vectors exist as gray region. The total number of distinct codewords in both CODE-1 and CODE-2 is:
-
T gO(m)=f m+2 +f m+1 −f m =f m+1 +f m +f m+1 −f m=2·f m+1 (15) - The reason that the near-optimal codes do not reach the maximum cardinality is due to the redundant FPF Fibonacci vectors for the values in the gray region. Table V shows that in one embodiment of our invention we remove this redundancy by moving the codewords in the CODE-2 gray region to the top of CODE-1.
-
TABLE V Input XB OPT ENC Encoder 2 Decimal f7 f6 f5 f4 f3 f2 f1 f6 f5 f4 f3 f2 f1 value 13 8 5 3 2 1 1 8 5 3 2 1 1 25* 1 1 0 0 1 1 1 24* 1 1 0 0 1 1 0 23* 1 1 0 0 0 1 1 22* 1 1 0 0 0 0 1 21* 1 1 0 0 0 0 0 20* 0 1 1 1 1 1 1 19* 0 1 1 1 1 1 0 18* 0 1 1 1 1 0 0 17* 0 1 1 1 0 0 1 16* 0 1 1 1 0 0 0 15 0 1 1 0 0 1 1 14 0 1 1 0 0 0 1 13 0 1 1 0 0 0 0 12 0 0 1 1 1 1 1 1 0 0 1 1 1 11 0 0 1 1 1 1 0 1 0 0 1 1 0 10 0 0 1 1 1 0 0 1 0 0 0 1 1 9 0 0 1 1 0 0 1 1 0 0 0 0 1 8 0 0 1 1 0 0 0 1 0 0 0 0 0 7 0 0 0 1 1 1 1 6 0 0 0 1 1 1 0 5 0 0 0 1 1 0 0 4 0 0 0 0 1 1 1 3 0 0 0 0 1 1 0 2 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 - In order to remove the redundancy, we shift the values of these codewords by fm+2−fm=fm+1. The MSB stage of the CODEC is modified to reflect this value shift in the new mapping scheme:
-
- The decoder is modified accordingly:
-
- Table V shows the codewords based on the optimal CODEC corresponding dataword value for each codeword. This mapping scheme can also be interpreted as the codewords having an extra bit as shown in the second column (XB) in the table V. This bit is not transmitted on the bus because its value can be recovered by the decoder based on the values of dm and dm−1.
- The overhead performance of the optimal coding scheme reaches the theoretical lower bound given in Equation (9).
- Optimization of the Near-Optimal Mapping Scheme
- The near-optimal mapping scheme can be modified to simplify the MSB stage. Let bnbn−1 . . . b1 be the binary input vector, dm=bn and rm=bn−1bn−2 . . . b1. The modified mapping can be expressed as
-
- This modification allows the encoder to directly output the input MSB bit as the output MSB bit. The outputs are still guaranteed to be the FPF codes for the following reasons: because to code a n-bit binary code to an m-bit Fibonacci code, n and m satisfies: 2n<fm+2 and we have 2n≦fm+2<2·fm+1, hence
-
2n−1 <f m+1. (19) - Equation (19) indicates that the n bit input binary data can be partitioned into the MSB bit and a (n−1) bit vector. The MSB bit is transmitted without coding and the n−1 bit vector is encoded into a m−1 bit bus.
-
FIG. 6 shows a block diagram of the modified CODEC with the simplified MSB stage. In theencoder 630, the MSB of theinput b n 640 is mapped directly to the MSB of theoutput d m 650. The remainder of the input vector bn−1bn−2 . . . b1 becomes the input of the (m−1)th stage. - The decoder 660 for the modified coding scheme is implemented according to Equation (18), similar to the
decoder 60 shown onFIG. 4B . - Bus Partitioning
- Embodiments of our invention can be used in combination with bus partitioning to further reduce the overall complexity of the encoder and increase the speed of the encoder. Reducing partition by half can increase the bus speed by approximately a factor of four. Similarly, the total area of the CODEC circuit has the quadratic relation with respect to the number of input bits, and therefore partitioning the bus reduces the area by ˜50%.
- The structure of the decoder is simpler than the structure of the encoder and has no delay rippling effect. However, as the bus width increases, the size of the summation stage also increases, and an increased delay is experienced. In some embodiments of our invention, there are no multiplication and logical AND operations. Because fk is a constant, the case of connecting dk to the non-zero bit positions of fk is simplified.
- In the example shown in
FIG. 7 , a n-bit input bus, wherein n is an even number, is partitioned into two n/2-bit groups: bn/2 . . . b1 (group A) 730 and bn . . . bn/2+1 (group B) 720. bn/2 . . . b1 730 and bn . . .b n/2+1 720 are encoded 740 and 741 into two k-bit FPF busses, dak . . . da1 and dbk . . . db1, where k satisfies 2fk+1>2n/2. Encoders for both group ENC-A 741 and ENC-B 740 are n/2-bit to k-bit encoders. Two k-bit to n/2-bit decoders DEC-A 751 and DEC-B 750 are used on the receiver side. That is, the encoding is performed independently for each group of lines. - The maximum delay of the encoders and decoders are τenc(n/2) and τdec(n/2), respectively, instead of τenc(n) and τdec(n). The gate count of the CODEC is reduced from GC(n) to 2·GC(n/2). To prevent the occurrence of forbidden patterns across the group boundary,
additional wires 710 are need on the bus. In the example inFIG. 7 , dak and db1 are duplicated so the bits in the bus at the group boundary are . . . db1db1dakdakdak−1 . . . . - The embodiments of the invention provide CODEC designs for forbidden-pattern-free crosstalk avoidance code (FPF-CAC). The mapping schemes are based on the representation of numbers in Fibonacci numeral system.
- One embodiment of the invention offers near-optimal area overhead performance. Another embodiment of the invention offers an improved area overhead that reaches theoretical lower bound.
- The described systems and methods enable CODECs for arbitrary bus sizes to be designed in a systematic fashion. With such a deterministic and systematic mapping, the construction of a CODEC with a wider bus is a simple extension of the CODEC for a smaller bus. The invented encoders have modularly structure, which allows the modules to be reusable.
- We described the modifications to our near-optimal CODEC that reduces the complexity and improve the delay performance of the CODEC.
- Although the invention has been described by way of examples of preferred embodiments, it is to be understood that various other adaptations and modifications may be made within the spirit and scope of the invention. Therefore, it is the object of the appended claims to cover all such variations and modifications as come within the true spirit and scope of the invention.
Claims (16)
1. A method for reducing crosstalk in a bus comprising:
encoding a dataword to produce a Fibonacci forbidden pattern free (FPF) codeword using a Fibonacci sequence;
shifting values of the FPF codeword by fm+1 to remove the values redundancy in a region where duplicated FPF Fibonacci vectors exist.
transmitting the FPF codeword via a plurality of adjacent lines of a bus; and
decoding the FPF codeword received from the bus to recover the dataword while eliminating crosstalk on all of the plurality of lines.
2. The method of claim 1 , further comprising:
presenting the dataword in a binary numeral system and the FPF codeword in a Fibonacci numeral system.
3. The method of claim 1 , wherein the encoding comprises of m−1 stages to produce the FPF codeword of a m-bit length, wherein an encoding for each stage k comprises:
comparing a remainder input rk+1 to a stage k with two corresponding consecutive elements fk+1 and fk of the Fibonacci sequence;
assigning a value of 1 to an output dk of the stage k, if rk+1≧fk+1;
assigning a value of 0 to the output dk of the stage k, if rk+1 <fk; and otherwise
assigning a value of an output dk+1 of previous stage k+1 to the output
4. The method of claim 3 , wherein the encoding for each stage k further comprises:
sending the remainder rk of the encoding for the stage k as an input to a following stage k−1.
5. The method of claim 3 , wherein the output dk of a most significant bit stage k is 0.
6. The method of claim 3 , wherein the output dk of a most significant bit stage k is 1.
7. The method of claim 3 , wherein the output dk of a most significant bit stage k equals to a most significant bit of the dataword.
8. (canceled)
9. The method of claim 1 , further comprising:
partitioning the plurality of lines of the bus into a set of groups of lines;
applying the encoding step independently to each group of lines in the set.
10. A method for encoding a dataword to a codeword, comprising:
converting a dataword into a set of codewords, in which each codeword is represented by a Fibonacci numeral system;
selecting a Fibonacci forbidden pattern free (FPF) codeword from the set of codewords;
shifting values of the FPF codeword by fm+1 to remove the values redundancy in a region where duplicated FPF Fibonacci vectors exist:
representing the dataword as an encoded FPF codeword; and
transmitting the FPF codeword via a plurality of adjacent lines of a bus while eliminating crosstalk on all of the plurality of lines.
11. The method of claim 10 , wherein the converting step and the selecting step are comprised of m−1 stages to produce the codeword of a m-bit length, wherein an encoding for each stage k comprises:
comparing an input rk+1 to the stage k with two corresponding consecutive elements of the Fibonacci sequence fk+1 and fk;
assigning a value of 1 to an output dk of the stage k, if rk+1≧fk+1;
assigning a value of 0 to the output dk of the stage k, if rk+<fk; and otherwise
assigning a value of an output dk+1 of previous stage k+1 to the output dk.
12. The method of claim 11 , wherein the encoding for each stage k further comprises:
sending a remainder rk of the encoding for the stage k as an input to a following stage k−1.
13. The method of claim 11 , wherein the output dk of a most significant bit stage k equals to a most significant bit of the dataword.
14. The method of claim 10 , further comprising:
shifting values of the selected codeword by fm+1 to remove the values redundancy in a gray region.
15. An apparatus for reducing crosstalk in a bus while transmitting a dataword over the bus, comprising:
an encoder, in which the encoder is configured to encode a dataword, such that the dataword is represented as a Fibonacci forbidden pattern free (FPF) codeword when the code word is transmitted via a plurality of adjacent lines of the bus while eliminating crosstalk on all of the plurality of lines, and wherein values of the FPF codeword are shifted by fm+1 to remove the values redundancy in a region where duplicated FPF Fibonacci vectors exist.
16. The apparatus of claim 15 , further comprising:
a decoder, the decoder configured to decode the codeword to recover the dataword; and
means for transmitting the codeword from the encoder to the decoder.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/051,192 US7583209B1 (en) | 2008-03-19 | 2008-03-19 | System and method for signaling on a bus using forbidden pattern free codes |
JP2009066496A JP2009232461A (en) | 2008-03-19 | 2009-03-18 | Method and apparatus for reducing crosstalk on bus, and method for converting dataword into codeword |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/051,192 US7583209B1 (en) | 2008-03-19 | 2008-03-19 | System and method for signaling on a bus using forbidden pattern free codes |
Publications (2)
Publication Number | Publication Date |
---|---|
US7583209B1 US7583209B1 (en) | 2009-09-01 |
US20090237279A1 true US20090237279A1 (en) | 2009-09-24 |
Family
ID=41009213
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/051,192 Expired - Fee Related US7583209B1 (en) | 2008-03-19 | 2008-03-19 | System and method for signaling on a bus using forbidden pattern free codes |
Country Status (2)
Country | Link |
---|---|
US (1) | US7583209B1 (en) |
JP (1) | JP2009232461A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110127990A1 (en) * | 2008-06-20 | 2011-06-02 | Rambus Inc. | Frequency responsive bus coding |
CN112953556A (en) * | 2021-02-05 | 2021-06-11 | 南京大学 | Anti-crosstalk interconnection codec based on Fibonacci number sequence and coding method |
Families Citing this family (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8730764B2 (en) * | 2009-07-30 | 2014-05-20 | Schlumberger Technology Corporation | Telemetry coding and surface detection for a mud pulser |
US9288089B2 (en) | 2010-04-30 | 2016-03-15 | Ecole Polytechnique Federale De Lausanne (Epfl) | Orthogonal differential vector signaling |
US9251873B1 (en) | 2010-05-20 | 2016-02-02 | Kandou Labs, S.A. | Methods and systems for pin-efficient memory controller interface using vector signaling codes for chip-to-chip communications |
US8964879B2 (en) * | 2012-07-18 | 2015-02-24 | Rambus Inc. | Crosstalk reduction coding schemes |
US8689159B1 (en) * | 2012-09-12 | 2014-04-01 | Nvidia Corporation | Redundancy for on-chip interconnect |
US8941430B2 (en) * | 2012-09-12 | 2015-01-27 | Nvidia Corporation | Timing calibration for on-chip interconnect |
US9632961B2 (en) * | 2012-12-26 | 2017-04-25 | Intel Corporation | Crosstalk aware decoding for a data bus |
US9330039B2 (en) * | 2012-12-26 | 2016-05-03 | Intel Corporation | Crosstalk aware encoding for a data bus |
EP2778940B1 (en) * | 2013-03-15 | 2016-08-03 | Intel Corporation | Crosstalk aware decoding for a data bus |
US9806761B1 (en) | 2014-01-31 | 2017-10-31 | Kandou Labs, S.A. | Methods and systems for reduction of nearest-neighbor crosstalk |
KR102299815B1 (en) | 2014-02-02 | 2021-09-10 | 칸도우 랩스 에스에이 | Method and apparatus for low power chip-to-chip communications with constrained isi ratio |
US9363114B2 (en) | 2014-02-28 | 2016-06-07 | Kandou Labs, S.A. | Clock-embedded vector signaling codes |
US9509437B2 (en) | 2014-05-13 | 2016-11-29 | Kandou Labs, S.A. | Vector signaling code with improved noise margin |
WO2016007863A2 (en) * | 2014-07-10 | 2016-01-14 | Kandou Labs, S.A. | Vector signaling codes with increased signal to noise characteristics |
US9432082B2 (en) | 2014-07-17 | 2016-08-30 | Kandou Labs, S.A. | Bus reversable orthogonal differential vector signaling codes |
CN111343112B (en) | 2014-07-21 | 2022-06-24 | 康杜实验室公司 | Method and apparatus for receiving data from a multi-point communication channel |
CN106576087B (en) | 2014-08-01 | 2019-04-12 | 康杜实验室公司 | Orthogonal differential vector signaling code with embedded clock |
US9674014B2 (en) | 2014-10-22 | 2017-06-06 | Kandou Labs, S.A. | Method and apparatus for high speed chip-to-chip communications |
EP3314835B1 (en) | 2015-06-26 | 2020-04-08 | Kandou Labs S.A. | High speed communications system |
US10157161B2 (en) * | 2015-10-16 | 2018-12-18 | Qualcomm Incorporated | Conditional embedding of dynamically shielded information on a bus |
US10055372B2 (en) | 2015-11-25 | 2018-08-21 | Kandou Labs, S.A. | Orthogonal differential vector signaling codes with embedded clock |
US9654251B1 (en) * | 2015-12-03 | 2017-05-16 | Qualcomm Incorporated | Joint crosstalk-avoidance and error-correction coding for parallel data busses |
US10116468B1 (en) | 2017-06-28 | 2018-10-30 | Kandou Labs, S.A. | Low power chip-to-chip bidirectional communications |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070271535A1 (en) * | 2006-05-16 | 2007-11-22 | National Tsing Hua University | Method for crosstalk elimination and bus architecture performing the same |
US20080086560A1 (en) * | 2006-09-15 | 2008-04-10 | Fabrice Monier | Number of sons management in a cell network |
-
2008
- 2008-03-19 US US12/051,192 patent/US7583209B1/en not_active Expired - Fee Related
-
2009
- 2009-03-18 JP JP2009066496A patent/JP2009232461A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070271535A1 (en) * | 2006-05-16 | 2007-11-22 | National Tsing Hua University | Method for crosstalk elimination and bus architecture performing the same |
US20080086560A1 (en) * | 2006-09-15 | 2008-04-10 | Fabrice Monier | Number of sons management in a cell network |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110127990A1 (en) * | 2008-06-20 | 2011-06-02 | Rambus Inc. | Frequency responsive bus coding |
US8498344B2 (en) * | 2008-06-20 | 2013-07-30 | Rambus Inc. | Frequency responsive bus coding |
CN112953556A (en) * | 2021-02-05 | 2021-06-11 | 南京大学 | Anti-crosstalk interconnection codec based on Fibonacci number sequence and coding method |
Also Published As
Publication number | Publication date |
---|---|
US7583209B1 (en) | 2009-09-01 |
JP2009232461A (en) | 2009-10-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20090237279A1 (en) | System and method for signaling on a bus using forbidden pattern free codes | |
US6844833B2 (en) | Methods and apparatus for constant-weight encoding and decoding | |
US5382955A (en) | Error tolerant thermometer-to-binary encoder | |
US7495587B2 (en) | Low power balance code using data bus inversion | |
US6614369B1 (en) | DC balanced 7B/8B, 9B/10B, and partitioned DC balanced 12B/14B, 17B/20B, and 16B/18B transmission codes | |
JPH0428180B2 (en) | ||
CN101147325B (en) | Fast compact decoder for Huffman codes and decoding method | |
US7583207B2 (en) | Logic circuit | |
US7250896B1 (en) | Method for pipelining analog-to-digital conversion and a pipelining analog-to-digital converter with successive approximation | |
US6542104B1 (en) | Method and apparatus for low power thermometer to binary coder | |
US5321640A (en) | Priority encoder and method of operation | |
KR101540539B1 (en) | Magnitude Comparator Using Logic Gates | |
GB1597468A (en) | Conversion between linear pcm representation and compressed pcm | |
CN115102553A (en) | Device for converting binary code into thermometer code and electronic equipment | |
Soleimani et al. | Crosstalk free coding systems to protect NoC channels against crosstalk faults | |
US8280937B2 (en) | Sparse-coded look-up table | |
US6346906B1 (en) | Thermometric-binary code conversion method, conversion circuit therefor and encoder element circuits used therefor | |
Marques et al. | A current steering architecture for 12-bit high-speed D/A converters | |
US6816098B2 (en) | High-speed oversampling modulator device | |
WO2006027742A1 (en) | Fault tolerant bus | |
US20070028022A1 (en) | Apparatus and methods for a static mux-based priority encoder | |
KR100201030B1 (en) | Select encoder network | |
Tripathi et al. | An Improved (24, 16) OLS Code for Single Error Correction-Double Adjacent Error Correction-Triple Adjacent Error Correction | |
US7742598B2 (en) | Shrinking key generator for parallel process | |
Gray | Viterbi Decoder for a Trellis Coded Modulation (R= 2/3, K= 2) Communication System |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: MITSUBISHI ELECTRIC RESEARCH LABORTORIES, INC., MA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:DUAN, CHUNJIE;REEL/FRAME:021036/0668 Effective date: 20080602 |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
REMI | Maintenance fee reminder mailed | ||
LAPS | Lapse for failure to pay maintenance fees |
Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.) |
|
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Expired due to failure to pay maintenance fee |
Effective date: 20170901 |