US20090001517A1

US20090001517A1 - Thermally enhanced semiconductor devices

Info

Publication number: US20090001517A1
Application number: US11/769,470
Authority: US
Inventors: Leland Scott Swanson; Gregory E. Howard
Original assignee: Texas Instruments Inc
Current assignee: Texas Instruments Inc
Priority date: 2007-06-27
Filing date: 2007-06-27
Publication date: 2009-01-01
Also published as: US20100193909A1; US8203197B2

Abstract

One embodiment relates to a circuit. In this circuit, a first semiconductor device with a first geometry is associated with a first region of a semiconductor body within a first isolation structure. A second semiconductor device with a geometry that matches the first geometry is associated with a second region of the semiconductor body within a second isolation structure. A member, which spans the semiconductor body between the first region and the second region, thermally couples the first region to the second region while retaining electrical isolation therebetween. Other circuits and methods are also disclosed.

Description

FIELD OF INVENTION

The present invention relates generally to semiconductor devices and more particularly to thermally enhanced semiconductor devices.

BACKGROUND OF THE INVENTION

In many integrated circuits, designers go to great lengths to match the characteristics of devices, particularly for analog applications. One way in which designers often attempt to “match” two transistors is by matching their geometries (i.e., layouts). By doing this, the transistors experience similar electrical stresses with respect to surrounding devices. Therefore, the two transistors may have similar gains (β), currents delivered (I_DS), voltage thresholds (V_T), etc.
Even with matched geometries, however, it is still difficult to achieve extremely precise transistor matching over time due to dynamic temperature variations between two matched devices. For example, at any given time one transistor of a matched pair of transistors may draw a much larger current than the other transistor. This large current may cause the transistor or its surrounding structures to heat up more than the other transistor, thereby creating a thermally induced offset (or “thermal drift”) between the two devices. This thermally induced offset may vary as a function of time and is particularly problematic between devices where precise matching is desired.

SUMMARY OF THE INVENTION

The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary presents one or more concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later and is not an extensive overview of the invention. In this regard, the summary is not intended to identify key or critical elements of the invention, nor does the summary delineate the scope of the invention.
One embodiment relates to a circuit. In this circuit, a first semiconductor device with a first geometry is associated with a first region of a semiconductor body within a first isolation structure. A second semiconductor device with a geometry that matches the first geometry is associated with a second region of the semiconductor body within a second isolation structure. A member, which spans the semiconductor body between the first region and the second region, thermally couples the first region to the second region while retaining electrical isolation therebetween.
The following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which the principles of the invention may be employed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows one embodiment in accordance with aspects of the present invention;

FIGS. 2A-G show other embodiments in accordance with aspects of the present invention;

FIG. 3A-3C show another embodiment; and

FIG. 4 shows a flow chart in accordance with aspects of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention will now be described with reference to the attached drawing figures, wherein like reference numerals are used to refer to like elements throughout, and wherein the illustrated structures and devices are not necessarily drawn to scale.
Referring now to FIG. 1, one can see one embodiment of a circuit 100 adapted to facilitate precise matching of device characteristics. The circuit 100 is formed over a semiconductor body 102, which may typically comprise a Si wafer, silicon-on-insulator (SOI) structure, GaAs wafer, or some other type of semiconductor substrate. Isolation structures 104, 106, such as isolation trenches, for example, are formed in the semiconductor body and electrically isolate a first region 108 of the semiconductor body from a second region 110 of the semiconductor body. First and second geometrically matched devices 112, 114, are formed within the first and second regions 108, 110, respectively.
During operation, one of the devices (e.g., first device 112) may draw more current than the other device (e.g., second device 114). This increased current can create excess heat in the region associated with the one device (e.g., first region 108). Because the isolation structures 104, 106 typically have a significant thermal resistance, the isolation structures inhibit this heat from quickly dissipating between the regions 108, 110. This could cause heat to buildup in one of the regions, thereby causing the one device (e.g., first device 112) to operate at a higher temperature than the other device (e.g., second device 114). Absent countermeasures, this temperature difference between the two geometrically matched devices could cause deviations between their otherwise matched characteristics (e.g., carrier mobility, voltage threshold, PN junction forward bias voltage, etc.).
In order to mitigate this temperature difference, a member 116, which spans the body 102 between the first and second regions, thermally couples the first region 108 to the second region 110. The member 116 has a relatively low thermal resistance and allows heat to efficiently flow (q-flow) between the regions 108, 110. For example, in one embodiment, the member may thermally couple the first and second regions 108, 110 so they are separated by a thermal resistance of less than approximately 100 K-m/W, or even less than 50 K-m/W.
To ensure proper device functionality, the member 116 also retains electrical isolation between the two regions 108, 110. For example, in one embodiment, the member will separate the regions 108, 110 by an effective series R-C electrical reactance of at least approximately 10 kΩ at frequencies near the bandwidth of the circuit. For example, in a linear circuit the bandwidth could typically be the frequency where the gain has dropped to unity. In a switching circuit, by contrast, the bandwidth could often be about three to five times that of the switching frequency, although this bandwidth could vary depending on the desired “squareness” of the switched waveform. This configuration allows the characteristics of the first and second devices to closely match one another even if one device draws more current or is otherwise heated more than the other. It will be appreciated that the term “electrically isolates” and variations thereof may include substantial electrical isolation, where there is still some limited electrical coupling between the devices.
In various embodiments, the first and second devices 112, 114 could comprise bipolar junction transistors (BJTs), metal oxide semiconductor field effect transistors (MOSFETs), junction-gate field effect transistors (JFETs), multi-gate field effect transistors (MUGFETs), diodes, etc. These devices could be formed within a single semi-conductor body (e.g., on a single die of an integrated circuit), or could be formed on different integrated circuits (e.g., on two integrated circuits that are mounted on a common circuit board). Thus, isolation structures could include oxide based isolation trenches, but could also include more generic devices for isolation, such as circuit boards or other elements interposed between integrated circuits. Although not illustrated, more than two devices could be thermally coupled to one another by a single member or multiple members.
FIGS. 2A-2H show an example of another circuit 200 that may achieve precise device matching. Generally speaking, FIG. 2A shows a top view (layout view) of the circuit 200, while FIGS. 2B-2H show cross sectional views of the circuit taken across the sectional lines as indicated. Note that for purposes of clarity and simplicity, not all layers are necessarily illustrated in all of these figures.
Referring now to FIGS. 2A-2B, one can see the circuit 200 is formed over an SOI semiconductor body 202. The SOI body 202 comprises a buried oxide region 204 that is formed over a semiconductor substrate 206, where silicon (Si) 208 overlies the buried oxide 204.
A first isolation trench 210 surrounds a first region 212 of the silicon, and a second isolation trench 214 surrounds a second region 216 of the silicon. The lower surfaces of the isolation trenches (e.g., 218) may contact the buried oxide layer 204 to facilitate effective isolation between the first and second regions 212, 216.
Due to variations in doping concentration (e.g., due to device features), the first and second regions may exhibit different electrical resistances therein. Thus, the first region 212 may be characterized by a first electrical resistance region 220 and a second electrical resistance region 222, where the first electrical resistance region has a higher doping (i.e., lower electrical resistance) than the second electrical resistance region. Similarly, the second region 216 may be characterized by a third electrical resistance region 224 and a fourth electrical resistance region 226, where the third electrical resistance region has lower electrical resistance than the fourth electrical resistance region. First and second devices may be formed within the first and third (highly doped, low resistivity) electrical resistance regions 220, 224, respectively.
There are numerous ways in which the various electrical resistance regions could manifest themselves. For example, the first and third electrical resistance regions will often have one doping type (e.g., n-type), while the second and fourth electrical resistance regions will have the opposite doping type (e.g., p-type). In various embodiments, the first and third electrical resistance regions could have approximately the same electrical resistance, which might range from approximately 1 E-5 Ω-cm to approximately 1 E-2 Ω-cm. In various embodiments, the second and fourth electrical resistance regions could have approximately the same electrical resistance, which might range from approximately 1 Ω-cm to approximately 100 Ω-cm.
To thermally match the two devices, a member 228, which may have one or more fingers, may be configured in one of several locations with respect to the various electrical resistivity regions. For example, in the illustrated embodiment, the member 228 includes one finger 230 that overlies the first and third electrical resistance regions 220, 224 and that spans the Si body therebetween; and another finger 232 that overlies the second and fourth electrical resistance regions 222, 226 and spans the Si body therebetween.
Generally speaking, finger 232 may be preferable, because it is positioned over the second and fourth (relatively-high) electrical resistance regions 222, 226 which efficiently provide a mechanism to retain electrical isolation between the devices. More particularly, the finger 232 is electrically separated from the first and third electrical resistance regions 220, 224 by resistances R₁and R₂, which contribute to the overall electrical reactance of the member. This finger 232 may be positioned far enough from the first and third electrical resistance regions so that the series resistance R₁and R₂limit the impact of the added capacitance on the devices to acceptable levels.
In real world implementations, these fingers 230, 232 may manifest themselves in various forms. For example, FIGS. 2B-2D show cross sections of some illustrative fingers 230 coupling the first and third electrical resistance regions 220, 224, and FIGS. 2E-2G show cross sections of some illustrative fingers 232 coupling the second and fourth electrical resistance regions 222, 226. It will be appreciated that a member could include any one of these fingers (or an un-illustrated finger), as well as any combination of these fingers (and/or other un-illustrated fingers).
Referring now to FIG. 2B, one can see an embodiment of a finger 230A that could overlie the first and third electrical resistance regions 220, 224. The finger 230A includes a metal layer 234 (e.g., metal1). In the first region 212, contacts 236 couple the metal layer 234 to a poly layer 238 that overlies a thin oxide layer 240. In the second region 216, contacts 242 connect the metal layer 234 to optional highly doped active regions 244 in the third electrical resistance region 224. These highly doped active regions 244 are the same doping type (i.e., n-type or p-type) as the surrounding region 224, albeit at a higher concentration. Therefore, during operation, as one of the devices heats up, the heat may pass (q-flow) through the thin oxide 240 and flow between the first and second regions 212, 216. Thus, the thin oxide 240 allows some heat to pass, but still functions as a DC isolation element between the two regions.
FIG. 2C shows another finger 230B similar to FIG. 2C, but where the highly doped active regions 244 have not been formed. Because the highly doped active regions 244 may facilitate “ohmic” contacts (i.e., stable, low resistivity contacts), the absence of the highly doped active regions may increase the effective electrical reactance of this finger 230B.
Referring now to FIG. 2D, one can see another finger 230C that comprises a polysilicon layer 246. In this embodiment, the heat flows across two oxide layers 248, 250.
Referring now to FIG. 2E, one can see another finger 232A that spans the second and fourth electrical resistance regions 222, 226, and which comprises a first metal layer 252 and a second metal layer 254. In the first region 212, contacts 256 and optional highly doped active regions 258 couple the first metal layer 254 to the second electrical resistance region 222. In the second region 216, contacts 260, vias 262, and optional highly doped active regions 264 couple the second metal layer 254 to the fourth electrical resistance region 226. The finger 232A also includes an interlevel dielectric 266 that separates the first metal layer 252 from the second metal layer 254. Thus, to facilitate precise matching of the devices, heat can flow across over the finger 232A by flowing through the dielectric 266.
Referring now to FIG. 2F, one can see another finger 232B that comprises a polysilicon layer 268 and metal layers 269, 271. Again, the finger 232B may be configured such that heat flows between the first and second regions 212, 214 by traversing the thin oxide layers 270, 272. The metal layers 269, 271 are optional, although they tend to improve lateral heat conduction.
Referring now to FIG. 2G, one can see another finger 232C that comprises a metal layer 274 and contacts 276. The finger 232C may also include optional highly doped active areas 278.
FIG. 3 shows another embodiment 300 where the first and second devices comprise first and second bipolar devices. Aspects of the present invention may be particularly useful for bipolar devices, which are often used in circuits where very precisely matched device characteristics are required. In addition, bipolar transistors are often formed inside of their own shallow-trench isolation structure (i.e., only one bipolar device in each shallow-trench isolation structure), such that large thermal offsets may tend to occur. NPN bipolar transistors 302, 304 are formed in the semiconductor body, where each transistor comprises three terminals, namely an n-type emitter 306; a p-type base (which includes a highly doped p+ region 308 and a lower doped shallow p-well 310); and an n-type collector 312. A deep n-well 314, a deep n-contact 316, and a highly doped buried n-layer 318 serve to more uniformly connect the collectors to the base. In other embodiments, the bipolar transistors would have the doping conventions reversed (i.e., in PNP transistor embodiments).
A member 320 comprising three inter-digitated fingers 322, 324, 326, thermally couple the transistors to one another. The first and second inter-digitated fingers 322, 324 comprise first and second metal layers, such as previously discussed with respect to FIG. 2E. The third inter-digitated finger comprises a polysilicon layer and metal layers such as previously discussed with respect to FIG. 2F. Therefore, in this embodiment, an IC designer can have a variety of fingers that couple heat between two devices, with the highest reactance fingers nearest to the devices and the lowest reactance fingers furthest from the devices.
Thus, in one embodiment, the lowest reactance fingers (where reactance is related to the resistance and capacitance associated with the fingers) can be furthest away from the transistors and the highest reactance fingers can be closer to the transistors. A designer will want to limit the electrical effect of the fingers on the behavior of the circuit while maximizing the effect they will have on the thermal characteristics.
In order to aid in the successful manufacturing of matched transistors, aspects of the present invention relate to a method 400 for manufacturing such transistors as illustrated in FIG. 4. While this method is illustrated and described below as a series of acts or events, it will be appreciated that the present invention is not limited by the illustrated ordering of such acts or events. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. In addition, not all illustrated steps may be required to implement a methodology in accordance with one or more aspects or embodiments of the present invention. Further, one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases.
In 402, isolation structures are formed in a semiconductor body to electrically isolate first and second regions within the semiconductor body. In one embodiment, these isolation structures are isolation trenches that are formed by etching the semiconductor body to form a recess, and then filling the recess with dielectric material.
In 404, first and second relatively-high electrical resistance regions are formed. Formation of the first and second relatively-high electrical resistance regions could be accomplished by masking off these regions, and then performing an implant. This implant could decrease the electrical resistance (i.e., increase the electrical conductivity) of the implanted regions such that the masked regions have a relatively-high electrical resistance.
In 406, first and second devices could be formed within the first and second relatively-low electrical resistance regions. As mentioned, the devices could include MOSFETs, BJTs, JFETs, MUGFETs, diodes, or other semiconductor devices. Therefore, suitable steps could be used to make these devices. In a typical embodiment, the devices will be formed such that they have matched geometries.
Finally, in 408, the first and second regions are thermally coupled to one another. In one embodiment, the member thermally couples the regions while providing a resistive element that retains electrical isolation between the devices.
Although the invention has been illustrated and described with respect to one or more implementations, alterations and/or modifications may be made to the illustrated examples without departing from the spirit and scope of the appended claims. In particular regard to the various functions performed by the above described components or structures (assemblies, devices, circuits, systems, etc.), the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component or structure which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the invention. In addition, while a particular feature of the invention may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms “including”, “includes”, “having”, “has”, “with”, or variants thereof are used in either the detailed description and the claims, such terms are intended to be inclusive in a manner similar to the term “comprising”.

Claims

1. A circuit, comprising:

a first semiconductor device having a first geometry and being associated with a first region within a first isolation structure;

a second semiconductor device having a geometry that matches the first geometry and being associated with a second region within a second isolation structure; and

a member, which spans the semiconductor body between the first region and the second region, that is configured to thermally couple the first region to the second region while retaining electrical isolation therebetween.

2. The circuit of claim 1, where the member thermally couples the first region to the second region so the regions are separated by a thermal resistance of no more than approximately 100 K-m/W.

3. The circuit of claim 2, where the member electrically isolates the first region from the second region by an effective electrical reactance at frequencies near a bandwidth of the circuit of at least approximately 10 kΩ.

4. The circuit of claim 1, where the first region comprises:

a first electrical resistance region having a first electrical resistance; and

a second electrical resistance region with a second electrical resistance that is greater than the first electrical resistance.

5. The circuit of claim 4, where the first electrical resistance region has a first doping concentration and the second electrical resistance region has a second doping concentration that is lower than the first doping concentration.

6. The circuit of claim 4, further comprising:

a contact that couples the member to the second electrical resistance region.

7. The circuit of claim 1, where the member comprises inter-digitated fingers.

8. The circuit of claim 7, where the inter-digitated fingers comprise a relatively high reactance finger nearer to the first and second semiconductor devices and relatively low reactance finger further from the first and second devices.

9. The circuit of claim 7, where the inter-digitated fingers comprise a poly layer; and further comprising:

an oxide layer that separates the poly layer from the semiconductor body, where poly layer is configured such that heat is exchanged between the first and second devices by passing though the oxide layer and into the inter-digitated fingers.

10. The circuit of claim 7, where the inter-digitated fingers comprise a metal layer; and further comprising:

a contact connecting the metal layer to the semiconductor body.

11. The circuit of claim 1, where the first and second semiconductor devices comprise bipolar junction transistors having matched geometries and formed within a single semiconductor body.

12. A circuit, comprising:

a first region of a semiconductor body associated with a first isolation structure in which a first device is formed, where the first region comprising a first electrical resistance region and a second electrical resistance region that has a greater resistivity than the first electrical resistance region, the first electrical resistance region being under at least the first device;

a second region of the semiconductor body associated with a second isolation structure in which a second device is formed, where the second region comprises a third electrical resistance region and a fourth electrical resistance region that has a greater resistivity than the third electrical resistance region, the third resistance region being under at least the second device; and

a member that is configured to thermally couple the first region to the second region while retaining electrical isolation therebetween.

13. The circuit of claim 12, where the member overlies the first electrical resistance region and the third electrical resistance region and spans the semiconductor body therebetween.

14. The circuit of claim 13, where the member comprises:

a metal layer;

a contact coupling the metal layer to a poly layer over the first electrical resistance region; and

another contact coupling the metal layer to the third electrical resistance region.

15. The circuit of claim 13, where the member comprises:

at least one poly layer that directly overlies an oxide layer associated with the first electrical resistance region and an oxide layer associated with the third electrical resistance region.

16. The circuit of claim 12, where the member overlies the second electrical resistance region and the fourth electrical resistance region and spans the semiconductor body therebetween.

17. The circuit of claim 16, where the member comprises:

a first metal layer;

a contact coupling the first metal layer to the second electrical resistance region;

a second metal layer;

a contact coupling the second metal layer to the fourth electrical resistance region; and

a dielectric through which heat can flow that separates the first metal layer and the second metal layer.

18. The circuit of claim 16, where the member comprises:

at least one poly layer that directly overlies oxide layers respectively associated with the second electrical resistance region and the fourth electrical resistance region.

19. The circuit of claim 16, where the member comprises:

a metal layer;

a contact that couples the metal to the second electrical resistance region; and

another contact that couples the metal to the fourth electrical resistance region.

20. A method for forming a circuit, comprising:

forming isolation structures in a semiconductor body; where the isolation structures are adapted to electrically isolate first and second regions within the semiconductor body;

in the first and second regions, forming first and second relatively-high electrical resistance regions, respectively, by performing an implant that forms first and second relatively-low electrical resistance regions, respectively;

in the first and second relatively-low electrical resistance regions, forming first and second devices, respectively; and

forming a member that thermally couples the first and second relatively-high electrical resistance regions to one another and retains electrical isolation therebetween.