US20080272366A1 - Field effect transistor having germanium nanorod and method of manufacturing the same - Google Patents
Field effect transistor having germanium nanorod and method of manufacturing the same Download PDFInfo
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- US20080272366A1 US20080272366A1 US12/010,806 US1080608A US2008272366A1 US 20080272366 A1 US20080272366 A1 US 20080272366A1 US 1080608 A US1080608 A US 1080608A US 2008272366 A1 US2008272366 A1 US 2008272366A1
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- 239000002073 nanorod Substances 0.000 title claims abstract description 71
- 230000005669 field effect Effects 0.000 title claims abstract description 37
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 229910052732 germanium Inorganic materials 0.000 title description 6
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 title description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 58
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 58
- 239000010703 silicon Substances 0.000 claims abstract description 58
- 239000000758 substrate Substances 0.000 claims abstract description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 36
- 239000002184 metal Substances 0.000 claims description 29
- 229910052751 metal Inorganic materials 0.000 claims description 29
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 22
- 238000000034 method Methods 0.000 claims description 21
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 20
- -1 Zr2O5 Inorganic materials 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 229920005591 polysilicon Polymers 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 7
- 229910004129 HfSiO Inorganic materials 0.000 claims description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 6
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 6
- 229910052593 corundum Inorganic materials 0.000 claims description 6
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 6
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 claims description 6
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 6
- 229910052691 Erbium Inorganic materials 0.000 claims description 5
- 229910052769 Ytterbium Inorganic materials 0.000 claims description 5
- 229910052759 nickel Inorganic materials 0.000 claims description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims description 5
- 229910052697 platinum Inorganic materials 0.000 claims description 5
- 230000004888 barrier function Effects 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims description 4
- 229910006990 Si1-xGex Inorganic materials 0.000 claims description 3
- 229910007020 Si1−xGex Inorganic materials 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims description 3
- 229910052720 vanadium Inorganic materials 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 113
- 229910052681 coesite Inorganic materials 0.000 description 7
- 229910052906 cristobalite Inorganic materials 0.000 description 7
- 239000000377 silicon dioxide Substances 0.000 description 7
- 229910052682 stishovite Inorganic materials 0.000 description 7
- 229910052905 tridymite Inorganic materials 0.000 description 7
- 239000000969 carrier Substances 0.000 description 6
- 230000008569 process Effects 0.000 description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 238000002513 implantation Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- SCCCLDWUZODEKG-UHFFFAOYSA-N germanide Chemical compound [GeH3-] SCCCLDWUZODEKG-UHFFFAOYSA-N 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
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- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
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- H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
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Definitions
- Example embodiments relate to a field effect transistor having a germanium nanorod as a channel and a method of manufacturing the same.
- a conventional field effect transistor includes a silicon channel region between a source and a drain on a silicon substrate as a moving path of carriers.
- a predetermined gate voltage must be applied between the source and the drain.
- the speed of the device is determined according to the mobility of the main carriers, for example, holes.
- the speed of a device that employs a transistor depends on the mobility of the main carriers in the silicon channel, and thus, much research to increase the mobility of the main carriers have been conducted.
- germanium which has a higher mobility than silicon, has been used.
- Example embodiments provide a field effect transistor having a germanium nanorod that may have improved mobility suitable for a high speed operation transistor.
- Example embodiments also provide a method of manufacturing a field effect transistor having a germanium nanorod and a method of manufacturing the germanium nanorod.
- a field effect transistor having Ge nanorods may comprise a gate oxide layer on a silicon substrate, at least one nanorod embedded in the gate oxide layer having both ends thereof exposed, a source electrode and a drain electrode connected to opposite sides of the Ge nanorod, and a gate electrode on the gate oxide layer between the source electrode and the drain electrode.
- the Ge nanorod may comprise 2 to 5 nanorods separated from each other.
- the Ge nanorod may have a diameter of about 1 to about 20 nm.
- the Ge nanorod in the channel region may have a circular or an oval cross-section.
- the source electrode and the drain electrode may form a Schottky barrier junction with the Ge nanorod, and may be formed of a metal selected from the group consisting of Pt, Ni, Co, V, Yb, and Er.
- the gate oxide layer may be a dielectric layer having a dielectric constant higher than that of silicon oxide or silicon nitride, and may be formed of one selected from the group consisting of Si 3 N 4 , Ta 2 O 5 , HfO 2 , Zr 2 O 5 , Al 2 O 3 , HfO x N y , HfSiO, and HfSiON.
- the gate electrode may comprise a first metal layer formed of one selected from Ta, TaN, and TiN, and a second metal layer formed of polysilicon on the first metal layer.
- a method of manufacturing a field effect transistor may comprise forming an insulating layer and a first silicon layer on a silicon substrate, sequentially forming a SiGe layer and a second silicon layer on the first silicon layer, forming silicon oxide layers by oxidizing the first and second silicon layers and the Si of the SiGe layer on the silicon substrate, and forming the Ge nanorod from the SiGe layer.
- the method may further comprise forming a source electrode and a drain electrode contacting opposite ends of the Ge nanorod, forming a gate oxide layer that surrounds the Ge nanorod in a region for forming a channel region between the source electrode and the drain electrode, and forming a gate electrode on the gate oxide layer.
- the sequentially forming of the SiGe layer and the second silicon layer on the first silicon layer may be repeated 2 to 5 times on the first silicon layer.
- the insulating layer may be formed of a material having an etching rate different from that of the silicon oxide layers.
- the forming of the source electrode and the drain electrode may comprise forming a first photoresist in the region for forming the channel region, exposing both ends of the Ge nanorod by removing the silicon oxide layers in the regions for forming the source electrode and the drain electrode, and depositing a metal having a work function greater than that of Ge in the regions for forming the source electrode and the drain electrode.
- the forming of the gate oxide layer may comprise exposing the Ge nanorod by removing the silicon oxide layer in the region for forming the channel region, and forming the gate oxide layer that surrounds the Ge nanorod using a material having a higher dielectric constant than that of silicon oxide.
- the method may further comprise forming a cross-section of the Ge nanorod in the channel region into a circle or an oval shape by annealing the silicon substrate in a H 2 or D 2 atmosphere prior to forming the gate oxide layer.
- the forming of the gate electrode on the gate oxide layer may comprise forming a first metal layer formed of one selected from Ta, TaN, and TiN and forming a second metal layer formed of polysilicon on the first metal layer.
- the SiGe layer may have a composition of Si 1-x Ge x , where 0.1 ⁇ x ⁇ 0.5.
- the gate oxide layer may be formed of silicon oxide, and the forming of the gate electrode on the gate oxide layer may comprise forming a polysilicon layer.
- FIGS. 1-10 represent non-limiting, example embodiments as described herein.
- FIG. 1 is a cross-sectional view of a field effect transistor having a Ge nanorod according to example embodiments.
- FIGS. 2 through 10 are perspective views illustrating a method of manufacturing a field effect transistor having a Ge nanorod according to example embodiments.
- first, second, third etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of example embodiments.
- spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” may encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
- Example embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of example embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle may, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.
- FIG. 1 is a cross-sectional view of a field effect transistor 100 having a Ge nanorod according to example embodiments.
- an insulating layer 120 may be formed on a silicon substrate 110 .
- a gate oxide layer 130 which may be a dielectric layer having a higher dielectric constant, may be formed on the silicon substrate 110 .
- the gate oxide layer 130 may be formed of SiO 2 or a material having a dielectric constant greater than SiO 2 (e.g., Si 3 N 4 , Ta 2 O 5 , HfO 2 , Zr 2 O 5 , Al 2 O 3 , HfO x N y , HfSiO, or HfSiON).
- x and y in HfO x N y may be integers.
- the insulating layer 120 may be formed of a material having an etching rate different from that of silicon oxide that may be produced in the oxidation process, and may be formed of silicon oxide by oxygen ion implantation or silicon nitride.
- Two Ge nanorods 140 separated from each other may be embedded horizontally in the gate oxide layer 130 .
- the two Ge nanorods 140 may have a circle or an oval cross-section with a diameter of about 1 to about 20 nm. If the cross-section of the Ge nanorods 140 is a circle, an electric field may uniformly enter the Ge nanorods 140 , and thus, leakage current may be reduced.
- the field effect transistor 100 in FIG. 1 may include two Ge nanorods 140 , example embodiments are not limited thereto, and 2 to 5 Ge nanorods may be formed parallel to each other. If only one Ge nanorod 140 is formed in the field effect transistor 100 , a disconnection failure may occur. If more than 6 Ge nanorods 140 are formed in the field effect transistor 100 , the manufacturing process may become more complicated.
- the Ge nanorods 140 may be channels (e.g., paths of main carriers) in the field effect transistor 100 , for example, holes.
- the Ge nanorods 140 may provide a carrier mobility in a channel region of the field effect transistor 100 higher than that of a conventional field effect transistor.
- the gate oxide layer 130 formed of a dielectric having a higher dielectric constant may reduce gate leakage current by surrounding the Ge nanorods 140 .
- a source electrode 151 and a drain electrode 152 which may be electrically connected to the Ge nanorods 140 , may be formed on opposite sides of the Ge nanorods 140 .
- the source electrode 151 and the drain electrode 152 may form a Schottky barrier junction with the Ge nanorods 140 .
- the source electrode 151 and the drain electrode 152 may be formed of a metal having a work function greater than Ge. Germanides may be formed on contact surfaces between the Ge nanorods 140 and the source electrode 151 , and between the Ge nanorods 140 and the drain electrode 152 .
- Pt or Ni may be used, and, in order to form an n-type electrode, Yb or Er may be used.
- a gate electrode 160 may be formed on the gate oxide layer 130 between the source electrode 151 and the drain electrode 152 .
- the gate electrode 160 may include a first metal layer 161 formed of Ta, TaN, or TiN and a second metal layer 162 formed of polysilicon. If the gate oxide layer 130 is formed of SiO 2 , the gate electrode 160 may include only the second metal layer 162 .
- the gate electrode 160 may have a structure in which the first metal layer 161 and the second metal layer 162 are stacked.
- X and y in HfO x N y may be integers.
- the second metal layer 162 may reduce the depletion region in the channel region, thereby facilitating the formation of the channel.
- the gate oxide layer 130 formed of a higher dielectric material may be disposed around the Ge nanorods 140 , channel opening may be easier when a gate voltage is applied to the gate electrode 160 , thereby reducing the driving voltage. Also, because the Ge nanorods 140 having a higher mobility than silicon may be used in the field effect transistor 100 , the speed of a device including the field effect transistor 100 according to example embodiments may be increased.
- a method of manufacturing the field effect transistor 100 having the Ge nanorods 140 and a method of manufacturing the Ge nanorods 140 according to example embodiments will now be described.
- FIGS. 2 through 10 are perspective views illustrating a method of manufacturing the field effect transistor 100 having the Ge nanorods 140 .
- the same reference numerals are used to indicate elements that are substantially similar to the elements of FIG. 1 , and thus, a detailed description thereof will be omitted.
- an insulating layer 120 having an etching rate different from silicon oxide, which may be formed in a process of oxidizing silicon, may be formed on a silicon substrate 110 .
- a first silicon layer 121 may be formed on the insulating layer 120 .
- the insulating layer 120 may be a silicon oxide layer of a silicon on insulator (SOI) substrate formed by implanting oxygen in the silicon substrate 110 or a silicon nitride layer.
- SOI silicon on insulator
- SiGe layers 122 and 124 and second silicon layers 123 and 125 may then be alternately formed on the first silicon layer 121 .
- the SiGe layers and the second silicon layers may be alternately deposited twice on the first silicon layer 121 , for example, and the SiGe layers and the second silicon layers may be alternately deposited 2 to 5 times on the first silicon layer 121 .
- the SiGe layers 122 and 124 and the silicon layers 121 , 123 , and 125 may be formed using a chemical vapour deposition (CVD) method.
- CVD chemical vapour deposition
- the SiGe layers 122 and 124 may have a composition of Si 1-x Ge x , where x may be about 0.1 to about 0.5, and may be deposited to a thickness of about 1 to about 20 nm.
- the silicon layers 121 , 123 , and 125 may also be formed to a thickness of about 1 to about 20 nm.
- the resultant product as illustrated in FIG. 2 may be obtained by patterning the silicon layers 121 , 123 , and 125 and the second silicon layers 123 and 125 .
- the resultant product of FIG. 2 may be annealed in a furnace at a temperature of about 800 to 900° C. for about 1 to 5 minutes under an oxygen atmosphere.
- the silicon layers 121 , 123 , and 125 and the SiGe layers 122 and 124 may be partly oxidized.
- silicon layers 121 ′, 123 ′, and 125 ′ formed by the oxidation may have a reduced width.
- SiGe layers 122 and 124 Si may be separated from Ge and may be oxidized. As a result, only Ge layers 122 ′ and 124 ′ having a rod shape may remain.
- the SiGe layers 122 and 124 may be oxidized faster than the silicon layers 121 , 123 , and 125 .
- the SiGe layers 122 and 124 may become Ge nanorods 122 ′ and 124 ′ (corresponding to the Ge nanorods 140 of FIG. 1 ) that may function as channels.
- Reference numeral 126 indicates a SiO 2 region formed due to the oxidation of the silicon layers 121 , 123 , and 125 and the Si of the SiGe layers 122 and 124 .
- SiO 2 that may not be covered by the first photoresist P 1 may be removed by wet etching.
- the resultant product in FIG. 4 may be annealed in a furnace at a temperature of about 800 to 900° C. for about 1 to 5 minutes under an oxygen atmosphere.
- the silicon layers 121 ′, 123 ′, and 125 ′ in the regions for forming the source and drain electrodes may be oxidized, and may be removed in the subsequent etching process. Both ends of the nanorods 122 ′ and 124 ′ in the regions for forming the source and drain electrodes may be exposed.
- a source electrode 151 and a drain electrode 152 may be formed by depositing a metal in the regions for forming the electrodes.
- the source electrode 151 and the drain electrode 152 may be formed of a metal having a work function greater than Ge so as to form a Schottky barrier junction therebetween.
- the Ge nanorods 122 ′ and 124 ′ and the source electrode 151 and the drain electrode 152 may form a germanide on the contact region therebetween.
- Pt or Ni may be used, and in order to form an n-type electrode, Yb or Er may be used.
- the first photoresist P 1 (refer to FIG. 6 ) may be removed, and SiO 2 126 (refer to FIG. 6 ) covering the region for forming a channel may be etched by wet etching.
- the silicon layers 121 ′, 123 ′, and 125 ′ in the regions for forming electrodes may then be oxidized into a first silicon oxide (not shown) by annealing the silicon substrate 110 .
- a second silicon oxide layer (not shown) is formed on the silicon substrate 110 to cover the first silicon to form the gate oxide layer 130 (refer to FIG. 1 )
- the gate electrode 160 (refer to FIG. 1 ) may be formed on the gate oxide layer.
- the gate electrode 160 may be formed as a monolayer using polysilicon.
- the gate oxide layer may be formed of a material having a dielectric constant greater than that of the silicon oxide layer.
- the first silicon oxide formed by oxidizing the silicon layers 121 ′, 123 ′, and 125 ′ in the regions for forming electrodes may be removed by etching.
- the silicon substrate 110 may be annealed under an atmosphere of H 2 or D 2 at a partial pressure of about 2% to about 5% of the total pressure.
- cross-sections of the Ge nanorods 122 ′ and 124 ′ may have a circle or an oval shape.
- the gate oxide layer 130 may then be formed using a higher dielectric material (e.g., one material selected from Si 3 N 4 , Ta 2 O 5 , HfO 2 , Zr 2 O 5 , Al 2 O 3 , HfO x N y , HfSiO, and HfSiON) in the region for forming a channel.
- the gate oxide layer 130 may be formed to surround the Ge nanorods 122 ′ and 124 ′.
- a gate electrode 160 may be formed on the gate oxide layer 130 .
- the gate electrode 160 may include a first metal layer 161 formed of one material selected from Ta, TaN, and TiN and a second metal layer 162 formed of polysilicon on the first metal layer 161 .
- a field effect transistor may include Ge nanorods having a mobility greater than silicon as a channel, thereby increasing the driving speed and reducing the driving voltage of a device including the field effect transistor.
- a p-type transistor or an n-type transistor may be formed according to the material used to form the electrodes. Because in example embodiments, Ge nanorods may be used as a channel, a higher speed and lower power consumption transistor may be developed.
- the Ge nanorods which may be a channel region, may be readily formed using an oxidation process and an etching process.
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Abstract
A field effect transistor having at least one Ge nanorod and a method of manufacturing the field effect transistor are provided. The field effect transistor may include a gate oxide layer formed on a silicon substrate, at least one nanorod embedded in the gate oxide layer having both ends thereof exposed, a source electrode and a drain electrode connected to opposite sides of the at least one Ge nanorod, and a gate electrode formed on the gate oxide layer between the source electrode and the drain electrode.
Description
- This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 2007-0043025, filed on May 3, 2007, in the Korean Intellectual Property Office (KIPO), the entire contents of which are herein incorporated by reference.
- 1. Field
- Example embodiments relate to a field effect transistor having a germanium nanorod as a channel and a method of manufacturing the same.
- 2. Description of Related Art
- A conventional field effect transistor includes a silicon channel region between a source and a drain on a silicon substrate as a moving path of carriers. In order to turn on the silicon channel region, a predetermined gate voltage must be applied between the source and the drain. As a result, the speed of the device is determined according to the mobility of the main carriers, for example, holes.
- The speed of a device that employs a transistor depends on the mobility of the main carriers in the silicon channel, and thus, much research to increase the mobility of the main carriers have been conducted. In order to increase the mobility of the main carriers, germanium, which has a higher mobility than silicon, has been used.
- Example embodiments provide a field effect transistor having a germanium nanorod that may have improved mobility suitable for a high speed operation transistor. Example embodiments also provide a method of manufacturing a field effect transistor having a germanium nanorod and a method of manufacturing the germanium nanorod.
- According to example embodiments, a field effect transistor having Ge nanorods may comprise a gate oxide layer on a silicon substrate, at least one nanorod embedded in the gate oxide layer having both ends thereof exposed, a source electrode and a drain electrode connected to opposite sides of the Ge nanorod, and a gate electrode on the gate oxide layer between the source electrode and the drain electrode.
- The Ge nanorod may comprise 2 to 5 nanorods separated from each other.
- The Ge nanorod may have a diameter of about 1 to about 20 nm.
- The Ge nanorod in the channel region may have a circular or an oval cross-section.
- The source electrode and the drain electrode may form a Schottky barrier junction with the Ge nanorod, and may be formed of a metal selected from the group consisting of Pt, Ni, Co, V, Yb, and Er.
- The gate oxide layer may be a dielectric layer having a dielectric constant higher than that of silicon oxide or silicon nitride, and may be formed of one selected from the group consisting of Si3N4, Ta2O5, HfO2, Zr2O5, Al2O3, HfOxNy, HfSiO, and HfSiON.
- The gate electrode may comprise a first metal layer formed of one selected from Ta, TaN, and TiN, and a second metal layer formed of polysilicon on the first metal layer.
- According to example embodiments, a method of manufacturing a field effect transistor may comprise forming an insulating layer and a first silicon layer on a silicon substrate, sequentially forming a SiGe layer and a second silicon layer on the first silicon layer, forming silicon oxide layers by oxidizing the first and second silicon layers and the Si of the SiGe layer on the silicon substrate, and forming the Ge nanorod from the SiGe layer. The method may further comprise forming a source electrode and a drain electrode contacting opposite ends of the Ge nanorod, forming a gate oxide layer that surrounds the Ge nanorod in a region for forming a channel region between the source electrode and the drain electrode, and forming a gate electrode on the gate oxide layer.
- The sequentially forming of the SiGe layer and the second silicon layer on the first silicon layer may be repeated 2 to 5 times on the first silicon layer.
- The insulating layer may be formed of a material having an etching rate different from that of the silicon oxide layers.
- The forming of the source electrode and the drain electrode may comprise forming a first photoresist in the region for forming the channel region, exposing both ends of the Ge nanorod by removing the silicon oxide layers in the regions for forming the source electrode and the drain electrode, and depositing a metal having a work function greater than that of Ge in the regions for forming the source electrode and the drain electrode.
- The forming of the gate oxide layer may comprise exposing the Ge nanorod by removing the silicon oxide layer in the region for forming the channel region, and forming the gate oxide layer that surrounds the Ge nanorod using a material having a higher dielectric constant than that of silicon oxide.
- The method may further comprise forming a cross-section of the Ge nanorod in the channel region into a circle or an oval shape by annealing the silicon substrate in a H2 or D2 atmosphere prior to forming the gate oxide layer.
- The forming of the gate electrode on the gate oxide layer may comprise forming a first metal layer formed of one selected from Ta, TaN, and TiN and forming a second metal layer formed of polysilicon on the first metal layer.
- The SiGe layer may have a composition of Si1-xGex, where 0.1<x<0.5.
- The gate oxide layer may be formed of silicon oxide, and the forming of the gate electrode on the gate oxide layer may comprise forming a polysilicon layer.
- Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.
FIGS. 1-10 represent non-limiting, example embodiments as described herein. -
FIG. 1 is a cross-sectional view of a field effect transistor having a Ge nanorod according to example embodiments; and -
FIGS. 2 through 10 are perspective views illustrating a method of manufacturing a field effect transistor having a Ge nanorod according to example embodiments. - Reference will now be made in detail to example embodiments, examples of which are illustrated in the accompanying drawings. However, example embodiments are not limited to the embodiments illustrated hereinafter, and the embodiments herein are rather introduced to provide easy and complete understanding of the scope and spirit of example embodiments. In the drawings, the thicknesses of layers and regions are exaggerated for clarity.
- It will be understood that when an element or layer is referred to as being “on,” “connected to” or “coupled to” another element or layer, it may be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. Like reference numerals refer to like elements throughout. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
- It will be understood that, although the terms first, second, third etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of example embodiments.
- Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” may encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
- The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
- Example embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of example embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle may, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.
- Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
-
FIG. 1 is a cross-sectional view of afield effect transistor 100 having a Ge nanorod according to example embodiments. - Referring to
FIG. 1 , an insulatinglayer 120 may be formed on asilicon substrate 110. Agate oxide layer 130, which may be a dielectric layer having a higher dielectric constant, may be formed on thesilicon substrate 110. Thegate oxide layer 130 may be formed of SiO2 or a material having a dielectric constant greater than SiO2 (e.g., Si3N4, Ta2O5, HfO2, Zr2O5, Al2O3, HfOxNy, HfSiO, or HfSiON). In this case, x and y in HfOxNy may be integers. - The insulating
layer 120 may be formed of a material having an etching rate different from that of silicon oxide that may be produced in the oxidation process, and may be formed of silicon oxide by oxygen ion implantation or silicon nitride. - Two Ge nanorods 140 separated from each other may be embedded horizontally in the
gate oxide layer 130. The twoGe nanorods 140 may have a circle or an oval cross-section with a diameter of about 1 to about 20 nm. If the cross-section of the Ge nanorods 140 is a circle, an electric field may uniformly enter the Ge nanorods 140, and thus, leakage current may be reduced. - Although the
field effect transistor 100 inFIG. 1 may include twoGe nanorods 140, example embodiments are not limited thereto, and 2 to 5 Ge nanorods may be formed parallel to each other. If only oneGe nanorod 140 is formed in thefield effect transistor 100, a disconnection failure may occur. If more than 6 Ge nanorods 140 are formed in thefield effect transistor 100, the manufacturing process may become more complicated. The Ge nanorods 140 may be channels (e.g., paths of main carriers) in thefield effect transistor 100, for example, holes. The Ge nanorods 140 may provide a carrier mobility in a channel region of thefield effect transistor 100 higher than that of a conventional field effect transistor. - The
gate oxide layer 130 formed of a dielectric having a higher dielectric constant may reduce gate leakage current by surrounding the Ge nanorods 140. - A
source electrode 151 and adrain electrode 152, which may be electrically connected to the Ge nanorods 140, may be formed on opposite sides of the Ge nanorods 140. Thesource electrode 151 and thedrain electrode 152 may form a Schottky barrier junction with the Ge nanorods 140. In this case, thesource electrode 151 and thedrain electrode 152 may be formed of a metal having a work function greater than Ge. Germanides may be formed on contact surfaces between the Ge nanorods 140 and thesource electrode 151, and between the Ge nanorods 140 and thedrain electrode 152. In order to form a p-type electrode, Pt or Ni may be used, and, in order to form an n-type electrode, Yb or Er may be used. - A
gate electrode 160 may be formed on thegate oxide layer 130 between thesource electrode 151 and thedrain electrode 152. Thegate electrode 160 may include afirst metal layer 161 formed of Ta, TaN, or TiN and asecond metal layer 162 formed of polysilicon. If thegate oxide layer 130 is formed of SiO2, thegate electrode 160 may include only thesecond metal layer 162. Also, if thegate oxide layer 130 is formed of a material having a dielectric constant higher than SiO2 (e.g., Si3N4, Ta2O5, HfO2, Zr2O5, Al2O3, HfOxNy, HfSiO, or HfSiON), thegate electrode 160 may have a structure in which thefirst metal layer 161 and thesecond metal layer 162 are stacked. X and y in HfOxNy may be integers. Thesecond metal layer 162 may reduce the depletion region in the channel region, thereby facilitating the formation of the channel. - In the
field effect transistor 100 according to example embodiments, because thegate oxide layer 130 formed of a higher dielectric material may be disposed around the Ge nanorods 140, channel opening may be easier when a gate voltage is applied to thegate electrode 160, thereby reducing the driving voltage. Also, because the Ge nanorods 140 having a higher mobility than silicon may be used in thefield effect transistor 100, the speed of a device including thefield effect transistor 100 according to example embodiments may be increased. - A method of manufacturing the
field effect transistor 100 having the Ge nanorods 140 and a method of manufacturing the Ge nanorods 140 according to example embodiments will now be described. -
FIGS. 2 through 10 are perspective views illustrating a method of manufacturing thefield effect transistor 100 having the Ge nanorods 140. The same reference numerals are used to indicate elements that are substantially similar to the elements ofFIG. 1 , and thus, a detailed description thereof will be omitted. - Referring to
FIG. 2 , an insulatinglayer 120 having an etching rate different from silicon oxide, which may be formed in a process of oxidizing silicon, may be formed on asilicon substrate 110. Afirst silicon layer 121 may be formed on the insulatinglayer 120. The insulatinglayer 120 may be a silicon oxide layer of a silicon on insulator (SOI) substrate formed by implanting oxygen in thesilicon substrate 110 or a silicon nitride layer. - SiGe layers 122 and 124 and second silicon layers 123 and 125 may then be alternately formed on the
first silicon layer 121. InFIG. 2 , the SiGe layers and the second silicon layers may be alternately deposited twice on thefirst silicon layer 121, for example, and the SiGe layers and the second silicon layers may be alternately deposited 2 to 5 times on thefirst silicon layer 121. The SiGe layers 122 and 124 and the silicon layers 121, 123, and 125 may be formed using a chemical vapour deposition (CVD) method. - The SiGe layers 122 and 124 may have a composition of Si1-xGex, where x may be about 0.1 to about 0.5, and may be deposited to a thickness of about 1 to about 20 nm. The silicon layers 121, 123, and 125 may also be formed to a thickness of about 1 to about 20 nm. The resultant product as illustrated in
FIG. 2 may be obtained by patterning the silicon layers 121, 123, and 125 and the second silicon layers 123 and 125. - Referring to
FIG. 3 , the resultant product ofFIG. 2 may be annealed in a furnace at a temperature of about 800 to 900° C. for about 1 to 5 minutes under an oxygen atmosphere. The silicon layers 121, 123, and 125 and the SiGe layers 122 and 124 may be partly oxidized. As a result, silicon layers 121′, 123′, and 125′ formed by the oxidation may have a reduced width. In the SiGe layers 122 and 124, Si may be separated from Ge and may be oxidized. As a result, only Ge layers 122′ and 124′ having a rod shape may remain. This result may indicate that the SiGe layers 122 and 124 may be oxidized faster than the silicon layers 121, 123, and 125. Thus, the SiGe layers 122 and 124 may become Ge nanorods 122′ and 124′ (corresponding to the Ge nanorods 140 ofFIG. 1 ) that may function as channels.Reference numeral 126 indicates a SiO2 region formed due to the oxidation of the silicon layers 121, 123, and 125 and the Si of the SiGe layers 122 and 124. - Referring to
FIG. 4 , after a first photoresist P1 is formed in a region between the regions for forming the source and drain electrodes on thesilicon substrate 110, SiO2 that may not be covered by the first photoresist P1 may be removed by wet etching. - Referring to
FIG. 5 , the resultant product inFIG. 4 may be annealed in a furnace at a temperature of about 800 to 900° C. for about 1 to 5 minutes under an oxygen atmosphere. The silicon layers 121′, 123′, and 125′ in the regions for forming the source and drain electrodes may be oxidized, and may be removed in the subsequent etching process. Both ends of thenanorods 122′ and 124′ in the regions for forming the source and drain electrodes may be exposed. - Referring to
FIG. 6 , asource electrode 151 and adrain electrode 152 may be formed by depositing a metal in the regions for forming the electrodes. At this point, thesource electrode 151 and thedrain electrode 152 may be formed of a metal having a work function greater than Ge so as to form a Schottky barrier junction therebetween. The Ge nanorods 122′ and 124′ and thesource electrode 151 and thedrain electrode 152 may form a germanide on the contact region therebetween. In order to form a p-type electrode, Pt or Ni may be used, and in order to form an n-type electrode, Yb or Er may be used. - Referring to
FIG. 7 , the first photoresist P1 (refer toFIG. 6 ) may be removed, and SiO2 126 (refer toFIG. 6 ) covering the region for forming a channel may be etched by wet etching. - The silicon layers 121′, 123′, and 125′ in the regions for forming electrodes may then be oxidized into a first silicon oxide (not shown) by annealing the
silicon substrate 110. After a second silicon oxide layer (not shown) is formed on thesilicon substrate 110 to cover the first silicon to form the gate oxide layer 130 (refer toFIG. 1 ), the gate electrode 160 (refer toFIG. 1 ) may be formed on the gate oxide layer. Thegate electrode 160 may be formed as a monolayer using polysilicon. - Alternatively, the gate oxide layer may be formed of a material having a dielectric constant greater than that of the silicon oxide layer. Referring to
FIG. 8 , the first silicon oxide formed by oxidizing the silicon layers 121′, 123′, and 125′ in the regions for forming electrodes may be removed by etching. - Referring to
FIG. 9 , thesilicon substrate 110 may be annealed under an atmosphere of H2 or D2 at a partial pressure of about 2% to about 5% of the total pressure. As a result, cross-sections of the Ge nanorods 122′ and 124′ may have a circle or an oval shape. - The
gate oxide layer 130 may then be formed using a higher dielectric material (e.g., one material selected from Si3N4, Ta2O5, HfO2, Zr2O5, Al2O3, HfOxNy, HfSiO, and HfSiON) in the region for forming a channel. Thegate oxide layer 130 may be formed to surround the Ge nanorods 122′ and 124′. - Referring to
FIG. 10 , agate electrode 160 may be formed on thegate oxide layer 130. Thegate electrode 160 may include afirst metal layer 161 formed of one material selected from Ta, TaN, and TiN and asecond metal layer 162 formed of polysilicon on thefirst metal layer 161. - A field effect transistor according to example embodiments may include Ge nanorods having a mobility greater than silicon as a channel, thereby increasing the driving speed and reducing the driving voltage of a device including the field effect transistor.
- Also, a p-type transistor or an n-type transistor may be formed according to the material used to form the electrodes. Because in example embodiments, Ge nanorods may be used as a channel, a higher speed and lower power consumption transistor may be developed.
- In a method of manufacturing a field effect transistor according to example embodiments, the Ge nanorods, which may be a channel region, may be readily formed using an oxidation process and an etching process.
- The foregoing is illustrative of example embodiments and is not to be construed as limiting thereof. Although example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in example embodiments without materially departing from the novel teachings and advantages of example embodiments. Accordingly, all such modifications are intended to be included within the scope of the claims. Therefore, it is to be understood that the foregoing is illustrative of example embodiments and is not to be construed as limited to the specific embodiments disclosed, and that modifications to the disclosed embodiments, as well as other embodiments, are intended to be included within the scope of the appended claims. Example embodiments are defined by the following claims, with equivalents of the claims to be included therein.
Claims (21)
1. A field effect transistor, comprising:
a gate oxide layer on a silicon substrate:
at least one Ge nanorod embedded in the gate oxide layer having both ends thereof exposed;
a source electrode and a drain electrode connected to opposite sides of the Ge nanorod; and
a gate electrode on the gate oxide layer between the source electrode and the drain electrode.
2. The field effect transistor of claim 1 , wherein the at least one Ge nanorod comprises 2 to 5 nanorods separated from each other.
3. The field effect transistor of claim 1 , wherein the at least one Ge nanorod has a diameter of about 1 to about 20 nm.
4. The field effect transistor of claim 1 , wherein the at least one Ge nanorod in a channel region has a circular or an oval cross-section.
5. The field effect transistor of claim 1 , wherein the source electrode and the drain electrode form a Schottky barrier junction with the at least one Ge nanorod.
6. The field effect transistor of claim 5 , wherein the source electrode and the drain electrode are formed of a metal selected from the group consisting of Pt, Ni, Co, V, Yb, and Er.
7. The field effect transistor of claim 1 , wherein the gate oxide layer is a dielectric layer having a dielectric constant higher than that of silicon oxide.
8. The field effect transistor of claim 7 , wherein the gate oxide layer is formed of one selected from the group consisting of Si3N4, Ta2O5, HfO2, Zr2O5, Al2O3, HfOxNy, HfSiO, and HfSiON.
9. The field effect transistor of claim 8 , wherein the gate electrode comprises:
a first metal layer formed of one selected from Ta, TaN, and TiN; and
a second metal layer formed of polysilicon on the first metal layer.
10. A method of manufacturing a field effect transistor, the method comprising:
forming an insulating layer and a first silicon layer on a silicon substrate;
sequentially forming a SiGe layer and a second silicon layer on the first silicon layer;
forming silicon oxide layers by oxidizing the first and second silicon layers and Si of the SiGe layer on the silicon substrate, and forming at least one Ge nanorod from the SiGe layer;
forming a source electrode and a drain electrode contacting opposite ends of the at least one Ge nanorod;
forming a gate oxide layer that surrounds the at least one Ge nanorod in a region for forming a channel region between the source electrode and the drain electrode; and
forming a gate electrode on the gate oxide layer.
11. The method of claim 10 , wherein the sequentially forming of the SiGe layer and the second silicon layer is repeated 2 to 5 times on the first silicon layer.
12. The method of claim 10 , wherein the insulating layer is formed of a material having an etching rate different from that of the silicon oxide layers.
13. The method of claim 10 , wherein forming the source electrode and the drain electrode comprises:
forming a first photoresist in the region for forming the channel region;
exposing both ends of the at least one Ge nanorod by removing the silicon oxide layers in regions for forming the source electrode and the drain electrode; and
depositing a metal having a work function greater than that of Ge in the regions for forming the source electrode and the drain electrode.
14. The method of claim 10 , wherein forming the gate oxide layer comprises:
exposing the at least one Ge nanorod by removing the silicon oxide layers in the region for forming the channel region; and
forming the gate oxide layer that surrounds the at least one Ge nanorod using a material having a dielectric constant higher than that of silicon oxide.
15. The method of claim 14 , further comprising:
forming a cross-section of the at least one Ge nanorod in the channel region into a circle or an oval shape by annealing the silicon substrate in a H2 or D2 atmosphere prior to forming the gate oxide layer.
16. The method of claim 14 , wherein the material is one selected from the group consisting of Si3N4, Ta2O5, HfO2, Zr2O5, Al2O3, HfOxNy, HfSiO, and HfSiON.
17. The method of claim 16 , wherein the forming of the gate electrode comprises forming a first metal layer formed of one selected from Ta, TaN, and TiN and forming a second metal layer formed of polysilicon on the first metal layer.
18. The method of claim 10 , wherein the SiGe layer has a composition of Si1-xGex, where 0.1<x<0.5.
19. The method of claim 10 , wherein the source electrode and the drain electrode are formed of a metal selected from the group consisting of Pt, Ni, Co, V, Yb, and Er.
20. The method of claim 10 , wherein the gate oxide layer is formed of silicon oxide, and the forming of the gate electrode comprises forming a polysilicon layer.
21. The method of claim 10 , wherein the at least one Ge nanorod has a diameter of about 1 to about 20 nm.
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US9318573B2 (en) | 2016-04-19 |
KR101375833B1 (en) | 2014-03-18 |
JP5408897B2 (en) | 2014-02-05 |
JP2008277814A (en) | 2008-11-13 |
CN101299440A (en) | 2008-11-05 |
KR20080097762A (en) | 2008-11-06 |
US20130344664A1 (en) | 2013-12-26 |
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