US20080010621A1 - System and Method for Stopping Functional Macro Clocks to Aid in Debugging - Google Patents
System and Method for Stopping Functional Macro Clocks to Aid in Debugging Download PDFInfo
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- US20080010621A1 US20080010621A1 US11/550,036 US55003606A US2008010621A1 US 20080010621 A1 US20080010621 A1 US 20080010621A1 US 55003606 A US55003606 A US 55003606A US 2008010621 A1 US2008010621 A1 US 2008010621A1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
Definitions
- the present invention relates in general to the field of data processing systems. More specifically, the present invention relates to a system and method for stopping functional macro clocks to aid in debugging.
- Modern computer systems include a large number of integrated circuits.
- the integrated circuits generally include multiple macros, which each include a collection of integrated circuit elements utilized to perform a discrete function in the integrated circuit.
- a circuit tester when debugging an integrated circuit, a circuit tester would like to view the latch data values in one or more macros at the time of an error.
- the particular macro sends an error detection signal to a master macro signifying error detection.
- the master macro upon receiving the error detection signal from the particular macro, sends a stop signal that halts the functional clock of all macros in the integrated circuit. This allows the values of the latches in the integrated circuit to then be “scanned out” for examination.
- the present invention includes a system and method for debugging an integrated circuit.
- the integrated circuit includes a collection of macros.
- a reliability and serviceability (RAS) macro controls a clock source, scans the contents of the collection of macros via scan chains, and stops operations within the macros by sending out a global clock stop signal in response to receiving an error detection signal sent by any of the macros within the integrated circuit.
- RAS reliability and serviceability
- Each macro may further include a collection of latches controlled by a local clock control.
- a pattern matcher monitors data patterns in a current macro.
- a check stop logic sends an error detection signal to the RAS macro and possibly to one or more neighboring macros.
- the local clock control in the current macro immediately halts operation within the current macro such that the data values that contributed to the data pattern indicated of a failure signature are more likely retained in the collection of latches.
- the neighboring macro(s) if enabled
- the RAS macro upon receiving the error detection signal from the current macro, sends a global clock stop signal to all macros within the integrated circuit. After all macros have been stopped, the latch values within the macro may be scanned out for examination.
- FIG. 1 is a block diagram illustrating an exemplary data processing system in which a preferred embodiment of the present invention may be implemented
- FIG. 2 is a block diagram depicting an exemplary integrated circuit in which a preferred embodiment of the present invention may be implemented
- FIG. 3 is a more detailed block diagram illustrating an exemplary macro as shown in FIG. 2 ;
- FIG. 4 is a more detailed block diagram depicting an exemplary check stop logic as illustrated in FIG. 3 ;
- FIG. 5 is a high-level logical flowchart illustrating an exemplary method for stopping functional macro clocks to aid in debugging in accordance with a preferred embodiment of the present invention.
- the present invention includes an integrated circuit that is implemented as a reliability and serviceability (RAS) macro, a collection of macros, and a clock source.
- RAS reliability and serviceability
- each macro including the RAS macro monitors activity within the macros to detect internal data patterns that are indicative of a failure signature (e.g., illegal value).
- the check stop logic sends an error detection signal to a local clock control, any neighboring macros that have elected to receive failure detection signals from the first macro, and to the RAS macro.
- any neighboring macros are also halted, if requested, thus more likely preserving the values that generated the illegal value, instead of halting the first macro upon receiving a global clock stop signal from the RAS macro.
- FIG. 1 there is depicted an exemplary data processing system 6 in which a preferred embodiment of the present invention may be implemented.
- the depicted embodiment can be realized, for example, as a workstation, server, or mainframe computer.
- data processing system 6 includes one or more processing nodes 8 a - 8 n, which, if more than one processing node 8 is implemented, are interconnected by node interconnect 22 .
- Processing nodes 8 a - 8 n may each include one or more processors 10 , a local interconnect 16 , and a system memory 18 that is accessed via a memory controller 17 .
- Processors 10 a - 10 m are preferably (but not necessarily) identical and may comprise a processor within the PowerPCTM line of processors available from International Business Machines (IBM) Corporation of Armonk, N.Y.
- each of processors 10 a - 10 m also includes an on-chip cache hierarchy 14 that is utilized to stage data to the associated processor core 12 from system memories 18 .
- Each of processing nodes 8 a - 8 n further includes a respective node controller 20 coupled between local interconnect 16 and node interconnect 22 .
- Each node controller 20 serves as a local agent for remote processing nodes 8 by performing at least two functions. First, each node controller 20 snoops the associated local interconnect 16 and facilitates the transmission of local communication transactions to remote processing nodes 8 . Second, each node controller 20 snoops communication transactions on node interconnect 22 and masters relevant communication transactions on the associated local interconnect 16 . Communication on each local interconnect 16 is controlled by an arbiter 24 . Arbiters 24 regulate access to local interconnects 16 based on bus request signals generated by processors 10 and compile coherency responses for snooped communication transactions on local interconnects 16 .
- Mezzanine bus bridge 26 provides both a low latency path through which processors 10 may directly access devices among I/O devices 32 and storage devices 34 that are mapped to bus memory and/or I/O address spaces and a high bandwidth path through which I/O devices 32 and storage devices 34 may access system memory 18 .
- I/O devices 32 may include, for example, a display device, a keyboard, a graphical pointer, and serial and parallel ports for connection to external networks or attached devices.
- Storage devices 34 may include, for example, optical or magnetic disks that provide non-volatile storage for operating system, middleware and application software.
- FIG. 2 is a block diagram illustrating an exemplary integrated circuit 200 , such as processor 10 within data processing system 6 of FIG. 1 .
- Integrated circuit 200 is preferably implemented as a semiconductor or insulating substrate with integrated circuitry, implemented in various functional blocks referred to herein as reliability and serviceability (RAS) macro 204 , macros 205 a - 205 n, and clock source 232 .
- RAS reliability and serviceability
- Clock source 232 supplies a clock signal to all the macros 205 a - 205 n and RAS macro 204 and is controlled by RAS macro 204 .
- RAS macro 204 controls clock source 232 , controls scanning of the contents of macros 205 a - 205 n via a scan chain or chains (discussed herein in more detail in conjunction with FIGS. 3-5 ), and stops operation of macros 205 a - 205 n by sending out a global clock stop signal in response to an error detection signal sent by any of the macros within integrated circuit 200 .
- RAS macro 204 may also include many of the similar structures (e.g., latches, functional logic, and check stop logic, all discussed herein in more detail in conjunction with FIGS. 3-4 ) as macro 205 a - n. While FIG. 2 depicts integrated circuit 200 with four macros (RAS macro 204 and macros 205 a - n ), those with skill in the art will appreciate that integrated circuit 200 is not limited to four macros and may include any number of macros.
- RAS macro 204 is coupled to macros 205 a - 205 n via a variety of signals lines 234 a - 234 n, 236 a - 236 n, and signal 240 a.
- signal lines 234 a - 234 n are signal lines that enable RAS macro 204 to stop macros 205 a - 205 n directly via clk_stop 208 located on RAS macro 204 and clk_stop 220 a - 220 n on macros 205 .
- Signal lines 236 a - 236 n enable macros 205 a - 205 n to send an error detection signal to RAS macro 204 from error_out 222 a - 222 n to error 210 located on RAS macro 204 .
- Signal lines 240 a - 220 n couple scan_out 228 a - 228 n and scan_in 230 a - 230 n and form a scan chain among macros 205 a - 205 n.
- the scan chain originates at scan_chain_out 216 and terminates at scan_chain_in 214 , located on RAS macro 204 .
- Test equipment 202 utilizes the scan chain to scan out the values of the latches in macros 205 a - 205 n and RAS macro 204 after RAS macro 204 sends a global clock stop signal in response to receiving an error detection signal from another macro 205 a - 205 n.
- clock source 232 supplies a clock signal to RAS macro 204 and macros 205 a - n.
- signal lines 238 a - 238 n supply the clock signal to macros 205 a - 205 n.
- Signal line 239 supplies the clock signal to RAS macro 204 .
- Macros 205 a - 205 b illustrate a pair of macros connected to enable one macro (macro 205 b ) to stop a neighboring macro (macro 205 a ) when the first macro detects an error if the second macro is enabled to receive a “local stop” signal.
- the “neighbor stop” procedure is accomplished by tying local stop 226 a of macro 205 a to error_out 222 b of macro 205 b via signal line 242 a.
- check stop logic within macro 205 b sends out an error detection signal that not only propagates to RAS macro 204 , but is forwarded to macro 205 a via signal line 242 a.
- the checkstop logic within macro 205 a is enabled to receive a local stop signal, the clocks within macro 205 a will be stopped upon receipt of local stop signal 242 a.
- This “neighbor stop” procedure enables neighboring macros to be stopped before RAS macro 204 sends the global clock stop signal, thus more likely preserving values present within macro 205 a at the time of the failure.
- Signal lines 242 a - 242 n are included in FIG. 2 , but those with skill in the art will appreciate that not all local stop 226 a - 226 n need to be coupled to neighboring macros and that it is also possible for a given macro 205 to have a plurality of local stop inputs connected to a number of neighboring macros.
- FIG. 3 is a block diagram depicting an exemplary macro 205 from FIG. 2 .
- macro 205 includes local clock control 302 , check stop logic 310 , and functional logic 304 .
- Local clock control is coupled to clock source 232 via signal line 238 and distributes the clock signal to functional logic 304 .
- Function logic 304 includes both latches 306 a - 306 n and logic gates 308 . While FIG. 3 illustrates only three latches within macro 205 , those with skill in the art will appreciate that macro 205 may include any number of latches.
- macro 205 there are three ways in which macro 205 may be stopped: (1) upon detection of a failure signature from signal line 300 ; (2) upon receiving an error detection signal from a neighboring macro on signal 226 ; and (3) upon receiving a global stop signal from RAS macro 204 on signal 220 .
- check stop logic 310 monitors signal line 300 for failure signatures (e.g., illegal values) generated by functional logic 304 . Once check stop logic 310 detects a failure signature, check stop logic 310 sends an error detection signal to local clock control 302 , which stops operation of macro 205 .
- failure signatures e.g., illegal values
- Macros within integrated circuit 200 may be coupled so that if one macro sends out an error detection signal, that signal propagates to neighboring macros via local stop 226 a - 226 n coupled to signal line 242 .
- an error detection signal sent from error_out 222 a in macro 205 b can stop operations within macro 205 a when the error detection signal is received via local stop 226 a.
- check stop logic 310 sends an error detection signal to local clock control 302 and to RAS macro 204 via error_out 222 .
- RAS macro 204 sends out a global stop signal to all macros 205 a - 205 n.
- any macros 205 a - 205 n still operating will stop.
- FIG. 4 is a more detailed block diagram illustrating check stop logic 310 from FIG. 3 .
- check stop logic 310 includes pattern matcher 402 , pattern matching configuration 404 , a collection of logic gates (OR gates 412 a - 412 b and AND gates 414 a - 414 c ), and latches 400 a - 400 c.
- Pattern matching configuration 404 is preferably implemented as a set of latches that instructs pattern matcher 402 of the patterns of signals on signal line 300 that are indicative of a failure signature.
- Pattern matcher 402 is preferably implemented as a set of logic that monitors signals within macro 205 to detect signals from signal line 300 that are indicative of a failure signature. As previously discussed, signal line 300 receives signals from functional logic 304 .
- AND gate 414 c, signal line 408 , and latch 400 a enable or disable the output of pattern matcher 402 depending on a current setting of latch 400 a. For example, a circuit tester may not be interested in whether or not a current macro encounters any signals indicated of a failure signature. To disable the output of pattern matcher 402 , latch 400 a may be scanned with a value of “0” at system startup.
- AND gates 414 a - 414 b, latches 400 b - 400 c and signal lines 242 a - 242 b enable or disable error detection signals from neighboring macros. For example, if a circuit tester requires that an error detection signal from macro 205 b be sent to not only RAS macro 204 , but macro 205 a as well, the error detection signal from macro 205 b would propagate to macro 205 a via a signal line, such as signal lines 242 a - 242 b. Latches 400 b - 400 c would be scanned with a value of “1” to enable the error detection signal to propagate from AND gates 414 a - 414 b to OR gate 412 a.
- OR gate 412 a combines the error detection signals from AND gates 414 a - 414 b sent from neighboring macros. OR gate 412 b further combines the signal from OR gate 412 a with the signal from AND gate 414 c, which represents the error detection signal from pattern matcher 402 . The output of AND gate 412 b then propagates to signals 222 and 314 to signal neighboring macros 205 and RAS macro 204 and to stop the local clocks via local clock control 302 .
- check stop logic 310 enables a circuit tester to enable or disable error detection signals from a current macro and/or neighboring macros. Depending on the configuration of the current macro, stopping operating of the current macro in response to an error detection signal from a neighboring macro is desired.
- latches 400 a - 400 c as well as the latches within pattern matching configuration 404 are also coupled via an unillustrated scan chain or chains to enable these latches to be initialized during scanning of integrated circuit 200 , as show in step 501 of FIG. 5 .
- test equipment 202 may configure which error patterns are detected and which macros, if any, are stopped in response to an error.
- FIG. 5 is a high-level logical flowchart depicting an exemplary method for stopping functional macro clocks to aid in debugging in accordance with a preferred embodiment of the present invention.
- the process begins at step 500 and proceeds to step 502 , which shows integrated circuit 200 being initialized by scanning initial values into the latches within integrated circuit 200 .
- latches 400 a - 400 c are initialized with values that either enable or disable error detection signals from passing through AND gates 414 a - 414 c in check stop logic 310 .
- latches within pattern match configuration 404 are initialized and specify signals patterns that are indicative of a failure signature.
- step 504 which depicts integrated circuit beginning operation.
- the process then proceeds to step 506 , which shows check stop logic 310 determining if an enabled local stop has been received via an error detection signal via local stop 226 and signal line 242 from a neighboring macro.
- step 508 which illustrates check stop logic 310 determining if pattern matcher 402 has detected a signal indicative of a failure signature. If pattern matcher 402 has not detected a signal indicative of a failure signature, the process returns to step 506 and proceeds in an iterative fashion. If pattern matcher 402 has detected a signal indicative of a failure signal, the process proceeds to step 510 .
- step 510 illustrates check stop logic 310 presenting an error detection signal via signal line 314 to local clock control 302 and error out 222 via signal line 236 , which propagates to neighboring macros (if connected and also configured by circuit tester to do so) and RAS macro 204 .
- RAS macro 204 upon receiving the error detection signal, sends a clock stop signal via CLK_stop 208 to all macros 205 to stop operation of all remaining macros 205 in integrated circuit 200 .
- step 512 illustrates test equipment 202 scanning latches via scan_chain_in 214 when all clocks within all macros 205 have been stopped.
- step 514 ends, as illustrated in step 514 .
- the present invention includes a system and method for debugging an integrated circuit.
- the integrated circuit includes a collection of macros.
- a reliability and serviceability (RAS) macro controls a clock sources, scans the contents of the collection of macros via scan chains, and stops operations within the macros by sending out a global clock stop signal in response to receiving an error detection signal sent by any of the macros within the integrated circuit.
- RAS reliability and serviceability
- Each macro further includes a collection of latches controlled by a local clock control.
- a pattern matcher monitors data patterns in a current macro.
- a check stop logic sends an error detection signal to the RAS macro and possibly to one or more neighboring macros.
- the local clock control in the current macro halts operation within the current macro such that the data values that contributed to the data pattern indicated of a failure signature are more likely retained in the collection of latches.
- the RAS macro sends a global clock stop signal to all macros within the integrated circuit in response to receiving the error detection signal.
- the neighboring macro In response to receiving the error detection signal from the current macro, the neighboring macro also halts operation, preferably before receiving the global clock stop signal from the RAS macro.
- the present invention may be alternatively implemented in a computer-readable medium that stores a program product.
- Programs defining functions in the present invention can be delivered to a data storage system or a computer system via a variety of signal-bearing media, which include, without limitation, non-writable storage media (e.g., CD-ROM), writable storage media (e.g., floppy diskette, hard disk drive, read/write CD-ROM, optical media), and communication media, such as computer and telephone networks including Ethernet.
- signal-bearing media when carrying or encoding computer-readable instructions that direct method functions in the present invention, represent alternative embodiments of the present invention.
- the present invention may be implemented by a system having means in the form of hardware, software, or a combination of software and hardware as described herein or their equivalent.
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Abstract
A system and method for debugging an integrated circuit. According to a preferred embodiment of the present invention, the integrated circuit includes a collection of macros. Each macro further includes a collection of latches controlled by a local clock control. A pattern matcher monitors data patterns in at least one macro. In response to detecting a data pattern indicative of a failure signature within the at least one macro, a check stop logic sends an error detection signal to at least one additional macro and to the local clock control. In response to receiving the error detection signal, the local clock control halts operation with the at least one macro such that data values contributing to said data pattern indicative of said failure signature are retained in the collection of latches.
Description
- 1. Technical Field
- The present invention relates in general to the field of data processing systems. More specifically, the present invention relates to a system and method for stopping functional macro clocks to aid in debugging.
- 2. Description of the Related Art
- Modern computer systems include a large number of integrated circuits. The integrated circuits generally include multiple macros, which each include a collection of integrated circuit elements utilized to perform a discrete function in the integrated circuit.
- Frequently, when debugging an integrated circuit, a circuit tester would like to view the latch data values in one or more macros at the time of an error. As well-known by those skilled in the art, often when a particular macro encounters an error, the particular macro sends an error detection signal to a master macro signifying error detection. The master macro, upon receiving the error detection signal from the particular macro, sends a stop signal that halts the functional clock of all macros in the integrated circuit. This allows the values of the latches in the integrated circuit to then be “scanned out” for examination. By the time the particular macro stops operating in response to the stop signal, the data values present in the macro at the time of the error are often lost because the functional clock was halted not at the time the error was detected, but many clock cycles later in response to the master macro's stop signal. Therefore, there is a need for a system and method for addressing the aforementioned limitations of the prior art.
- The present invention includes a system and method for debugging an integrated circuit. According to a preferred embodiment of the present invention, the integrated circuit includes a collection of macros. A reliability and serviceability (RAS) macro controls a clock source, scans the contents of the collection of macros via scan chains, and stops operations within the macros by sending out a global clock stop signal in response to receiving an error detection signal sent by any of the macros within the integrated circuit.
- Each macro may further include a collection of latches controlled by a local clock control. A pattern matcher monitors data patterns in a current macro. In response to detecting a data pattern indicative of a failure signature within the current macro, a check stop logic sends an error detection signal to the RAS macro and possibly to one or more neighboring macros. The local clock control in the current macro immediately halts operation within the current macro such that the data values that contributed to the data pattern indicated of a failure signature are more likely retained in the collection of latches. In response to receiving the error detection signal from the current macro, the neighboring macro(s) (if enabled) will also immediately stop operations to preserve values in the neighboring macro(s). The RAS macro, upon receiving the error detection signal from the current macro, sends a global clock stop signal to all macros within the integrated circuit. After all macros have been stopped, the latch values within the macro may be scanned out for examination.
- The aforementioned features, as well as additional objectives, features, and advantages of the present invention will become apparent in the following detailed description.
- The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as a preferred mode of use, further objects and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying figures, wherein:
-
FIG. 1 is a block diagram illustrating an exemplary data processing system in which a preferred embodiment of the present invention may be implemented; -
FIG. 2 is a block diagram depicting an exemplary integrated circuit in which a preferred embodiment of the present invention may be implemented; -
FIG. 3 is a more detailed block diagram illustrating an exemplary macro as shown inFIG. 2 ; -
FIG. 4 is a more detailed block diagram depicting an exemplary check stop logic as illustrated inFIG. 3 ; -
FIG. 5 is a high-level logical flowchart illustrating an exemplary method for stopping functional macro clocks to aid in debugging in accordance with a preferred embodiment of the present invention. - The present invention includes an integrated circuit that is implemented as a reliability and serviceability (RAS) macro, a collection of macros, and a clock source. Utilizing check stop logic, each macro, including the RAS macro monitors activity within the macros to detect internal data patterns that are indicative of a failure signature (e.g., illegal value). In response to detecting internal data patterns that are indicative of a failure signature within a first macro, the check stop logic sends an error detection signal to a local clock control, any neighboring macros that have elected to receive failure detection signals from the first macro, and to the RAS macro. While the local clock control halts operation of the first macro, any neighboring macros are also halted, if requested, thus more likely preserving the values that generated the illegal value, instead of halting the first macro upon receiving a global clock stop signal from the RAS macro.
- With reference now to the figures, and in particular, with reference to
FIG. 1 , there is depicted an exemplarydata processing system 6 in which a preferred embodiment of the present invention may be implemented. The depicted embodiment can be realized, for example, as a workstation, server, or mainframe computer. - As illustrated,
data processing system 6 includes one ormore processing nodes 8 a-8 n, which, if more than oneprocessing node 8 is implemented, are interconnected bynode interconnect 22.Processing nodes 8 a-8 n may each include one ormore processors 10, alocal interconnect 16, and asystem memory 18 that is accessed via amemory controller 17.Processors 10 a-10 m are preferably (but not necessarily) identical and may comprise a processor within the PowerPC™ line of processors available from International Business Machines (IBM) Corporation of Armonk, N.Y. In addition to the registers, instruction flow logic and execution units utilized to execute program instructions, which are generally designated asprocessor core 12, each ofprocessors 10 a-10 m also includes an on-chip cache hierarchy 14 that is utilized to stage data to the associatedprocessor core 12 fromsystem memories 18. - Each of
processing nodes 8 a-8 n further includes arespective node controller 20 coupled betweenlocal interconnect 16 andnode interconnect 22. Eachnode controller 20 serves as a local agent forremote processing nodes 8 by performing at least two functions. First, eachnode controller 20 snoops the associatedlocal interconnect 16 and facilitates the transmission of local communication transactions toremote processing nodes 8. Second, eachnode controller 20 snoops communication transactions on node interconnect 22 and masters relevant communication transactions on the associatedlocal interconnect 16. Communication on eachlocal interconnect 16 is controlled by anarbiter 24.Arbiters 24 regulate access tolocal interconnects 16 based on bus request signals generated byprocessors 10 and compile coherency responses for snooped communication transactions onlocal interconnects 16. -
Local interconnect 16 is coupled, viamezzanine bus bridge 26, to amezzanine bus 30. Mezzaninebus bridge 26 provides both a low latency path through whichprocessors 10 may directly access devices among I/O devices 32 andstorage devices 34 that are mapped to bus memory and/or I/O address spaces and a high bandwidth path through which I/O devices 32 andstorage devices 34 may accesssystem memory 18. I/O devices 32 may include, for example, a display device, a keyboard, a graphical pointer, and serial and parallel ports for connection to external networks or attached devices.Storage devices 34 may include, for example, optical or magnetic disks that provide non-volatile storage for operating system, middleware and application software. -
FIG. 2 is a block diagram illustrating an exemplary integratedcircuit 200, such asprocessor 10 withindata processing system 6 ofFIG. 1 .Integrated circuit 200 is preferably implemented as a semiconductor or insulating substrate with integrated circuitry, implemented in various functional blocks referred to herein as reliability and serviceability (RAS)macro 204, macros 205 a-205 n, andclock source 232.Clock source 232 supplies a clock signal to all the macros 205 a-205 n andRAS macro 204 and is controlled by RASmacro 204. - According to a preferred embodiment of the present invention,
RAS macro 204controls clock source 232, controls scanning of the contents of macros 205 a-205 n via a scan chain or chains (discussed herein in more detail in conjunction withFIGS. 3-5 ), and stops operation of macros 205 a-205 n by sending out a global clock stop signal in response to an error detection signal sent by any of the macros within integratedcircuit 200. Those with skill in the art will appreciate thatRAS macro 204 may also include many of the similar structures (e.g., latches, functional logic, and check stop logic, all discussed herein in more detail in conjunction withFIGS. 3-4 ) as macro 205 a-n. WhileFIG. 2 depicts integratedcircuit 200 with four macros (RAS macro 204 and macros 205 a-n), those with skill in the art will appreciate that integratedcircuit 200 is not limited to four macros and may include any number of macros. - RAS
macro 204 is coupled to macros 205 a-205 n via a variety ofsignals lines 234 a-234 n, 236 a-236 n, and signal 240 a. As illustrated,signal lines 234 a-234 n are signal lines that enableRAS macro 204 to stop macros 205 a-205 n directly viaclk_stop 208 located onRAS macro 204 andclk_stop 220 a-220 n on macros 205.Signal lines 236 a-236 n enable macros 205 a-205 n to send an error detection signal toRAS macro 204 fromerror_out 222 a-222 n toerror 210 located onRAS macro 204.Signal lines 240 a-220 n couple scan_out 228 a-228 n andscan_in 230 a-230 n and form a scan chain among macros 205 a-205 n. The scan chain originates atscan_chain_out 216 and terminates atscan_chain_in 214, located on RAS macro 204.Test equipment 202 utilizes the scan chain to scan out the values of the latches in macros 205 a-205 n and RAS macro 204 afterRAS macro 204 sends a global clock stop signal in response to receiving an error detection signal from another macro 205 a-205 n. - As previously discussed,
clock source 232 supplies a clock signal toRAS macro 204 and macros 205 a-n. As illustrated,signal lines 238 a-238 n supply the clock signal to macros 205 a-205 n.Signal line 239 supplies the clock signal toRAS macro 204. - Macros 205 a-205 b illustrate a pair of macros connected to enable one macro (macro 205 b) to stop a neighboring macro (macro 205 a) when the first macro detects an error if the second macro is enabled to receive a “local stop” signal. The “neighbor stop” procedure is accomplished by tying local stop 226 a of
macro 205 a to error_out 222 b ofmacro 205 b via signal line 242 a. For example, ifmacro 205 b encounters a failure signature, check stop logic withinmacro 205 b sends out an error detection signal that not only propagates toRAS macro 204, but is forwarded to macro 205 a via signal line 242 a. If the checkstop logic withinmacro 205 a is enabled to receive a local stop signal, the clocks withinmacro 205 a will be stopped upon receipt of local stop signal 242 a. This “neighbor stop” procedure enables neighboring macros to be stopped before RAS macro 204 sends the global clock stop signal, thus more likely preserving values present withinmacro 205 a at the time of the failure.Signal lines 242 a-242 n are included inFIG. 2 , but those with skill in the art will appreciate that not alllocal stop 226 a-226 n need to be coupled to neighboring macros and that it is also possible for a given macro 205 to have a plurality of local stop inputs connected to a number of neighboring macros. -
FIG. 3 is a block diagram depicting an exemplary macro 205 fromFIG. 2 . As illustrated, macro 205 includeslocal clock control 302, checkstop logic 310, andfunctional logic 304. Local clock control is coupled toclock source 232 viasignal line 238 and distributes the clock signal tofunctional logic 304.Function logic 304 includes bothlatches 306 a-306 n andlogic gates 308. WhileFIG. 3 illustrates only three latches within macro 205, those with skill in the art will appreciate that macro 205 may include any number of latches. - During operation of macro 205, there are three ways in which macro 205 may be stopped: (1) upon detection of a failure signature from
signal line 300; (2) upon receiving an error detection signal from a neighboring macro onsignal 226; and (3) upon receiving a global stop signal from RAS macro 204 onsignal 220. When enabled, checkstop logic 310 monitors signalline 300 for failure signatures (e.g., illegal values) generated byfunctional logic 304. Oncecheck stop logic 310 detects a failure signature, checkstop logic 310 sends an error detection signal tolocal clock control 302, which stops operation of macro 205. - Macros within
integrated circuit 200 may be coupled so that if one macro sends out an error detection signal, that signal propagates to neighboring macros vialocal stop 226 a-226 n coupled to signalline 242. For example, ifmacro 205 a andmacro 205 b are paired, an error detection signal sent from error_out 222 a inmacro 205 b can stop operations withinmacro 205 a when the error detection signal is received via local stop 226 a. - Also, as previously discussed, after a macro 205 detects a failure signature, check
stop logic 310 sends an error detection signal tolocal clock control 302 and toRAS macro 204 viaerror_out 222. In response to receiving the error detection signal,RAS macro 204 sends out a global stop signal to all macros 205 a-205 n. Upon receipt of the global stop signal onsignal line 234 viaCLK_stop 220, any macros 205 a-205 n still operating will stop. -
FIG. 4 is a more detailed block diagram illustratingcheck stop logic 310 fromFIG. 3 . As depicted, checkstop logic 310 includespattern matcher 402,pattern matching configuration 404, a collection of logic gates (ORgates 412 a-412 b and ANDgates 414 a-414 c), and latches 400 a-400 c.Pattern matching configuration 404 is preferably implemented as a set of latches that instructspattern matcher 402 of the patterns of signals onsignal line 300 that are indicative of a failure signature.Pattern matcher 402 is preferably implemented as a set of logic that monitors signals within macro 205 to detect signals fromsignal line 300 that are indicative of a failure signature. As previously discussed,signal line 300 receives signals fromfunctional logic 304. - AND gate 414 c,
signal line 408, and latch 400 a enable or disable the output ofpattern matcher 402 depending on a current setting of latch 400 a. For example, a circuit tester may not be interested in whether or not a current macro encounters any signals indicated of a failure signature. To disable the output ofpattern matcher 402, latch 400 a may be scanned with a value of “0” at system startup. - AND
gates 414 a-414 b, latches 400 b-400 c andsignal lines 242 a-242 b enable or disable error detection signals from neighboring macros. For example, if a circuit tester requires that an error detection signal frommacro 205 b be sent to not onlyRAS macro 204, but macro 205 a as well, the error detection signal frommacro 205 b would propagate to macro 205 a via a signal line, such assignal lines 242 a-242 b. Latches 400 b-400 c would be scanned with a value of “1” to enable the error detection signal to propagate from ANDgates 414 a-414 b to OR gate 412 a. - OR gate 412 a combines the error detection signals from AND
gates 414 a-414 b sent from neighboring macros. ORgate 412 b further combines the signal from OR gate 412 a with the signal from AND gate 414 c, which represents the error detection signal frompattern matcher 402. The output of ANDgate 412 b then propagates tosignals RAS macro 204 and to stop the local clocks vialocal clock control 302. - As previously discussed, the logic within
check stop logic 310 enables a circuit tester to enable or disable error detection signals from a current macro and/or neighboring macros. Depending on the configuration of the current macro, stopping operating of the current macro in response to an error detection signal from a neighboring macro is desired. - Those with skill in the art will appreciate that latches 400 a-400 c as well as the latches within
pattern matching configuration 404 are also coupled via an unillustrated scan chain or chains to enable these latches to be initialized during scanning ofintegrated circuit 200, as show in step 501 ofFIG. 5 . In thismanner test equipment 202 may configure which error patterns are detected and which macros, if any, are stopped in response to an error. -
FIG. 5 is a high-level logical flowchart depicting an exemplary method for stopping functional macro clocks to aid in debugging in accordance with a preferred embodiment of the present invention. The process begins atstep 500 and proceeds to step 502, which showsintegrated circuit 200 being initialized by scanning initial values into the latches withinintegrated circuit 200. In this process, latches 400 a-400 c are initialized with values that either enable or disable error detection signals from passing through ANDgates 414 a-414 c incheck stop logic 310. Also, latches withinpattern match configuration 404 are initialized and specify signals patterns that are indicative of a failure signature. The process continues to step 504, which depicts integrated circuit beginning operation. The process then proceeds to step 506, which showscheck stop logic 310 determining if an enabled local stop has been received via an error detection signal vialocal stop 226 andsignal line 242 from a neighboring macro. - If an enabled local stop has not been received, the process continues to step 508, which illustrates
check stop logic 310 determining if pattern matcher 402 has detected a signal indicative of a failure signature. Ifpattern matcher 402 has not detected a signal indicative of a failure signature, the process returns to step 506 and proceeds in an iterative fashion. Ifpattern matcher 402 has detected a signal indicative of a failure signal, the process proceeds to step 510. - Returning to step 506, if
check stop logic 310 has received an enabled local stop signal, the process continues to step 510, which illustratescheck stop logic 310 presenting an error detection signal viasignal line 314 tolocal clock control 302 and error out 222 viasignal line 236, which propagates to neighboring macros (if connected and also configured by circuit tester to do so) andRAS macro 204.RAS macro 204, upon receiving the error detection signal, sends a clock stop signal viaCLK_stop 208 to all macros 205 to stop operation of all remaining macros 205 inintegrated circuit 200. - The process continues to step 512, which illustrates
test equipment 202 scanning latches viascan_chain_in 214 when all clocks within all macros 205 have been stopped. The process then ends, as illustrated instep 514. - The present invention includes a system and method for debugging an integrated circuit. According to a preferred embodiment of the present invention, the integrated circuit includes a collection of macros. A reliability and serviceability (RAS) macro controls a clock sources, scans the contents of the collection of macros via scan chains, and stops operations within the macros by sending out a global clock stop signal in response to receiving an error detection signal sent by any of the macros within the integrated circuit.
- Each macro further includes a collection of latches controlled by a local clock control. A pattern matcher monitors data patterns in a current macro. In response to detecting a data pattern indicative of a failure signature within the current macro, a check stop logic sends an error detection signal to the RAS macro and possibly to one or more neighboring macros. The local clock control in the current macro halts operation within the current macro such that the data values that contributed to the data pattern indicated of a failure signature are more likely retained in the collection of latches.
- The RAS macro sends a global clock stop signal to all macros within the integrated circuit in response to receiving the error detection signal. In response to receiving the error detection signal from the current macro, the neighboring macro also halts operation, preferably before receiving the global clock stop signal from the RAS macro.
- Also, it should be understood that at least some aspects of the present invention may be alternatively implemented in a computer-readable medium that stores a program product. Programs defining functions in the present invention can be delivered to a data storage system or a computer system via a variety of signal-bearing media, which include, without limitation, non-writable storage media (e.g., CD-ROM), writable storage media (e.g., floppy diskette, hard disk drive, read/write CD-ROM, optical media), and communication media, such as computer and telephone networks including Ethernet. It should be understood, therefore, in such signal-bearing media, when carrying or encoding computer-readable instructions that direct method functions in the present invention, represent alternative embodiments of the present invention. Further, it is understood that the present invention may be implemented by a system having means in the form of hardware, software, or a combination of software and hardware as described herein or their equivalent.
- While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.
Claims (8)
1. A method for debugging an integrated circuit, wherein said integrated circuit includes a plurality of macros, wherein each macro among said plurality of macros further includes a plurality of latches controlled by a local clock control, said method comprising:
monitoring data patterns in at least one macro among said plurality of macros;
in response to detecting a data pattern indicative of a failure signature within said at least one macro, sending an error detection signal to at least one additional macro among said plurality of macros and to said local clock control;
in response to receiving said error detection signal, halting operation within said at least one macro via said local clock control such that data values contributing to said data pattern indicative of said failure signature are retained in said plurality of latches.
2. The method according to claim 1 , further comprising:
in response to said halting operation within said at least one macro, reading contents of said plurality of latches.
3. The method according to claim 1 , further comprising:
in response to receiving said error detection signal in a master macro, sending out a global stop signal to said plurality of macros.
4. The method according to claim 3 , further comprising:
stopping said at least one additional macro among said plurality of macros with said error detection signal transmitted from said at least one macro instead of waiting for said global stop signal.
5. A system for debugging an integrated circuit, wherein said integrated circuit includes a plurality of macros, wherein each macro among said plurality of macros further includes a plurality of latches controlled by a local clock control, said system comprising:
a pattern matcher for monitoring data patterns in at least one macro among said plurality of macros;
check stop logic for sending an error detection signal to at least one additional macro among said plurality of macros and to said local clock control, in response to detecting a data pattern indicative of a failure signature within said at least one macro;
a local clock control for halting operation within said at least one macro via said local clock control such that data values contributing to said data pattern indicative of said failure signature are retained in said plurality of latches, in response to receiving said error detection signal.
6. The system according to claim 5 , further comprising:
test equipment for reading contents of said plurality of latches, in response to said halting operation within said at least one macro.
7. The system according to claim 5 , further comprising:
a master macro for sending out a global stop signal to said plurality of macros, in response to receiving said error detection signal.
8. The system according to claim 7 , wherein said check stop logic stops said at least one additional macro among said plurality of macros with said error detection signal transmitted from said at least one macro instead of waiting for said global stop signal.
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Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10803007B1 (en) | 2018-09-28 | 2020-10-13 | Amazon Technologies, Inc. | Reconfigurable instruction |
US10896001B1 (en) | 2018-09-27 | 2021-01-19 | Amazon Technologies, Inc. | Notifications in integrated circuits |
US10949321B1 (en) | 2018-11-26 | 2021-03-16 | Amazon Technologies, Inc. | Operational management of a device |
US10956248B1 (en) * | 2018-11-26 | 2021-03-23 | Amazon Technologies, Inc. | Configurable reporting for device conditions |
US11204826B2 (en) * | 2018-09-28 | 2021-12-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory error detection and correction |
US11281967B1 (en) | 2018-12-11 | 2022-03-22 | Amazon Technologies, Inc. | Event-based device performance monitoring |
US11416749B2 (en) | 2018-12-11 | 2022-08-16 | Amazon Technologies, Inc. | Execution synchronization and tracking |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101221261B1 (en) * | 2006-02-15 | 2013-01-11 | 엘지디스플레이 주식회사 | Array substrate for LCD and the fabrication method thereof |
KR101569766B1 (en) | 2009-01-29 | 2015-11-17 | 삼성디스플레이 주식회사 | Thin film transistor array panel and method for manufacturing the same |
CN103135302B (en) * | 2011-12-02 | 2015-06-10 | 上海中航光电子有限公司 | Thin film transistor-liquid crystal display in mode of plane switch control and manufacturing method thereof |
CN103488012B (en) * | 2012-06-08 | 2016-02-17 | 瀚宇彩晶股份有限公司 | The method for making of dot structure, dot structure and active elements array substrates |
CN105336742A (en) * | 2014-07-03 | 2016-02-17 | 上海和辉光电有限公司 | Polycrystalline silicon display substrate and manufacturing method thereof |
CN105355631A (en) * | 2015-10-10 | 2016-02-24 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method therefor, display apparatus and mask plate |
CN111629201B (en) * | 2020-04-30 | 2022-01-11 | 昆山丘钛微电子科技股份有限公司 | Debugging method, device, equipment and medium for camera module |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060282732A1 (en) * | 2005-05-23 | 2006-12-14 | Toshiba America Electronic Components | Multi-test method for using compare MISR |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100483358B1 (en) * | 2001-09-07 | 2005-04-14 | 엘지.필립스 엘시디 주식회사 | method for fabricating a Transflective liquid crystal display device and the same |
KR100853220B1 (en) * | 2002-04-04 | 2008-08-20 | 삼성전자주식회사 | Method for manufacturing thin film transistor array panel for display device |
KR100499371B1 (en) * | 2002-04-17 | 2005-07-04 | 엘지.필립스 엘시디 주식회사 | Thin film transistor array substrate and method of manufacturing the same |
KR100853216B1 (en) * | 2002-06-25 | 2008-08-20 | 삼성전자주식회사 | an etchant for a wiring, a method for manufacturing the wiring, a thin film transistor array panel including the wiring, and a method for manufacturing the same including the method |
US6897925B2 (en) * | 2002-07-31 | 2005-05-24 | Lg.Philips Lcd Co. Ltd. | Transflective liquid crystal display device and method for manufacturing the same |
US6888604B2 (en) * | 2002-08-14 | 2005-05-03 | Samsung Electronics Co., Ltd. | Liquid crystal display |
JP3794393B2 (en) * | 2003-03-13 | 2006-07-05 | セイコーエプソン株式会社 | Liquid crystal display device and electronic device |
JP3900141B2 (en) * | 2003-03-13 | 2007-04-04 | セイコーエプソン株式会社 | Liquid crystal display device and electronic device |
KR101043675B1 (en) * | 2004-06-05 | 2011-06-22 | 엘지디스플레이 주식회사 | Thin Film Transistor Substrate of Transflective Type And Method for Fabricating The Same |
-
2006
- 2006-06-13 TW TW095121086A patent/TWI303487B/en active
- 2006-10-06 JP JP2006274664A patent/JP4463255B2/en active Active
- 2006-10-17 US US11/550,040 patent/US7393728B2/en active Active
- 2006-10-17 US US11/550,036 patent/US20080010621A1/en not_active Abandoned
- 2006-10-30 KR KR1020060105913A patent/KR100830601B1/en active IP Right Grant
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060282732A1 (en) * | 2005-05-23 | 2006-12-14 | Toshiba America Electronic Components | Multi-test method for using compare MISR |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10896001B1 (en) | 2018-09-27 | 2021-01-19 | Amazon Technologies, Inc. | Notifications in integrated circuits |
US10803007B1 (en) | 2018-09-28 | 2020-10-13 | Amazon Technologies, Inc. | Reconfigurable instruction |
US11204826B2 (en) * | 2018-09-28 | 2021-12-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory error detection and correction |
US10949321B1 (en) | 2018-11-26 | 2021-03-16 | Amazon Technologies, Inc. | Operational management of a device |
US10956248B1 (en) * | 2018-11-26 | 2021-03-23 | Amazon Technologies, Inc. | Configurable reporting for device conditions |
US11281967B1 (en) | 2018-12-11 | 2022-03-22 | Amazon Technologies, Inc. | Event-based device performance monitoring |
US11416749B2 (en) | 2018-12-11 | 2022-08-16 | Amazon Technologies, Inc. | Execution synchronization and tracking |
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US7393728B2 (en) | 2008-07-01 |
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