US20070200229A1 - Chip underfill in flip-chip technologies - Google Patents
Chip underfill in flip-chip technologies Download PDFInfo
- Publication number
- US20070200229A1 US20070200229A1 US11/276,380 US27638006A US2007200229A1 US 20070200229 A1 US20070200229 A1 US 20070200229A1 US 27638006 A US27638006 A US 27638006A US 2007200229 A1 US2007200229 A1 US 2007200229A1
- Authority
- US
- United States
- Prior art keywords
- corner
- chip
- underfill
- region
- solder balls
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000005516 engineering process Methods 0.000 title description 4
- 229910000679 solder Inorganic materials 0.000 claims abstract description 68
- 239000000758 substrate Substances 0.000 claims abstract description 49
- 239000000463 material Substances 0.000 claims abstract description 38
- 239000004065 semiconductor Substances 0.000 claims abstract description 32
- 238000000034 method Methods 0.000 claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 230000009477 glass transition Effects 0.000 claims description 3
- 238000005336 cracking Methods 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000930 thermomechanical effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/1401—Structure
- H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/1405—Shape
- H01L2224/14051—Bump connectors having different shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81194—Lateral distribution of the bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/8121—Applying energy for connecting using a reflow oven
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
- H01L2224/81815—Reflow soldering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83194—Lateral distribution of the layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Definitions
- the present invention relates to flip-chip technologies, and more specifically, to flip chip underfill in flip-chip technologies.
- chip solder balls are typically formed on top of a semiconductor chip and then the chip is flipped upside down and bonded to a substrate.
- the present invention provides a semiconductor structure, comprising (a) a substrate; (b) a chip which includes N chip solder balls, wherein N is a positive integer, and wherein the N chip solder balls are in electrical contact with the substrate; (c) a first corner underfill region, a second corner underfill region, a third corner underfill region, and a fourth corner underfill region which are respectively at a first corner, a second corner, a third corner, and a fourth corner of the chip, and which are sandwiched between the chip and the substrate; and (d) a main underfill region sandwiched between the chip and the substrate, wherein the first, second, third, and fourth corner underfill regions, and the main underfill region occupy essentially an entire space between the chip and the substrate, and wherein a corner underfill material of the first, second, third, and fourth corner underfill regions is different from a main underfill material of the main underfill region.
- the present invention provides a semiconductor structure fabrication method, comprising providing a semiconductor structure which includes (a) a substrate, (b) a chip which includes N chip solder balls, wherein N is a positive integer, and wherein the N chip solder balls are in electrical contact with the substrate; after said providing is performed, forming a first corner underfill region, a second corner underfill region, a third corner underfill region, and a fourth corner underfill region which are respectively at a first corner, a second corner, a third corner, and a fourth corner of the chip, and which are sandwiched between the chip and the substrate; and after said forming the first, second, third, and fourth corner underfill regions is performed, forming a main underfill region sandwiched between the chip and the substrate, wherein the first, second, third, and fourth corner underfill regions, and the main underfill region occupy essentially an entire space between the chip and the substrate, and wherein a corner underfill material of the first, second, third, and fourth corner underfill regions is different from a main underfill
- the present invention provides a structure (and a method for forming the same) in which the difference between thermal expansion coefficients of the chip and the substrate does not cause solder ball fatigue or chip cracking.
- FIGS. 1A-1C illustrate a first semiconductor structure, in accordance with embodiments of the present invention.
- FIGS. 1D-1F illustrate modeling data of the strain of some chip solder balls of the semiconductor structure of FIG. 1A , in accordance with embodiments of the present invention.
- FIGS. 2A-2B illustrate a second semiconductor structure, in accordance with embodiments of the present invention.
- FIGS. 3A-3B illustrate a third semiconductor structure, in accordance with embodiments of the present invention.
- FIG. 1A illustrates a top down view of a semiconductor structure 100 , in accordance with embodiments of the present invention.
- FIG. 1B illustrates a cross section view of the semiconductor structure 100 of FIG. 1A along a line 1 B- 1 B.
- the semiconductor structure 100 comprises a laminate substrate 110 , an integrated circuit (chip) 120 , a main underfill region 130 , chip solder balls 140 , and four corner underfill regions 160 a , 160 b , 160 c , and 160 d.
- the semiconductor structure 100 is formed according to the following fabrication process.
- the fabrication process starts with the formation of the chip 120 .
- the chip solder balls 140 are then formed on top of the chip 120 wherein the chip solder balls 140 are electrically connected to devices (not shown) in the chip 120 via chip bond pads (not shown).
- the chip 120 is flipped upside down and bonded to the laminate substrate 110 such that the chip solder balls 140 of the chip 120 are directly and one-to-one bonded with substrate bond pads (not shown) on the laminate substrate 110 .
- the four corner underfill regions 160 a , 160 b , 160 c , and 160 d are formed by dispensing a corner underfill material to the four corner spaces between the chip 120 and the laminate substrate 110 .
- the corner underfill material has a coefficient of thermal-expansion (CTE) in a range of 20-30 ppm/° C., has an elastic modulus (E) in a range of 7-10 Gpa, and has a glass transition temperature (Tg) in a range of 90-110° C.
- the main underfill region 130 is formed by dispensing a main underfill material to the remaining empty spaces between the chip 120 and the laminate substrate 110 .
- the main underfill material has a coefficient of thermal-expansion (CTE) of about 25 ppm/° C., has an elastic modulus (E) of about 9.5 Gpa, and has a glass transition temperature (Tg) of about 94° C.
- CTE coefficient of thermal-expansion
- E elastic modulus
- Tg glass transition temperature
- the laminate substrate 110 comprises substrate solder balls 150 which electrically connect the chip solder balls 140 to a printed wire board (not shown) via the conducting lines (not shown) in the laminate substrate 110 .
- the laminate substrate 110 comprises E679FG-R, a dielectric material made by Hitachi Semiconductor
- the corner underfill material is selected so as to reduce thermo-mechanical strains of the chip solder balls 140 at four corner regions 160 a , 160 b , 160 c , and 160 d.
- the shape of the portions of the four corner underfill regions 160 a , 160 b , 160 c , and 160 d which are sandwiched between the chip 120 and the substrate 110 are approximately a quarter circle since the corner underfill material is dispensed by capillary action in all directions from the four corners.
- the radius of the quarter circle shape is in a range of 0.5 mm-1.0 mm.
- the sizes and shapes of the chip solder balls 140 at the four corner regions of the chip 120 are chosen so as to reinforce the bond between the chip 120 and the laminate substrate 110 by (a) increasing the size of the footprint of the corner solder connection or by (b) placing additional, smaller dummy (non-functional) solder balls 140 at the four corner regions 160 a , 160 b , 160 c , and 160 d . More details are below with reference to FIG. 2 and FIG. 3 .
- FIG. 1C illustrates an exploded view of a corner region 161 of the semiconductor structure 100 of FIG. 1A .
- FIG. 1A only one chip solder ball 140 d is in the corner underfill region 160 d of the semiconductor structure 100 , but it should be understood that there may be multiple chip solder balls 140 in the corner underfill region 160 d as shown in FIG. 1C .
- the chip 120 has only 60 chip solder balls 140 , but it should be understood that the chip 120 can have many more chip solder balls 140 than as shown in FIG. 1A such as shown in FIG. 1C .
- FIG. 1D illustrates a strain distribution plot 171 for 25 chip solder balls 140 in a region 162 of FIG. 1C , for the case in which the main underfill material is used to form both the four corner underfill regions 160 a , 160 b , 160 c , 160 d and the main underfill region 130 . It can be seen in FIG. 1D that, the maximum strain value of 2.16% corresponds to the chip solder ball 140 d ′ in the region 162 of the chip 120 .
- FIG. 2A illustrates a top down view of a semiconductor structure 200 , in accordance with embodiments of the present invention.
- FIG. 2B illustrates a cross section view of the semiconductor structure 200 of FIG. 2A along a line 2 B- 2 B.
- the structure of the semiconductor structure 200 is similar to the structure of the semiconductor structure 100 of FIGS. 1A and 1B , except that chip solder balls 270 at four corner regions of the chip 120 are formed larger in size than the other chip solder balls 140 .
- the chip solder balls 270 can have an “L” shape. As a result, the large chip solder balls 270 reinforce the bond between the chip 120 and the laminate substrate 110 .
- the chip solder balls 270 can have any shape (e.g., triangle, etc.)
- the main underfill material is dispensed to fill the entire empty spaces between the chip 120 and the laminate substrate 110 including the four corner regions of the chip 120 .
- the corner underfill material is used to fill the empty spaces at the four corners of the chip 120 first and then the main underfill material is used to fill the remaining empty spaces between the chip 120 and the laminate substrate 110 .
- the four corner regions of the chip 120 have a lower chip solder ball concentration than the other regions of the chip 120 .
- FIG. 3A illustrates a top down view of a semiconductor structure 300 , in accordance with embodiments of the present invention.
- FIG. 3B illustrates a cross section view of the semiconductor structure 300 of FIG. 3A along a line 3 B- 3 B.
- the structure of the semiconductor structure 300 is similar to the structure of the semiconductor structure 100 of FIGS. 1A and 1B , except that chip solder balls 380 at the four corner regions of the chip 120 are smaller in size than the other chip solder balls 140 . As a result of having a smaller size, more chip solder balls 380 can be formed at the four corner regions of the chip 120 .
- the main underfill material is dispensed to fill the entire empty spaces between the chip 120 and the laminate substrate 110 including the four corner regions of the chip 120 .
- the corner underfill material is used to fill the empty spaces at the four corners of the chip 120 first and then the main underfill material is used to fill the remaining empty spaces between the chip 120 and the laminate substrate 110 .
- the four corner regions of the chip 120 have a higher chip solder ball concentration than the other regions of the chip 120 .
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Abstract
Description
- 1. Technical Field
- The present invention relates to flip-chip technologies, and more specifically, to flip chip underfill in flip-chip technologies.
- 2. Related Art
- In flip-chip technologies, chip solder balls are typically formed on top of a semiconductor chip and then the chip is flipped upside down and bonded to a substrate.
- The difference in thermal expansion coefficients of the chip and the substrate may cause solder ball fatigue or cracking in the chip resulting in chip failure. Therefore, there is a need for a structure (and a method for forming the same) in which the difference between thermal expansion coefficients of the chip and the substrate does not cause solder ball fatigue or chip cracking as in the prior art.
- The present invention provides a semiconductor structure, comprising (a) a substrate; (b) a chip which includes N chip solder balls, wherein N is a positive integer, and wherein the N chip solder balls are in electrical contact with the substrate; (c) a first corner underfill region, a second corner underfill region, a third corner underfill region, and a fourth corner underfill region which are respectively at a first corner, a second corner, a third corner, and a fourth corner of the chip, and which are sandwiched between the chip and the substrate; and (d) a main underfill region sandwiched between the chip and the substrate, wherein the first, second, third, and fourth corner underfill regions, and the main underfill region occupy essentially an entire space between the chip and the substrate, and wherein a corner underfill material of the first, second, third, and fourth corner underfill regions is different from a main underfill material of the main underfill region.
- The present invention provides a semiconductor structure fabrication method, comprising providing a semiconductor structure which includes (a) a substrate, (b) a chip which includes N chip solder balls, wherein N is a positive integer, and wherein the N chip solder balls are in electrical contact with the substrate; after said providing is performed, forming a first corner underfill region, a second corner underfill region, a third corner underfill region, and a fourth corner underfill region which are respectively at a first corner, a second corner, a third corner, and a fourth corner of the chip, and which are sandwiched between the chip and the substrate; and after said forming the first, second, third, and fourth corner underfill regions is performed, forming a main underfill region sandwiched between the chip and the substrate, wherein the first, second, third, and fourth corner underfill regions, and the main underfill region occupy essentially an entire space between the chip and the substrate, and wherein a corner underfill material of the first, second, third, and fourth corner underfill regions is different from a main underfill material of the main underfill region.
- The present invention provides a structure (and a method for forming the same) in which the difference between thermal expansion coefficients of the chip and the substrate does not cause solder ball fatigue or chip cracking.
-
FIGS. 1A-1C illustrate a first semiconductor structure, in accordance with embodiments of the present invention. -
FIGS. 1D-1F illustrate modeling data of the strain of some chip solder balls of the semiconductor structure ofFIG. 1A , in accordance with embodiments of the present invention. -
FIGS. 2A-2B illustrate a second semiconductor structure, in accordance with embodiments of the present invention. -
FIGS. 3A-3B illustrate a third semiconductor structure, in accordance with embodiments of the present invention. -
FIG. 1A illustrates a top down view of asemiconductor structure 100, in accordance with embodiments of the present invention.FIG. 1B illustrates a cross section view of thesemiconductor structure 100 ofFIG. 1A along aline 1B-1B. With reference toFIGS. 1A and 1B , in one embodiment, more specifically, thesemiconductor structure 100 comprises alaminate substrate 110, an integrated circuit (chip) 120, amain underfill region 130,chip solder balls 140, and fourcorner underfill regions - In one embodiment, the
semiconductor structure 100 is formed according to the following fabrication process. Illustratively, the fabrication process starts with the formation of thechip 120. Thechip solder balls 140 are then formed on top of thechip 120 wherein thechip solder balls 140 are electrically connected to devices (not shown) in thechip 120 via chip bond pads (not shown). Next, in one embodiment, thechip 120 is flipped upside down and bonded to thelaminate substrate 110 such that thechip solder balls 140 of thechip 120 are directly and one-to-one bonded with substrate bond pads (not shown) on thelaminate substrate 110. Next, in one embodiment, the fourcorner underfill regions chip 120 and thelaminate substrate 110. In one embodiment, the corner underfill material has a coefficient of thermal-expansion (CTE) in a range of 20-30 ppm/° C., has an elastic modulus (E) in a range of 7-10 Gpa, and has a glass transition temperature (Tg) in a range of 90-110° C. Next, in one embodiment, themain underfill region 130 is formed by dispensing a main underfill material to the remaining empty spaces between thechip 120 and thelaminate substrate 110. In one embodiment, the main underfill material has a coefficient of thermal-expansion (CTE) of about 25 ppm/° C., has an elastic modulus (E) of about 9.5 Gpa, and has a glass transition temperature (Tg) of about 94° C. - In one embodiment, the
laminate substrate 110 comprisessubstrate solder balls 150 which electrically connect thechip solder balls 140 to a printed wire board (not shown) via the conducting lines (not shown) in thelaminate substrate 110. In one embodiment, thelaminate substrate 110 comprises E679FG-R, a dielectric material made by Hitachi Semiconductor In one embodiment, the corner underfill material is selected so as to reduce thermo-mechanical strains of thechip solder balls 140 at fourcorner regions - In one embodiment, the shape of the portions of the four
corner underfill regions chip 120 and thesubstrate 110 are approximately a quarter circle since the corner underfill material is dispensed by capillary action in all directions from the four corners. In one embodiment, the radius of the quarter circle shape is in a range of 0.5 mm-1.0 mm. - In one embodiment, the sizes and shapes of the
chip solder balls 140 at the four corner regions of thechip 120 are chosen so as to reinforce the bond between thechip 120 and thelaminate substrate 110 by (a) increasing the size of the footprint of the corner solder connection or by (b) placing additional, smaller dummy (non-functional)solder balls 140 at the fourcorner regions FIG. 2 andFIG. 3 . -
FIG. 1C illustrates an exploded view of acorner region 161 of thesemiconductor structure 100 ofFIG. 1A . For simplicity, inFIG. 1A , only onechip solder ball 140 d is in thecorner underfill region 160 d of thesemiconductor structure 100, but it should be understood that there may be multiplechip solder balls 140 in thecorner underfill region 160 d as shown inFIG. 1C . For simplicity, inFIG. 1A , thechip 120 has only 60chip solder balls 140, but it should be understood that thechip 120 can have many morechip solder balls 140 than as shown inFIG. 1A such as shown inFIG. 1C . -
FIG. 1D illustrates astrain distribution plot 171 for 25chip solder balls 140 in a region 162 ofFIG. 1C , for the case in which the main underfill material is used to form both the fourcorner underfill regions main underfill region 130. It can be seen inFIG. 1D that, the maximum strain value of 2.16% corresponds to thechip solder ball 140 d′ in the region 162 of thechip 120. -
FIG. 1E illustrates astrain distribution plot 172 for the 25chip solder balls 140 in the region 162 ofFIG. 1C , for the case in which the main underfill material is used to form themain underfill region 130 whereas a first corner underfill material is used to form the fourcorner underfill regions FIG. 1E that, the maximum strain value of 1.56%, corresponding to thechip solder ball 140 d′, is reduced compared with the value 2.16% for the case in which the main underfill material is used to form both the fourcorner underfill regions FIG. 1D ). -
FIG. 1F illustrates astrain distribution plot 172 for 25chip solder 140 in the region 162 ofFIG. 1C , for the case in which the main underfill material is used to form themain underfill region 130 whereas a second corner underfill material is used to form the fourcorner underfill regions FIG. 1F that, the maximum strain value of 1.52%, corresponding to thechip solder ball 140 d′, is reduced compared with the value 2.16% for the case in which the main underfill material is used to form both the fourcorner underfill regions FIG. 1D ). -
FIG. 2A illustrates a top down view of asemiconductor structure 200, in accordance with embodiments of the present invention.FIG. 2B illustrates a cross section view of thesemiconductor structure 200 ofFIG. 2A along aline 2B-2B. In one embodiment, with reference toFIGS. 2A and 2B , the structure of thesemiconductor structure 200 is similar to the structure of thesemiconductor structure 100 ofFIGS. 1A and 1B , except thatchip solder balls 270 at four corner regions of thechip 120 are formed larger in size than the otherchip solder balls 140. In one embodiment, thechip solder balls 270 can have an “L” shape. As a result, the largechip solder balls 270 reinforce the bond between thechip 120 and thelaminate substrate 110. Alternatively, thechip solder balls 270 can have any shape (e.g., triangle, etc.) In one embodiment, for thesemiconductor structure 200, after thechip 120 is bonded to thelaminate substrate 110, the main underfill material is dispensed to fill the entire empty spaces between thechip 120 and thelaminate substrate 110 including the four corner regions of thechip 120. Alternatively, the corner underfill material is used to fill the empty spaces at the four corners of thechip 120 first and then the main underfill material is used to fill the remaining empty spaces between thechip 120 and thelaminate substrate 110. - In one embodiment, the four corner regions of the
chip 120 have a lower chip solder ball concentration than the other regions of thechip 120. -
FIG. 3A illustrates a top down view of asemiconductor structure 300, in accordance with embodiments of the present invention.FIG. 3B illustrates a cross section view of thesemiconductor structure 300 ofFIG. 3A along aline 3B-3B. In one embodiment, with reference toFIGS. 3A and 3B , the structure of thesemiconductor structure 300 is similar to the structure of thesemiconductor structure 100 ofFIGS. 1A and 1B , except thatchip solder balls 380 at the four corner regions of thechip 120 are smaller in size than the otherchip solder balls 140. As a result of having a smaller size, morechip solder balls 380 can be formed at the four corner regions of thechip 120. Therefore, more mechanical support can be achieved and more signals can be transmitted via thechip solder balls 380. In one embodiment, for thesemiconductor structure 300, after thechip 120 is bonded to thelaminate substrate 110, the main underfill material is dispensed to fill the entire empty spaces between thechip 120 and thelaminate substrate 110 including the four corner regions of thechip 120. Alternatively, the corner underfill material is used to fill the empty spaces at the four corners of thechip 120 first and then the main underfill material is used to fill the remaining empty spaces between thechip 120 and thelaminate substrate 110. - In one embodiment, the four corner regions of the
chip 120 have a higher chip solder ball concentration than the other regions of thechip 120. - While particular embodiments of the present invention have been described herein for purposes of illustration, many modifications and changes will become apparent to those skilled in the art. Accordingly, the appended claims are intended to encompass all such modifications and changes as fall within the true spirit and scope of this invention.
Claims (20)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/276,380 US7256503B2 (en) | 2006-02-27 | 2006-02-27 | Chip underfill in flip-chip technologies |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/276,380 US7256503B2 (en) | 2006-02-27 | 2006-02-27 | Chip underfill in flip-chip technologies |
Publications (2)
Publication Number | Publication Date |
---|---|
US7256503B2 US7256503B2 (en) | 2007-08-14 |
US20070200229A1 true US20070200229A1 (en) | 2007-08-30 |
Family
ID=38337158
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/276,380 Active US7256503B2 (en) | 2006-02-27 | 2006-02-27 | Chip underfill in flip-chip technologies |
Country Status (1)
Country | Link |
---|---|
US (1) | US7256503B2 (en) |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090243091A1 (en) * | 2008-03-26 | 2009-10-01 | Oh Han Kim | Mock bump system for flip chip integrated circuits |
US20090243090A1 (en) * | 2008-03-26 | 2009-10-01 | Youngmin Kim | Mock bump system for flip chip integrated circuits |
US20100289191A1 (en) * | 2006-06-15 | 2010-11-18 | Advanced Cardiovascular Systems, Inc. | Methods of fabricating stents with enhanced fracture toughness |
US20110018130A1 (en) * | 2009-07-24 | 2011-01-27 | Murata Manufacturing Co., Ltd. | Semiconductor package and semiconductor package module |
US20110037181A1 (en) * | 2009-08-11 | 2011-02-17 | International Business Machines Corporation | Underfill method and chip package |
US20120113608A1 (en) * | 2006-11-30 | 2012-05-10 | Cisco Technology, Inc. | Method and apparatus for supporting a computer chip on a printed circuit board assembly |
CN103311200A (en) * | 2012-03-06 | 2013-09-18 | 北京君正集成电路股份有限公司 | Chip package |
US9198782B2 (en) | 2006-05-30 | 2015-12-01 | Abbott Cardiovascular Systems Inc. | Manufacturing process for polymeric stents |
US9216238B2 (en) | 2006-04-28 | 2015-12-22 | Abbott Cardiovascular Systems Inc. | Implantable medical device having reduced chance of late inflammatory response |
US9517149B2 (en) | 2004-07-26 | 2016-12-13 | Abbott Cardiovascular Systems Inc. | Biodegradable stent with enhanced fracture toughness |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4274280B2 (en) * | 2005-03-14 | 2009-06-03 | 住友ベークライト株式会社 | Semiconductor device |
US7871919B2 (en) * | 2008-12-29 | 2011-01-18 | International Business Machines Corporation | Structures and methods for improving solder bump connections in semiconductor devices |
US20100295173A1 (en) * | 2009-05-21 | 2010-11-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Composite Underfill and Semiconductor Package |
KR102065648B1 (en) | 2013-08-14 | 2020-01-13 | 삼성전자주식회사 | Semiconductor package |
KR20200097316A (en) * | 2017-12-29 | 2020-08-18 | 후아웨이 테크놀러지 컴퍼니 리미티드 | Electronic package, terminal and electronic package processing method |
CN110676231A (en) * | 2019-08-29 | 2020-01-10 | 江苏长电科技股份有限公司 | FCBGA packaging structure and manufacturing method thereof |
US11171104B2 (en) * | 2019-10-24 | 2021-11-09 | Marvell Asia Pte, Ltd. | IC chip package with dummy solder structure under corner, and related method |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040080043A1 (en) * | 2002-10-25 | 2004-04-29 | Siliconware Precision Industries, Ltd. | Semiconductor device with reinforced under-support structure and method of fabricating the same |
US20050074547A1 (en) * | 2003-05-23 | 2005-04-07 | Paul Morganelli | Method of using pre-applied underfill encapsulant |
US20050146050A1 (en) * | 2003-11-14 | 2005-07-07 | Yu-Wen Chen | Flip chip package structure and chip structure thereof |
US20050170630A1 (en) * | 2004-01-29 | 2005-08-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Methods for reducing flip chip stress |
US20050170188A1 (en) * | 2003-09-03 | 2005-08-04 | General Electric Company | Resin compositions and methods of use thereof |
US20060071337A1 (en) * | 2004-09-28 | 2006-04-06 | Song-Hua Shi | Underfill material to reduce ball limiting metallurgy delamination and cracking potential in semiconductor devices |
US20060163749A1 (en) * | 2005-01-25 | 2006-07-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | IC chip package structure and underfill process |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6570245B1 (en) | 2000-03-09 | 2003-05-27 | Intel Corporation | Stress shield for microelectronic dice |
-
2006
- 2006-02-27 US US11/276,380 patent/US7256503B2/en active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040080043A1 (en) * | 2002-10-25 | 2004-04-29 | Siliconware Precision Industries, Ltd. | Semiconductor device with reinforced under-support structure and method of fabricating the same |
US20050074547A1 (en) * | 2003-05-23 | 2005-04-07 | Paul Morganelli | Method of using pre-applied underfill encapsulant |
US20050170188A1 (en) * | 2003-09-03 | 2005-08-04 | General Electric Company | Resin compositions and methods of use thereof |
US20050146050A1 (en) * | 2003-11-14 | 2005-07-07 | Yu-Wen Chen | Flip chip package structure and chip structure thereof |
US20050170630A1 (en) * | 2004-01-29 | 2005-08-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Methods for reducing flip chip stress |
US20060071337A1 (en) * | 2004-09-28 | 2006-04-06 | Song-Hua Shi | Underfill material to reduce ball limiting metallurgy delamination and cracking potential in semiconductor devices |
US20060163749A1 (en) * | 2005-01-25 | 2006-07-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | IC chip package structure and underfill process |
Cited By (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9517149B2 (en) | 2004-07-26 | 2016-12-13 | Abbott Cardiovascular Systems Inc. | Biodegradable stent with enhanced fracture toughness |
US9216238B2 (en) | 2006-04-28 | 2015-12-22 | Abbott Cardiovascular Systems Inc. | Implantable medical device having reduced chance of late inflammatory response |
US10390979B2 (en) | 2006-05-30 | 2019-08-27 | Advanced Cardiovascular Systems, Inc. | Manufacturing process for polymeric stents |
US9554925B2 (en) | 2006-05-30 | 2017-01-31 | Abbott Cardiovascular Systems Inc. | Biodegradable polymeric stents |
US9198782B2 (en) | 2006-05-30 | 2015-12-01 | Abbott Cardiovascular Systems Inc. | Manufacturing process for polymeric stents |
US8658081B2 (en) * | 2006-06-15 | 2014-02-25 | Advanced Cardiovascular Systems, Inc. | Methods of fabricating stents with enhanced fracture toughness |
US20100289191A1 (en) * | 2006-06-15 | 2010-11-18 | Advanced Cardiovascular Systems, Inc. | Methods of fabricating stents with enhanced fracture toughness |
US9522503B2 (en) | 2006-06-15 | 2016-12-20 | Abbott Cardiovascular Systems Inc. | Methods of treatment with stents with enhanced fracture toughness |
US20120113608A1 (en) * | 2006-11-30 | 2012-05-10 | Cisco Technology, Inc. | Method and apparatus for supporting a computer chip on a printed circuit board assembly |
US8962388B2 (en) * | 2006-11-30 | 2015-02-24 | Cisco Technology, Inc. | Method and apparatus for supporting a computer chip on a printed circuit board assembly |
US8624402B2 (en) | 2008-03-26 | 2014-01-07 | Stats Chippac Ltd | Mock bump system for flip chip integrated circuits |
US8633586B2 (en) | 2008-03-26 | 2014-01-21 | Stats Chippac Ltd. | Mock bump system for flip chip integrated circuits |
US20090243091A1 (en) * | 2008-03-26 | 2009-10-01 | Oh Han Kim | Mock bump system for flip chip integrated circuits |
US20090243090A1 (en) * | 2008-03-26 | 2009-10-01 | Youngmin Kim | Mock bump system for flip chip integrated circuits |
US8378501B2 (en) * | 2009-07-24 | 2013-02-19 | Murata Manufacturing Co., Ltd. | Semiconductor package and semiconductor package module |
US20110018130A1 (en) * | 2009-07-24 | 2011-01-27 | Murata Manufacturing Co., Ltd. | Semiconductor package and semiconductor package module |
US8492910B2 (en) | 2009-08-11 | 2013-07-23 | International Business Machines Corporation | Underfill method and chip package |
US8129230B2 (en) * | 2009-08-11 | 2012-03-06 | International Business Machines Corporation | Underfill method and chip package |
US20110037181A1 (en) * | 2009-08-11 | 2011-02-17 | International Business Machines Corporation | Underfill method and chip package |
CN103311200A (en) * | 2012-03-06 | 2013-09-18 | 北京君正集成电路股份有限公司 | Chip package |
Also Published As
Publication number | Publication date |
---|---|
US7256503B2 (en) | 2007-08-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7256503B2 (en) | Chip underfill in flip-chip technologies | |
TWI653713B (en) | Methods and apparatus for providing an interposer for interconnecting semiconductor chips | |
US20130001797A1 (en) | Package on package using through substrate vias | |
US8884421B2 (en) | Multi-chip package and method of manufacturing the same | |
US7989959B1 (en) | Method of forming stacked-die integrated circuit | |
US20080128916A1 (en) | Semiconductor device including microstrip line and coplanar line | |
US20070278657A1 (en) | Chip stack, method of fabrication thereof, and semiconductor package having the same | |
TW201701432A (en) | Semiconductor package with high routing density patch | |
US20190385996A1 (en) | Semiconductor dice assemblies, packages and systems, and methods of operation | |
US6184570B1 (en) | Integrated circuit dies including thermal stress reducing grooves and microelectronic packages utilizing the same | |
JP2010161102A (en) | Semiconductor device | |
US11658148B2 (en) | Semiconductor package and a method for manufacturing the same | |
KR101047485B1 (en) | Electronic printed circuit board | |
JP2007109790A (en) | Flip-chip semiconductor device | |
US9041180B2 (en) | Semiconductor package and method of manufacturing the semiconductor package | |
CN112420652A (en) | Interconnection substrate with reinforcing layer and warped balance member and semiconductor assembly thereof | |
JP2009152423A (en) | Semiconductor device | |
WO2011021364A1 (en) | Semiconductor device and manufacturing method therefor | |
KR100298829B1 (en) | Structure and Method of Solder Joint for Chip Size Package | |
US8618673B2 (en) | Package structures | |
US20220415777A1 (en) | Semiconductor package | |
CN102655132B (en) | Semiconductor structure and method for fabricating the same | |
US20070209835A1 (en) | Semiconductor device having pad structure capable of reducing failures in mounting process | |
TWI735034B (en) | Interconnect substrate with stiffener and warp balancer and semiconductor assembly using the same | |
US20220285299A1 (en) | Via structure for semiconductor dies |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:DAUBENSPECK, TIMOTHT H.;GAMBINO, JEFFREY P.;MUZZY, CHRISTOPHER D.;AND OTHERS;REEL/FRAME:017221/0489;SIGNING DATES FROM 20060223 TO 20060227 |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. 2 LLC, NEW YORK Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:036550/0001 Effective date: 20150629 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GLOBALFOUNDRIES U.S. 2 LLC;GLOBALFOUNDRIES U.S. INC.;REEL/FRAME:036779/0001 Effective date: 20150910 |
|
AS | Assignment |
Owner name: WILMINGTON TRUST, NATIONAL ASSOCIATION, DELAWARE Free format text: SECURITY AGREEMENT;ASSIGNOR:GLOBALFOUNDRIES INC.;REEL/FRAME:049490/0001 Effective date: 20181127 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 12 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. INC., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GLOBALFOUNDRIES INC.;REEL/FRAME:050122/0001 Effective date: 20190821 |
|
AS | Assignment |
Owner name: MARVELL INTERNATIONAL LTD., BERMUDA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GLOBALFOUNDRIES U.S. INC.;REEL/FRAME:051070/0625 Effective date: 20191105 |
|
AS | Assignment |
Owner name: CAVIUM INTERNATIONAL, CAYMAN ISLANDS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MARVELL INTERNATIONAL LTD.;REEL/FRAME:052918/0001 Effective date: 20191231 |
|
AS | Assignment |
Owner name: MARVELL ASIA PTE, LTD., SINGAPORE Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CAVIUM INTERNATIONAL;REEL/FRAME:053475/0001 Effective date: 20191231 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WILMINGTON TRUST, NATIONAL ASSOCIATION;REEL/FRAME:054636/0001 Effective date: 20201117 |