US20070194342A1 - GaN SEMICONDUCTOR DEVICE AND PROCESS EMPLOYING GaN ON THIN SAPHIRE LAYER ON POLYCRYSTALLINE SILICON CARBIDE - Google Patents

GaN SEMICONDUCTOR DEVICE AND PROCESS EMPLOYING GaN ON THIN SAPHIRE LAYER ON POLYCRYSTALLINE SILICON CARBIDE Download PDF

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Publication number
US20070194342A1
US20070194342A1 US11/622,162 US62216207A US2007194342A1 US 20070194342 A1 US20070194342 A1 US 20070194342A1 US 62216207 A US62216207 A US 62216207A US 2007194342 A1 US2007194342 A1 US 2007194342A1
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layer
gan
sapphire
atop
substrate
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US11/622,162
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Daniel Kinzer
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Infineon Technologies Americas Corp
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International Rectifier Corp USA
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Priority to US11/622,162 priority Critical patent/US20070194342A1/en
Priority to FR0700243A priority patent/FR2896090B1/en
Priority to JP2007004563A priority patent/JP2007243155A/en
Assigned to INTERNATIONAL RECTIFIER CORP. reassignment INTERNATIONAL RECTIFIER CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KINZER, DANIEL M.
Publication of US20070194342A1 publication Critical patent/US20070194342A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02378—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7781—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with inverted single heterostructure, i.e. with active layer formed on top of wide bandgap layer, e.g. IHEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds

Definitions

  • This invention relates to semiconductor devices and more specifically relates to a novel structure and process for the manufacture of semiconductor devices.
  • GaN based semiconductor devices In order to manufacture effective GaN based semiconductor devices, a relatively thick GaN layer, for example, 6 microns, is needed. However, thick GaN layers are difficult to produce economically.
  • Silicon is a desirable and economical substrate for such devices.
  • it is difficult to grow thick layers or films of GaN type material on a silicon substrate because of thermal and lattice mismatch.
  • it is difficult to obtain a high blocking voltage through the film due to defects and the relatively high conductivity through the silicon substrate.
  • the thermal properties of silicon substrates are not optimal, silicon having a medium thermal resistance.
  • GaN or Al GaN on sapphire substrates have somewhat better crystal properties, but have severe thermal limitations.
  • SiC monocrystalline silicon carbide
  • Polycrystalline SiC as a substrate is inexpensive and has good thermal characteristics but it is highly conductive and cannot be used as a template for high quality GaN growth.
  • Silicon on insulator has been proposed, bonded to silicon carbide to isolate the substrate and provide a template for GaN film growth.
  • SOI Silicon on insulator
  • a thin film or wafer for example, 0.1 to 1.0 micrometers thick, of sapphire is bonded to a polycrystalline SiC substrate.
  • the sapphire layer then provides an excellent substrate for film growth, to form a III-nitride heterjunction device, for example, an AlN, AlGaN and GaN layered film.
  • FIG. 1 shows a cross-section of a polysilicon SiC substrate with a thin sapphire layer bonded thereto.
  • FIG. 2 shows the starting wafer of FIG. 1 with a series of an AlN buffer, an AlGaN layer, and a GaN layer deposited thereon.
  • FIG. 3 shows the wafer of FIG. 2 after the formation of source, drain and gate contacts thereon.
  • a thin (most likely in the range of 0.1-1 um thick) sapphire layer is formed by bonding a sapphire wafer to the SiC wafer.
  • the sapphire wafer has been prepared so that a thin film of sapphire may be cleaved from the bulk of the sapphire to remain atop SiC substrate layer 10 . This can be done with a damage layer 11 in the sapphire wafer, as by implantation or other means, on the plane where the wafer is intended to be cleaved.
  • This serves as a substrate for the growth of a III-nitride heretojunction or GaN based device.
  • a series of layers 20 which may be an AlN transition layer, an AlGaN layer and a relatively thick GaN layer are grown on sapphire layer 11 .
  • the wafer of FIG. 2 may then be conventionally completed with standard metallizing and dicing process as well known.
  • the AlN transition layer 30 , AlGaN layer 31 and GaN layer 32 are more conventionally shown. Any other desired transition layer can be used, of any desired thickness.
  • a conventional 2DEG layer 40 is formed between the AlGaN layer 31 and GaN layer 32 .
  • a contact metal layer is conventionally formed atop the surface of GaN layer 32 and is etched or otherwise separated into segments 50 , 51 and 52 , forming drain, gate and source electrodes, respectively.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

A substrate for a GaN based semiconductor device is formed by a poly SiC substrate having a thin sapphire layer on the top surface thereof Sapphire layer may be 0.1 to 1.0 microns thick. GaN type layers are then grown atop the sapphire layer with a transition layer between them if desired.

Description

    RELATED APPLICATION
  • This application claims the benefit of U.S. Provisional Application No. 60/758,328, filed Jan. 12, 2006, the entire disclosure of which is incorporated by reference herein.
    • FIELD OF THE INVENTION
  • This invention relates to semiconductor devices and more specifically relates to a novel structure and process for the manufacture of semiconductor devices.
    • BACKGROUND OF THE INVENTION
  • In order to manufacture effective GaN based semiconductor devices, a relatively thick GaN layer, for example, 6 microns, is needed. However, thick GaN layers are difficult to produce economically.
  • Silicon is a desirable and economical substrate for such devices. However, it is difficult to grow thick layers or films of GaN type material on a silicon substrate because of thermal and lattice mismatch. Further, it is difficult to obtain a high blocking voltage through the film due to defects and the relatively high conductivity through the silicon substrate. Still further, the thermal properties of silicon substrates are not optimal, silicon having a medium thermal resistance.
  • GaN or Al GaN on sapphire substrates have somewhat better crystal properties, but have severe thermal limitations.
  • GaN growth on monocrystalline silicon carbide (SiC) allows growth of thicker GaN film with less lattice mismatch and excellent thermal characteristics but the SiC substrate is expensive and SiC wafers are available in only small diameters.
  • Polycrystalline SiC as a substrate is inexpensive and has good thermal characteristics but it is highly conductive and cannot be used as a template for high quality GaN growth.
  • Silicon on insulator (SOI) has been proposed, bonded to silicon carbide to isolate the substrate and provide a template for GaN film growth. However, this requires two bonding steps and the conductive silicon template has a large lattice mismatch to the GaN film.
    • SUMMARY OF THE INVENTION
  • In accordance with the invention, a thin film or wafer, for example, 0.1 to 1.0 micrometers thick, of sapphire is bonded to a polycrystalline SiC substrate. The sapphire layer then provides an excellent substrate for film growth, to form a III-nitride heterjunction device, for example, an AlN, AlGaN and GaN layered film.
  • This combination provides the following advantages:
      • 1. The polycrystalline SiC substrate is inexpensive.
      • 2. The very thin sapphire layer provides a good template (non-conductive, and close lattice match) for GaN layers.
      • 3. The polycrystalline SiC has a high thermal conductivity.
      • 4. Both sapphire and polycrystalline silicon carbide are available with diameters up to 150 mm.
      • 5. The sapphire layer or wafer can be cleaved in process similar to an SOI process, leaving only a thin film of sapphire on the poly SiC wafer, with the sapphire substrate being used many times to form many wafer templates for initial AlN growth.
    BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 shows a cross-section of a polysilicon SiC substrate with a thin sapphire layer bonded thereto.
  • FIG. 2 shows the starting wafer of FIG. 1 with a series of an AlN buffer, an AlGaN layer, and a GaN layer deposited thereon.
  • FIG. 3 shows the wafer of FIG. 2 after the formation of source, drain and gate contacts thereon.
    • DETAILED DESCRIPTION OF THE DRAWINGS
  • Referring first to FIG. 1, there is shown a polysiliconcarbide substrate 10 of any desired thickness and diameter (or surface area). A thin (most likely in the range of 0.1-1 um thick) sapphire layer is formed by bonding a sapphire wafer to the SiC wafer. The sapphire wafer has been prepared so that a thin film of sapphire may be cleaved from the bulk of the sapphire to remain atop SiC substrate layer 10. This can be done with a damage layer 11 in the sapphire wafer, as by implantation or other means, on the plane where the wafer is intended to be cleaved. This then serves as a substrate for the growth of a III-nitride heretojunction or GaN based device.
  • Thus, as shown in FIG. 2, a series of layers 20, which may be an AlN transition layer, an AlGaN layer and a relatively thick GaN layer are grown on sapphire layer 11.
  • The wafer of FIG. 2 may then be conventionally completed with standard metallizing and dicing process as well known.
  • Thus, as shown in FIG. 3, the AlN transition layer 30, AlGaN layer 31 and GaN layer 32 are more conventionally shown. Any other desired transition layer can be used, of any desired thickness.
  • A conventional 2DEG layer 40 is formed between the AlGaN layer 31 and GaN layer 32.
  • A contact metal layer is conventionally formed atop the surface of GaN layer 32 and is etched or otherwise separated into segments 50, 51 and 52, forming drain, gate and source electrodes, respectively.
  • Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein.

Claims (8)

1. A substrate for a GaN based semiconductor device; said substrate comprising a polycrystalline silicon carbide wafer having parallel top and bottom surfaces of given thickness, and a thin sapphire layer atop said top surface of said polycrystalline silicon carbide substrate; the top surface of said sapphire layer adapted to receive the layers of a GaN based device having a relatively thick GaN layer.
2. The substrate of claim 1, wherein said sapphire layer has a thickness greater than about 0.1 microns.
3. The substrate of claim 1, wherein said sapphire layer has a thickness of between about 0.1 microns and 1.0 microns.
4. A GaN type semiconductor device comprising a poly SiC substrate having an upper flat surface; a thin sapphire layer atop and in contact with said upper flat surface; a transition layer atop the surface of said sapphire layer; an AlGaN layer atop and in contact with said transition layer; a GaN layer atop and in contact with said AlGaN layer and said GaN layer; and spaced source, drain and gate contacts atop aid GaN layer.
5. The device of claim 4, wherein said sapphire layer has a thickness greater than about 0.1 micron.
6. The device of claim 4, wherein said sapphire layer has a thickness of from about 0.1 microns to about 1.0 microns.
7. The process of manufacture of a III-nitride heterojunction device comprising the steps of forming a thin layer of sapphire atop a poly SiC substrate, and thereafter depositing a plurality of nitride-containing layers atop said sapphire to define a 2DEG layer and a thick GaN layer, and thereafter depositing conductive electrodes atop said thick GaN layer.
8. The process of claim 7, wherein said sapphire layer has a thickness which is less than that of said Poly SiC substrate and is greater than about 0.1 micron and less than about 1.0 micron.
US11/622,162 2006-01-12 2007-01-11 GaN SEMICONDUCTOR DEVICE AND PROCESS EMPLOYING GaN ON THIN SAPHIRE LAYER ON POLYCRYSTALLINE SILICON CARBIDE Abandoned US20070194342A1 (en)

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Application Number Priority Date Filing Date Title
US11/622,162 US20070194342A1 (en) 2006-01-12 2007-01-11 GaN SEMICONDUCTOR DEVICE AND PROCESS EMPLOYING GaN ON THIN SAPHIRE LAYER ON POLYCRYSTALLINE SILICON CARBIDE
FR0700243A FR2896090B1 (en) 2006-01-12 2007-01-12 GaN SEMICONDUCTOR DEVICE AND METHOD USING GaN ON A FINE SAPHIR LAYER DEPOSITED ON A POLYCRYSTALLINE SILICON CARBIDE SUBSTRATE
JP2007004563A JP2007243155A (en) 2006-01-12 2007-01-12 Gan semiconductor device, and method of using gan on sapphire thin layer on polycrystalline silicon carbide substrate

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US11/622,162 US20070194342A1 (en) 2006-01-12 2007-01-11 GaN SEMICONDUCTOR DEVICE AND PROCESS EMPLOYING GaN ON THIN SAPHIRE LAYER ON POLYCRYSTALLINE SILICON CARBIDE

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Cited By (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110095335A1 (en) * 2008-07-03 2011-04-28 Panasonic Corporation Nitride semiconductor device
CN104979195A (en) * 2015-07-15 2015-10-14 中国科学院半导体研究所 SiC-based HEMT device manufacturing method
US20170004962A1 (en) * 2013-03-14 2017-01-05 U.S.A. As Represented By The Administrator Of The National Aeronautics And Space Administration Double sided si(ge)/sapphire/iii-nitride hybrid structure
WO2017106788A1 (en) * 2015-12-16 2017-06-22 Ostendo Technologies, Inc. Methods for improving wafer planarity and bonded wafer assemblies made from the methods
WO2019195428A1 (en) * 2018-04-04 2019-10-10 Qorvo Us, Inc. Gallium-nitride-based module with enhanced electrical performance and process for making the same
US10486965B2 (en) 2016-08-12 2019-11-26 Qorvo Us, Inc. Wafer-level package with enhanced performance
US10490471B2 (en) 2017-07-06 2019-11-26 Qorvo Us, Inc. Wafer-level packaging for enhanced performance
US20200235054A1 (en) 2019-01-23 2020-07-23 Qorvo Us, Inc. Rf devices with enhanced performance and methods of forming the same
US10749518B2 (en) 2016-11-18 2020-08-18 Qorvo Us, Inc. Stacked field-effect transistor switch
US10773952B2 (en) 2016-05-20 2020-09-15 Qorvo Us, Inc. Wafer-level package with enhanced performance
US10784149B2 (en) 2016-05-20 2020-09-22 Qorvo Us, Inc. Air-cavity module with enhanced device isolation
US10804246B2 (en) 2018-06-11 2020-10-13 Qorvo Us, Inc. Microelectronics package with vertically stacked dies
US10804179B2 (en) 2016-08-12 2020-10-13 Qorvo Us, Inc. Wafer-level package with enhanced performance
US10964554B2 (en) 2018-10-10 2021-03-30 Qorvo Us, Inc. Wafer-level fan-out package with enhanced performance
US10985033B2 (en) 2016-09-12 2021-04-20 Qorvo Us, Inc. Semiconductor package with reduced parasitic coupling effects and process for making the same
US11069590B2 (en) 2018-10-10 2021-07-20 Qorvo Us, Inc. Wafer-level fan-out package with enhanced performance
US20210296199A1 (en) 2018-11-29 2021-09-23 Qorvo Us, Inc. Thermally enhanced semiconductor package with at least one heat extractor and process for making the same
US11152363B2 (en) 2018-03-28 2021-10-19 Qorvo Us, Inc. Bulk CMOS devices with enhanced performance and methods of forming the same utilizing bulk CMOS process
US20220139862A1 (en) 2019-01-23 2022-05-05 Qorvo Us, Inc. Rf devices with enhanced performance and methods of forming the same
US11387157B2 (en) 2019-01-23 2022-07-12 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US11646289B2 (en) 2019-12-02 2023-05-09 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US11710680B2 (en) 2019-01-23 2023-07-25 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US11923238B2 (en) 2019-12-12 2024-03-05 Qorvo Us, Inc. Method of forming RF devices with enhanced performance including attaching a wafer to a support carrier by a bonding technique without any polymer adhesive
US12009251B2 (en) 2019-04-22 2024-06-11 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same utilizing localized SOI formation

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JP4756418B2 (en) * 2006-02-28 2011-08-24 公立大学法人大阪府立大学 Method for manufacturing single crystal gallium nitride substrate
DE102009047881B4 (en) * 2009-09-30 2022-03-03 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Process for producing an epitaxially produced layer structure

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Cited By (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110095335A1 (en) * 2008-07-03 2011-04-28 Panasonic Corporation Nitride semiconductor device
US20170004962A1 (en) * 2013-03-14 2017-01-05 U.S.A. As Represented By The Administrator Of The National Aeronautics And Space Administration Double sided si(ge)/sapphire/iii-nitride hybrid structure
US9824885B2 (en) * 2013-03-14 2017-11-21 The Unites States of America as represented by the Administrator of NASA Method of fabricating double sided Si(Ge)/Sapphire/III-nitride hybrid structure
CN104979195A (en) * 2015-07-15 2015-10-14 中国科学院半导体研究所 SiC-based HEMT device manufacturing method
WO2017106788A1 (en) * 2015-12-16 2017-06-22 Ostendo Technologies, Inc. Methods for improving wafer planarity and bonded wafer assemblies made from the methods
US9978582B2 (en) 2015-12-16 2018-05-22 Ostendo Technologies, Inc. Methods for improving wafer planarity and bonded wafer assemblies made from the methods
US10882740B2 (en) 2016-05-20 2021-01-05 Qorvo Us, Inc. Wafer-level package with enhanced performance and manufacturing method thereof
US10784149B2 (en) 2016-05-20 2020-09-22 Qorvo Us, Inc. Air-cavity module with enhanced device isolation
US10773952B2 (en) 2016-05-20 2020-09-15 Qorvo Us, Inc. Wafer-level package with enhanced performance
US10486965B2 (en) 2016-08-12 2019-11-26 Qorvo Us, Inc. Wafer-level package with enhanced performance
US10804179B2 (en) 2016-08-12 2020-10-13 Qorvo Us, Inc. Wafer-level package with enhanced performance
US10985033B2 (en) 2016-09-12 2021-04-20 Qorvo Us, Inc. Semiconductor package with reduced parasitic coupling effects and process for making the same
US10749518B2 (en) 2016-11-18 2020-08-18 Qorvo Us, Inc. Stacked field-effect transistor switch
US10490471B2 (en) 2017-07-06 2019-11-26 Qorvo Us, Inc. Wafer-level packaging for enhanced performance
US10755992B2 (en) 2017-07-06 2020-08-25 Qorvo Us, Inc. Wafer-level packaging for enhanced performance
US11152363B2 (en) 2018-03-28 2021-10-19 Qorvo Us, Inc. Bulk CMOS devices with enhanced performance and methods of forming the same utilizing bulk CMOS process
WO2019195428A1 (en) * 2018-04-04 2019-10-10 Qorvo Us, Inc. Gallium-nitride-based module with enhanced electrical performance and process for making the same
US10804246B2 (en) 2018-06-11 2020-10-13 Qorvo Us, Inc. Microelectronics package with vertically stacked dies
US11063021B2 (en) 2018-06-11 2021-07-13 Qorvo Us, Inc. Microelectronics package with vertically stacked dies
US10964554B2 (en) 2018-10-10 2021-03-30 Qorvo Us, Inc. Wafer-level fan-out package with enhanced performance
US11069590B2 (en) 2018-10-10 2021-07-20 Qorvo Us, Inc. Wafer-level fan-out package with enhanced performance
US11942389B2 (en) 2018-11-29 2024-03-26 Qorvo Us, Inc. Thermally enhanced semiconductor package with at least one heat extractor and process for making the same
US20210296199A1 (en) 2018-11-29 2021-09-23 Qorvo Us, Inc. Thermally enhanced semiconductor package with at least one heat extractor and process for making the same
US11646242B2 (en) 2018-11-29 2023-05-09 Qorvo Us, Inc. Thermally enhanced semiconductor package with at least one heat extractor and process for making the same
US11387157B2 (en) 2019-01-23 2022-07-12 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
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