US20070151859A1 - Method of forming copper interconnections in semiconductor devices - Google Patents

Method of forming copper interconnections in semiconductor devices Download PDF

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Publication number
US20070151859A1
US20070151859A1 US11/614,713 US61471306A US2007151859A1 US 20070151859 A1 US20070151859 A1 US 20070151859A1 US 61471306 A US61471306 A US 61471306A US 2007151859 A1 US2007151859 A1 US 2007151859A1
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Prior art keywords
dielectric layer
copper
metal
electroplating
forming
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US11/614,713
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Sang Chul Kim
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DB HiTek Co Ltd
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Dongbu Electronics Co Ltd
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Assigned to DONGBU ELECTRONICS CO., LTD. reassignment DONGBU ELECTRONICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KIM, SANG CHUL
Publication of US20070151859A1 publication Critical patent/US20070151859A1/en
Assigned to WELLS FARGO BANK, NATIONAL ASSOCIATION, AS AGENT reassignment WELLS FARGO BANK, NATIONAL ASSOCIATION, AS AGENT PATENT SECURITY AGREEMENT Assignors: COLLIDER MEDIA, INC., LUCIDMEDIA NETWORKS, INC., VIDEOLOGY MEDIA TECHNOLOGIES, LLC, VIDEOLOGY, INC.
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    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02—Electroplating of selected surface areas
    • C25D5/022—Electroplating of selected surface areas using masking means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating

Definitions

  • Some semiconductor device may have relatively fast response speeds.
  • Semiconductor device may use low dielectric materials (i.e. low-k materials) for a relatively low dielectric constant in materials, which may minimize RC delays.
  • Semiconductor devices may use copper (Cu) with relatively low resistivity in metal interconnections, which may reduce RC delays.
  • via holes and/or trenches may be formed by selectively etching an interlayer dielectric layer (e.g. having a low dielectric layer) to form via holes and/or trenches.
  • via holes and/or trenches may be filled with copper (e.g. through an electroplating process) to form metal interconnections.
  • Electro-chemical plating may be used as an electroplating process to form a copper interconnection.
  • ECP equipment may precipitate a wafer in a water tank including an electrolyte.
  • ECP equipment may apply a voltage to a copper electrode in the water tank and a semiconductor wafer to electroplate copper on the wafer.
  • a copper layer electroplated on a wafer may be formed on the entire surface of the wafer covered with an electrolytic solution.
  • copper may be plated in patterns 5 (e.g. via holes, trenches and similar structures) and over other surfaces of a wafer.
  • current may be concentrated in area A (e.g. a second of a dielectric layer having an elaborate pattern). Concentration of current may result in a hump phenomenon with a relatively large amount of copper being formed in area A.
  • a smaller amount of copper may be deposited in area B, due to current distribution during electroplating. Copper may be electroplated in area B relatively slow, resulting in a relatively broad pattern width.
  • Copper may be formed to have a thickness of about 3000 ⁇ or more in area A during an approximate 10 seconds electroplating duration. Since copper may be plated higher in area A than area B, a step difference in a copper layer may be formed. A step difference in a copper layer may cause complications during planarization of the copper layer. If a step difference is too large, a copper layer in area A may remain higher than a desired height and/or a copper layer in area B may be shorter than a desired height, as illustrated in FIG. 1 b.
  • a step difference of a copper layer may be reduced by excessively depositing a copper layer, which may be accomplished by excessive electroplating.
  • copper may be excessively electroplated to a height of approximately 10000 ⁇ . Excessively electroplating may increase manufacturing costs and/or increase the time of a planarization process.
  • Embodiments relate to a method of forming a copper interconnection.
  • a surface of a wafer may be uniformly planarized after electroplating in a damascene process.
  • Embodiments relate to a method of forming a copper interconnection including at least one of: forming an interlayer dielectric layer over a silicon substrate; forming a plurality of via holes and trench patterns in an interlayer dielectric layer; forming a photoresist pattern over an interlayer dielectric layer between a plurality of via hole and trench patterns; performing an electroplating process on a silicon substrate so that copper may be filled in a plurality of via holes and trench patterns; and planarizing a copper layer so that a photoresist pattern is removed.
  • the thickness of a copper layer formed through an electroplating process is less than approximately 5000 ⁇ .
  • a plurality of via holes and trench patterns may be formed in concentration and non-concentration areas.
  • FIGS. 1 a and 1 b are sectional views illustrating the formation of a copper interconnection.
  • FIGS. 2 a to 2 d are sectional views illustrating methods of forming a copper interconnection, according to embodiments.
  • FIGS. 2 a to 2 d are sectional views illustrating methods of forming a copper interconnection, according to embodiments.
  • dielectric layer 2 may be formed over a semiconductor substrate, in accordance with embodiments.
  • An oxide layer 4 may be formed over dielectric layer 2 .
  • a photo-etching process may be performed on interlayer dielectric layer 2 and/or oxide layer 4 to form patterns 15 .
  • Patterns 15 may include at least one via hole and/or at least one trench and/or a similar structure. Copper may fill patterns 15 to form interconnections.
  • barrier layer 8 may be formed.
  • Barrier 8 may facilitate the deposition of copper during an electroplating process, in accordance with embodiments.
  • barrier 8 may prevent the diffusion of copper.
  • barrier 8 may include TaN.
  • Photoresist material 6 may be formed over unetched areas of interlayer dielectric layer 2 and/or unetched areas of oxide layer 4 . Photoresist material 6 may be formed between patterns 15 (e.g. via holes and/or trenches).
  • an electroplating process may be performed over interlayer dielectric layer 2 , oxide layer 4 , barrier 8 , and/or photoresist material 6 , in accordance with embodiments.
  • electroplating may be performed using electrochemical plating (ECP) equipment. From electroplating, copper layer 21 may be formed.
  • ECP electrochemical plating
  • ECP equipment may include a copper electrode in a water tank, containing an electrolytic solution.
  • a wafer may be electroplated by being precipitated with an electrolytic solution in a water tank.
  • a voltage may be applied to a copper electrode and a wafer such that copper is plated on the wafer through electrolysis.
  • copper may be deposited with a thickness of less than approximately 7000 ⁇ . In embodiments, copper may be deposited with a thickness of less than approximately 5000 ⁇ .
  • a photoresist pattern having low solidity may be formed on areas in which patterns are not formed before electroplating copper.
  • a photoresist pattern may allow for effective planarization of copper, without excessive electroplating of copper, in accordance with embodiments.
  • copper layer 21 is formed relatively high in area A′.
  • Area A′ may include finely formed patterns 15 . Because photoresist pattern 6 is formed at a lower portion of copper layer 21 , planarization may be performed with relative ease, such that the copper layer 21 is prevented from being over etched or under etched, in accordance with embodiments.
  • area B′ since photoresist pattern 6 is not formed in area B′ (in which copper layer 21 may be formed relatively low), area B′ may be planarized to a level substantially the same as area A′.
  • Pattern area A′ may be a concentration area.
  • Pattern area B′ may be a non-concentration area. In embodiments, concentration areas and non-concentration areas may be planarized to substantially the same level.
  • the planarity of a surface of a wafer may be adjusted in a chemical mechanical polishing process.
  • a surface may be uniformly planarized, as illustrated in example FIG. 2 d .
  • excessive deposition of copper layer may not be necessary.
  • manufacturing costs may be reduced.
  • the time required for a planarization process may be reduce, which may increase the efficiency of a manufacturing process.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A method of forming a copper interconnection including at least one of: Forming an interlayer dielectric layer over a silicon substrate. Forming a plurality of via holes and trench patterns in an interlayer dielectric layer; forming a photoresist pattern over an interlayer dielectric layer between a plurality of via hole and trench patterns. Performing an electroplating process on a silicon substrate so that copper may be filled in a plurality of via holes and trench patterns. Planarizing a copper layer so that a photoresist pattern is removed.

Description

  • The present application claims priority under 35 U.S.C. 119 and 35 U.S.C. 365 to Korean Patent Application No. 10-2005-0133479 (filed on Dec. 29, 2005), which is hereby incorporated by reference in its entirety.
    • BACKGROUND
  • Some semiconductor device may have relatively fast response speeds. Semiconductor device may use low dielectric materials (i.e. low-k materials) for a relatively low dielectric constant in materials, which may minimize RC delays. Semiconductor devices may use copper (Cu) with relatively low resistivity in metal interconnections, which may reduce RC delays.
  • Since wet etching copper may be difficult, a damascene process may be used to form copper interconnections. In a damascene process, via holes and/or trenches may be formed by selectively etching an interlayer dielectric layer (e.g. having a low dielectric layer) to form via holes and/or trenches. In a damascene process via holes and/or trenches may be filled with copper (e.g. through an electroplating process) to form metal interconnections.
  • Electro-chemical plating (ECP) may be used as an electroplating process to form a copper interconnection. ECP equipment may precipitate a wafer in a water tank including an electrolyte. ECP equipment may apply a voltage to a copper electrode in the water tank and a semiconductor wafer to electroplate copper on the wafer. A copper layer electroplated on a wafer may be formed on the entire surface of the wafer covered with an electrolytic solution.
  • As illustrated in FIG. 1 a, copper may be plated in patterns 5 (e.g. via holes, trenches and similar structures) and over other surfaces of a wafer. During electroplating, current may be concentrated in area A (e.g. a second of a dielectric layer having an elaborate pattern). Concentration of current may result in a hump phenomenon with a relatively large amount of copper being formed in area A. A smaller amount of copper may be deposited in area B, due to current distribution during electroplating. Copper may be electroplated in area B relatively slow, resulting in a relatively broad pattern width.
  • Copper may be formed to have a thickness of about 3000 Å or more in area A during an approximate 10 seconds electroplating duration. Since copper may be plated higher in area A than area B, a step difference in a copper layer may be formed. A step difference in a copper layer may cause complications during planarization of the copper layer. If a step difference is too large, a copper layer in area A may remain higher than a desired height and/or a copper layer in area B may be shorter than a desired height, as illustrated in FIG. 1 b.
  • A step difference of a copper layer may be reduced by excessively depositing a copper layer, which may be accomplished by excessive electroplating. For example, copper may be excessively electroplated to a height of approximately 10000 Å. Excessively electroplating may increase manufacturing costs and/or increase the time of a planarization process.
    • SUMMARY
  • Embodiments relate to a method of forming a copper interconnection. In embodiments, a surface of a wafer may be uniformly planarized after electroplating in a damascene process.
  • Embodiments relate to a method of forming a copper interconnection including at least one of: forming an interlayer dielectric layer over a silicon substrate; forming a plurality of via holes and trench patterns in an interlayer dielectric layer; forming a photoresist pattern over an interlayer dielectric layer between a plurality of via hole and trench patterns; performing an electroplating process on a silicon substrate so that copper may be filled in a plurality of via holes and trench patterns; and planarizing a copper layer so that a photoresist pattern is removed.
  • In embodiments, the thickness of a copper layer formed through an electroplating process is less than approximately 5000 Å. In embodiments, a plurality of via holes and trench patterns may be formed in concentration and non-concentration areas.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIGS. 1 a and 1 b are sectional views illustrating the formation of a copper interconnection.
  • Example FIGS. 2 a to 2 d are sectional views illustrating methods of forming a copper interconnection, according to embodiments.
    •  DETAILED DESCRIPTION
  • Example FIGS. 2 a to 2 d are sectional views illustrating methods of forming a copper interconnection, according to embodiments. As illustrated in FIG. 2 a, dielectric layer 2 may be formed over a semiconductor substrate, in accordance with embodiments. An oxide layer 4 may be formed over dielectric layer 2. A photo-etching process may be performed on interlayer dielectric layer 2 and/or oxide layer 4 to form patterns 15. Patterns 15 may include at least one via hole and/or at least one trench and/or a similar structure. Copper may fill patterns 15 to form interconnections.
  • After forming patterns 15, barrier layer 8 may be formed. Barrier 8 may facilitate the deposition of copper during an electroplating process, in accordance with embodiments. In embodiments, barrier 8 may prevent the diffusion of copper. In embodiments, barrier 8 may include TaN.
  • As illustrated in FIG. 2 b, a photoresist pattern 6 is formed between the patterns 15, in accordance with embodiments. Photoresist material 6 may be formed over unetched areas of interlayer dielectric layer 2 and/or unetched areas of oxide layer 4. Photoresist material 6 may be formed between patterns 15 (e.g. via holes and/or trenches).
  • As illustrated in FIG. 2 c, an electroplating process may be performed over interlayer dielectric layer 2, oxide layer 4, barrier 8, and/or photoresist material 6, in accordance with embodiments. In embodiments, electroplating may be performed using electrochemical plating (ECP) equipment. From electroplating, copper layer 21 may be formed.
  • ECP equipment may include a copper electrode in a water tank, containing an electrolytic solution. A wafer may be electroplated by being precipitated with an electrolytic solution in a water tank. A voltage may be applied to a copper electrode and a wafer such that copper is plated on the wafer through electrolysis. In embodiments, copper may be deposited with a thickness of less than approximately 7000 Å. In embodiments, copper may be deposited with a thickness of less than approximately 5000 Å.
  • In embodiments, a photoresist pattern having low solidity may be formed on areas in which patterns are not formed before electroplating copper. A photoresist pattern may allow for effective planarization of copper, without excessive electroplating of copper, in accordance with embodiments.
  • In embodiments, copper layer 21 is formed relatively high in area A′. Area A′ may include finely formed patterns 15. Because photoresist pattern 6 is formed at a lower portion of copper layer 21, planarization may be performed with relative ease, such that the copper layer 21 is prevented from being over etched or under etched, in accordance with embodiments. In embodiments, since photoresist pattern 6 is not formed in area B′ (in which copper layer 21 may be formed relatively low), area B′ may be planarized to a level substantially the same as area A′. Pattern area A′ may be a concentration area. Pattern area B′ may be a non-concentration area. In embodiments, concentration areas and non-concentration areas may be planarized to substantially the same level.
  • In embodiments, the planarity of a surface of a wafer may be adjusted in a chemical mechanical polishing process. In embodiments, a surface may be uniformly planarized, as illustrated in example FIG. 2 d. In embodiments, when a copper interconnection is formed, excessive deposition of copper layer may not be necessary. In embodiments, by avoiding excessive copper deposition, manufacturing costs may be reduced. In embodiments, by avoiding excessive copper deposition, the time required for a planarization process may be reduce, which may increase the efficiency of a manufacturing process.
  • It will be apparent to those skilled in the art that various modifications and variations can be made to embodiments. Thus, it is intended that embodiments cover modifications and variations thereof within the scope of the appended claims.

Claims (20)

1. A method comprising:
forming a dielectric layer over a semiconductor substrate;
forming at least one of a via hole and a trench pattern in the dielectric layer;
forming a photoresist pattern over the dielectric layer in areas wherein said at least one of a via hole and a trench pattern are not formed; and
electroplating metal over said photoresist pattern.
2. The method of claim 1, comprising planarizing electroplated metal.
3. The method of claim 2, wherein said planarizing comprises removing the photoresist pattern.
4. The method of claim 1, wherein the method forms a copper interconnection.
5. The method of claim 1, wherein the dielectric layer is an interlayer dielectric layer.
6. The method of claim 1, wherein said electroplating metal is electroplating copper.
7. The method of claim 1, wherein said electroplating metal comprises filling said at least one of a via hole and a trench pattern with metal.
8. The method of claim 1, wherein the dielectric layer comprises a low-k dielectric material.
9. The method of claim 1, wherein said electroplating metal comprises electroplating metal to have a thickness less than approximately 7000 Å.
10. The method of claim 9, wherein said electroplating metal comprises electroplating metal to have a thickness less than approximately 5000 Å.
11. The method of claim 1, wherein said at least one of a via hole and a trench pattern include concentration and non-concentration areas.
12. An apparatus comprising:
a dielectric layer formed over a semiconductor substrate;
at least one of a via hole and a trench pattern formed in the dielectric layer; and
metal electroplated over said photoresist pattern, wherein the metal is electroplated by forming a photoresist pattern formed over the dielectric layer in areas wherein said at least one of a via hole and a trench pattern are not formed.
13. The apparatus of claim 12, wherein the metal is planarized.
14. The apparatus of claim 13, wherein photoresist pattern is removed when the metal is planarized.
15. The apparatus of claim 12, wherein the dielectric layer is an interlayer dielectric layer.
16. The apparatus of claim 12, wherein said metal is copper.
17. The apparatus of claim 12, wherein the dielectric layer comprises a low-k dielectric material.
18. The apparatus of claim 12, wherein the metal is electroplated to have a thickness less than approximately 7000 Å.
19. The apparatus of claim 18, wherein the metal is electroplated to have a thickness less than approximately 5000 Å.
20. The apparatus of claim 12, wherein said at least one of a via hole and a trench pattern include concentration and non-concentration areas.
US11/614,713 2005-12-29 2006-12-21 Method of forming copper interconnections in semiconductor devices Abandoned US20070151859A1 (en)

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Application Number Priority Date Filing Date Title
KR10-2005-0133479 2005-12-29
KR1020050133479A KR100788352B1 (en) 2005-12-29 2005-12-29 Method for Forming Copper Line of Semiconductor

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8517769B1 (en) 2012-03-16 2013-08-27 Globalfoundries Inc. Methods of forming copper-based conductive structures on an integrated circuit device
US8673766B2 (en) 2012-05-21 2014-03-18 Globalfoundries Inc. Methods of forming copper-based conductive structures by forming a copper-based seed layer having an as-deposited thickness profile and thereafter performing an etching process and electroless copper deposition

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6107186A (en) * 1999-01-27 2000-08-22 Advanced Micro Devices, Inc. High planarity high-density in-laid metallization patterns by damascene-CMP processing
US6468895B2 (en) * 2000-04-04 2002-10-22 Nippon Telegraph And Telephone Corporation Pattern forming method
US20030184912A1 (en) * 2002-04-02 2003-10-02 International Business Machines Magnetic head coil structure and method for manufacturing the same

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020051155A (en) * 2000-12-22 2002-06-28 윤종용 Method for manufacturing Cu wiring using electroplating for semiconductor device.

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6107186A (en) * 1999-01-27 2000-08-22 Advanced Micro Devices, Inc. High planarity high-density in-laid metallization patterns by damascene-CMP processing
US6468895B2 (en) * 2000-04-04 2002-10-22 Nippon Telegraph And Telephone Corporation Pattern forming method
US20030184912A1 (en) * 2002-04-02 2003-10-02 International Business Machines Magnetic head coil structure and method for manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8517769B1 (en) 2012-03-16 2013-08-27 Globalfoundries Inc. Methods of forming copper-based conductive structures on an integrated circuit device
US8673766B2 (en) 2012-05-21 2014-03-18 Globalfoundries Inc. Methods of forming copper-based conductive structures by forming a copper-based seed layer having an as-deposited thickness profile and thereafter performing an etching process and electroless copper deposition

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KR20070070673A (en) 2007-07-04
KR100788352B1 (en) 2008-01-02

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