US20070023203A1 - Method and system for customized radio frequency shielding using solder bumps - Google Patents

Method and system for customized radio frequency shielding using solder bumps Download PDF

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Publication number
US20070023203A1
US20070023203A1 US11/189,250 US18925005A US2007023203A1 US 20070023203 A1 US20070023203 A1 US 20070023203A1 US 18925005 A US18925005 A US 18925005A US 2007023203 A1 US2007023203 A1 US 2007023203A1
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Prior art keywords
substrate
radio frequency
ground plane
solder
compartment
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US11/189,250
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Gustavo Leizerovich
Vahid Goudarzi
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Motorola Solutions Inc
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Motorola Inc
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Priority to US11/189,250 priority Critical patent/US20070023203A1/en
Assigned to MOTOROLA, INC. reassignment MOTOROLA, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GOUDARZI, VAHID, LEIZEROVICH, GUSTAVO D.
Publication of US20070023203A1 publication Critical patent/US20070023203A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K9/00—Screening of apparatus or components against electric or magnetic fields
    • H05K9/0007—Casings
    • H05K9/002—Casings with localised screening
    • H05K9/0022—Casings with localised screening of components mounted on printed circuit boards [PCB]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/144—Stacked arrangements of planar printed circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/0929—Conductive planes
    • H05K2201/09354—Ground conductor along edge of main surface
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09972—Partitioned, e.g. portions of a PCB dedicated to different functions; Boundary lines therefore; Portions of a PCB being processed separately or differently
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components

Definitions

  • This invention relates generally to shielding, and more particularly to a method and system for providing a customizable shield using solder balls or bumps.
  • PCB printed circuit board
  • RF radio frequency
  • Another approach is to dispense conductive epoxy to provide electrical connection between the shield and the track on the PCB.
  • This method utilizes cladding by dispensing a smaller amount of solder paste, reflowing the paste, applying a thin film of flux to the shield, placing the fluxed shield on top of the cladded track and reflowing the cladded track and shield together.
  • This methodology demands a series of extra steps and has limitations on the shape of the cavities that can be shielded.
  • the cladding technique requires keep out areas in the corners to accommodate the metal shield radius. None of the techniques discussed above enable shielding of multiple sections of a radio PCB or RF module with the ability to customize the shape of the shield in a space efficient manner.
  • Embodiments in accordance with the present invention can provide a method and system for customizing a radio frequency shield with one or more compartments or cavities in a space efficient manner.
  • a radio frequency (RF) shield arrangement can include a first substrate having a top ground plane, a second substrate having a bottom ground plane, and a plurality of solder bumped areas coupled between the top ground plane and the bottom ground plane forming at least one radio frequency shielded compartment.
  • the radio frequency shield arrangement can include at least one component within the RF shielded compartment.
  • the plurality of solder bumped areas can form a wall for the one or more RF shielded compartments.
  • the first substrate can include a plated through hole or a conductive via electrically coupled to the top ground plane while the second substrate includes a plated through-hole or a conductive via electrically coupled to the bottom ground plane.
  • the second substrate can further include a plurality of ground pads on a surface of the second substrate for mating with the a plurality of solder bumped areas.
  • the plurality of solder bumped areas coupled between the top ground plane and the bottom ground plane can form a multi-compartment RF shield.
  • the plurality of solder bumped areas can be a plurality of polymer-filled solder bumps.
  • the RF shield arrangement can further include at least one package on package (PoP) stacked integrated circuit (IC) stacked between the first substrate and the second substrate such that a plurality of solder bumps and conductive vias within the at least one package on package forms a ground shield wall.
  • PoP package on package
  • IC integrated circuit
  • a multi-compartment radio frequency shield arrangement can include a first substrate having a first ground plane, a second substrate having a second ground plane, and a plurality of solder bumped areas coupled between the first ground plane and the second ground plane forming a plurality of radio frequency shielded compartments.
  • the RF shield arrangement can further include at least one component within each compartment among the plurality of RF shielded compartments.
  • the plurality of solder bumped areas can form a wall for the plurality of radio frequency shielded compartments.
  • the second substrate can further include a plurality of ground pads on a surface of the second substrate for mating with the a plurality of solder bumped areas.
  • the multi-compartment RF shield arrangement can further include at least one package on package stacked integrated circuit stacked between the first substrate and the second substrate such that a plurality of solder bumps and conductive vias within the at least one package on package forms a ground shield wall.
  • the first ground plane can be a top ground plane and the second ground plane can be a bottom ground plane, embodiments herein certainly contemplate ground planes that lie either on top surfaces, bottom surfaces, as well as embedded within surfaces of respective substrates.
  • a method of forming a customized RF shielded compartment or compartments can include the steps of solder bumping a first substrate with a plurality of solder bumps in a pattern matching a shield track, placing at least one component on a second substrate, and applying the first substrate to the second substrate such that the plurality of solder bumps mate with the plurality of ground pads in a pattern matching a shield track.
  • the first substrate has a first ground plane coupled to the plurality of solder bumps and the second substrate has a plurality of ground pads in the pattern matching the shield track and coupled to a second ground plane.
  • the pattern matching the shield track can form a multi-compartment radio frequency shield and the plurality of solder bumps form a wall for the customized radio frequency shielded compartment or compartments.
  • the method can further include the step of reflowing the plurality of solder bumps to form the customized shielded compartment or compartments.
  • the plurality of solder bumps can electrically couple to the first ground plane by a plated through hole or a conductive via in the first substrate coupled to the first ground plane and the plurality of solder bumps can electrically couple to the second ground plane by a plated through-hole or a conductive via in the second substrate coupled to the second ground plane.
  • solder bumps or balls can be used, polymer-filled or resin-filled solder bumps or balls can also be used for the plurality of solder bumps.
  • FIG. 1 is a top view of a bottom side of a first or top substrate having a plurality of solder bumps in accordance with an embodiment of the present invention.
  • FIG. 2 is a top view of a second or bottom substrate having a plurality of solder pads in accordance with an embodiment of the present invention.
  • FIG. 3 is a side view of a RF shield arrangement in accordance with an embodiment of the present invention.
  • FIG. 4 is an expanded view of a portion of the side view of FIG. 3 illustrating the use of the plurality of solder bumps to form the RF shield arrangement.
  • FIG. 5 is a side view of a package on package stacked integrated circuit using the plurality of solder bumps and ground planes to form a shielded cavity in accordance with an embodiment of the present invention.
  • FIG. 6 is a flow chart illustrating a method of forming a customized RF shielded compartment or compartments in accordance with an embodiment of the present invention.
  • Embodiments in accordance with present invention enable the formation of a shield by using a substrate having a metalized surface such as a printed circuit board (PCB) having the top ground plane and solder bumps or balls to create the walls.
  • the shield can be created with similar technology as currently used for ball grid array (BGA) packages.
  • BGA ball grid array
  • the distance between balls can be selected so that the gap between the balls is a very small fraction of the wavelength involved to maintain the electromagnetic shielding integrity.
  • the spacing used in current BGA packages can serve more than adequately for shielding purposes for operating frequencies up to 5 GigaHertz and possibly higher.
  • an RF shielded arrangement 30 having a first or top substrate 12 having a plurality of solder bumps or balls 14 formed in a shield track pattern.
  • the substrate 12 along with the solder bumps 14 form a solder bumped substrate 10 that can be placed on top of a second or bottom substrate 22 having a plurality of solder pads 24 formed in the shield track pattern to mate with the plurality of solder bumps 14 when the first substrate 12 and second substrate 22 are sandwiched together as illustrated in FIG. 3 .
  • the shield track pattern will form three separate cavities or compartments between areas 11 and 21 , areas 13 and 23 , and areas 15 and 25 among the first and second substrates respectively.
  • second or bottom substrate 22 can further include at least one component 26 or a plurality of components 26 placed within each of the areas 21 , 23 , and 25 of the substrate 22 for form a populated printed circuit board 20 .
  • the RF shield arrangement 30 more particularly includes the first substrate 12 having a first or top ground plane 41 , a second substrate 22 having a second or bottom ground plane 42 , and a plurality of solder bumped areas 14 coupled between the top ground plane 41 and the bottom ground plane 42 forming at least one radio frequency shielded compartment.
  • the ground planes shown in FIG. 4 are for illustration purposes and do not necessarily need to be placed on a top surface or a bottom surface of a substrate or even need to be embedded within a substrate.
  • the top and bottom ground planes can be placed on or within the respective substrate so long as they serve to form the RF shielding in accordance with the embodiments herein.
  • the radio frequency shield arrangement can further include at least one component 26 (see FIG. 2 ) within the RF shielded compartment.
  • the plurality of solder bumped areas 14 can form a wall for the one or more RF shielded compartments.
  • the first substrate 12 can include a plated through hole or a conductive via 44 electrically coupled to the top ground plane 41 while the second substrate 22 can include a plated through-hole or a conductive via 47 electrically coupled to the bottom ground plane 42 .
  • the second substrate 22 can further include a plurality of ground pads 24 on a surface of the second substrate 22 for mating with the a plurality of solder bumped areas 14 .
  • the first substrate 12 can also include a plurality of ground pads 45 .
  • the plurality of solder bumped areas 14 coupled between the top ground plane 41 and the bottom ground plane 42 can form a multi-compartment RF shield or arrangement 30 .
  • the plurality of solder bumped areas 14 can be a plurality of polymer-filled solder bumps such as resin-filled solder made by Sekisui Chemical Co., Ltd of Japan. Such resin-filled or polymer-filled solder can provide added height to a shield if needed even after reflow.
  • a RF shield arrangement 50 as illustrated in FIG. 5 can further include at least one package on package (PoP) stacked integrated circuit (IC) stacked between the first substrate 12 and the second substrate 22 such that a plurality of solder bumps 14 and conductive vias ( 54 and 58 ) within the at least one package on package forms a ground shield wall.
  • PoP package on package
  • IC integrated circuit
  • the PoP RF shield arrangement 50 can include the top substrate 12 and bottom substrate 22 with their respective ground planes 41 and 42 and at least one stacked package-on-package which can include a first package substrate 52 having a component such as an integrated circuit (IC) die 51 wirebonded with wires 53 to circuitry on the substrate 52 .
  • IC integrated circuit
  • flip chip technology or other suitable techniques can be used alternatively instead of wirebonding in order to attach IC 51 to the substrates 52 and 56 .
  • the IC die 51 and wirebond wires 53 can be overmolded with glob-top, resin or other insulative material 55 .
  • a second package substrate 56 stacked below the first package substrate 52 also includes an integrated circuit (IC) die 51 wirebonded with wires 53 to circuitry on the substrate 56 all overmolded with glob-top, resin or other insulative material 55 .
  • the arrangement 50 forms a RF shielded cavity using the top ground plane 41 , the bottom ground plane 42 , and shield ground walls 60 formed from solder bumps or balls 14 , conductive vias or through-holes 44 , 54 , 58 , and 47 .
  • RF shield arrangements in accordance with the present invention can use a laminate substrate for a top plane and balls or solder columns to create the side walls to not only provide multi-cavity shielding by forming multiple shielded cavities of arbitrary shapes, but also to shield stacked packages of varying heights based on the number of stacked packages.
  • substrates 52 and 56 can also include ground planes connected to vias 54 and 56 in order to provide shielding between the different ICs ( 51 ) on the respective substrates 52 and 56 .
  • a flow chart illustrating a method 100 of forming a customized RF shielded compartment or compartments can include the step 102 of solder bumping a first substrate with a plurality of solder bumps in a pattern matching (which can include substantially matching) a shield track, placing at least one component on a second substrate at step 104 , and applying the first substrate to the second substrate such that the plurality of solder bumps mate with the plurality of ground pads in a pattern matching a shield track at step 106 .
  • the first substrate has a first ground plane coupled to the plurality of solder bumps and the second substrate has a plurality of ground pads in the pattern matching the shield track and coupled to a second ground plane.
  • the pattern matching the shield track can form a multi-compartment radio frequency shield and the plurality of solder bumps form a wall for the customized radio frequency shielded compartment or compartments.
  • the method 100 can further include the step 110 of reflowing the plurality of solder bumps to form the customized shielded compartment or compartments.
  • the plurality of solder bumps can electrically couple to the first ground plane by a plated through hole or a conductive via in the first substrate coupled to the first ground plane and the plurality of solder bumps can electrically couple to the second ground plane by a plated through-hole or a conductive via in the second substrate coupled to the second ground plane.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

An RF shield arrangement (30) includes a first substrate (12) having a first or top ground plane (41), a second substrate (22) having a second or bottom ground plane (42), and a plurality of solder bumped areas (14) coupled between the top ground plane and the bottom ground plane forming at least one radio frequency shielded compartment. The top and bottom ground planes can be placed on or within the respective substrate so long as they serve to form the RF shielding in accordance with the embodiments herein.

Description

    FIELD OF THE INVENTION
  • This invention relates generally to shielding, and more particularly to a method and system for providing a customizable shield using solder balls or bumps.
    • BACKGROUND OF THE INVENTION
  • The current approach to shielding multiple cavities in subscriber radios uses individual shields for each section. Even though this is a valid approach in terms of shielding effectiveness, such approach unnecessarily uses added printed circuit board (PCB) space since adjacent sections or cavities or shields end up taking two or more shield tracks.
  • Another approach used in radio frequency (RF) modules is to use a single shield with multiple cavities or compartments. To accommodate for co-planarities a large amount of solder paste is dispensed via overprinting. However this method requires clearance around the shield track to allow for over printing and as a result the module size is increased.
  • Another approach is to dispense conductive epoxy to provide electrical connection between the shield and the track on the PCB. There are reliability issues with this method due to poor adhesion. Yet another method utilizes cladding by dispensing a smaller amount of solder paste, reflowing the paste, applying a thin film of flux to the shield, placing the fluxed shield on top of the cladded track and reflowing the cladded track and shield together. This methodology demands a series of extra steps and has limitations on the shape of the cavities that can be shielded. Additionally, the cladding technique requires keep out areas in the corners to accommodate the metal shield radius. None of the techniques discussed above enable shielding of multiple sections of a radio PCB or RF module with the ability to customize the shape of the shield in a space efficient manner.
    • SUMMARY OF THE INVENTION
  • Embodiments in accordance with the present invention can provide a method and system for customizing a radio frequency shield with one or more compartments or cavities in a space efficient manner.
  • In a first embodiment of the present invention, a radio frequency (RF) shield arrangement can include a first substrate having a top ground plane, a second substrate having a bottom ground plane, and a plurality of solder bumped areas coupled between the top ground plane and the bottom ground plane forming at least one radio frequency shielded compartment. The radio frequency shield arrangement can include at least one component within the RF shielded compartment. The plurality of solder bumped areas can form a wall for the one or more RF shielded compartments. The first substrate can include a plated through hole or a conductive via electrically coupled to the top ground plane while the second substrate includes a plated through-hole or a conductive via electrically coupled to the bottom ground plane. The second substrate can further include a plurality of ground pads on a surface of the second substrate for mating with the a plurality of solder bumped areas. Thus, the plurality of solder bumped areas coupled between the top ground plane and the bottom ground plane can form a multi-compartment RF shield. Note, the plurality of solder bumped areas can be a plurality of polymer-filled solder bumps. In a further alternative of the first arrangement, the RF shield arrangement can further include at least one package on package (PoP) stacked integrated circuit (IC) stacked between the first substrate and the second substrate such that a plurality of solder bumps and conductive vias within the at least one package on package forms a ground shield wall.
  • In a second embodiment of the present invention, a multi-compartment radio frequency shield arrangement can include a first substrate having a first ground plane, a second substrate having a second ground plane, and a plurality of solder bumped areas coupled between the first ground plane and the second ground plane forming a plurality of radio frequency shielded compartments. The RF shield arrangement can further include at least one component within each compartment among the plurality of RF shielded compartments. The plurality of solder bumped areas can form a wall for the plurality of radio frequency shielded compartments. The second substrate can further include a plurality of ground pads on a surface of the second substrate for mating with the a plurality of solder bumped areas. The multi-compartment RF shield arrangement can further include at least one package on package stacked integrated circuit stacked between the first substrate and the second substrate such that a plurality of solder bumps and conductive vias within the at least one package on package forms a ground shield wall. Note, although in one embodiment the first ground plane can be a top ground plane and the second ground plane can be a bottom ground plane, embodiments herein certainly contemplate ground planes that lie either on top surfaces, bottom surfaces, as well as embedded within surfaces of respective substrates.
  • In a third embodiment of the present invention, a method of forming a customized RF shielded compartment or compartments can include the steps of solder bumping a first substrate with a plurality of solder bumps in a pattern matching a shield track, placing at least one component on a second substrate, and applying the first substrate to the second substrate such that the plurality of solder bumps mate with the plurality of ground pads in a pattern matching a shield track. Note, the first substrate has a first ground plane coupled to the plurality of solder bumps and the second substrate has a plurality of ground pads in the pattern matching the shield track and coupled to a second ground plane. Further note, the pattern matching the shield track can form a multi-compartment radio frequency shield and the plurality of solder bumps form a wall for the customized radio frequency shielded compartment or compartments. The method can further include the step of reflowing the plurality of solder bumps to form the customized shielded compartment or compartments. The plurality of solder bumps can electrically couple to the first ground plane by a plated through hole or a conductive via in the first substrate coupled to the first ground plane and the plurality of solder bumps can electrically couple to the second ground plane by a plated through-hole or a conductive via in the second substrate coupled to the second ground plane. Although conventional solder bumps or balls can be used, polymer-filled or resin-filled solder bumps or balls can also be used for the plurality of solder bumps.
  • Other embodiments, when configured in accordance with the inventive arrangements disclosed herein, can include a system for performing and a machine readable storage for causing a machine to perform the various processes and methods disclosed herein.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a top view of a bottom side of a first or top substrate having a plurality of solder bumps in accordance with an embodiment of the present invention.
  • FIG. 2 is a top view of a second or bottom substrate having a plurality of solder pads in accordance with an embodiment of the present invention.
  • FIG. 3 is a side view of a RF shield arrangement in accordance with an embodiment of the present invention.
  • FIG. 4 is an expanded view of a portion of the side view of FIG. 3 illustrating the use of the plurality of solder bumps to form the RF shield arrangement.
  • FIG. 5 is a side view of a package on package stacked integrated circuit using the plurality of solder bumps and ground planes to form a shielded cavity in accordance with an embodiment of the present invention.
  • FIG. 6 is a flow chart illustrating a method of forming a customized RF shielded compartment or compartments in accordance with an embodiment of the present invention.
    • DETAILED DESCRIPTION OF THE DRAWINGS
  • While the specification concludes with claims defining the features of embodiments of the invention that are regarded as novel, it is believed that the invention will be better understood from a consideration of the following description in conjunction with the figures, in which like reference numerals are carried forward.
  • Embodiments in accordance with present invention enable the formation of a shield by using a substrate having a metalized surface such as a printed circuit board (PCB) having the top ground plane and solder bumps or balls to create the walls. The shield can be created with similar technology as currently used for ball grid array (BGA) packages. There are no limitations in the type or form of shape of the cavities or compartments, as well as the number of cavities or compartments. The distance between balls can be selected so that the gap between the balls is a very small fraction of the wavelength involved to maintain the electromagnetic shielding integrity. The spacing used in current BGA packages can serve more than adequately for shielding purposes for operating frequencies up to 5 GigaHertz and possibly higher.
  • Referring to FIGS. 1-4, an RF shielded arrangement 30 is illustrated having a first or top substrate 12 having a plurality of solder bumps or balls 14 formed in a shield track pattern. The substrate 12 along with the solder bumps 14 form a solder bumped substrate 10 that can be placed on top of a second or bottom substrate 22 having a plurality of solder pads 24 formed in the shield track pattern to mate with the plurality of solder bumps 14 when the first substrate 12 and second substrate 22 are sandwiched together as illustrated in FIG. 3. In this particular embodiment, the shield track pattern will form three separate cavities or compartments between areas 11 and 21, areas 13 and 23, and areas 15 and 25 among the first and second substrates respectively. Besides the plurality of solder pads 24, second or bottom substrate 22 can further include at least one component 26 or a plurality of components 26 placed within each of the areas 21, 23, and 25 of the substrate 22 for form a populated printed circuit board 20.
  • Referring to the magnified area 40 in FIG. 3 and the expanded or magnified view in FIG. 4 the RF shield arrangement 30 more particularly includes the first substrate 12 having a first or top ground plane 41, a second substrate 22 having a second or bottom ground plane 42, and a plurality of solder bumped areas 14 coupled between the top ground plane 41 and the bottom ground plane 42 forming at least one radio frequency shielded compartment. Note, the ground planes shown in FIG. 4 are for illustration purposes and do not necessarily need to be placed on a top surface or a bottom surface of a substrate or even need to be embedded within a substrate. The top and bottom ground planes can be placed on or within the respective substrate so long as they serve to form the RF shielding in accordance with the embodiments herein.
  • The radio frequency shield arrangement can further include at least one component 26 (see FIG. 2) within the RF shielded compartment. The plurality of solder bumped areas 14 can form a wall for the one or more RF shielded compartments. The first substrate 12 can include a plated through hole or a conductive via 44 electrically coupled to the top ground plane 41 while the second substrate 22 can include a plated through-hole or a conductive via 47 electrically coupled to the bottom ground plane 42. The second substrate 22 can further include a plurality of ground pads 24 on a surface of the second substrate 22 for mating with the a plurality of solder bumped areas 14. The first substrate 12 can also include a plurality of ground pads 45. Thus, the plurality of solder bumped areas 14 coupled between the top ground plane 41 and the bottom ground plane 42 can form a multi-compartment RF shield or arrangement 30. Note, the plurality of solder bumped areas 14 can be a plurality of polymer-filled solder bumps such as resin-filled solder made by Sekisui Chemical Co., Ltd of Japan. Such resin-filled or polymer-filled solder can provide added height to a shield if needed even after reflow.
  • In a further alternative of the first arrangement, a RF shield arrangement 50 as illustrated in FIG. 5 can further include at least one package on package (PoP) stacked integrated circuit (IC) stacked between the first substrate 12 and the second substrate 22 such that a plurality of solder bumps 14 and conductive vias (54 and 58) within the at least one package on package forms a ground shield wall.
  • More specifically, the PoP RF shield arrangement 50 can include the top substrate 12 and bottom substrate 22 with their respective ground planes 41 and 42 and at least one stacked package-on-package which can include a first package substrate 52 having a component such as an integrated circuit (IC) die 51 wirebonded with wires 53 to circuitry on the substrate 52. Note, “flip chip” technology or other suitable techniques can be used alternatively instead of wirebonding in order to attach IC 51 to the substrates 52 and 56. The IC die 51 and wirebond wires 53 can be overmolded with glob-top, resin or other insulative material 55. Likewise, a second package substrate 56 stacked below the first package substrate 52 also includes an integrated circuit (IC) die 51 wirebonded with wires 53 to circuitry on the substrate 56 all overmolded with glob-top, resin or other insulative material 55. The arrangement 50 forms a RF shielded cavity using the top ground plane 41, the bottom ground plane 42, and shield ground walls 60 formed from solder bumps or balls 14, conductive vias or through- holes 44, 54, 58, and 47. Thus, RF shield arrangements in accordance with the present invention can use a laminate substrate for a top plane and balls or solder columns to create the side walls to not only provide multi-cavity shielding by forming multiple shielded cavities of arbitrary shapes, but also to shield stacked packages of varying heights based on the number of stacked packages. Note, although not shown, substrates 52 and 56 can also include ground planes connected to vias 54 and 56 in order to provide shielding between the different ICs (51) on the respective substrates 52 and 56.
  • Referring to FIG. 6, a flow chart illustrating a method 100 of forming a customized RF shielded compartment or compartments can include the step 102 of solder bumping a first substrate with a plurality of solder bumps in a pattern matching (which can include substantially matching) a shield track, placing at least one component on a second substrate at step 104, and applying the first substrate to the second substrate such that the plurality of solder bumps mate with the plurality of ground pads in a pattern matching a shield track at step 106. Note, the first substrate has a first ground plane coupled to the plurality of solder bumps and the second substrate has a plurality of ground pads in the pattern matching the shield track and coupled to a second ground plane. Further note at step 108, the pattern matching the shield track can form a multi-compartment radio frequency shield and the plurality of solder bumps form a wall for the customized radio frequency shielded compartment or compartments. The method 100 can further include the step 110 of reflowing the plurality of solder bumps to form the customized shielded compartment or compartments. The plurality of solder bumps can electrically couple to the first ground plane by a plated through hole or a conductive via in the first substrate coupled to the first ground plane and the plurality of solder bumps can electrically couple to the second ground plane by a plated through-hole or a conductive via in the second substrate coupled to the second ground plane.
  • In light of the foregoing description, it should also be recognized that embodiments in accordance with the present invention can be realized in numerous configurations contemplated to be within the scope and spirit of the claims. For example, although the embodiments shown illustrate a solder bumped top substrate placed on a bottom substrate having matching solder pads, other embodiments within contemplation of the scope of the claims can also include a solder bumped bottom substrate that mates with a top substrate having corresponding solder pads. Additionally, the description above is intended by way of example only and is not intended to limit the present invention in any way, except as set forth in the following claims.

Claims (20)

1. A radio frequency shield arrangement, comprising:
a first substrate having a top ground plane;
a second substrate having a bottom ground plane; and
a plurality of solder bumped areas coupled between the top ground plane and the bottom ground plane forming at least one radio frequency shielded compartment.
2. The radio frequency shield arrangement of claim 1, wherein the plurality of solder bumped areas form a wall for the at least one radio frequency shielded compartment.
3. The radio frequency shield arrangement of claim 1, wherein the first substrate further comprises a plated through hole or a conductive via electrically coupled to the top ground plane.
4. The radio frequency shield arrangement of claim 1, wherein the second substrate further comprises a plated through-hole or a conductive via electrically coupled to the bottom ground plane.
5. The radio frequency shield arrangement of claim 1, wherein the second substrate further comprises a plurality of ground pads on a surface of the second substrate for mating with the plurality of solder bumped areas.
6. The radio frequency shield arrangement of claim 1, wherein the radio frequency shield arrangement further comprises at least one component within the at least one radio frequency shielded compartment.
7. The radio frequency shield arrangement of claim 1, wherein the plurality of solder bumped areas comprises a plurality of polymer-filled solder bumps.
8. The radio frequency shield arrangement of claim 1, wherein the plurality of solder bumped areas coupled between the top ground plane and the bottom ground plane form a multi-compartment radio frequency shield.
9. The radio frequency shield arrangement of claim 1, wherein the radio frequency shield arrangement further comprises at least one package on package stacked integrated circuit stacked between the first substrate and the second substrate such that a plurality of solder bumps and conductive vias within the at least one package on package form a ground shield wall.
10. A multi-compartment radio frequency shield arrangement, comprising:
a first substrate having a first ground plane;
a second substrate having a second ground plane; and
a plurality of solder bumped areas coupled between the first ground plane and the second ground plane forming a plurality of radio frequency shielded compartments.
11. The multi-compartment radio frequency shield arrangement of claim 10, wherein the plurality of solder bumped areas form a wall for the plurality of radio frequency shielded compartments.
12. The multi-compartment radio frequency shield arrangement of claim 10, wherein the second substrate further comprises a plurality of ground pads on a surface of the second substrate for mating with the plurality of solder bumped areas.
13. The multi-compartment radio frequency shield arrangement of claim 10, wherein the radio frequency shield arrangement further comprises at least one component within each compartment among the plurality of radio frequency shielded compartments.
14. The multi-compartment radio frequency shield arrangement of claim 10, wherein the multi-compartment radio frequency shield arrangement further comprises at least one package on package stacked integrated circuit stacked between the first substrate and the second substrate such that a plurality of solder bumps and conductive vias within the at least one package on package form a ground shield wall.
15. A method of forming a customized radio frequency shielded compartment or compartments, comprising the steps of:
solder bumping a first substrate with a plurality of solder bumps in a pattern matching a shield track, wherein the first substrate has a first ground plane coupled to the plurality of solder bumps;
placing at least one component on a second substrate, wherein the second substrate has a plurality of ground pads in the pattern matching the shield track and coupled to a second ground plane; and
applying the first substrate to the second substrate such that the plurality of solder bumps mate with the plurality of ground pads in the pattern matching the shield track.
16. The method of claim 15, wherein the method further comprises the step of reflowing the plurality of solder bumps to form the customized shielded compartment or compartments.
17. The method of claim 15, wherein the plurality of solder bumps form a wall for the customized radio frequency shielded compartment or compartments.
18. The method of claim 15, wherein the plurality of solder bumps electrically couples to the first ground plane by a plated through hole or a conductive via in the first substrate coupled to the first ground plane and the plurality of solder bumps electrically couples to the second ground plane by a plated through-hole or a conductive via in the second substrate coupled to the second ground plane.
19. The method of claim 15, wherein the step of solder bumping the first substrate with the plurality of solder bumps comprises solder bumping with a plurality of polymer-filled solder bumps.
20. The method of claim 15, wherein the pattern matching the shield track forms a multi-compartment radio frequency shield.
US11/189,250 2005-07-26 2005-07-26 Method and system for customized radio frequency shielding using solder bumps Abandoned US20070023203A1 (en)

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Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070170565A1 (en) * 2006-01-25 2007-07-26 Samsung Electronics Co., Ltd. RF module, multi RF module including the RF module, and method of manufacturing the RF module
US20080137315A1 (en) * 2006-12-11 2008-06-12 Shinko Electric Industries Co., Ltd. Electronic component device and method of mounting electronic component
US20080308933A1 (en) * 2007-06-14 2008-12-18 Lionel Chien Hui Tay Integrated circuit package system with different connection structures
US20090290319A1 (en) * 2008-05-20 2009-11-26 Apple Inc. Electromagnetic shielding in small-form-factor device
US20100078771A1 (en) * 2008-09-30 2010-04-01 Hans-Joachim Barth On-Chip RF Shields with Through Substrate Conductors
US20100182765A1 (en) * 2009-01-21 2010-07-22 Delphi Technologies, Inc. Rf/emi shield
US20100224993A1 (en) * 2009-03-04 2010-09-09 Rajasekaran Swaminathan Forming sacrificial composite materials for package-on-package architectures and structures formed thereby
US20110051381A1 (en) * 2009-08-27 2011-03-03 Hitachi Cable, Ltd. Flexible harness and electrical connector cable using same
US8102032B1 (en) * 2008-12-09 2012-01-24 Amkor Technology, Inc. System and method for compartmental shielding of stacked packages
US8178953B2 (en) 2008-09-30 2012-05-15 Infineon Technologies Ag On-chip RF shields with front side redistribution lines
JPWO2011058688A1 (en) * 2009-11-10 2013-03-28 日本電気株式会社 Semiconductor device and noise suppression method
US8536683B2 (en) 2008-09-30 2013-09-17 Infineon Technologies Ag System on a chip with on-chip RF shield
US8889548B2 (en) 2008-09-30 2014-11-18 Infineon Technologies Ag On-chip RF shields with backside redistribution lines
US20150035145A1 (en) * 2013-02-21 2015-02-05 International Business Machines Corporation Millimeter wave wafer level chip scale packaging (wlcsp) device
US9030841B2 (en) 2012-02-23 2015-05-12 Apple Inc. Low profile, space efficient circuit shields
US20170324395A1 (en) * 2015-07-07 2017-11-09 Skyworks Solutions, Inc. Stacked wafer-level packaging devices
US20190043811A1 (en) * 2017-01-30 2019-02-07 Skyworks Solutions, Inc. Signal isolation for module with ball grid array
US10373901B1 (en) * 2018-09-26 2019-08-06 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
CN111199926A (en) * 2019-10-29 2020-05-26 浙江大学 Semiconductor packaging structure with micro-separation cavity
US11239876B2 (en) * 2017-06-02 2022-02-01 Murata Manufacturing Co., Ltd. High-frequency module and communication device
US11792913B2 (en) 2022-10-13 2023-10-17 Google Llc Mitigation of physical impact-induced mechanical stress damage to printed circuit boards

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6137693A (en) * 1998-07-31 2000-10-24 Agilent Technologies Inc. High-frequency electronic package with arbitrarily-shaped interconnects and integral shielding
US6297551B1 (en) * 1999-09-22 2001-10-02 Agere Systems Guardian Corp. Integrated circuit packages with improved EMI characteristics
US6377475B1 (en) * 2001-02-26 2002-04-23 Gore Enterprise Holdings, Inc. Removable electromagnetic interference shield
US6734368B1 (en) * 1997-07-09 2004-05-11 International Business Machines Corporation Metal backed printed circuit board assemblies
US20040240191A1 (en) * 2003-04-15 2004-12-02 Wavezero, Inc. Electromagnetic interference shielding for a printed circuit board

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6734368B1 (en) * 1997-07-09 2004-05-11 International Business Machines Corporation Metal backed printed circuit board assemblies
US6137693A (en) * 1998-07-31 2000-10-24 Agilent Technologies Inc. High-frequency electronic package with arbitrarily-shaped interconnects and integral shielding
US6297551B1 (en) * 1999-09-22 2001-10-02 Agere Systems Guardian Corp. Integrated circuit packages with improved EMI characteristics
US6377475B1 (en) * 2001-02-26 2002-04-23 Gore Enterprise Holdings, Inc. Removable electromagnetic interference shield
US20040240191A1 (en) * 2003-04-15 2004-12-02 Wavezero, Inc. Electromagnetic interference shielding for a printed circuit board

Cited By (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070170565A1 (en) * 2006-01-25 2007-07-26 Samsung Electronics Co., Ltd. RF module, multi RF module including the RF module, and method of manufacturing the RF module
US7675154B2 (en) * 2006-01-25 2010-03-09 Samsung Electronics Co., Ltd. RF module with multi-stack structure
US20080137315A1 (en) * 2006-12-11 2008-06-12 Shinko Electric Industries Co., Ltd. Electronic component device and method of mounting electronic component
US20080308933A1 (en) * 2007-06-14 2008-12-18 Lionel Chien Hui Tay Integrated circuit package system with different connection structures
US20090290319A1 (en) * 2008-05-20 2009-11-26 Apple Inc. Electromagnetic shielding in small-form-factor device
US9390973B2 (en) 2008-09-30 2016-07-12 Infineon Technologies Ag On-chip RF shields with backside redistribution lines
US8889548B2 (en) 2008-09-30 2014-11-18 Infineon Technologies Ag On-chip RF shields with backside redistribution lines
US20100078771A1 (en) * 2008-09-30 2010-04-01 Hans-Joachim Barth On-Chip RF Shields with Through Substrate Conductors
US8748287B2 (en) 2008-09-30 2014-06-10 Infineon Technologies Ag System on a chip with on-chip RF shield
US8617929B2 (en) 2008-09-30 2013-12-31 Infineon Technologies Ag On-Chip RF shields with front side redistribution lines
US8536683B2 (en) 2008-09-30 2013-09-17 Infineon Technologies Ag System on a chip with on-chip RF shield
US8169059B2 (en) * 2008-09-30 2012-05-01 Infineon Technologies Ag On-chip RF shields with through substrate conductors
US8178953B2 (en) 2008-09-30 2012-05-15 Infineon Technologies Ag On-chip RF shields with front side redistribution lines
US8102032B1 (en) * 2008-12-09 2012-01-24 Amkor Technology, Inc. System and method for compartmental shielding of stacked packages
US20100182765A1 (en) * 2009-01-21 2010-07-22 Delphi Technologies, Inc. Rf/emi shield
US20100224993A1 (en) * 2009-03-04 2010-09-09 Rajasekaran Swaminathan Forming sacrificial composite materials for package-on-package architectures and structures formed thereby
US9793233B2 (en) 2009-03-04 2017-10-17 Intel Corporation Forming sacrificial composite materials for package-on-package architectures and structures formed thereby
US9006887B2 (en) * 2009-03-04 2015-04-14 Intel Corporation Forming sacrificial composite materials for package-on-package architectures and structures formed thereby
US9472519B2 (en) 2009-03-04 2016-10-18 Intel Corporation Forming sacrificial composite materials for package-on-package architectures and structures formed thereby
US8541685B2 (en) * 2009-08-27 2013-09-24 Hitachi Cable, Ltd. Flexible harness and electrical connector cable using same
CN102005657A (en) * 2009-08-27 2011-04-06 日立电线株式会社 Flexible harness, electric connecting component, electric/electronic component module and electric connecting method
US20110051381A1 (en) * 2009-08-27 2011-03-03 Hitachi Cable, Ltd. Flexible harness and electrical connector cable using same
JPWO2011058688A1 (en) * 2009-11-10 2013-03-28 日本電気株式会社 Semiconductor device and noise suppression method
US9030841B2 (en) 2012-02-23 2015-05-12 Apple Inc. Low profile, space efficient circuit shields
US9236361B2 (en) * 2013-02-21 2016-01-12 International Business Machines Corporation Millimeter wave wafer level chip scale packaging (WLCSP) device
US9159692B2 (en) 2013-02-21 2015-10-13 International Business Machines Corporation Millimeter wave wafer level chip scale packaging (WLCSP) device and related method
US20150035145A1 (en) * 2013-02-21 2015-02-05 International Business Machines Corporation Millimeter wave wafer level chip scale packaging (wlcsp) device
US20170324395A1 (en) * 2015-07-07 2017-11-09 Skyworks Solutions, Inc. Stacked wafer-level packaging devices
US10396753B2 (en) * 2015-07-07 2019-08-27 Skyworks Solutions, Inc. Stacked wafer-level packaging devices
US20190043811A1 (en) * 2017-01-30 2019-02-07 Skyworks Solutions, Inc. Signal isolation for module with ball grid array
US11233014B2 (en) * 2017-01-30 2022-01-25 Skyworks Solutions, Inc. Packaged module having a ball grid array with grounding shielding pins for electromagnetic isolation, method of manufacturing the same, and wireless device comprising the same
US11239876B2 (en) * 2017-06-02 2022-02-01 Murata Manufacturing Co., Ltd. High-frequency module and communication device
US10373901B1 (en) * 2018-09-26 2019-08-06 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
CN111199926A (en) * 2019-10-29 2020-05-26 浙江大学 Semiconductor packaging structure with micro-separation cavity
US11792913B2 (en) 2022-10-13 2023-10-17 Google Llc Mitigation of physical impact-induced mechanical stress damage to printed circuit boards

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