US20060170062A1 - Self-aligned semiconductor contact structures and methods for fabricating the same - Google Patents
Self-aligned semiconductor contact structures and methods for fabricating the same Download PDFInfo
- Publication number
- US20060170062A1 US20060170062A1 US11/395,270 US39527006A US2006170062A1 US 20060170062 A1 US20060170062 A1 US 20060170062A1 US 39527006 A US39527006 A US 39527006A US 2006170062 A1 US2006170062 A1 US 2006170062A1
- Authority
- US
- United States
- Prior art keywords
- insulation layer
- layer
- forming
- contact window
- gate electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000000034 method Methods 0.000 title claims abstract description 115
- 239000004065 semiconductor Substances 0.000 title claims description 76
- 239000010410 layer Substances 0.000 claims description 418
- 238000009413 insulation Methods 0.000 claims description 177
- 239000000758 substrate Substances 0.000 claims description 76
- 239000011229 interlayer Substances 0.000 claims description 68
- 238000009792 diffusion process Methods 0.000 claims description 57
- 239000012535 impurity Substances 0.000 claims description 56
- 230000002093 peripheral effect Effects 0.000 claims description 48
- 229910021332 silicide Inorganic materials 0.000 claims description 43
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 43
- 125000006850 spacer group Chemical group 0.000 claims description 41
- 238000005530 etching Methods 0.000 claims description 30
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 21
- 229920005591 polysilicon Polymers 0.000 claims description 21
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 21
- 239000004020 conductor Substances 0.000 claims description 18
- 238000005468 ion implantation Methods 0.000 claims description 16
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 15
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims description 9
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 6
- 239000010937 tungsten Substances 0.000 claims description 6
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 6
- 238000011049 filling Methods 0.000 claims description 5
- 238000004891 communication Methods 0.000 claims description 2
- 150000004767 nitrides Chemical class 0.000 description 16
- 238000004519 manufacturing process Methods 0.000 description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 14
- 229910052814 silicon oxide Inorganic materials 0.000 description 14
- 239000000463 material Substances 0.000 description 10
- 238000007796 conventional method Methods 0.000 description 9
- 238000011068 loading method Methods 0.000 description 6
- 239000003870 refractory metal Substances 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000003860 storage Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 238000013459 approach Methods 0.000 description 2
- 238000000429 assembly Methods 0.000 description 2
- 230000000712 assembly Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 125000001475 halogen functional group Chemical group 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- -1 spacer nitride Chemical class 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
- H01L21/823425—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
Definitions
- the present invention relates to semiconductor devices and methods of forming the same and more specifically to lower electrode contact structures over an underlying layer and methods of forming the same.
- Semiconductor device manufacturing typically includes alternately forming conductive layers (or conductive regions) and insulation layers, and electrically connecting upper and lower conductive layers that are otherwise electrically insulated by the insulation layers, using contacts that are formed in predetermined regions of the insulation layer.
- conductive regions between gate electrodes which include source and drain regions, can be electrically connected to a bit line or a storage node.
- an insulation layer is typically formed and then etched through a photolithographic etching process to form a contact window that exposes the drain region. Then, the contact window may be filled with conductive material to form what can be referred to as a “bit line” contact plug.
- the manufacturing process can also include forming a bit line that is electrically connected to the bit line contact plug, then depositing an insulation layer again, and etching the insulation layer to form a contact window that exposes the source region. Then, a storage node contact plug is formed. A storage node can be formed that is electrically contacted to the storage node contact plug.
- the distance between adjacent elements in the semiconductor substrate i.e., the gate electrodes
- the distance between adjacent elements in the semiconductor substrate can be reduced or made more narrow as manufacturing procedures and/or processes accommodate increased density configurations.
- the aspect ratio of the contact window that extends through the insulation layer may increase, such that the contact window may not entirely penetrate the insulation layer during the photolithographic process.
- a gate electrode may be exposed during the contact window etching process, particularly if there is misalignment, thereby potentially causing electrical bridging between the gate electrode and the contact plugs.
- self-aligned contact technologies have been used in order to decrease the aspect ratio of the contact window or hole and to inhibit or prevent the electrical bridge.
- the self-aligned contact technologies typically use a material property between two separate insulating layers to establish a different etch rate with respect to a predetermined etch gas.
- one insulation layer e.g., a silicon nitride layer
- An interlayer insulation layer e.g., a silicon oxide layer having etch selectivity with respect to the one insulation layer can be used.
- the photolithographic process can be performed to selectively etch the interlayer insulation layer, thereby forming a contact window that exposes conductive regions between the gate electrodes.
- conductive materials can be filled in the contact window to form self-aligned contact pads.
- the gate electrode may be protected by the one insulation layer (such as the silicon nitride layer), so that even in the presence of misalignment, the gate electrodes, especially the top thereof, may not be exposed when the interlayer insulation layer (the silicon oxide layer) is etched.
- a silicon nitride capping layer can be formed on the top of the gate electrode and silicon nitride sidewall spacers can be formed on the sidewalls of the gate electrodes.
- silicon nitride sidewall spacers can be formed on the sidewalls of the gate electrodes.
- the silicon nitride capping layer typically increases a height of the stacked layer structure used to form the gate electrode(s).
- the space between neighboring gate electrodes may decrease due to the silicon nitride sidewall spacers. Therefore, during fabrication, the space between neighboring gate electrodes may not fill properly with the interlayer insulating layer, thereby potentially causing void and undesired electrical bridging in the subsequent process.
- the gate-stacked structure is relatively high, ion implantation may be difficult to perform.
- the conductive region i.e., the source and drain regions
- the gate electrode can be surrounded by the silicon nitride layer, such that loading capacitance may increase and the operation speed of the device may decrease.
- a self-aligned silicide layer i.e., salicide
- refractory metal can be formed on top of the gate electrode and on the source/drain regions at both sides thereof.
- the refractory metal and silicon can then be thermally treated to form a silicide layer based on the reaction between the refractory metal and the silicon.
- a top of the gate electrode of the memory device should be protected with an insulating layer, such as a silicon nitride layer, in order to use a conventional self-aligned contact method to form the memory device.
- an insulating layer such as a silicon nitride layer
- the top of the gate should typically be exposed for forming the silicide layer.
- the fabrication process can become increasingly complicated.
- the silicide layer may be formed in order to secure a low resistance.
- the top of the gate may be protected by silicon nitride such that it may be difficult to form a silicide layer.
- the silicide layer can be formed in the source/drain regions, such that the gate sidewall spacers may be formed relatively thick to make the source/drain regions have an increased length.
- the length may depend on the width or thickness of the gate sidewall spacers.
- the sidewall spacers should be formed relatively thin at the cell region in order to inhibit generating voids.
- Embodiments of the present invention are directed to self-aligned contact structures and methods of forming the same. Certain embodiments of the present invention are directed to methods of forming self-aligned contact structures at a cell region and simultaneously forming a silicide layer on top surfaces of a gate electrode at a cell array region and a peripheral region.
- the self-aligned contact structure of the present invention includes gate electrodes with top and side surfaces covered by a thin nitride liner.
- This configuration is in contrast to a conventional structure where the gate electrode can be surrounded by a silicon nitride capping layer and sidewall spacers.
- an aspect ratio of a self-aligned contact window can decrease, a contact resistance can be lowered, and a loading capacitance can be reduced.
- void(s) can be inhibited and/or prevented while an interlayer insulation layer is deposited.
- a self-aligned contact structure of the present invention includes gate electrodes, a first liner layer, a self-aligned contact pad, an interlayer insulation layer and a second liner layer.
- the gate electrodes are disposed on a semiconductor substrate, separated from each other, and interposed with a gate insulation layer therebetween.
- Upper portions of respective gate electrodes may have inclined profiles, such that the width of the upper portions is narrower than the width of the lower portions.
- first and second liner layers are selectively disposed on the semiconductor substrate to surround certain surfaces (typically the first liner layer surrounds a major portion of the target surfaces and the second liner layer surrounds a minor portion of the target surfaces with the gate electrodes having only a small dual liner coverage area to thereby surround all of the exposed upper surfaces) of the gate electrodes.
- the self-aligned contact pad is electrically connected to the exposed semiconductor substrate between selected neighboring gate electrodes, and disposed to contact at least portions of the second liner layer. That is, the self-aligned contact pad is disposed between selected pairs of adjacent sidewalls of neighboring gate electrodes and has a length sufficient to protrude above the top surface of the gate electrodes.
- the interlayer insulation layer is disposed on the first liner layer about certain external portions of respective gate electrodes, and on the second liner layer above the top surface of the gate electrodes about the upper portions of sidewalls of the protruding self-aligned contact pad such that the second liner layer is interposed between the contact pad and the interlayer insulation layer.
- the present invention can further include a buffer insulation layer that is disposed between the second liner layer and at least the upper portion of the self-aligned contact pad.
- the first liner layer and the second liner layer can comprise silicon nitride and the interlayer insulation layer and the buffer insulation layer can comprise silicon oxide.
- the interlayer insulation layer is a silicon oxide layer having good step coverage and the buffer insulation layer may be a silicon oxide layer having poor step coverage.
- Certain embodiments of the present invention are directed toward self-aligned contact structures.
- the structures include: (a) a plurality of spaced apart gate electrodes disposed on a semiconductor substrate with the gate electrodes having opposing first and second sidewalls and top and bottom surfaces, wherein adjacent sidewalls of selected neighboring gate electrodes have respective upper portions that angle toward each other to present a sloped profile; (b) a first liner layer that is disposed on the semiconductor substrate and covers one of the first and second sidewalls, a minor portion of the other sidewall and a major portion of the top surface of the gate electrodes; (c) a plurality of self-aligned contact pads that are separately electrically connected to selected regions of the semiconductor substrate, each self-aligned contact pad having opposing upwardly extending sidewalls, wherein a respective self-aligned contact pad is positioned between the selected neighboring gate electrodes, and have a length sufficient so that the self-aligned contact pads extend a distance above the top surface of the gate electrodes; (d) an
- Certain embodiments include methods of forming a self-aligned contact window configured to hold a self-aligned contact pad therein in communication with a semiconductor substrate.
- the methods include removing a selected portion of an interlayer insulation layer and then an underlying upper portion of adjacent sidewalls of first and second gate electrodes held proximate to each other on a semiconductor substrate to form first and second gate electrodes with sloped sidewalls that angle toward each other and define a portion of the shape of sidewalls of a self-aligned contact window configured to hold a self-aligned contact pad therein.
- the methods can include: (a) forming gate electrodes that are spaced apart from each other on a semiconductor substrate; (b) forming a first liner layer on the semiconductor substrate and the gate electrodes; (c) forming an interlayer insulation layer over the first liner layer; (d) forming a contact window having opposing spaced apart sidewalls and a bottom by selectively etching the interlayer insulation layer with respect to the first liner layer; (e) forming a second liner layer over the interlayer insulation layer and the bottom and sidewalls of the contact window; (f) forming a buffer insulation layer to extend laterally a distance beyond the second liner layer to overhang in the contact window; (g) exposing the semiconductor substrate between adjacent gate electrodes by performing an etch back process to remove the buffer insulation layer and the second and first insulation layers at a bottom portion of the contact window; and (h) filling the contact window with conductive material to thereby substantially and/or entirely fill at least a
- a thin nitride liner may be formed on the gate electrode without forming a gate sidewall spacer nitride layer and a capping nitride layer. Therefore, during the etching of the interlayer insulation layer for forming the self-aligned contact window, a portion of the upper part of the gate electrode is etched, so that the self-aligned contact window have an inclined profile. That is, because a thin nitride liner covers the gate electrodes, the upper part of the gate is continuously attacked to weaken during the etching of the interlayer insulation layer.
- the thin nitride layer on the upper part of the gate electrode is etched, such that the upper part of the gate electrode is exposed and etched.
- the contact window having inclined profile is formed.
- upper part of the gate electrode is narrower than lower part thereof.
- a nitride liner can be additionally formed to protect the exposed upper part of the gate electrode and then an insulation layer having poor step coverage is formed to cause overhang.
- the insulation layer can be formed thin on the bottom of the contact window and thicker on the sidewalls and the upper part of the contact window. Therefore, when etching is performed, the insulation layer and the nitride liner are etched to expose the conductive region because the insulation layer is formed thin on the bottom of the contact window. However, the insulation layer is formed thicker on the sidewalls, such that the nitride liner is not etched.
- inventions are directed toward an integrated circuit (such as a semiconductor) assembly.
- the assembly includes a plurality of gate electrodes disposed on a substrate, the gate electrodes having opposing sidewalls and top and bottom surfaces, wherein portions of selected adjacent sidewalls of neighboring electrodes (i.e., the sidewalls that face each other) angle generally downwardly and inwardly toward each other while the opposing sidewall of each of the selected sidewalls are substantially linear.
- the assembly further includes a plurality of elongate contact windows, a respective one positioned between the selected adjacent sidewalls of neighboring electrodes, wherein the contact window sidewalls comprise an angled profile that correspond to the angled gate electrode sidewall configuration; and a contact pad disposed in each contact window, the contact pad extending generally downwardly and having a length that is greater than the height of the gate electrodes.
- the assembly may also include a gate protection liner layer that extends in the contact window and covers the angled sidewall portion of a respective gate electrode, and a first liner layer that covers the remaining surfaces of the top and opposing sidewalls of the respective gate electrode.
- Other embodiments are directed to semiconductor assemblies that include a conductive contact on a substrate in a recess adjacent to a gate electrode having a gate electrode sidewall and a top surface.
- the sidewall angling inwardly from the top surface to an intermediate portion of the sidewall toward the recess.
- the conductive contact has a height that extends above the top surface of the gate electrode.
- a height of the gate stacked structure and a distance therebetween may be increased, such that voids may be inhibited and/or prevented when the interlayer insulation layer is formed. Moreover, in certain embodiments, even though voids may occur, electrical bridging is inhibited and/or prevented because the nitride liner is formed after the etching of the interlayer insulation layer.
- the gate-stacked structure can have a relatively low height, so that the thickness of the material layer may also be relatively thin. Thus, manufacturing costs may be reduced and throughput may be increased.
- methods of forming the self-aligned contact structure can include the following operations. Gate electrodes are formed on a semiconductor substrate. The gate electrodes can run in parallel and separated from each other. A first liner layer is formed on the semiconductor substrate and on surfaces of the gate electrodes. An interlayer insulation layer is formed on the first liner layer. A contact window is formed by etching selectively the interlayer insulation layer with respect to the first liner layer. A second liner layer is formed on the resultant structure with the contact window and a buffer insulation layer is formed to cause overhang on the second liner layer, thereby forming the buffer insulation layer thin on a bottom of the contact window and thicker toward the sidewalls and upper part of the contact window. An etch back process is performed under the condition without etch selectivity between the buffer insulation layer and the liner layers to expose the semiconductor substrate between the gate electrodes. Conductive material is formed to fill the entire self-aligned contact window.
- a step of removing the buffer insulation layer can be more performed before forming the conductive material. Therefore, an area of the upper part of the conductive material is widened that is filled in the contact structure, thereby increasing misalignment margin in a subsequent process.
- the first liner and the second liner layer may be formed of a silicon nitride layer and the interlayer insulation layer may be formed an oxide layer having good step coverage.
- the buffer insulation layer may be formed of an oxide layer having poor step coverage.
- the interlayer insulation layer may be patterned to form the Contact window
- the upper part of the gate electrodes can be attacked by the etching and the first liner layer thereon can be simultaneously etched.
- the exposed upper part of the gate electrode can be etched to be inclined.
- the liner layers on the upper and intermediate sidewalls of the contact window can be protected by the buffer insulation layer while allowing the liner layers on the bottom of the contact window to be etched.
- the buffer insulation layer may remain on the upper sidewall of the temporary contact window, so that sidewall spacers are formed.
- a sacrificial insulating layer is formed, the sacrificial insulation layer is etched back to expose the gate electrodes; a metal silicide layer is formed on the exposed gate electrodes; and the residual sacrificial insulation layer is removed.
- a capping nitride layer is not formed on top of the gate, such that the gate electrode is easily exposed and a silicide layer can be formed thereon.
- a silicide layer can be easily formed at the peripheral circuit area where a logic circuit is formed and at the cell array region where a memory element is formed.
- certain methods can be carried out to simultaneously form a silicide layer on the upper part of the gate electrode at the cell array region and at the peripheral circuit region.
- Certain embodiments are directed toward methods of forming a self-aligned contact.
- the methods include: (a) forming gate electrodes that are spaced apart from each other with a plurality of the gate electrodes positioned at a cell array region and at least one gate electrode positioned at a peripheral circuit region of the semiconductor substrate, respectively; (b) forming a first liner layer over the semiconductor substrate and surfaces of the gate electrodes; (c) forming a sacrificial insulation layer on the first liner layer in an amount sufficient to cover spaces between the gate electrodes of the cell array region; (d) etching back the sacrificial insulation layer so as to form temporary sidewall spacers on sidewalls of the at least one gate electrode at the peripheral circuit region; (e) forming a metal silicide layer at least on the semiconductor substrate exposed adjacent the temporary sidewall spacers; then (f) removing the sacrificial insulation layer remaining at the cell array region and the temporary sidewall spacers of the peripheral circuit region; (g) forming an interlayer insulation
- the liner layers on the upper and intermediate parts of the contact window are protected by the buffer insulation layer, but the liner layers on the bottom of the contact window are etched.
- the buffer insulation layer remains the upper and intermediate sidewalls of the contact window to form sidewall spacers.
- the following operations may be additionally carried out.
- lightly doped impurity diffusion layers are formed in the semiconductor substrate at both sides of the gate electrodes by performing an ion implantation process.
- heavily doped impurity diffusion layers are formed in the semiconductor substrate at both sides of the temporary sidewall spacers.
- the gate electrodes may be formed of polysilicon.
- the upper parts of the gate electrodes are exposed at the cell region and the peripheral circuit region, and the sacrificial insulation layer of the cell region remains on sidewalls of the gate electrodes and on the semiconductor substrate therebetween. Therefore, the metal silicide layer is formed on the exposed gate electrodes and on the heavily doped impurity diffusion layer.
- the gate electrodes may be formed of polysilicon and tungsten silicide or formed of polysilicon and tungsten that are sequentially stacked.
- the upper parts of gate electrodes are exposed at the cell region and the peripheral circuit region.
- the sacrificial insulation layer of the cell region remains on the sidewalls of the gate electrodes and the semiconductor substrate therebetween.
- the metal silicide layer may be formed only on the semiconductor substrate at both sides of the gate electrodes of the peripheral circuit region, that is, only on the heavily doped impurity diffusion layer.
- the photoresist pattern covering the cell region may be further formed.
- a metal silicide layer may not be formed at the cell region.
- a step of forming a protection liner layer may be further performed in order to protect the metal silicide layer.
- a step of removing the buffer insulation layer may be further performed.
- an area of the upper part of the self-aligned contact pad increases to be capable to improve a margin of the subsequent process.
- the first liner layer, the second liner layer and the shield liner layer are formed of silicon nitride.
- the sacrificial insulation layer and the buffer insulation layer are formed of silicon oxide. More specifically, the interlayer insulation layer is formed of oxide having good step coverage and the buffer insulation layer is formed of oxide having poor step coverage.
- the temporary sidewall spacers which are formed from the sacrificial insulation layer at the peripheral circuit region, can be easily formed relatively thick.
- an individual photolithographic etching process for forming a silicide layer at the cell region and the peripheral circuit region is not required, such that the process is simplified and a silicide layer can be more easily formed.
- semiconductor assemblies with self-aligned contact pads can include a cell array region and a peripheral circuit region on the semiconductor substrate.
- the cell array region can include: (a) first and second gate electrodes disposed on a semiconductor substrate, the first and gate electrodes having opposing first and second sidewalls and top and bottom surfaces, wherein portions of the adjacent sidewalls of the first and second gate electrodes are configured to angle generally downwardly and inwardly toward each other; (b) a contact window positioned between the adjacent sidewalls of the first and second gate electrodes, wherein the contact window sidewalls comprise an angled profile that correspond to the angled gate electrode sidewalls; and (c) a contact pad disposed in the contact window, the contact pad extending generally downwardly and having a length that is greater than the height of the gate electrode.
- the peripheral circuit region is disposed on the semiconductor substrate spaced apart from the cell array region.
- the peripheral circuit region can include: (a) at least one gate electrode; (b) lightly doped impurity diffusion regions in the semiconductor substrate positioned on opposing sides of the at least one gate electrode; and (c) heavily doped impurity diffusion regions in the semiconductor substrate positioned on opposing sides of the at least one gate electrode so that the heavily doped impurity diffusion regions reside a further distance away from the at least one gate electrode and so that the heavily doped impurity diffusion regions abut the lightly doped impurity diffusion regions.
- FIG. 1 is a cross-sectional view schematically showing a self-aligned contact structure in accordance with embodiments of the present invention.
- FIG. 2 is a cross-sectional view schematically showing a self-aligned contact structure and other structures in accordance with other embodiments of the present invention.
- FIGS. 3A through 3I are cross-sectional views showing operations of a method for forming a self-aligned contact structure and/or other intermediate and resultant structures in accordance with embodiments of the present invention.
- FIGS. 4A through 4J are cross-sectional views showing operations of a method for simultaneously forming silicide layers in a cell region and in a peripheral circuit region using methods for forming a self-aligned contact structure and/or other intermediate and resultant structures in accordance with embodiments of the present invention.
- FIGS. 5A through 5B are cross-sectional views showing operations of methods for simultaneously forming a silicide layer in a cell region and in a peripheral region using methods for forming a self-aligned contact structure and/or other structures in accordance with embodiments of the present invention.
- spatially relative terms such as “beneath”, “below”, “lower”, “above”, “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
- the terms “liner layer”, formation of the “liner layer,” or derivatives thereof, mean a layer that has a substantially uniform thickness along an entire target outline of a lower and/or underlying structure or a formation of the same.
- the liner layer may be configured to be substantially conformal to an underlying material layer or structure so as to provide substantially the same shaped profile as the underlying structure.
- FIG. 1 shows a cross-sectional view of a self-aligned contact structure in accordance with an exemplary embodiment of the present invention.
- Gate electrodes 160 can be configured to run substantially parallel with, but separated apart from, each other on a semiconductor substrate 100 .
- Each of the gate electrodes 160 may comprise a polysilicon single-layered structure, a double-layered structure of polysilicon and tungsten silicide, and/or polysilicon and tungsten.
- a metal silicide layer may be formed on the polysilicon layer.
- a gate oxide layer 140 can be interposed between the gate electrodes 160 and the semiconductor substrate 100 .
- Impurity diffusion regions (i.e., conductive regions) 180 can be formed in the semiconductor substrate 100 .
- the conductive regions 180 may be formed at both sides of the gate electrodes 160 as shown.
- An interlayer insulation and/or dielectric layer 220 can be disposed on the semiconductor substrate 100 .
- a self-aligned contact window 240 can be configured to penetrate the interlayer insulation layer 220 to expose the impurity diffusion region 180 between the gate electrodes 160 .
- the self-aligned contact window 240 can be configured to expose both the top of the gate electrode 160 and the impurity diffusion regions 180 , respectively.
- the self-aligned contact window 240 can be positioned intermediate adjacent gate electrodes 160 and configured with longitudinally extending opposing sidewalls that may extend to contact and/or terminate at the diffusion region 180 .
- the sidewalls of the self-aligned contact window 240 can be defined by the interlayer insulation layer 220 and adjacent sides of neighboring gate electrodes 160 .
- the bottom of the contact window 240 can end at and/or be formed by the impurity diffusion region 180 .
- the self-aligned contact window 240 includes a channel that has downwardly extending sidewalls that can be formed by the stacked configuration of the interlayer insulation layer 220 , sidewalls of neighboring gate electrodes 160 , the liner layer 200 formed over a lower portion of the gate electrode 160 sidewalls that terminate into a bottom formed by the impurity diffusion region 180 .
- an upper sidewall 240 a of the self-aligned contact window 240 may be defined by an etched out portion of the interlayer insulation layer 220 .
- An intermediate sidewall 240 b of the self-aligned contact window 240 may be defined by an intermediate portion of the sidewall of a gate electrode 160 .
- a lower sidewall 240 c of the self-aligned contact window 240 can be defined by a liner layer 200 disposed on the lower sidewall of the gate electrode 160 .
- a bottom 240 d of the self-aligned contact window 240 can be defined by the impurity diffusion region 180 .
- the self-aligned contact window 240 exposes the upper portion of the gate electrode 160 .
- the intermediate portion of the sidewall 240 b of the contact window 240 can be defined by etching the innermost perimeter and/or boundary of the upper portion of adjacent gate electrodes 160 , such that a profile of the contact window 240 may be inclined. That is, the upper portion of the gate electrode 160 and the corresponding intermediate portion of the contact window sidewall 240 b have a profile with a slope that travels inwardly to narrow as the self-aligned contact window 240 approaches the impurity diffusion region 180 and widens as the contact window 240 approaches the upper portion of the gate electrodes 160 . Thus, a bottom width of the gate electrode 160 is wider than a top width thereof.
- the gate electrodes 160 can include at least one liner layer that conforms to and covers substantially the entire exposed perimeter and/or upper portion thereof (that is, both opposing sidewalls and the top of the gate electrode but not the bottom). As shown, the upper portion of the gate electrode 160 is covered by either a first liner layer 200 and/or a second liner layer 260 .
- the second liner layer 260 is disposed on a minor portion of the perimeter, typically the upper and intermediate portion of one sidewall of the gate electrode 160 (i.e., the intermediate portion of the sidewall 240 b of the self aligned contact window 240 ).
- the first liner layer 200 can be disposed on the remainder of the exposed perimeter of the gate electrode 160 .
- the exposed perimeter of gate electrodes 160 are covered and/or surrounded by thin liner layers 200 and 260 .
- the liner layer may be thin, which includes a layer that has a thickness of about 100 ⁇ or less.
- the second liner layer 260 can be configured to continuously extend from the upper sidewall 240 a to the lower sidewall 240 c of the self-aligned contact window 240 .
- the self-aligned contact window 240 can be substantially entirely filled with a conductive material (the conductive material can be disposed on and/or over the second liner layer 260 ) to form a self-aligned contact pad 300 a . That is, the self-aligned contact pad 300 a is electrically connected to the impurity diffusion region 180 between adjacent gate electrodes 160 but electrically insulated from the gate electrodes 160 by the liner layers 200 and 260 .
- the contact structure comprises liner layers 200 and 260 , which can include a silicon nitride layer, and the interlayer insulation layer 220 , which can include a silicon oxide layer.
- the self-aligned contact structure can be configured so that the exposed upper surfaces (the surfaces facing away from the substrate 100 ) of the gate electrode 160 are surrounded by the thin liner layers 200 and 260 on the upper perimeter, and the gate oxide layer 140 on the bottom or lower perimeter, such that a height of the gate electrode 160 can be lower than in certain conventional configurations.
- a deposition thickness of the interlayer insulation layer 220 can be reduced and production cost and time may also be reduced.
- the distance and/or spacing between neighboring gate electrodes 160 can increase due to the liner employing reduced space under a given minimum line width.
- contact resistance between the impurity diffusion region 180 and the self-aligned contact pad 300 a can be improved.
- the upper portion of the gate electrode 160 can be surrounded by a thin (typically nitride) liner layer 200 , 260 , so that loading capacitance can be reduced.
- FIG. 2 shows a schematic of a self-aligned contact structure in accordance with another exemplary embodiment of the present invention.
- a buffer insulation layer 280 a is further interposed between the second liner layer 260 disposed on the upper sidewall 240 a of a self-aligned contact window 240 and a self-aligned contact pad 300 a .
- the buffer insulation layer 280 a can comprise silicon oxide. This configuration may allow the, loading capacitance to be even further reduced.
- FIGS. 3A through 3I A method for forming the self-aligned contact structure will be explained with reference to FIGS. 3A through 3I .
- FIGS. 3A through 3I For brevity and/or clarity, only a few gate electrodes 160 , one self-aligned contact window 240 and one contact pad 300 a are illustrated in the drawings.
- a device isolation layer 120 is formed in a semiconductor substrate 100 using a conventional method.
- a shallow trench isolation (STI) method or a local oxidation of silicon (LOCOS) method can be employed.
- a thermal oxidation process can be performed to form a gate oxide layer 140 on an entire target surface of the semiconductor substrate. Then, a conductive material is formed on the gate oxide layer 140 and the conductive material is patterned to form gate electrodes 160 .
- the gate electrodes 160 are arranged to be parallel and spaced apart from each other by a predetermined distance (i.e., a distance corresponding to a minimum line width).
- each of the gate electrodes 160 may comprise a polysilicon single-layered structure or a double-layered structure of polysilicon and tungsten silicide or polysilicon and tungsten that are sequentially stacked, respectively.
- a capping nitride layer is not required to be formed on the gate electrodes 160 .
- the gate electrode 160 can comprise polysilicon, and the polysilican may be re-oxidized. Then, an ion implantation process can be performed using the gate electrodes 160 as an ion implantation mask in order to form a conductive region, i.e., impurity diffusion regions 180 .
- the impurity diffusion regions 180 can be formed in the substrate on both sides of the gate electrodes 180 .
- a liner layer 200 can be a substantially continuous layer that is formed over a semiconductor substrate 100 , over the exposed upper surfaces of the gate electrodes 160 , and over the impurity diffusion layer 180 .
- the liner layer 200 comprises a material having etch selectivity with respect to the interlayer insulation layer 220 that will be formed in a subsequent process.
- the interlayer insulation layer 220 is formed of silicon oxide
- the liner layer 200 can be formed of silicon nitride.
- sidewall spacers are not required to be formed on sidewalls of the gate electrode.
- a thin silicon nitride layer is conformally formed as the liner layer 200 .
- the liner layer 200 of the present invention can be configured as a thin layer having a thickness of, for example, about 100 ⁇ or less. Therefore, contrary to the conventional method, the separation distance between adjacent gate structures (which in the past typically included spacers) can be about 300-500 ⁇ or more under an identical design rule used in conventional configurations. This separation distance may improve contact resistance between the impurity diffusion layer 180 and a self-aligned contact pad ( 300 a , FIG. 1 ) that will be formed in a subsequent process.
- an interlayer insulation layer 220 is formed on the liner layer 200 in art amount sufficient to cover the space between the gate electrodes 160 .
- the interlayer dielectric layer 220 can be formed of silicon oxide.
- the interlayer dielectric layer 220 is formed of silicon oxide having good step coverage.
- a mask pattern, for example, a photoresist pattern (not shown) can be formed on the interlayer insulation layer 220 . The pattern defines a self-aligned contact window ( 240 , FIG. 1 ).
- the exposed interlayer insulation layer 220 can be etched.
- the interlayer insulation layer 220 is selectively etched with respect to the liner layer 200 to form the self-aligned contact window 240 . While the etching is performed, the thin liner layer 200 of a top edge of a respective gate electrode 160 may be weakened by repeated etching. Therefore, a top edge portion and an upper sidewall portion of the thin liner layer 200 on the gate electrode 160 is etched and then a corresponding portion of the exposed gate electrode 160 can be etched to provide an inclined profile at a respective top edge and upper sidewall (typically ending at an intermediate) portion of the gate electrode 160 .
- the separation distance between the gate electrodes 160 can be substantially uniform, that is, a minimum substantially uniform line width can be generated.
- the formed self-aligned contact window 240 may be described as having an upper sidewall 240 a , a middle sidewall 240 b , a lower sidewall 240 c , and a bottom 240 d .
- the upper sidewall 240 a of the self-aligned contact window 240 is defined by the interlayer insulation layer 220 .
- the middle sidewall 240 b is defined by the sloped gate electrode (i.e., the upper sidewall portion of the gate electrode 160 ).
- the lower sidewall 240 c is defined by the liner layer 200 residing over the lower sidewall of the gate electrode 160 .
- the bottom 240 d is defined by the liner layer 200 on the impurity diffusion region 180 between adjacent gate electrodes 160 .
- the upper sidewall portion of the gate electrode 160 can be etched to provide a sloped profile.
- a gate protection liner layer 260 can be formed to cover the exposed upper portion of the gate electrode 160 . Therefore, the exposed upper surfaces of the gate electrodes 160 can be completely covered and/or protected by the liner layers 200 and 260 . As shown in FIG. 3E , the upper portion of the gate electrode 160 is covered by the gate protection liner layer 260 and the remaining portion of the upper surfaces of the gate electrode is protected by the liner layer 200 .
- the gate shield protection layer 260 may be formed of the same material as the liner layer 200 , for example, silicon nitride. In addition, the protection liner layer 260 can be formed to about 200 ⁇ or less. As shown in FIG. 3E and FIG. 1 , the gate protection liner layer 260 may overlie a lower portion of the liner layer 200 at a lower portion of the sidewall 240 c.
- liner layers 200 and 260 formed on the bottom of the contact window 240 d can be removed to expose the impurity diffusion layer 180 .
- a buffer insulation layer 280 having relatively poor step coverage can be formed on the gate protection and/or shield liner layer 260 to cause overhang (i.e., the buffer insulation layer 280 material resides above the top of the gate and overhangs the contact window 240 to extend down into the contact window 240 ).
- the buffer insulation layer 280 can be formed of differential thickness along the window 240 so that it is relatively thin on the bottom 240 d and lower sidewalls 240 c of the self aligned contact window 240 , but formed with increased thickness on the middle sidewall 240 b and the upper sidewall 240 a of the self-aligned contact window 240 .
- An opening 250 in the buffer insulation layer 280 can extend downwardly to terminate substantially at and/or expose the bottom of the contact window 240 d.
- the buffer insulation layer 280 can be formed of silicon oxide using, for example, chemical vapor deposition. As described above, the upper part of the contact window 240 b has a sloped profile, such that the overhang can be more easily formed.
- an etch-back process can be applied to the stacked surface of the semiconductor substrate 100 holding the buffer insulation layer 280 ( FIG. 3F ).
- the buffer insulation layer 280 and the liner layers 200 , 260 are simultaneously etched in the etch-back process.
- the buffer insulation layer 280 is configured sufficiently thin, the buffer insulation layer 280 and the liner layers 200 , 260 thereunder are removed to expose the underlying material or surface, such as the impurity diffusion region 180 .
- the thin portion of the buffer insulation layer 280 and the liner layers 200 , 260 thereunder are on the bottom 240 d of the contact window 240 that is exposed through the opening 250 defined by the buffer insulation layer 280 .
- the buffer insulation layer 280 is formed with increased thickness on the intermediate and upper portion of the sidewalls 240 b , 240 a , respectively of the contact window 240 , a portion of the buffer insulation layer 280 can remain as a spacer 280 a after the etch-back process is carried out to expose the impurity diffusion region 180 . Accordingly, the residual buffer insulation layer 280 a protects the liner layers 260 and/or 200 on the middle sidewalls 240 c and the upper sidewall 240 b of the contact window 240 so that the underlying liner(s) is not exposed during the etch-back process.
- the gate protection liner layer 260 is formed before a formation of a conductive layer 300 . Therefore, even though voids may occur when the interlayer dielectric layer 220 is formed, electrical bridging is inhibited and/or prevented.
- the protection liner layer 260 may be etched.
- the contact window 240 is filled with conductive material 300 .
- an etching process can be carried out to remove excess conductive material 300 until the interlayer insulation layer 220 is exposed at the upper part thereof.
- the etching process can be performed to form a self-aligned contact pad 300 a as illustrated in FIG. 3I .
- the residual buffer insulation layer 280 a may optionally be removed and then conductive material may be provided as a filler as desired. In this case, the cross-sectional size of the upper portion of the contact pad 300 a increases, so that the subsequent process margin may also increase.
- a capping layer and a spacer layer are not required to be formed on the upper portion and the sidewall of the gate electrode, respectively. This is an aspect that is contrary to the conventional method. Therefore, a silicide layer can be easily formed at the peripheral circuit area and the cell area where a memory device is formed at the same time.
- a device isolation process is illustrated to form a device isolation layer 120 that defines an active region in the semiconductor substrate 100 with a cell array region “a” and a peripheral circuit region “b”.
- a gate oxide layer 140 is formed on a surface of the semiconductor substrate 100 by a thermal oxidation process.
- a conductive layer for forming a gate electrode is formed on the gate oxide layer 140 .
- the gate electrode conductive layer is patterned to form gate electrodes 160 a and 160 b at the cell array region “a” and the peripheral circuit region “b” of the semiconductor substrate 100 , respectively.
- the gate electrodes In the cell array region “a” the gate electrodes can be densely formed, but in the peripheral region “b” the gate electrodes may be formed more sparsely.
- the gate electrodes 160 a and 160 b comprise, for example, polysilicon.
- a re-oxidation process can be performed and then an ion implantation process can be carried out to form lightly doped impurity diffusion regions 180 a and 180 b in the semiconductor substrate 100 at both sides of the gate electrodes 160 a and 160 b in the respective regions a, b.
- a liner layer 200 and a sacrificial insulation layer 350 are formed on target exposed surfaces of the semiconductor substrate 100 including over the gate electrodes 160 b , 160 a , and the impurity diffusion regions 180 a , 180 b .
- the liner layer 200 can comprise, for example, silicon nitride.
- the sacrificial insulation layer 350 can comprise, for example, silicon oxide.
- the gate electrodes 160 b can be densely formed at the cell region “a”, so that the sacrificial insulation layer 350 completely covers the lower structures including the space between the gate electrodes 160 b at the cell region “a”, and have a substantially planar top surface.
- the sacrificial insulation layer 350 may be stepped to travel about the outline of the lower structure at the peripheral circuit region “b” with the sacrificial layer 350 at region “b” having the greatest height above the underlying top surface of the gate electrode 160 a.
- an etch-back process can be applied to the surface of the stacked semiconductor substrate with the sacrificial insulation layer 350 so that the sacrificial insulation layer 350 remains only on the sidewalls of the gate electrode 160 a to form temporary sidewall spacers 350 a at the peripheral circuit region “b”. That is, a top of the gate electrode 160 a of the peripheral circuit region “b” and portions of the lightly doped impurity diffusion regions 180 a at both sides of the gate electrode 160 a are exposed.
- the exposed lightly doped impurity diffusion regions 180 a are separated from the gate electrode 160 a as far as a predetermined distance (i.e., a width W of a temporary sidewall spacer 350 a ).
- a width W of a temporary sidewall spacer 350 a determines a length L of the lightly doped impurity diffusion regions 180 a that are covered with the temporary sidewall spacers 350 a (the length L can correspond to the length of a final lightly doped impurity diffusion region).
- the sacrificial insulation layer 350 b still remains on the impurity diffusion region 180 b at both opposing sides of the gate electrode 160 b and on the sidewalls of the gate electrode 160 b.
- the thickness of the temporary spacers 350 a at the peripheral region “b” can be adjusted.
- a distance between the exposed lightly doped impurity diffusion region 180 a and the gate electrode 160 a i.e., the final length L of the lightly doped impurity diffusion region
- the final length L of the lightly doped impurity diffusion region can be controlled to a desired length/thickness.
- an ion implantation process is illustrated and may, in operation, be substantially continuously carried out.
- the gate electrodes 160 a and 160 b and the residual sacrificial insulation layer, i.e., a residual sacrificial insulation layer 350 b at a cell region “a” and the temporary sidewall spacers 350 a at the peripheral circuit region “b” are used as an ion implantation mask. Therefore, heavily doped impurity diffusion regions 180 c can be formed at the peripheral circuit region “b”. The heavily doped impurity diffusion regions 180 c continue to the lightly doped impurity diffusion regions 180 a at both sides of the gate electrodes 160 a .
- the lightly doped impurity diffusion regions 180 a are formed in the semiconductor substrate 100 under the temporary sidewall spacers 350 a .
- impurity diffusion ions can be implanted into the upper or top portion of the exposed gate electrodes 160 a and 160 b . That is, gate electrodes 160 a and 160 b can be concurrently doped while the heavily doped impurity diffusion regions 180 c are formed.
- the cell region “a” and the peripheral circuit region “b” can include, for example, NMOS transistors.
- the gate electrodes (not shown) for a PMOS transistor, which can be formed in the peripheral circuit region “b”, can be covered with a photoresist pattern and the top thereof may be protected.
- the gate electrodes 160 a and 160 b can be protected by the photoresist pattern during an ion implantation process for the gate electrode of a PMOS transistor.
- silicide (or other desired material) layers 400 a , 400 b and 400 c can be substantially concurrently formed on top of the gate electrode 160 a of the exposed peripheral circuit region “b”, on the heavily doped impurity diffusion regions 180 c , and on the exposed gate electrodes 160 b of the exposed cell region “a”, respectively.
- a refractory metal having a relatively high melting point can be conformably formed and then thermally treated to cause a silicidation reaction between silicon and the refractory metal in order to form a silicide layer 400 a , 400 b and/or 400 c .
- the non-reacting refractory metal can be removed in an automated manner.
- the residual sacrificial oxide layers 350 a and 350 b are removed and then a silicide shield liner layer 420 can be formed on an entire exposed surface of the stacked semiconductor substrate for protecting silicide layers 400 a , 400 b , 400 c .
- the silicide protection liner layer 420 can comprise silicon nitride.
- the silicide protection liner layer 420 is optional and may be excluded. In certain embodiments, typically depending on processes, a portion of the sacrificial oxide layer 350 a remaining at the peripheral circuit region “b” may remain. That is, a portion of sidewall spacers 350 a may remain.
- an interlayer insulation layer 220 is formed on the silicide protection liner layer 420 .
- the interlayer insulation layer 220 can be provided so that it has a planar top surface as shown. That is to say, an interlayer insulation layer 220 can be stacked relatively thick and then a chemical mechanical polishing (CMP) process, an etch-back or other suitable process can be performed to planarize this layer 220 .
- CMP chemical mechanical polishing
- the interlayer insulation layer 220 is formed of material having etch selectivity with respect to the liner layer 200 and the silicide protection liner layer 420 .
- the interlayer insulation layer 220 can comprise and/or be formed of silicon oxide having good step coverage.
- the interlayer insulation layer 220 on the cell region “a” can be etched to form a self-aligned contact window 240 .
- the gate electrodes 160 b of the cell region “a” are etched to slope at an upper portion thereof.
- a gate shield liner layer 260 and a buffer insulation layer 280 can be formed in the same way as the method mentioned above.
- an etch-back process can be applied to the surface of the stacked semiconductor substrate with the buffer insulation layer 280 , so that liner layers 200 , 260 , 420 on a bottom 240 d of the contact window 240 are removed to expose a lightly doped impurity diffusion region 180 b.
- conductive material is provided to the window 240 and formed therein, then an etching process is performed to form a self-aligned contact pad 300 a.
- the gate electrode 160 may comprise two sequentially stacked layers of different materials, such as, for example, polysilicon 150 and tungsten silicide 155 or polysilicon 150 and tungsten 155 , instead of forming the gate electrode 160 with polysilicon as described for certain embodiments of FIG. 4A .
- a silicide layer 400 b can be formed to overly substantially only the heavily doped impurity diffusion regions 180 c that are formed in the semiconductor substrate 100 at both sides of the gate electrode 160 a at the peripheral region “b” (i.e., the top silicide layer 400 a is not necessary).
- an etch-back process can be applied to a stacked surface of the semiconductor substrate.
- the etch back process may be performed after forming a photoresist pattern 500 covering the cell region “a”, as illustrated FIGS. 5A and 5B .
- a gate electrode 150 is formed with a multi-layered structure of polysilicon 150 and tungsten silicide 155 or of polysilicon 150 and tungsten 155 . Then, lightly doped impurity diffusion regions 180 a and 180 b are formed by an ion implantation process, and a buffer insulation layer 350 is formed.
- a photoresist pattern 500 that covers a cell region “a” is formed, and then an etch-back process can be performed to form temporary sidewall spacers 350 a on sidewalls of the gate electrode 160 b at the peripheral circuit region “b”. Then, heavily doped impurity diffusion regions 180 c can be formed in the peripheral region “b” by an ion implantation process.
- the photoresist pattern 500 and residual buffer insulation layers 350 and 350 a are removed.
- the top of the gate electrode 160 b is not exposed at a cell region “a”, such that a silicide layer 400 b is formed substantially only at the peripheral circuit region “b”.
- FIGS. 4E through 4J can be substantially continuously serially performed in an automated mass production process.
- Embodiments of the present invention may provide one or more of the following advantages compared to conventional self-aligned contact processes.
- the present invention is directed to integrated circuits and can include structures formed on other substrates.
- undesired electrical bridging may occur in a subsequent process for forming a self-aligned contact pad due to voids that may be formed while an interlayer insulation layer is deposited.
- embodiments of the present invention reduce the likelihood that voids will be present when the interlayer insulation layer is formed because the sidewall spacers and the capping layer are not formed.
- electrical bridging can be inhibited because a nitride liner can be formed.
- the gate electrode stacked structure is relatively high and the distance between the gate electrodes is narrow, such that the halo ion implantation is difficult to apply.
- the spacing is such that halo ion implantation can be used.
- the gate electrode of the present invention can be configured with a relatively low height, so that the interlayer insulation layer can be lowered in a thickness. As a result, production cost may be reduced and/or the throughput can be improved.
- loading capacitance may be relatively large due to the presence of a capping nitride layer and a space nitride layer.
- the loading capacitance is reduced and relatively small because of the generation of a nitride liner, thereby potentially providing improved device operational characteristics.
- the distance between neighboring gate electrodes may be relatively narrow owing to the use of a spacer nitride layer making it difficult to generate sufficient self-aligned contact resistance, and integration is not easy.
- the self-aligned contact resistance can be more easily preserved and integration can be easier.
- conventional fabrication methods may have difficulties forming a silicide layer at the cell region and the peripheral region at the same time.
- the silicide layer can be simultaneously formed at the cell region and the peripheral region.
- the thickness of the sidewall spacers of the gate electrode at the peripheral region may be more easily controlled.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
A self-aligned contact structure and a method of forming the same include selected neighboring gate electrodes with adjacent sidewalls that are configured to angle toward each other. The angled surfaces of the gate electrodes can be protected using a liner layer that can extend the length of the contact window to define the sidewalls of the contact window.
Description
- This application is a divisional of U.S. patent Ser. No. 10/695,061, filed Oct. 28, 2003 which claims the benefit of priority to Korean Patent Application 2002-66874, filed on Oct. 31, 2002, the contents of which are incorporated by reference herein in their entirety.
- The present invention relates to semiconductor devices and methods of forming the same and more specifically to lower electrode contact structures over an underlying layer and methods of forming the same.
- Semiconductor device manufacturing typically includes alternately forming conductive layers (or conductive regions) and insulation layers, and electrically connecting upper and lower conductive layers that are otherwise electrically insulated by the insulation layers, using contacts that are formed in predetermined regions of the insulation layer.
- For example, when manufacturing a semiconductor memory device, conductive regions between gate electrodes which include source and drain regions, can be electrically connected to a bit line or a storage node. To provide this feature after forming the gate electrode, an insulation layer is typically formed and then etched through a photolithographic etching process to form a contact window that exposes the drain region. Then, the contact window may be filled with conductive material to form what can be referred to as a “bit line” contact plug. The manufacturing process can also include forming a bit line that is electrically connected to the bit line contact plug, then depositing an insulation layer again, and etching the insulation layer to form a contact window that exposes the source region. Then, a storage node contact plug is formed. A storage node can be formed that is electrically contacted to the storage node contact plug.
- However, the distance between adjacent elements in the semiconductor substrate (i.e., the gate electrodes) can be reduced or made more narrow as manufacturing procedures and/or processes accommodate increased density configurations. As a result, the aspect ratio of the contact window that extends through the insulation layer may increase, such that the contact window may not entirely penetrate the insulation layer during the photolithographic process. In addition, a gate electrode may be exposed during the contact window etching process, particularly if there is misalignment, thereby potentially causing electrical bridging between the gate electrode and the contact plugs.
- Accordingly, self-aligned contact technologies have been used in order to decrease the aspect ratio of the contact window or hole and to inhibit or prevent the electrical bridge. The self-aligned contact technologies typically use a material property between two separate insulating layers to establish a different etch rate with respect to a predetermined etch gas. Briefly explained, one insulation layer (e.g., a silicon nitride layer) can be formed on a top and sidewalls of the gate electrode in order to protect the gate electrode. An interlayer insulation layer (e.g., a silicon oxide layer) having etch selectivity with respect to the one insulation layer can be used. Then, the photolithographic process can be performed to selectively etch the interlayer insulation layer, thereby forming a contact window that exposes conductive regions between the gate electrodes. After this step, conductive materials can be filled in the contact window to form self-aligned contact pads. According to these conventional self-aligned contact technologies, the gate electrode may be protected by the one insulation layer (such as the silicon nitride layer), so that even in the presence of misalignment, the gate electrodes, especially the top thereof, may not be exposed when the interlayer insulation layer (the silicon oxide layer) is etched.
- In conventional self-aligned contact technologies, in order to increase the likelihood that the gate electrode is protected during fabrication, a silicon nitride capping layer can be formed on the top of the gate electrode and silicon nitride sidewall spacers can be formed on the sidewalls of the gate electrodes. Unfortunately, these spacers and the capping layer may cause problems, examples of which will be explained hereinafter.
- For example, the silicon nitride capping layer typically increases a height of the stacked layer structure used to form the gate electrode(s). In addition, the space between neighboring gate electrodes may decrease due to the silicon nitride sidewall spacers. Therefore, during fabrication, the space between neighboring gate electrodes may not fill properly with the interlayer insulating layer, thereby potentially causing void and undesired electrical bridging in the subsequent process. Moreover, because the gate-stacked structure is relatively high, ion implantation may be difficult to perform. The conductive region (i.e., the source and drain regions), which is exposed by the self-aligned contact window, is typically limited in an area by the sidewall spacers. As a result, contact resistance between the source/drain region and self-aligned contact pad can increase. In addition, the gate electrode can be surrounded by the silicon nitride layer, such that loading capacitance may increase and the operation speed of the device may decrease.
- Meanwhile, in the case of a transistor composing a logic circuit, a self-aligned silicide layer (i.e., salicide) may be used for high-speed operation. That is, refractory metal can be formed on top of the gate electrode and on the source/drain regions at both sides thereof. The refractory metal and silicon can then be thermally treated to form a silicide layer based on the reaction between the refractory metal and the silicon. When a logic circuit and a memory device are formed in the same chip for a high-speed operation and a highly integrated memory device, the conventional self-aligned contact techniques may cause several problems.
- During operation, a top of the gate electrode of the memory device should be protected with an insulating layer, such as a silicon nitride layer, in order to use a conventional self-aligned contact method to form the memory device. However, in case of the logic device, the top of the gate should typically be exposed for forming the silicide layer. To compensate for the two disparate features, the fabrication process can become increasingly complicated. In addition, when forming the memory device, the silicide layer may be formed in order to secure a low resistance. However, the top of the gate may be protected by silicon nitride such that it may be difficult to form a silicide layer. In addition, when forming the logic device, the silicide layer can be formed in the source/drain regions, such that the gate sidewall spacers may be formed relatively thick to make the source/drain regions have an increased length. In other words, the length may depend on the width or thickness of the gate sidewall spacers. However, the sidewall spacers should be formed relatively thin at the cell region in order to inhibit generating voids.
- Embodiments of the present invention are directed to self-aligned contact structures and methods of forming the same. Certain embodiments of the present invention are directed to methods of forming self-aligned contact structures at a cell region and simultaneously forming a silicide layer on top surfaces of a gate electrode at a cell array region and a peripheral region.
- In particular embodiments, the self-aligned contact structure of the present invention includes gate electrodes with top and side surfaces covered by a thin nitride liner. This configuration is in contrast to a conventional structure where the gate electrode can be surrounded by a silicon nitride capping layer and sidewall spacers. Accordingly, in particular embodiments, an aspect ratio of a self-aligned contact window can decrease, a contact resistance can be lowered, and a loading capacitance can be reduced. In addition, void(s) can be inhibited and/or prevented while an interlayer insulation layer is deposited.
- In certain embodiments, a self-aligned contact structure of the present invention includes gate electrodes, a first liner layer, a self-aligned contact pad, an interlayer insulation layer and a second liner layer. The gate electrodes are disposed on a semiconductor substrate, separated from each other, and interposed with a gate insulation layer therebetween. Upper portions of respective gate electrodes may have inclined profiles, such that the width of the upper portions is narrower than the width of the lower portions. Together, the first and second liner layers are selectively disposed on the semiconductor substrate to surround certain surfaces (typically the first liner layer surrounds a major portion of the target surfaces and the second liner layer surrounds a minor portion of the target surfaces with the gate electrodes having only a small dual liner coverage area to thereby surround all of the exposed upper surfaces) of the gate electrodes.
- The self-aligned contact pad is electrically connected to the exposed semiconductor substrate between selected neighboring gate electrodes, and disposed to contact at least portions of the second liner layer. That is, the self-aligned contact pad is disposed between selected pairs of adjacent sidewalls of neighboring gate electrodes and has a length sufficient to protrude above the top surface of the gate electrodes. The interlayer insulation layer is disposed on the first liner layer about certain external portions of respective gate electrodes, and on the second liner layer above the top surface of the gate electrodes about the upper portions of sidewalls of the protruding self-aligned contact pad such that the second liner layer is interposed between the contact pad and the interlayer insulation layer.
- In particular embodiments, the present invention can further include a buffer insulation layer that is disposed between the second liner layer and at least the upper portion of the self-aligned contact pad.
- The first liner layer and the second liner layer can comprise silicon nitride and the interlayer insulation layer and the buffer insulation layer can comprise silicon oxide. In an exemplary embodiment, the interlayer insulation layer is a silicon oxide layer having good step coverage and the buffer insulation layer may be a silicon oxide layer having poor step coverage.
- Certain embodiments of the present invention are directed toward self-aligned contact structures. The structures include: (a) a plurality of spaced apart gate electrodes disposed on a semiconductor substrate with the gate electrodes having opposing first and second sidewalls and top and bottom surfaces, wherein adjacent sidewalls of selected neighboring gate electrodes have respective upper portions that angle toward each other to present a sloped profile; (b) a first liner layer that is disposed on the semiconductor substrate and covers one of the first and second sidewalls, a minor portion of the other sidewall and a major portion of the top surface of the gate electrodes; (c) a plurality of self-aligned contact pads that are separately electrically connected to selected regions of the semiconductor substrate, each self-aligned contact pad having opposing upwardly extending sidewalls, wherein a respective self-aligned contact pad is positioned between the selected neighboring gate electrodes, and have a length sufficient so that the self-aligned contact pads extend a distance above the top surface of the gate electrodes; (d) an interlayer insulation layer disposed on the first liner layer above the top surface and about selected sidewalls of respective gate electrodes, the selected sidewalls of respective gate electrodes being those sidewalls that are positioned away from the self-aligned contact pad electrodes; and (e) a second liner layer disposed on the angled portions of the adjacent sidewalls of neighboring gate electrodes.
- Certain embodiments include methods of forming a self-aligned contact window configured to hold a self-aligned contact pad therein in communication with a semiconductor substrate. The methods include removing a selected portion of an interlayer insulation layer and then an underlying upper portion of adjacent sidewalls of first and second gate electrodes held proximate to each other on a semiconductor substrate to form first and second gate electrodes with sloped sidewalls that angle toward each other and define a portion of the shape of sidewalls of a self-aligned contact window configured to hold a self-aligned contact pad therein.
- Other embodiments are directed to methods of forming the self-aligned contact structures. The methods can include: (a) forming gate electrodes that are spaced apart from each other on a semiconductor substrate; (b) forming a first liner layer on the semiconductor substrate and the gate electrodes; (c) forming an interlayer insulation layer over the first liner layer; (d) forming a contact window having opposing spaced apart sidewalls and a bottom by selectively etching the interlayer insulation layer with respect to the first liner layer; (e) forming a second liner layer over the interlayer insulation layer and the bottom and sidewalls of the contact window; (f) forming a buffer insulation layer to extend laterally a distance beyond the second liner layer to overhang in the contact window; (g) exposing the semiconductor substrate between adjacent gate electrodes by performing an etch back process to remove the buffer insulation layer and the second and first insulation layers at a bottom portion of the contact window; and (h) filling the contact window with conductive material to thereby substantially and/or entirely fill at least a lower portion of the contact window.
- Different from the conventional method, in a method of forming the self-aligned contact according to embodiments of the present invention, a thin nitride liner may be formed on the gate electrode without forming a gate sidewall spacer nitride layer and a capping nitride layer. Therefore, during the etching of the interlayer insulation layer for forming the self-aligned contact window, a portion of the upper part of the gate electrode is etched, so that the self-aligned contact window have an inclined profile. That is, because a thin nitride liner covers the gate electrodes, the upper part of the gate is continuously attacked to weaken during the etching of the interlayer insulation layer. Therefore, the thin nitride layer on the upper part of the gate electrode is etched, such that the upper part of the gate electrode is exposed and etched. As a result, the contact window having inclined profile is formed. Namely, upper part of the gate electrode is narrower than lower part thereof. A nitride liner can be additionally formed to protect the exposed upper part of the gate electrode and then an insulation layer having poor step coverage is formed to cause overhang. The insulation layer can be formed thin on the bottom of the contact window and thicker on the sidewalls and the upper part of the contact window. Therefore, when etching is performed, the insulation layer and the nitride liner are etched to expose the conductive region because the insulation layer is formed thin on the bottom of the contact window. However, the insulation layer is formed thicker on the sidewalls, such that the nitride liner is not etched.
- Yet other embodiments are directed toward an integrated circuit (such as a semiconductor) assembly. The assembly includes a plurality of gate electrodes disposed on a substrate, the gate electrodes having opposing sidewalls and top and bottom surfaces, wherein portions of selected adjacent sidewalls of neighboring electrodes (i.e., the sidewalls that face each other) angle generally downwardly and inwardly toward each other while the opposing sidewall of each of the selected sidewalls are substantially linear.
- In particular embodiments, the assembly further includes a plurality of elongate contact windows, a respective one positioned between the selected adjacent sidewalls of neighboring electrodes, wherein the contact window sidewalls comprise an angled profile that correspond to the angled gate electrode sidewall configuration; and a contact pad disposed in each contact window, the contact pad extending generally downwardly and having a length that is greater than the height of the gate electrodes.
- In particular embodiments, the assembly may also include a gate protection liner layer that extends in the contact window and covers the angled sidewall portion of a respective gate electrode, and a first liner layer that covers the remaining surfaces of the top and opposing sidewalls of the respective gate electrode.
- Other embodiments are directed to semiconductor assemblies that include a conductive contact on a substrate in a recess adjacent to a gate electrode having a gate electrode sidewall and a top surface. The sidewall angling inwardly from the top surface to an intermediate portion of the sidewall toward the recess. The conductive contact has a height that extends above the top surface of the gate electrode.
- According to embodiments of the invention, a height of the gate stacked structure and a distance therebetween may be increased, such that voids may be inhibited and/or prevented when the interlayer insulation layer is formed. Moreover, in certain embodiments, even though voids may occur, electrical bridging is inhibited and/or prevented because the nitride liner is formed after the etching of the interlayer insulation layer. In addition, the gate-stacked structure can have a relatively low height, so that the thickness of the material layer may also be relatively thin. Thus, manufacturing costs may be reduced and throughput may be increased.
- In certain embodiments, methods of forming the self-aligned contact structure can include the following operations. Gate electrodes are formed on a semiconductor substrate. The gate electrodes can run in parallel and separated from each other. A first liner layer is formed on the semiconductor substrate and on surfaces of the gate electrodes. An interlayer insulation layer is formed on the first liner layer. A contact window is formed by etching selectively the interlayer insulation layer with respect to the first liner layer. A second liner layer is formed on the resultant structure with the contact window and a buffer insulation layer is formed to cause overhang on the second liner layer, thereby forming the buffer insulation layer thin on a bottom of the contact window and thicker toward the sidewalls and upper part of the contact window. An etch back process is performed under the condition without etch selectivity between the buffer insulation layer and the liner layers to expose the semiconductor substrate between the gate electrodes. Conductive material is formed to fill the entire self-aligned contact window.
- Depending on exemplary embodiments, before forming the conductive material, a step of removing the buffer insulation layer can be more performed. Therefore, an area of the upper part of the conductive material is widened that is filled in the contact structure, thereby increasing misalignment margin in a subsequent process.
- In certain embodiments, the first liner and the second liner layer may be formed of a silicon nitride layer and the interlayer insulation layer may be formed an oxide layer having good step coverage. The buffer insulation layer may be formed of an oxide layer having poor step coverage.
- While the interlayer insulation layer may be patterned to form the Contact window, the upper part of the gate electrodes can be attacked by the etching and the first liner layer thereon can be simultaneously etched. Thus, the exposed upper part of the gate electrode can be etched to be inclined.
- In certain embodiments, during an etch back process, under the condition without etch selectivity between the buffer insulation layer and the liner layers, the liner layers on the upper and intermediate sidewalls of the contact window can be protected by the buffer insulation layer while allowing the liner layers on the bottom of the contact window to be etched. The buffer insulation layer may remain on the upper sidewall of the temporary contact window, so that sidewall spacers are formed.
- In particular embodiments, after forming the first liner layer and before forming the interlayer insulation layer, the following steps may be further performed: a sacrificial insulating layer is formed, the sacrificial insulation layer is etched back to expose the gate electrodes; a metal silicide layer is formed on the exposed gate electrodes; and the residual sacrificial insulation layer is removed. Different from the conventional method for forming a self-aligned contact, a capping nitride layer is not formed on top of the gate, such that the gate electrode is easily exposed and a silicide layer can be formed thereon.
- Using the method for forming the self-aligned contact window, a silicide layer can be easily formed at the peripheral circuit area where a logic circuit is formed and at the cell array region where a memory element is formed.
- In particular embodiments, certain methods can be carried out to simultaneously form a silicide layer on the upper part of the gate electrode at the cell array region and at the peripheral circuit region.
- Certain embodiments are directed toward methods of forming a self-aligned contact. The methods include: (a) forming gate electrodes that are spaced apart from each other with a plurality of the gate electrodes positioned at a cell array region and at least one gate electrode positioned at a peripheral circuit region of the semiconductor substrate, respectively; (b) forming a first liner layer over the semiconductor substrate and surfaces of the gate electrodes; (c) forming a sacrificial insulation layer on the first liner layer in an amount sufficient to cover spaces between the gate electrodes of the cell array region; (d) etching back the sacrificial insulation layer so as to form temporary sidewall spacers on sidewalls of the at least one gate electrode at the peripheral circuit region; (e) forming a metal silicide layer at least on the semiconductor substrate exposed adjacent the temporary sidewall spacers; then (f) removing the sacrificial insulation layer remaining at the cell array region and the temporary sidewall spacers of the peripheral circuit region; (g) forming an interlayer insulation layer having a substantially planar top surface; (h) selectively etching the interlayer insulation layer with respect to the first liner layer to form at least one contact window in the cell array region between adjacent first and second gate electrodes, the contact window having opposing spaced apart sidewalls and a bottom; (i) forming a second liner layer on the sidewalls and bottom of the contact window; (j) forming a buffer insulation layer on the second liner layer so that the buffer insulation layer extends a lateral distance into the contact window to leave a gap space in the contact window, the buffer insulation layer having a greater thickness at a top portion of the sidewalls of the contact window than at a lower portion of the sidewalls of the contact window; (k) exposing the semiconductor substrate between the gate electrodes of the cell array region by performing an etch back process; and (l) filling at least a lower portion of the contact window with conductive material.
- In certain embodiments, after forming the buffer insulation layer, in the etching back process, the liner layers on the upper and intermediate parts of the contact window are protected by the buffer insulation layer, but the liner layers on the bottom of the contact window are etched. Thus, the buffer insulation layer remains the upper and intermediate sidewalls of the contact window to form sidewall spacers.
- In the above method(s), the following operations may be additionally carried out. After forming the gate electrodes, lightly doped impurity diffusion layers are formed in the semiconductor substrate at both sides of the gate electrodes by performing an ion implantation process. After forming the temporary sidewall spacers, heavily doped impurity diffusion layers, which are continued to the lightly doped impurity diffusion layers of the peripheral circuit region, are formed in the semiconductor substrate at both sides of the temporary sidewall spacers.
- In the exemplary embodiment, the gate electrodes may be formed of polysilicon. At this time during an etch back process following the formation of the sacrificial insulation layer, the upper parts of the gate electrodes are exposed at the cell region and the peripheral circuit region, and the sacrificial insulation layer of the cell region remains on sidewalls of the gate electrodes and on the semiconductor substrate therebetween. Therefore, the metal silicide layer is formed on the exposed gate electrodes and on the heavily doped impurity diffusion layer.
- In another exemplary embodiment, the gate electrodes may be formed of polysilicon and tungsten silicide or formed of polysilicon and tungsten that are sequentially stacked. In this case, during an etch back process following the formation of sacrificial insulation layer, the upper parts of gate electrodes are exposed at the cell region and the peripheral circuit region. The sacrificial insulation layer of the cell region remains on the sidewalls of the gate electrodes and the semiconductor substrate therebetween. Thus, the metal silicide layer may be formed only on the semiconductor substrate at both sides of the gate electrodes of the peripheral circuit region, that is, only on the heavily doped impurity diffusion layer.
- After forming the sacrificial insulation layer and before performing the etch back process, the photoresist pattern covering the cell region may be further formed. In this case, a metal silicide layer may not be formed at the cell region.
- After forming the metal silicide layer, a step of forming a protection liner layer may be further performed in order to protect the metal silicide layer.
- In the above method(s), a step of removing the buffer insulation layer may be further performed. Thus, an area of the upper part of the self-aligned contact pad increases to be capable to improve a margin of the subsequent process.
- In the above method, the first liner layer, the second liner layer and the shield liner layer are formed of silicon nitride. The sacrificial insulation layer and the buffer insulation layer are formed of silicon oxide. More specifically, the interlayer insulation layer is formed of oxide having good step coverage and the buffer insulation layer is formed of oxide having poor step coverage.
- According to the method, with adjusting the thickness of the interlayer insulation layer, the temporary sidewall spacers, which are formed from the sacrificial insulation layer at the peripheral circuit region, can be easily formed relatively thick. In addition, an individual photolithographic etching process for forming a silicide layer at the cell region and the peripheral circuit region is not required, such that the process is simplified and a silicide layer can be more easily formed.
- In certain embodiments, semiconductor assemblies with self-aligned contact pads can include a cell array region and a peripheral circuit region on the semiconductor substrate. The cell array region can include: (a) first and second gate electrodes disposed on a semiconductor substrate, the first and gate electrodes having opposing first and second sidewalls and top and bottom surfaces, wherein portions of the adjacent sidewalls of the first and second gate electrodes are configured to angle generally downwardly and inwardly toward each other; (b) a contact window positioned between the adjacent sidewalls of the first and second gate electrodes, wherein the contact window sidewalls comprise an angled profile that correspond to the angled gate electrode sidewalls; and (c) a contact pad disposed in the contact window, the contact pad extending generally downwardly and having a length that is greater than the height of the gate electrode. The peripheral circuit region is disposed on the semiconductor substrate spaced apart from the cell array region. The peripheral circuit region can include: (a) at least one gate electrode; (b) lightly doped impurity diffusion regions in the semiconductor substrate positioned on opposing sides of the at least one gate electrode; and (c) heavily doped impurity diffusion regions in the semiconductor substrate positioned on opposing sides of the at least one gate electrode so that the heavily doped impurity diffusion regions reside a further distance away from the at least one gate electrode and so that the heavily doped impurity diffusion regions abut the lightly doped impurity diffusion regions.
-
FIG. 1 is a cross-sectional view schematically showing a self-aligned contact structure in accordance with embodiments of the present invention. -
FIG. 2 is a cross-sectional view schematically showing a self-aligned contact structure and other structures in accordance with other embodiments of the present invention. -
FIGS. 3A through 3I are cross-sectional views showing operations of a method for forming a self-aligned contact structure and/or other intermediate and resultant structures in accordance with embodiments of the present invention. -
FIGS. 4A through 4J are cross-sectional views showing operations of a method for simultaneously forming silicide layers in a cell region and in a peripheral circuit region using methods for forming a self-aligned contact structure and/or other intermediate and resultant structures in accordance with embodiments of the present invention. -
FIGS. 5A through 5B are cross-sectional views showing operations of methods for simultaneously forming a silicide layer in a cell region and in a peripheral region using methods for forming a self-aligned contact structure and/or other structures in accordance with embodiments of the present invention. - The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. Like numbers refer to like elements and repeated explanation of identical elements may be avoided with reference to subsequent figures in the specification. In the figures, certain features, layers or components may be exaggerated for clarity. When a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers, films, coatings and the like may also be present unless the word “directly” is used which indicates that the feature or layer directly contacts the feature or layer. In addition, spatially relative terms, such as “beneath”, “below”, “lower”, “above”, “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
- As used herein, the terms “liner layer”, formation of the “liner layer,” or derivatives thereof, mean a layer that has a substantially uniform thickness along an entire target outline of a lower and/or underlying structure or a formation of the same. The liner layer may be configured to be substantially conformal to an underlying material layer or structure so as to provide substantially the same shaped profile as the underlying structure.
-
FIG. 1 shows a cross-sectional view of a self-aligned contact structure in accordance with an exemplary embodiment of the present invention.Gate electrodes 160 can be configured to run substantially parallel with, but separated apart from, each other on asemiconductor substrate 100. Each of thegate electrodes 160 may comprise a polysilicon single-layered structure, a double-layered structure of polysilicon and tungsten silicide, and/or polysilicon and tungsten. In certain embodiments, such as when thegate electrode 160 comprises a polysilicon single-layered structure, a metal silicide layer may be formed on the polysilicon layer. - As also shown in
FIG. 1 , for electrical insulation, agate oxide layer 140 can be interposed between thegate electrodes 160 and thesemiconductor substrate 100. Impurity diffusion regions (i.e., conductive regions) 180 can be formed in thesemiconductor substrate 100. Theconductive regions 180 may be formed at both sides of thegate electrodes 160 as shown. An interlayer insulation and/ordielectric layer 220 can be disposed on thesemiconductor substrate 100. A self-alignedcontact window 240 can be configured to penetrate theinterlayer insulation layer 220 to expose theimpurity diffusion region 180 between thegate electrodes 160. The self-alignedcontact window 240 can be configured to expose both the top of thegate electrode 160 and theimpurity diffusion regions 180, respectively. - The self-aligned
contact window 240 can be positioned intermediateadjacent gate electrodes 160 and configured with longitudinally extending opposing sidewalls that may extend to contact and/or terminate at thediffusion region 180. The sidewalls of the self-alignedcontact window 240 can be defined by theinterlayer insulation layer 220 and adjacent sides of neighboringgate electrodes 160. The bottom of thecontact window 240 can end at and/or be formed by theimpurity diffusion region 180. That is, the self-alignedcontact window 240 includes a channel that has downwardly extending sidewalls that can be formed by the stacked configuration of theinterlayer insulation layer 220, sidewalls of neighboringgate electrodes 160, theliner layer 200 formed over a lower portion of thegate electrode 160 sidewalls that terminate into a bottom formed by theimpurity diffusion region 180. - Stated differently, an
upper sidewall 240 a of the self-alignedcontact window 240 may be defined by an etched out portion of theinterlayer insulation layer 220. Anintermediate sidewall 240 b of the self-alignedcontact window 240 may be defined by an intermediate portion of the sidewall of agate electrode 160. Alower sidewall 240 c of the self-alignedcontact window 240 can be defined by aliner layer 200 disposed on the lower sidewall of thegate electrode 160. A bottom 240 d of the self-alignedcontact window 240 can be defined by theimpurity diffusion region 180. - The self-aligned
contact window 240 exposes the upper portion of thegate electrode 160. In addition, as shown, the intermediate portion of thesidewall 240 b of thecontact window 240 can be defined by etching the innermost perimeter and/or boundary of the upper portion ofadjacent gate electrodes 160, such that a profile of thecontact window 240 may be inclined. That is, the upper portion of thegate electrode 160 and the corresponding intermediate portion of thecontact window sidewall 240 b have a profile with a slope that travels inwardly to narrow as the self-alignedcontact window 240 approaches theimpurity diffusion region 180 and widens as thecontact window 240 approaches the upper portion of thegate electrodes 160. Thus, a bottom width of thegate electrode 160 is wider than a top width thereof. - In certain embodiments, the
gate electrodes 160 can include at least one liner layer that conforms to and covers substantially the entire exposed perimeter and/or upper portion thereof (that is, both opposing sidewalls and the top of the gate electrode but not the bottom). As shown, the upper portion of thegate electrode 160 is covered by either afirst liner layer 200 and/or asecond liner layer 260. Thesecond liner layer 260 is disposed on a minor portion of the perimeter, typically the upper and intermediate portion of one sidewall of the gate electrode 160 (i.e., the intermediate portion of thesidewall 240 b of the self aligned contact window 240). Thefirst liner layer 200 can be disposed on the remainder of the exposed perimeter of thegate electrode 160. As a result, the exposed perimeter ofgate electrodes 160 are covered and/or surrounded by thin liner layers 200 and 260. In particular embodiments, the liner layer may be thin, which includes a layer that has a thickness of about 100 Å or less. - As shown in
FIGS. 1 and 2 , thesecond liner layer 260 can be configured to continuously extend from theupper sidewall 240 a to thelower sidewall 240 c of the self-alignedcontact window 240. - The self-aligned
contact window 240 can be substantially entirely filled with a conductive material (the conductive material can be disposed on and/or over the second liner layer 260) to form a self-alignedcontact pad 300 a. That is, the self-alignedcontact pad 300 a is electrically connected to theimpurity diffusion region 180 betweenadjacent gate electrodes 160 but electrically insulated from thegate electrodes 160 by the liner layers 200 and 260. - In certain embodiments, the contact structure comprises liner layers 200 and 260, which can include a silicon nitride layer, and the
interlayer insulation layer 220, which can include a silicon oxide layer. - According to embodiments of the present invention, the self-aligned contact structure can be configured so that the exposed upper surfaces (the surfaces facing away from the substrate 100) of the
gate electrode 160 are surrounded by the thin liner layers 200 and 260 on the upper perimeter, and thegate oxide layer 140 on the bottom or lower perimeter, such that a height of thegate electrode 160 can be lower than in certain conventional configurations. As a result, a deposition thickness of theinterlayer insulation layer 220 can be reduced and production cost and time may also be reduced. In addition, the distance and/or spacing between neighboringgate electrodes 160 can increase due to the liner employing reduced space under a given minimum line width. Thus, contact resistance between theimpurity diffusion region 180 and the self-alignedcontact pad 300 a can be improved. In addition, the upper portion of thegate electrode 160 can be surrounded by a thin (typically nitride)liner layer -
FIG. 2 shows a schematic of a self-aligned contact structure in accordance with another exemplary embodiment of the present invention. Compared withFIG. 1 , abuffer insulation layer 280 a is further interposed between thesecond liner layer 260 disposed on theupper sidewall 240 a of a self-alignedcontact window 240 and a self-alignedcontact pad 300 a. Thebuffer insulation layer 280 a can comprise silicon oxide. This configuration may allow the, loading capacitance to be even further reduced. - A method for forming the self-aligned contact structure will be explained with reference to
FIGS. 3A through 3I . For brevity and/or clarity, only afew gate electrodes 160, one self-alignedcontact window 240 and onecontact pad 300 a are illustrated in the drawings. - Referring to
FIG. 3A , adevice isolation layer 120 is formed in asemiconductor substrate 100 using a conventional method. For example, a shallow trench isolation (STI) method or a local oxidation of silicon (LOCOS) method can be employed. - A thermal oxidation process can be performed to form a
gate oxide layer 140 on an entire target surface of the semiconductor substrate. Then, a conductive material is formed on thegate oxide layer 140 and the conductive material is patterned to formgate electrodes 160. Thegate electrodes 160 are arranged to be parallel and spaced apart from each other by a predetermined distance (i.e., a distance corresponding to a minimum line width). For example, each of thegate electrodes 160 may comprise a polysilicon single-layered structure or a double-layered structure of polysilicon and tungsten silicide or polysilicon and tungsten that are sequentially stacked, respectively. In contrast to conventional methods, a capping nitride layer is not required to be formed on thegate electrodes 160. - The
gate electrode 160 can comprise polysilicon, and the polysilican may be re-oxidized. Then, an ion implantation process can be performed using thegate electrodes 160 as an ion implantation mask in order to form a conductive region, i.e.,impurity diffusion regions 180. Theimpurity diffusion regions 180 can be formed in the substrate on both sides of thegate electrodes 180. - Next, referring to
FIG. 3B , aliner layer 200 can be a substantially continuous layer that is formed over asemiconductor substrate 100, over the exposed upper surfaces of thegate electrodes 160, and over theimpurity diffusion layer 180. Theliner layer 200 comprises a material having etch selectivity with respect to theinterlayer insulation layer 220 that will be formed in a subsequent process. For example, when theinterlayer insulation layer 220 is formed of silicon oxide, theliner layer 200 can be formed of silicon nitride. In the present invention, sidewall spacers are not required to be formed on sidewalls of the gate electrode. - According to an exemplary embodiment, a thin silicon nitride layer is conformally formed as the
liner layer 200. In contrast to previous methods, in certain embodiments, theliner layer 200 of the present invention can be configured as a thin layer having a thickness of, for example, about 100 Å or less. Therefore, contrary to the conventional method, the separation distance between adjacent gate structures (which in the past typically included spacers) can be about 300-500 Å or more under an identical design rule used in conventional configurations. This separation distance may improve contact resistance between theimpurity diffusion layer 180 and a self-aligned contact pad (300 a,FIG. 1 ) that will be formed in a subsequent process. - Referring to
FIG. 3C , aninterlayer insulation layer 220 is formed on theliner layer 200 in art amount sufficient to cover the space between thegate electrodes 160. In an exemplary embodiment, theinterlayer dielectric layer 220 can be formed of silicon oxide. In particular embodiments, theinterlayer dielectric layer 220 is formed of silicon oxide having good step coverage. A mask pattern, for example, a photoresist pattern (not shown) can be formed on theinterlayer insulation layer 220. The pattern defines a self-aligned contact window (240,FIG. 1 ). - Referring to
FIG. 3D , using the photoresist pattern as an etching mask, the exposedinterlayer insulation layer 220 can be etched. In certain embodiments, theinterlayer insulation layer 220 is selectively etched with respect to theliner layer 200 to form the self-alignedcontact window 240. While the etching is performed, thethin liner layer 200 of a top edge of arespective gate electrode 160 may be weakened by repeated etching. Therefore, a top edge portion and an upper sidewall portion of thethin liner layer 200 on thegate electrode 160 is etched and then a corresponding portion of the exposedgate electrode 160 can be etched to provide an inclined profile at a respective top edge and upper sidewall (typically ending at an intermediate) portion of thegate electrode 160. Meanwhile, because theinterlayer insulation layer 220 is selectively etched, the lower portion of thegate electrodes 160 and theliner layer 200 formed on thesemiconductor substrate 100 therebetween remain intact (i.e., are not etched away). Therefore, the separation distance between thegate electrodes 160 can be substantially uniform, that is, a minimum substantially uniform line width can be generated. - The formed self-aligned
contact window 240 may be described as having anupper sidewall 240 a, amiddle sidewall 240 b, alower sidewall 240 c, and a bottom 240 d. Theupper sidewall 240 a of the self-alignedcontact window 240 is defined by theinterlayer insulation layer 220. Themiddle sidewall 240 b is defined by the sloped gate electrode (i.e., the upper sidewall portion of the gate electrode 160). Thelower sidewall 240 c is defined by theliner layer 200 residing over the lower sidewall of thegate electrode 160. The bottom 240 d is defined by theliner layer 200 on theimpurity diffusion region 180 betweenadjacent gate electrodes 160. - In the etching process for forming the self-aligned
contact window 240, the upper sidewall portion of thegate electrode 160 can be etched to provide a sloped profile. - Referring to
FIG. 3E , a gateprotection liner layer 260 can be formed to cover the exposed upper portion of thegate electrode 160. Therefore, the exposed upper surfaces of thegate electrodes 160 can be completely covered and/or protected by the liner layers 200 and 260. As shown inFIG. 3E , the upper portion of thegate electrode 160 is covered by the gateprotection liner layer 260 and the remaining portion of the upper surfaces of the gate electrode is protected by theliner layer 200. The gateshield protection layer 260 may be formed of the same material as theliner layer 200, for example, silicon nitride. In addition, theprotection liner layer 260 can be formed to about 200 Å or less. As shown inFIG. 3E andFIG. 1 , the gateprotection liner layer 260 may overlie a lower portion of theliner layer 200 at a lower portion of thesidewall 240 c. - Next, referring to
FIGS. 3F and 3G , liner layers 200 and 260 formed on the bottom of thecontact window 240 d can be removed to expose theimpurity diffusion layer 180. First, referring toFIG. 3F , abuffer insulation layer 280 having relatively poor step coverage can be formed on the gate protection and/orshield liner layer 260 to cause overhang (i.e., thebuffer insulation layer 280 material resides above the top of the gate and overhangs thecontact window 240 to extend down into the contact window 240). Thebuffer insulation layer 280 can be formed of differential thickness along thewindow 240 so that it is relatively thin on the bottom 240 d andlower sidewalls 240 c of the self alignedcontact window 240, but formed with increased thickness on themiddle sidewall 240 b and theupper sidewall 240 a of the self-alignedcontact window 240. Anopening 250 in thebuffer insulation layer 280 can extend downwardly to terminate substantially at and/or expose the bottom of thecontact window 240 d. - The
buffer insulation layer 280 can be formed of silicon oxide using, for example, chemical vapor deposition. As described above, the upper part of thecontact window 240 b has a sloped profile, such that the overhang can be more easily formed. - Referring to
FIG. 3G , an etch-back process can be applied to the stacked surface of thesemiconductor substrate 100 holding the buffer insulation layer 280 (FIG. 3F ). Thebuffer insulation layer 280 and the liner layers 200, 260 are simultaneously etched in the etch-back process. Thus, where thebuffer insulation layer 280 is configured sufficiently thin, thebuffer insulation layer 280 and the liner layers 200, 260 thereunder are removed to expose the underlying material or surface, such as theimpurity diffusion region 180. The thin portion of thebuffer insulation layer 280 and the liner layers 200, 260 thereunder are on the bottom 240 d of thecontact window 240 that is exposed through theopening 250 defined by thebuffer insulation layer 280. In this case, because thebuffer insulation layer 280 is formed with increased thickness on the intermediate and upper portion of thesidewalls contact window 240, a portion of thebuffer insulation layer 280 can remain as aspacer 280 a after the etch-back process is carried out to expose theimpurity diffusion region 180. Accordingly, the residualbuffer insulation layer 280 a protects the liner layers 260 and/or 200 on themiddle sidewalls 240 c and theupper sidewall 240 b of thecontact window 240 so that the underlying liner(s) is not exposed during the etch-back process. The gateprotection liner layer 260 is formed before a formation of aconductive layer 300. Therefore, even though voids may occur when theinterlayer dielectric layer 220 is formed, electrical bridging is inhibited and/or prevented. - Depending on manufacturing processes employed and/or desired applications, the
protection liner layer 260 may be etched. - Referring to
FIG. 3H , thecontact window 240 is filled withconductive material 300. Subsequently, an etching process can be carried out to remove excessconductive material 300 until theinterlayer insulation layer 220 is exposed at the upper part thereof. The etching process can be performed to form a self-alignedcontact pad 300 a as illustrated inFIG. 3I . The residualbuffer insulation layer 280 a may optionally be removed and then conductive material may be provided as a filler as desired. In this case, the cross-sectional size of the upper portion of thecontact pad 300 a increases, so that the subsequent process margin may also increase. - According to embodiments of the present invention for forming the self-aligned
contact pads 300 a, a capping layer and a spacer layer are not required to be formed on the upper portion and the sidewall of the gate electrode, respectively. This is an aspect that is contrary to the conventional method. Therefore, a silicide layer can be easily formed at the peripheral circuit area and the cell area where a memory device is formed at the same time. - Referring to
FIG. 4A , a device isolation process is illustrated to form adevice isolation layer 120 that defines an active region in thesemiconductor substrate 100 with a cell array region “a” and a peripheral circuit region “b”. Agate oxide layer 140 is formed on a surface of thesemiconductor substrate 100 by a thermal oxidation process. Then, a conductive layer for forming a gate electrode is formed on thegate oxide layer 140. The gate electrode conductive layer is patterned to formgate electrodes semiconductor substrate 100, respectively. In the cell array region “a” the gate electrodes can be densely formed, but in the peripheral region “b” the gate electrodes may be formed more sparsely. Thegate electrodes - After the
gate electrodes impurity diffusion regions semiconductor substrate 100 at both sides of thegate electrodes - Referring to
FIG. 4B , aliner layer 200 and asacrificial insulation layer 350 are formed on target exposed surfaces of thesemiconductor substrate 100 including over thegate electrodes impurity diffusion regions liner layer 200 can comprise, for example, silicon nitride. Thesacrificial insulation layer 350 can comprise, for example, silicon oxide. - The
gate electrodes 160 b can be densely formed at the cell region “a”, so that thesacrificial insulation layer 350 completely covers the lower structures including the space between thegate electrodes 160 b at the cell region “a”, and have a substantially planar top surface. However, thesacrificial insulation layer 350 may be stepped to travel about the outline of the lower structure at the peripheral circuit region “b” with thesacrificial layer 350 at region “b” having the greatest height above the underlying top surface of thegate electrode 160 a. - Referring to
FIG. 4C , an etch-back process can be applied to the surface of the stacked semiconductor substrate with thesacrificial insulation layer 350 so that thesacrificial insulation layer 350 remains only on the sidewalls of thegate electrode 160 a to formtemporary sidewall spacers 350 a at the peripheral circuit region “b”. That is, a top of thegate electrode 160 a of the peripheral circuit region “b” and portions of the lightly dopedimpurity diffusion regions 180 a at both sides of thegate electrode 160 a are exposed. In this case, the exposed lightly dopedimpurity diffusion regions 180 a, in which a heavily doped impurity diffusion regions can be formed in a subsequent process, are separated from thegate electrode 160 a as far as a predetermined distance (i.e., a width W of atemporary sidewall spacer 350 a). In other words, the width W of the lower portion of thetemporary sidewall spacers 350 a determines a length L of the lightly dopedimpurity diffusion regions 180 a that are covered with thetemporary sidewall spacers 350 a (the length L can correspond to the length of a final lightly doped impurity diffusion region). - Meanwhile, in the cell region “a”, only the top of the
gate electrode 160 b is exposed by the etch-back process for thesacrificial insulation layer 350. Thesacrificial insulation layer 350 b still remains on theimpurity diffusion region 180 b at both opposing sides of thegate electrode 160 b and on the sidewalls of thegate electrode 160 b. - By adjusting the thickness of the
sacrificial insulation layer 350, the thickness of thetemporary spacers 350 a at the peripheral region “b” can be adjusted. A distance between the exposed lightly dopedimpurity diffusion region 180 a and thegate electrode 160 a (i.e., the final length L of the lightly doped impurity diffusion region) can be controlled to a desired length/thickness. - Referring to
FIG. 4D , an ion implantation process is illustrated and may, in operation, be substantially continuously carried out. Thegate electrodes sacrificial insulation layer 350 b at a cell region “a” and thetemporary sidewall spacers 350 a at the peripheral circuit region “b” are used as an ion implantation mask. Therefore, heavily dopedimpurity diffusion regions 180 c can be formed at the peripheral circuit region “b”. The heavily dopedimpurity diffusion regions 180 c continue to the lightly dopedimpurity diffusion regions 180 a at both sides of thegate electrodes 160 a. The lightly dopedimpurity diffusion regions 180 a are formed in thesemiconductor substrate 100 under thetemporary sidewall spacers 350 a. In addition, impurity diffusion ions can be implanted into the upper or top portion of the exposedgate electrodes gate electrodes impurity diffusion regions 180 c are formed. In certain embodiments, the cell region “a” and the peripheral circuit region “b” can include, for example, NMOS transistors. The gate electrodes (not shown) for a PMOS transistor, which can be formed in the peripheral circuit region “b”, can be covered with a photoresist pattern and the top thereof may be protected. Similarly, thegate electrodes - Still referring to
FIG. 4D , silicide (or other desired material) layers 400 a, 400 b and 400 c can be substantially concurrently formed on top of thegate electrode 160 a of the exposed peripheral circuit region “b”, on the heavily dopedimpurity diffusion regions 180 c, and on the exposedgate electrodes 160 b of the exposed cell region “a”, respectively. In certain embodiments, a refractory metal having a relatively high melting point can be conformably formed and then thermally treated to cause a silicidation reaction between silicon and the refractory metal in order to form asilicide layer - Referring to
FIG. 4E , the residual sacrificial oxide layers 350 a and 350 b are removed and then a silicideshield liner layer 420 can be formed on an entire exposed surface of the stacked semiconductor substrate for protectingsilicide layers protection liner layer 420 can comprise silicon nitride. The silicideprotection liner layer 420 is optional and may be excluded. In certain embodiments, typically depending on processes, a portion of thesacrificial oxide layer 350 a remaining at the peripheral circuit region “b” may remain. That is, a portion ofsidewall spacers 350 a may remain. - Referring to
FIG. 4F , aninterlayer insulation layer 220 is formed on the silicideprotection liner layer 420. Theinterlayer insulation layer 220 can be provided so that it has a planar top surface as shown. That is to say, aninterlayer insulation layer 220 can be stacked relatively thick and then a chemical mechanical polishing (CMP) process, an etch-back or other suitable process can be performed to planarize thislayer 220. Theinterlayer insulation layer 220 is formed of material having etch selectivity with respect to theliner layer 200 and the silicideprotection liner layer 420. For example, theinterlayer insulation layer 220 can comprise and/or be formed of silicon oxide having good step coverage. - The subsequent processes can be carried out in the same way as that explained above with reference to
FIGS. 3D through 31 . Referring toFIG. 4G , in certain embodiments, theinterlayer insulation layer 220 on the cell region “a” can be etched to form a self-alignedcontact window 240. In this case, as mentioned above, thegate electrodes 160 b of the cell region “a” are etched to slope at an upper portion thereof. - Referring to
FIG. 4H , a gateshield liner layer 260 and abuffer insulation layer 280 can be formed in the same way as the method mentioned above. - Referring to
FIG. 4I , an etch-back process can be applied to the surface of the stacked semiconductor substrate with thebuffer insulation layer 280, so that liner layers 200, 260, 420 on a bottom 240 d of thecontact window 240 are removed to expose a lightly dopedimpurity diffusion region 180 b. - Referring to
FIG. 4J , conductive material is provided to thewindow 240 and formed therein, then an etching process is performed to form a self-alignedcontact pad 300 a. - As shown in
FIG. 5A , in certain embodiments, thegate electrode 160 may comprise two sequentially stacked layers of different materials, such as, for example,polysilicon 150 andtungsten silicide 155 orpolysilicon 150 andtungsten 155, instead of forming thegate electrode 160 with polysilicon as described for certain embodiments ofFIG. 4A . In the embodiment illustrated inFIG. 5B , asilicide layer 400 b can be formed to overly substantially only the heavily dopedimpurity diffusion regions 180 c that are formed in thesemiconductor substrate 100 at both sides of thegate electrode 160 a at the peripheral region “b” (i.e., thetop silicide layer 400 a is not necessary). - In certain embodiments, after forming the
sacrificial insulation layer 350, an etch-back process can be applied to a stacked surface of the semiconductor substrate. In particular embodiments, the etch back process may be performed after forming aphotoresist pattern 500 covering the cell region “a”, as illustratedFIGS. 5A and 5B . - In particular embodiments, described with reference to
FIG. 5A , agate electrode 150 is formed with a multi-layered structure ofpolysilicon 150 andtungsten silicide 155 or ofpolysilicon 150 andtungsten 155. Then, lightly dopedimpurity diffusion regions buffer insulation layer 350 is formed. - Referring to
FIG. 5B , aphotoresist pattern 500 that covers a cell region “a” is formed, and then an etch-back process can be performed to formtemporary sidewall spacers 350 a on sidewalls of thegate electrode 160 b at the peripheral circuit region “b”. Then, heavily dopedimpurity diffusion regions 180 c can be formed in the peripheral region “b” by an ion implantation process. - Next, the
photoresist pattern 500 and residual buffer insulation layers 350 and 350 a are removed. In this case, the top of thegate electrode 160 b is not exposed at a cell region “a”, such that asilicide layer 400 b is formed substantially only at the peripheral circuit region “b”. - In particular embodiments, the operations shown in
FIGS. 4E through 4J can be substantially continuously serially performed in an automated mass production process. - Embodiments of the present invention may provide one or more of the following advantages compared to conventional self-aligned contact processes. In addition, although described above with respect to semiconductor substrates and devices, the present invention is directed to integrated circuits and can include structures formed on other substrates.
- In typical conventional methods, undesired electrical bridging may occur in a subsequent process for forming a self-aligned contact pad due to voids that may be formed while an interlayer insulation layer is deposited. However, embodiments of the present invention reduce the likelihood that voids will be present when the interlayer insulation layer is formed because the sidewall spacers and the capping layer are not formed. In addition, if voids occur, electrical bridging can be inhibited because a nitride liner can be formed.
- Further, in the typical conventional methods, the gate electrode stacked structure is relatively high and the distance between the gate electrodes is narrow, such that the halo ion implantation is difficult to apply. However, in embodiments of the present invention, the spacing is such that halo ion implantation can be used. In addition, the gate electrode of the present invention can be configured with a relatively low height, so that the interlayer insulation layer can be lowered in a thickness. As a result, production cost may be reduced and/or the throughput can be improved.
- Further, in conventional methods, loading capacitance may be relatively large due to the presence of a capping nitride layer and a space nitride layer. In certain embodiments of the present invention, the loading capacitance is reduced and relatively small because of the generation of a nitride liner, thereby potentially providing improved device operational characteristics.
- As noted above, in typical conventional fabrication methods, the distance between neighboring gate electrodes may be relatively narrow owing to the use of a spacer nitride layer making it difficult to generate sufficient self-aligned contact resistance, and integration is not easy. In contrast, in embodiments of the present invention, the self-aligned contact resistance can be more easily preserved and integration can be easier.
- Still further, conventional fabrication methods may have difficulties forming a silicide layer at the cell region and the peripheral region at the same time. In certain embodiments of the present invention, the silicide layer can be simultaneously formed at the cell region and the peripheral region. Moreover, the thickness of the sidewall spacers of the gate electrode at the peripheral region may be more easily controlled.
- While the present invention has been described in connection with embodiments thereof, it is capable of various changes and modifications without departing from the spirit and scope of the invention. It should be appreciated that the scope of the invention is not limited to the detailed description of the invention hereinabove, which is intended merely to be illustrative, of the examples of subject matter encompassed by the following claims.
Claims (20)
1. A method of forming a self-aligned contact comprising:
forming gate electrodes that are spaced apart from each other on a semiconductor substrate;
forming a first liner layer on the semiconductor substrate and the gate electrodes;
forming an interlayer insulation layer over the first liner layer;
forming a contact window having opposing spaced apart sidewalls and a bottom by selectively etching the interlayer insulation layer with respect to the first liner layer;
forming a second liner layer over the interlayer insulation layer and the bottom and sidewalls of the contact window;
forming a buffer insulation layer to extend laterally a distance beyond the second liner layer to overhang in the contact window;
exposing the semiconductor substrate between adjacent gate electrodes by performing an etch back process to remove the buffer insulation layer and the second and first insulation layers at a bottom portion of the contact window; and
filling the contact window with conductive material to thereby substantially and/or entirely fill at least a lower portion of the contact window.
2. The method of claim 1 , wherein forming the contact window comprises angling the opposing sidewalls thereof so that the sidewalls travel toward each a distance along at least a portion of a length thereof.
3. The method of claim 1 , wherein the first and the second liner layers comprise silicon nitride.
4. The method of claim 1 , wherein the interlayer insulation layer comprises an oxide layer having a substantially planar surface, and the buffer insulation layer is formed of an oxide layer having an upper surface formed over the interlayer insulation layer disrupted with recesses formed into respective contact windows.
5. The method of claim 1 , wherein in the step of forming the contact window by selectively etching the interlayer insulation layer, is carried out so that an upper portion of a gate electrode is etched as well as the first liner layer thereon.
6. The method of claim 1 , wherein in the step of exposing the semiconductor substrate is carried out so that the first and second liner layers on the upper and intermediate portions of the sidewalls of the contact window are protected by the buffer insulation layer but the first and second liner layers on the bottom of the contact window are etched away, and wherein, the buffer insulation layer remains on the upper and intermediate portions of the sidewalls of the contact window to form buffer insulation sidewall spacers while the buffer insulation layer on the bottom of the contact window is etched away.
7. The method of claim 1 , wherein, after forming the first liner layer and before forming the interlayer insulation layer, the method further comprises:
forming a sacrificial insulation layer;
exposing an upper portion of a gate electrode by etching back the sacrificial insulation layer leaving residual portions of the sacrificial insulation layer;
forming a metal silicide layer on the exposed upper portion of the gate electrode; and
removing the residual portions of the sacrificial insulation layer.
8. A method of forming a self-aligned contact comprising:
forming gate electrodes that are spaced apart from each other with a plurality of the gate electrodes positioned at a cell array region and at least one gate electrode positioned at a peripheral circuit region of the semiconductor substrate, respectively;
forming a first liner layer over the semiconductor substrate and surfaces of the gate electrodes;
forming a sacrificial insulation layer on the first liner layer in an amount sufficient to cover spaces between the gate electrodes of the cell array region;
etching back the sacrificial insulation layer so as to form temporary sidewall spacers on sidewalls of the at least one gate electrode at the peripheral circuit region;
forming a metal silicide layer at least on the semiconductor substrate exposed adjacent the temporary sidewall spacers; then
removing the sacrificial insulation layer remaining at the cell array region and the temporary sidewall spacers of the peripheral circuit region;
forming an interlayer insulation layer having a substantially planar top surface;
selectively etching the interlayer insulation layer with respect to the first liner layer to form at least one contact window in the cell array region between adjacent first and second gate electrodes, the contact window having opposing spaced apart sidewalls and a bottom;
forming a second liner layer on the sidewalls and bottom of the contact window;
forming a buffer insulation layer on the second liner layer so that the buffer insulation layer extends a lateral distance into the contact window to leave a gap space in the contact window, the buffer insulation layer having a greater thickness at a top portion of the sidewalls of the contact window than at a lower portion of the sidewalls of the contact window;
exposing the semiconductor substrate between the gate electrodes of the cell array region by performing an etch back process; and
filling at least a lower portion of the contact window with conductive material.
9. The method of claim 8 , wherein in the step of forming a contact window by selectively etching the interlayer insulation layer, the first liner layer is etched exposing a selected upper portion of the gate electrodes of the cell array region allowing the selected upper portion of the gate electrodes to be removed by the etching while the lower portion is protected from the etching, thereby generating a gate electrode that has an inclined side profile.
10. The method of claim 8 , wherein the exposing step is carried out so that the first and/or second liner layers on the upper, intermediate, and/or lower sidewall portions of the contact window are protected by the buffer insulation layer, but the first and second liner layers on the bottom of the contact window are etched away, and wherein the buffer insulation remains on sidewalls of the upper and intermediate portions of the contact window to form sidewall spacers while the buffer insulation layer on the bottom of the contact window is etched away.
11. The method of claim 8 , further comprising,
after forming the gate electrodes:
forming lightly doped impurity diffusion regions in the semiconductor substrate at both sides of the gate electrodes using ion implantation; and
after forming the sidewall spacers, performing a second ion implantation process in the peripheral circuit region to form heavily doped impurity diffusion regions, which are spatially positioned proximate the lightly doped impurity diffusion regions, in the semiconductor substrate, at both sides of the temporary sidewall spacers, so that the heavily doped regions reside a greater distance away from the gate electrode than the lightly doped regions.
12. The method of claim 11 , wherein the gate electrodes comprise polysilicon, wherein when in an etch back process the sacrificial insulation layer is removed to expose top portions of the gate electrodes at the cell array region and the peripheral circuit region, and the sacrificial insulation layer remains on the sidewalls of the gate electrodes and on the semiconductor substrate therebetween in the cell array region but is removed with the first liner layer in the peripheral circuit region to expose the semiconductor substrate proximate the sidewall spacers, and wherein a metal silicide layer is concurrently formed on the exposed semiconductor substrate over the heavily doped impurity diffusion regions of the peripheral circuit region and on the exposed top portions of the gate electrodes.
13. The method of claim 8 , wherein, after forming the gate electrodes, performing ion implantation to form lightly doped impurity diffusion regions in the semiconductor substrate at both sides of the gate electrodes; and
after forming the temporary sidewall spacers, performing ion implantation to form heavily doped impurity diffusion regions which terminate into the lightly doped impurity diffusion regions of the peripheral circuit region in the semiconductor substrate at both sides of the temporary sidewall spacers.
14. The method of claim 13 , wherein the gate electrodes comprise a double-layered structure of polysilicon and tungsten silicide or of polysilicon and tungsten that are sequentially stacked,
wherein in an etch back process after forming the sacrificial insulation layer, the upper portions of the gate electrodes of the cell region and peripheral circuit region are exposed while the sacrificial insulation layer remains on the sidewalls of the gate electrodes and on the semiconductor substrate therebetween, and
wherein the forming the metal silicide layer comprises forming the metal silicide layeron the semiconductor substrate over the heavily doped impurity diffusion regions of the peripheral circuit area.
15. The method of claim 8 , after forming the sacrificial insulation layer and before performing the etch back process, the method further comprises forming a photoresist pattern that covers the top surface of the cell array region.
16. The method of claim 8 , after forming the metal silicide layer, further comprising a step of forming a protection liner layer thereover for protecting the metal silicide layer.
17. The method of claim 8 , further comprising removing at least a portion of the buffer insulation layer from the contact window before filling the contact window with conductive material.
18. The method of claim 16 , wherein the first liner layer, the second liner layer, and the protection liner layer comprise silicon nitride.
19. The method of claim 8 , wherein the interlayer insulation layer comprises an oxide that is applied to be substantially continuous over the underlying structure with a planar surface, and wherein the buffer insulation layer comprises an oxide that is configured with a substantially planar upper surface and a recess that extends down into the contact window and provides a gap space therein.
20. A method of forming a self-aligned contact window configured to hold a self-aligned contact pad therein in communication with a semiconductor substrate, comprising:
removing a selected portion of an interlayer insulation layer and then an underlying upper portion of adjacent sidewalls of first and second gate electrodes held proximate to each other on a semiconductor substrate to form first and second gate electrodes with sloped sidewalls that angle toward each other and define a portion of the shape of sidewalls of a self-aligned contact window configured to hold a self-aligned contact pad therein.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/395,270 US20060170062A1 (en) | 2002-10-31 | 2006-03-31 | Self-aligned semiconductor contact structures and methods for fabricating the same |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2002-0066874A KR100467023B1 (en) | 2002-10-31 | 2002-10-31 | Self-aligned contact structure and method for fabricating the same |
KR2002-66874 | 2002-10-31 | ||
US10/695,061 US7071517B2 (en) | 2002-10-31 | 2003-10-29 | Self-aligned semiconductor contact structures and methods for fabricating the same |
US11/395,270 US20060170062A1 (en) | 2002-10-31 | 2006-03-31 | Self-aligned semiconductor contact structures and methods for fabricating the same |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/695,061 Division US7071517B2 (en) | 2002-10-31 | 2003-10-29 | Self-aligned semiconductor contact structures and methods for fabricating the same |
Publications (1)
Publication Number | Publication Date |
---|---|
US20060170062A1 true US20060170062A1 (en) | 2006-08-03 |
Family
ID=32171566
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/695,061 Expired - Fee Related US7071517B2 (en) | 2002-10-31 | 2003-10-29 | Self-aligned semiconductor contact structures and methods for fabricating the same |
US11/395,270 Abandoned US20060170062A1 (en) | 2002-10-31 | 2006-03-31 | Self-aligned semiconductor contact structures and methods for fabricating the same |
US11/396,819 Expired - Fee Related US7397131B2 (en) | 2002-10-31 | 2006-04-03 | Self-aligned semiconductor contact structures |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/695,061 Expired - Fee Related US7071517B2 (en) | 2002-10-31 | 2003-10-29 | Self-aligned semiconductor contact structures and methods for fabricating the same |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/396,819 Expired - Fee Related US7397131B2 (en) | 2002-10-31 | 2006-04-03 | Self-aligned semiconductor contact structures |
Country Status (4)
Country | Link |
---|---|
US (3) | US7071517B2 (en) |
JP (1) | JP2004153251A (en) |
KR (1) | KR100467023B1 (en) |
CN (1) | CN100565808C (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090050959A1 (en) * | 2007-08-21 | 2009-02-26 | Madson Gordon K | Method and Structure for Shielded Gate Trench FET |
US20090321817A1 (en) * | 2008-06-26 | 2009-12-31 | Hunt Scott L | Structure and Method for Forming a Shielded Gate Trench FET with an Inter-Electrode Dielectric Having a Nitride Layer Therein |
US8642425B2 (en) | 2012-05-29 | 2014-02-04 | Semiconductor Components Industries, Llc | Method of making an insulated gate semiconductor device and structure |
US20140159115A1 (en) * | 2012-12-11 | 2014-06-12 | Eelectronics and Telecommunications Research Institute | Transistor and method of fabricating the same |
Families Citing this family (42)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100467023B1 (en) * | 2002-10-31 | 2005-01-24 | 삼성전자주식회사 | Self-aligned contact structure and method for fabricating the same |
JP3946724B2 (en) * | 2004-01-29 | 2007-07-18 | シャープ株式会社 | Manufacturing method of semiconductor device |
US7718479B2 (en) * | 2004-08-25 | 2010-05-18 | Intel Corporation | Forming integrated circuits with replacement metal gate electrodes |
KR100550345B1 (en) * | 2004-10-11 | 2006-02-08 | 삼성전자주식회사 | Method for forming silicide layer of semiconductor device |
JP2006245578A (en) * | 2005-02-28 | 2006-09-14 | Hynix Semiconductor Inc | Manufacturing method of semiconductor device |
CN100442476C (en) | 2005-09-29 | 2008-12-10 | 中芯国际集成电路制造(上海)有限公司 | Nano-device with enhanced strain inductive transferring rate for CMOS technology and its process |
US7223650B2 (en) * | 2005-10-12 | 2007-05-29 | Intel Corporation | Self-aligned gate isolation |
CN1959959B (en) * | 2005-10-31 | 2010-04-21 | 中芯国际集成电路制造(上海)有限公司 | Single mask design method and structure in use for integrating PMOS and MMOS transistors of strain silicon |
KR100654000B1 (en) * | 2005-10-31 | 2006-12-06 | 주식회사 하이닉스반도체 | Method of manufacturing semiconductor device having metal silicide layer |
KR100732272B1 (en) * | 2006-01-26 | 2007-06-25 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
US20070197021A1 (en) * | 2006-02-21 | 2007-08-23 | Hynix Semiconductor Inc. | Semiconductor device including spacer with nitride/nitride/oxide structure and method for fabricating the same |
JP4667279B2 (en) * | 2006-03-14 | 2011-04-06 | Okiセミコンダクタ株式会社 | Manufacturing method of semiconductor device |
KR100843550B1 (en) * | 2006-11-06 | 2008-07-04 | 삼성전자주식회사 | Nonvolatile memory devices and Method of fabricating the same |
US7968949B2 (en) * | 2007-01-30 | 2011-06-28 | International Business Machines Corporation | Contact forming method and related semiconductor device |
US7772064B2 (en) * | 2007-03-05 | 2010-08-10 | United Microelectronics Corp. | Method of fabricating self-aligned contact |
KR20090000324A (en) * | 2007-06-28 | 2009-01-07 | 주식회사 하이닉스반도체 | Method of forming a contact plug in semiconductor device |
CN101364545B (en) | 2007-08-10 | 2010-12-22 | 中芯国际集成电路制造(上海)有限公司 | Germanium-silicon and polycrystalline silicon grating construction of strain silicon transistor |
KR20090097737A (en) | 2008-03-12 | 2009-09-16 | 삼성전자주식회사 | Nonvolatile memory device having buried shield plate and method for manufacturing the same |
KR20110003191A (en) * | 2009-07-03 | 2011-01-11 | 삼성전자주식회사 | Methods of fabricating device isolation layer and semiconductor device |
JP5673536B2 (en) | 2009-07-21 | 2015-02-18 | 日亜化学工業株式会社 | Manufacturing method of conductive material, conductive material obtained by the method, electronic device including the conductive material, and light emitting device |
CN102024761A (en) | 2009-09-18 | 2011-04-20 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor integrated circuit device |
KR101194919B1 (en) * | 2010-07-06 | 2012-10-25 | 에스케이하이닉스 주식회사 | Semiconductor device and method for forming the same |
KR20120102932A (en) * | 2011-03-09 | 2012-09-19 | 에스케이하이닉스 주식회사 | Method of fabricating a semiconductor device |
US20120244700A1 (en) * | 2011-03-22 | 2012-09-27 | Globalfoundries Inc. | Methods for fabricating semiconductor devices including metal silicide |
JP2013187335A (en) * | 2012-03-07 | 2013-09-19 | Toshiba Corp | Semiconductor device and manufacturing method of the same |
US8921947B1 (en) * | 2013-06-10 | 2014-12-30 | United Microelectronics Corp. | Multi-metal gate semiconductor device having triple diameter metal opening |
CN105097813B (en) * | 2014-05-12 | 2018-10-23 | 中芯国际集成电路制造(上海)有限公司 | The contact structures and its manufacturing method of flash memory |
KR102243492B1 (en) | 2014-07-21 | 2021-04-23 | 삼성전자주식회사 | Semiconductor device and method for manufacturing the same |
KR102317023B1 (en) * | 2014-08-14 | 2021-10-26 | 삼성전자주식회사 | semiconductor device, method and apparatus for manufacturing the same |
CN105575946A (en) * | 2014-10-16 | 2016-05-11 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and formation method thereof |
KR102342079B1 (en) | 2015-05-20 | 2021-12-21 | 삼성전자주식회사 | Method for fabricating semiconductor device |
KR20170020604A (en) | 2015-08-12 | 2017-02-23 | 삼성전자주식회사 | A method for manufacturing semiconductor device |
US10580650B2 (en) * | 2016-04-12 | 2020-03-03 | Tokyo Electron Limited | Method for bottom-up formation of a film in a recessed feature |
US10068799B2 (en) * | 2016-06-27 | 2018-09-04 | International Business Machines Corporation | Self-aligned contact |
US10037918B2 (en) | 2016-11-29 | 2018-07-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Contact structure and method of fabricating the same |
DE102017117800B4 (en) * | 2016-12-29 | 2024-03-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor devices and methods for their manufacture |
US10872980B2 (en) | 2017-04-25 | 2020-12-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
JP2019153694A (en) * | 2018-03-02 | 2019-09-12 | 東芝メモリ株式会社 | Semiconductor device and manufacturing method therefor |
US10593599B2 (en) * | 2018-03-07 | 2020-03-17 | Globalfoundries Inc. | Contact structures |
KR102560695B1 (en) * | 2018-09-05 | 2023-07-27 | 삼성전자주식회사 | Integrated circuit devices |
US10950497B2 (en) * | 2018-11-26 | 2021-03-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Electrical connection for semiconductor devices |
KR20210024384A (en) * | 2019-08-23 | 2021-03-05 | 삼성전자주식회사 | Semiconductor device and method of fabricating the same |
Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5470777A (en) * | 1991-05-24 | 1995-11-28 | Texas Instruments Incorporated | Method of fabricating random access memory device having sidewall insulating layer on the laminate structure |
US5556373A (en) * | 1992-09-16 | 1996-09-17 | Motloch; Wallace M. | Body-worn orthopedic device that includes individual connected modules, and a method of manufacturing and designing such an orthopedic device |
US6043116A (en) * | 1998-03-04 | 2000-03-28 | United Microelectronics Corp. | Method of fabricating self-align-contact |
US6078492A (en) * | 1998-04-21 | 2000-06-20 | United Microelectronics Corp. | Structure of a capacitor in a semiconductor device having a self align contact window which has a slanted sidewall |
US6177319B1 (en) * | 1999-01-16 | 2001-01-23 | United Microelectronics Corp. | Method of manufacturing salicide layer |
US6284596B1 (en) * | 1998-12-17 | 2001-09-04 | Taiwan Semiconductor Manufacturing Company | Method of forming split-gate flash cell for salicide and self-align contact |
US6294449B1 (en) * | 1999-11-23 | 2001-09-25 | International Business Machines Corporation | Self-aligned contact for closely spaced transistors |
US20020079492A1 (en) * | 2000-11-15 | 2002-06-27 | Hiroki Koga | Semiconductor device and method of manufacturing the same |
US20020195672A1 (en) * | 1999-11-30 | 2002-12-26 | Samsung Electronics Co., Ltd. | Method of forming a MOS transistor in a semiconductor device and a MOS transistor fabricated thereby |
US20030122185A1 (en) * | 2001-12-27 | 2003-07-03 | Wang Chih Hsin | Self aligned method of forming a semiconductor memory array of floating gate memory cells with horizontally oriented edges, and a memory array thereby |
US6734564B1 (en) * | 1999-01-04 | 2004-05-11 | International Business Machines Corporation | Specially shaped contact via and integrated circuit therewith |
US7397131B2 (en) * | 2002-10-31 | 2008-07-08 | Samsung Electronics Co., Ltd. | Self-aligned semiconductor contact structures |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09260656A (en) * | 1996-03-25 | 1997-10-03 | Toshiba Corp | Method for manufacturing semiconductor device |
EP0967640A3 (en) * | 1998-06-25 | 2000-01-05 | Siemens Aktiengesellschaft | Method of making a self-aligned contact |
KR100284905B1 (en) * | 1998-10-16 | 2001-04-02 | 윤종용 | Contact Forming Method of Semiconductor Device |
KR20000046812A (en) * | 1998-12-31 | 2000-07-25 | 김영환 | Method of manufacturing semiconductor device |
KR20010008839A (en) * | 1999-07-05 | 2001-02-05 | 윤종용 | Method of forming self-aligned contacts in semiconductor device |
JP2001230383A (en) * | 2000-02-16 | 2001-08-24 | Hitachi Ltd | Method of manufacturing semiconductor integrated circuit device |
KR100393555B1 (en) | 2000-07-12 | 2003-08-09 | 삼성전기주식회사 | Brushless motor of single phase |
JP2002222858A (en) | 2001-01-25 | 2002-08-09 | Mitsubishi Electric Corp | Semiconductor device and its fabricating method |
-
2002
- 2002-10-31 KR KR10-2002-0066874A patent/KR100467023B1/en not_active IP Right Cessation
-
2003
- 2003-09-30 JP JP2003342268A patent/JP2004153251A/en not_active Withdrawn
- 2003-10-29 US US10/695,061 patent/US7071517B2/en not_active Expired - Fee Related
- 2003-10-31 CN CNB2003101045571A patent/CN100565808C/en not_active Expired - Fee Related
-
2006
- 2006-03-31 US US11/395,270 patent/US20060170062A1/en not_active Abandoned
- 2006-04-03 US US11/396,819 patent/US7397131B2/en not_active Expired - Fee Related
Patent Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5470777A (en) * | 1991-05-24 | 1995-11-28 | Texas Instruments Incorporated | Method of fabricating random access memory device having sidewall insulating layer on the laminate structure |
US5556373A (en) * | 1992-09-16 | 1996-09-17 | Motloch; Wallace M. | Body-worn orthopedic device that includes individual connected modules, and a method of manufacturing and designing such an orthopedic device |
US6043116A (en) * | 1998-03-04 | 2000-03-28 | United Microelectronics Corp. | Method of fabricating self-align-contact |
US6078492A (en) * | 1998-04-21 | 2000-06-20 | United Microelectronics Corp. | Structure of a capacitor in a semiconductor device having a self align contact window which has a slanted sidewall |
US6284596B1 (en) * | 1998-12-17 | 2001-09-04 | Taiwan Semiconductor Manufacturing Company | Method of forming split-gate flash cell for salicide and self-align contact |
US6734564B1 (en) * | 1999-01-04 | 2004-05-11 | International Business Machines Corporation | Specially shaped contact via and integrated circuit therewith |
US6177319B1 (en) * | 1999-01-16 | 2001-01-23 | United Microelectronics Corp. | Method of manufacturing salicide layer |
US6294449B1 (en) * | 1999-11-23 | 2001-09-25 | International Business Machines Corporation | Self-aligned contact for closely spaced transistors |
US20020195672A1 (en) * | 1999-11-30 | 2002-12-26 | Samsung Electronics Co., Ltd. | Method of forming a MOS transistor in a semiconductor device and a MOS transistor fabricated thereby |
US20020079492A1 (en) * | 2000-11-15 | 2002-06-27 | Hiroki Koga | Semiconductor device and method of manufacturing the same |
US20030122185A1 (en) * | 2001-12-27 | 2003-07-03 | Wang Chih Hsin | Self aligned method of forming a semiconductor memory array of floating gate memory cells with horizontally oriented edges, and a memory array thereby |
US7397131B2 (en) * | 2002-10-31 | 2008-07-08 | Samsung Electronics Co., Ltd. | Self-aligned semiconductor contact structures |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090050959A1 (en) * | 2007-08-21 | 2009-02-26 | Madson Gordon K | Method and Structure for Shielded Gate Trench FET |
US8497549B2 (en) | 2007-08-21 | 2013-07-30 | Fairchild Semiconductor Corporation | Method and structure for shielded gate trench FET |
US20090321817A1 (en) * | 2008-06-26 | 2009-12-31 | Hunt Scott L | Structure and Method for Forming a Shielded Gate Trench FET with an Inter-Electrode Dielectric Having a Nitride Layer Therein |
US7872305B2 (en) | 2008-06-26 | 2011-01-18 | Fairchild Semiconductor Corporation | Shielded gate trench FET with an inter-electrode dielectric having a nitride layer therein |
US20110081773A1 (en) * | 2008-06-26 | 2011-04-07 | Hunt Scott L | Method for Forming a Shielded Gate Trench FET |
US8129241B2 (en) | 2008-06-26 | 2012-03-06 | Fairchild Semiconductor Corporation | Method for forming a shielded gate trench FET |
US8642425B2 (en) | 2012-05-29 | 2014-02-04 | Semiconductor Components Industries, Llc | Method of making an insulated gate semiconductor device and structure |
US20140159115A1 (en) * | 2012-12-11 | 2014-06-12 | Eelectronics and Telecommunications Research Institute | Transistor and method of fabricating the same |
US8901608B2 (en) * | 2012-12-11 | 2014-12-02 | Electronics And Telecommunications Research Institute | Transistor and method of fabricating the same |
Also Published As
Publication number | Publication date |
---|---|
US20060192255A1 (en) | 2006-08-31 |
JP2004153251A (en) | 2004-05-27 |
US7071517B2 (en) | 2006-07-04 |
CN100565808C (en) | 2009-12-02 |
CN1499578A (en) | 2004-05-26 |
US7397131B2 (en) | 2008-07-08 |
KR100467023B1 (en) | 2005-01-24 |
KR20040038015A (en) | 2004-05-08 |
US20040084746A1 (en) | 2004-05-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7397131B2 (en) | Self-aligned semiconductor contact structures | |
US7518210B2 (en) | Trench isolated integrated circuit devices including grooves | |
US9275937B2 (en) | Semiconductor device with damascene bit line and method for fabricating the same | |
US7560759B2 (en) | Semiconductor device and method of manufacturing the same | |
US7696570B2 (en) | Transistors of semiconductor device having channel region in a channel-portion hole and methods of forming the same | |
US20040161881A1 (en) | Semiconductor device and method of manufacturing the same | |
US20050201155A1 (en) | Memory device and fabrication method thereof | |
US7138675B2 (en) | Semiconductor devices having storage nodes | |
US7411240B2 (en) | Integrated circuits including spacers that extend beneath a conductive line | |
US8900968B2 (en) | Method for manufacturing a semiconductor device | |
JP2002134506A (en) | Semiconductor device | |
US8044467B2 (en) | Semiconductor device and method of fabricating the same | |
KR100625188B1 (en) | Method of manufacturing a semiconductor device | |
US20100019305A1 (en) | Semiconductor device and method of manufacturing the same | |
US8823107B2 (en) | Method for protecting the gate of a transistor and corresponding integrated circuit | |
KR100416607B1 (en) | Semiconductor device including transistor and manufacturing methode thereof | |
US11688764B2 (en) | Semiconductor structure and method of forming same | |
JP4160846B2 (en) | Semiconductor device and manufacturing method thereof | |
US20060081909A1 (en) | Semiconductor device and manufacturing method therefor | |
KR100660552B1 (en) | Interconnection structure of semiconductor device and method of forming the same | |
US6750543B2 (en) | Semiconductor device with fully self-aligned local interconnects, and method for fabricating the device | |
KR100744681B1 (en) | A fabricating method of semiconductor device | |
CN115148689A (en) | Semiconductor device and method of forming the same | |
KR20020091935A (en) | Method for fabricating semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |