US20060108651A1 - Lowered Source/Drain Transistors - Google Patents
Lowered Source/Drain Transistors Download PDFInfo
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- US20060108651A1 US20060108651A1 US10/904,660 US90466004A US2006108651A1 US 20060108651 A1 US20060108651 A1 US 20060108651A1 US 90466004 A US90466004 A US 90466004A US 2006108651 A1 US2006108651 A1 US 2006108651A1
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- 239000004065 semiconductor Substances 0.000 claims abstract description 66
- 238000000034 method Methods 0.000 claims abstract description 41
- 229910052710 silicon Inorganic materials 0.000 claims description 30
- 239000010703 silicon Substances 0.000 claims description 30
- 239000002019 doping agent Substances 0.000 claims description 24
- 125000006850 spacer group Chemical group 0.000 claims description 14
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 12
- 229910052732 germanium Inorganic materials 0.000 claims description 12
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 238000001020 plasma etching Methods 0.000 claims description 8
- 229910052757 nitrogen Inorganic materials 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 239000007943 implant Substances 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 28
- 238000002513 implantation Methods 0.000 description 9
- 150000004767 nitrides Chemical class 0.000 description 9
- 125000001475 halogen functional group Chemical group 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000000151 deposition Methods 0.000 description 3
- 238000010849 ion bombardment Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
Definitions
- the present invention relates to semiconductor transistors, and more particularly, to lowered source/drain semiconductor transistors.
- a typical semiconductor transistor comprises a channel region and first and second source/drain (S/D) regions formed in a semiconductor layer, wherein the channel region is disposed between the first and second S/D regions.
- the typical semiconductor transistor further comprises a gate stack (that includes a gate dielectric region directly on top the channel region and a gate region on top of the gate dielectric region) directly above the channel region.
- first and second gate spacers are formed on sidewalls of the gate stack so as to define the first and second S/D regions, respectively.
- the capacitance between the gate region and the first S/D region has several components one of which is defined by a path from the gate region to the first S/D region through the first gate spacer.
- This capacitance component is usually referred to as the out-fringing capacitance.
- the out-fringing capacitance between the gate region and the second S/D region is defined by a path from the gate region to the second S/D region through the second gate spacer.
- the present invention provides a semiconductor structure, comprising (a) a semiconductor layer including a channel region and first and second source/drain regions, wherein the channel region is disposed between the first and second source/drain regions, and wherein top surfaces of the first and second source/drain regions are below a top surface of the channel region; (b) a gate dielectric region on the channel region; and (c) a gate region on the gate dielectric region, wherein the gate region is electrically isolated from the channel region by the gate dielectric region.
- the present invention also provides a method for fabricating a semiconductor structure, the method comprising the steps of (a) providing a semiconductor layer and a gate stack on the semiconductor layer, wherein the semiconductor layer comprises (i) a channel region directly beneath the gate stack and (ii) first and second semiconductor regions essentially not covered by the gate stack, and wherein the channel region is disposed between the first and second semiconductor regions; (b) removing the first and second semiconductor regions; and (c) doping regions directly beneath the removed first and second semiconductor regions so as to form first and second source/drain regions, respectively, such that top surfaces of the first and second source/drain regions are below a top surface of the channel region.
- the present invention also provides a method for fabricating a semiconductor structure, the method comprising the steps of (a) providing (i) an underlying dielectric layer, (ii) a semiconductor layer on the underlying dielectric layer, and (iii) a gate stack on the semiconductor layer; (b) implanting first dopants in a top layer of the underlying dielectric layer except in a separating dielectric region of the top layer directly beneath the gate stack; (c) removing the top layer of the underlying dielectric layer except the separating dielectric region; (d) epitaxially growing semiconductor regions to fill the removed top layer of the underlying dielectric layer; and (e) implanting second dopants in semiconductor regions of the semiconductor layer and the epitaxially grown semiconductor regions on opposing sides of the gate stack so as to form first and second source/drain regions such that the separating dielectric region is disposed between the first and second source/drain regions.
- the present invention provides a novel transistor structure in which the out-fringing capacitances between the gate region and the first and second S/D regions are relatively less than those of the prior art.
- the present invention also provides a method for fabricating the novel transistor structure.
- FIGS. 1A-1K show cross-section views of a semiconductor structure used to illustrate a method of fabricating semiconductor structures, in accordance with embodiments of the present invention.
- FIGS. 1A-1K show cross-section views of a semiconductor structure 100 used to illustrate a method of fabricating semiconductor structures, in accordance with embodiments of the present invention. More specifically, with reference to FIG. 1A , in one embodiment, the method starts out with an SOI (silicon on insulator) substrate 110 comprising, illustratively, a silicon layer 110 a , an underlying dielectric layer 110 b (usually referred to as BOX, i.e., buried oxide layer) on top of the silicon layer 110 a , and another silicon layer 110 c on top of the underlying dielectric layer 110 b . Starting from FIG. 1B , the silicon layer 110 a is omitted for simplicity.
- SOI silicon on insulator
- the method comprises the step of forming a gate dielectric layer 120 on top of the silicon layer 110 c .
- the gate dielectric layer 120 can comprise silicon dioxide and can be formed by thermally oxidizing a top surface 112 of the silicon layer 110 c.
- a gate layer 130 is formed on top of the gate dielectric layer 120 .
- the gate layer 130 can comprise poly-silicon.
- a hard mask dielectric layer 140 is formed on top of the poly-silicon layer 130 .
- hard mask dielectric layer 140 can comprise silicon dioxide and can be formed by, illustratively, chemical vapor deposition (i.e., CVD).
- CVD chemical vapor deposition
- a photoresist layer 150 is formed on top of the hard mask dielectric layer 140 .
- the photoresist layer 150 is patterned to become the patterned photoresist layer 150 ′ by, illustratively, photolithography (i.e., the regions of the photoresist layer 150 represented by the dashed lines are removed).
- the patterned photoresist layer 150 ′ can be used as a mask to etch the hard mask dielectric layer 140 and then the gate layer 130 so as to form the hard mask dielectric region 140 ′ and the gate region 130 ′, respectively.
- the regions of the hard mask dielectric layer 140 and the gate layer 130 represented by the dashed lines are removed.
- the method proceeds with an implantation step of using the regions 130 ′, 140 ′, and 150 ′ as a mask to implant nitrogen in a top layer 114 of the underlying dielectric layer 110 b .
- regions 114 a and 114 b of the top layer 114 are doped with nitrogen except for a separating dielectric region 114 c directly beneath the regions 130 ′, 140 ′, and 150 ′.
- any dopants can be used here instead of nitrogen provided that the doped regions 114 a and 114 b doped with the dopants can be later etched away (i.e., removed) essentially without affecting the other regions of the underlying dielectric layer 110 b.
- the patterned photoresist layer 150 ′ ( FIG. 1B ) can be removed, and a nitride layer 150 can be blanket-deposited on top of the structure 100 .
- the method can proceed with an anisotropic etching step that removes most of the nitride layer 150 and leaves nitride spacers 150 a and 150 b on sidewalls of the gate stack 130 ′, 140 ′ (that comprises the gate region 130 ′ and the hard mask dielectric region 140 ′).
- the anisotropic etching step can be RIE (Reactive Ion Etching).
- an oxide (e.g., SiO 2 ) layer 160 can be blanket-deposited on the structure 100 by, illustratively, CVD.
- the gate stack 130 ′, 140 ′ can be used as a mask to implant germanium in a top layer 116 of the silicon layer 110 c .
- doped regions 116 a and 116 b of the top layer 116 are doped with germanium except for a region 116 c directly beneath the gate stack 130 ′, 140 ′.
- any dopants can be used here instead of germanium provided that the resulting silicon regions 116 a and 116 b doped with the dopants can be later etched away essentially without affecting the other regions of the silicon layer 110 c.
- nitride spacers 170 a and 170 b can be formed on sidewalls of the gate stack 130 ′, 140 ′ (that now includes a portion of the oxide layer 160 that covers the gate stack 130 ′, 140 ′).
- the nitride spacers 170 a and 170 b can be formed by blanket-depositing a nitride layer (not shown) on top of the structure 100 and then etching back.
- the method proceeds with an implantation step (represented by arrow 117 a ′) of implanting germanium in the silicon layer 110 c at an angle such that the resulting doped region 117 a is deeper than the doped region 116 a and extends under the nitride spacer 170 a .
- the method proceeds with an implantation step (represented by arrow 117 b ′) of implanting germanium in the silicon layer 110 c at an angle such that the resulting doped region 117 b is deeper than the doped region 116 b and extends under the nitride spacer 170 b .
- the arrows 117 a ′ and 117 b ′ also indicate the respective directions of germanium bombardments.
- the method proceeds with an implantation step (represented by arrow 118 ) of implanting germanium vertically in the silicon layer 110 c such that the resulting doped regions 118 a and 118 b are deeper than the doped regions 117 a and 117 b , respectively.
- the arrow 118 also indicates the direction of germanium bombardment.
- the doped regions 116 a , 117 a , and 118 a are collectively referred to as the doped region 119 a .
- the doped regions 116 b , 117 b , and 118 b are collectively referred to as the doped region 119 b.
- oxide spacers 180 a and 180 b are formed on sidewalls of the nitride spacers 170 a and 170 b , respectively.
- the oxide spacers 180 a and 180 b can be formed by blanket-depositing an oxide layer (not shown) on top of the structure 100 and then etching back. As a result, a top region of the oxide layer 160 is etched away, and the nitride spacers 160 a and 160 b are exposed to the atmosphere. Also as a result, the doped regions 119 a and 119 b are exposed to the atmosphere.
- the oxide layer 160 is reduced to the oxide regions 160 a and 160 b .
- the gate dielectric layer 120 is reduced to gate dielectric region 120 ′.
- the method proceeds with an etching step of anisotropically etching away (illustratively, using RIE) silicon regions exposed to the atmosphere while leaving essentially intact other regions comprising other materials such as oxide and nitride. As a result, regions 119 a and 119 b of the silicon layer 110 c are removed.
- etching step of anisotropically etching away (illustratively, using RIE) silicon regions exposed to the atmosphere while leaving essentially intact other regions comprising other materials such as oxide and nitride.
- the nitrogen-doped regions 114 a and 114 b can be removed by a wet-etching process which essentially affects only nitrogen-doped oxide material and essentially does not affect other materials such as nitride, silicon, and undoped oxide.
- silicon is epitaxially grown from the silicon layer 110 c (including the doped regions 119 a and 119 b ) to top surfaces 192 a and 192 b.
- the resulting silicon layer 110 c is anisotropically etched back (illustratively, using RIE) to top surfaces 194 a and 194 b , respectively.
- the top surfaces 194 a and 194 b of the resulting silicon layer 110 c after etching back are below the bottom surfaces 195 a and 195 b ( FIG. 1G ) of the germanium-doped regions 119 a and 119 b , respectively.
- an anneal process can be performed to diffuse germanium in the germanium-doped regions 119 a and 119 b into the silicon layer 110 c.
- the germanium-doped regions 119 a and 119 b ( FIG. 1H ) of the silicon layer 110 c can be removed (illustratively, by wet etching) while leaving essentially intact other regions of the silicon layer 110 c that are not doped with germanium.
- an S/D implantation step can be performed to form S/D regions 210 a and 210 b in the silicon layer 110 c .
- an S/D anneal step can be performed after the S/D implantation step.
- the method proceeds with a step of anisotropically etching (illustratively, using RIE) the exposed nitride regions 150 a , 150 b , 170 a , and 170 b ( FIG. 1I ).
- RIE anisotropically etching
- the nitride spacers 170 a and 170 b are removed.
- the nitride regions 150 a and 150 b are thin and protected by surrounding oxide regions 160 a , 160 b , and 140 ′ ( FIG. 1I ).
- the etch rate for the nitride regions 150 a and 150 b is much slower than that for the nitride spacers 170 a and 170 b . Therefore, when the nitride spacers 170 a and 170 b are completely removed, the nitride regions 150 a and 150 b can be almost intact.
- the method proceeds with a step of anisotropically etching (illustratively, using RIE) the exposed oxide regions 160 a , 160 b , and 140 ′ ( FIG. 1I ).
- RIE anisotropically etching
- the hard mask dielectric region 140 ′ is removed, while the oxide regions 160 a and 160 b are reduced to the oxide spacers 160 a ′ and 160 b ′, respectively.
- a halo implantation step (represented by an arrow 220 a ′) can be performed to form a halo region 220 a .
- another halo implantation step (represented by an arrow 220 b ′) can be performed to form a halo region 220 b .
- the arrows 220 a ′ and 220 b ′ also indicate the respective directions of halo ion bombardments.
- an extension implantation step (represented by arrows 230 ) can be performed to form extension regions 230 a and 230 b .
- the arrow 230 also indicates the direction of extension ion bombardments.
- a halo and extension anneal step can be performed to anneal the resulting halo regions 220 a and 220 b and the resulting extension regions 230 a and 230 b.
- oxide spacers 240 a and 240 b are formed on sidewalls of the oxide spacers 160 a ′ and 160 b ′, respectively.
- the oxide spacers 240 a and 240 b can be formed by blanket-depositing an oxide layer (not shown) on top of the structure 100 and then etching back.
- the gate region 130 ′ and the gate dielectric region 120 ′ can be collectively referred to as the gate stack 120 ′, 130 ′ of the structure 100 .
- the method for forming lowered S/D transistor 100 starts out with a planar silicon layer 110 c ( FIG. 1A ). Then, the silicon regions 119 a and 119 b ( FIG. 1H ) are doped with germanium so that they can be removed later ( FIG. 1I ) without affecting other silicon regions of the silicon layer 110 c . As a result, the transistor 100 ( FIG. 1K ) has lowered S/D regions 210 a and 210 b (i.e., top surfaces 212 a and 212 b of the S/D regions 210 a and 210 b , respectively, are lower than a top surface 242 of the channel region 240 ).
- the separating dielectric region 114 c is disposed between the S/D regions 210 a and 210 b ( FIG. 1K ). Because of the separating dielectric region 114 c , the channel region 240 (immediately beneath the gate dielectric region 120 ′) is thinner. As a result, short channel effects are improved.
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Abstract
Description
- 1. Technical Field
- The present invention relates to semiconductor transistors, and more particularly, to lowered source/drain semiconductor transistors.
- 2. Related Art
- A typical semiconductor transistor comprises a channel region and first and second source/drain (S/D) regions formed in a semiconductor layer, wherein the channel region is disposed between the first and second S/D regions. The typical semiconductor transistor further comprises a gate stack (that includes a gate dielectric region directly on top the channel region and a gate region on top of the gate dielectric region) directly above the channel region. In addition, first and second gate spacers are formed on sidewalls of the gate stack so as to define the first and second S/D regions, respectively. The capacitance between the gate region and the first S/D region has several components one of which is defined by a path from the gate region to the first S/D region through the first gate spacer. This capacitance component is usually referred to as the out-fringing capacitance. For example, the out-fringing capacitance between the gate region and the second S/D region is defined by a path from the gate region to the second S/D region through the second gate spacer.
- It is desirable to minimize the out-fringing capacitances between the gate region and the first and second S/D regions in order to increase transistor performance or to reduce transistor switching time. Therefore, there is a need for a novel transistor structure in which the out-fringing capacitances between the gate region and the first and second S/D regions are relatively less than those of the prior art. There is also a need for a method for fabricating the novel transistor structure.
- The present invention provides a semiconductor structure, comprising (a) a semiconductor layer including a channel region and first and second source/drain regions, wherein the channel region is disposed between the first and second source/drain regions, and wherein top surfaces of the first and second source/drain regions are below a top surface of the channel region; (b) a gate dielectric region on the channel region; and (c) a gate region on the gate dielectric region, wherein the gate region is electrically isolated from the channel region by the gate dielectric region.
- The present invention also provides a method for fabricating a semiconductor structure, the method comprising the steps of (a) providing a semiconductor layer and a gate stack on the semiconductor layer, wherein the semiconductor layer comprises (i) a channel region directly beneath the gate stack and (ii) first and second semiconductor regions essentially not covered by the gate stack, and wherein the channel region is disposed between the first and second semiconductor regions; (b) removing the first and second semiconductor regions; and (c) doping regions directly beneath the removed first and second semiconductor regions so as to form first and second source/drain regions, respectively, such that top surfaces of the first and second source/drain regions are below a top surface of the channel region.
- The present invention also provides a method for fabricating a semiconductor structure, the method comprising the steps of (a) providing (i) an underlying dielectric layer, (ii) a semiconductor layer on the underlying dielectric layer, and (iii) a gate stack on the semiconductor layer; (b) implanting first dopants in a top layer of the underlying dielectric layer except in a separating dielectric region of the top layer directly beneath the gate stack; (c) removing the top layer of the underlying dielectric layer except the separating dielectric region; (d) epitaxially growing semiconductor regions to fill the removed top layer of the underlying dielectric layer; and (e) implanting second dopants in semiconductor regions of the semiconductor layer and the epitaxially grown semiconductor regions on opposing sides of the gate stack so as to form first and second source/drain regions such that the separating dielectric region is disposed between the first and second source/drain regions.
- The present invention provides a novel transistor structure in which the out-fringing capacitances between the gate region and the first and second S/D regions are relatively less than those of the prior art. The present invention also provides a method for fabricating the novel transistor structure.
-
FIGS. 1A-1K show cross-section views of a semiconductor structure used to illustrate a method of fabricating semiconductor structures, in accordance with embodiments of the present invention. -
FIGS. 1A-1K show cross-section views of asemiconductor structure 100 used to illustrate a method of fabricating semiconductor structures, in accordance with embodiments of the present invention. More specifically, with reference toFIG. 1A , in one embodiment, the method starts out with an SOI (silicon on insulator)substrate 110 comprising, illustratively, asilicon layer 110 a, an underlyingdielectric layer 110 b (usually referred to as BOX, i.e., buried oxide layer) on top of thesilicon layer 110 a, and anothersilicon layer 110 c on top of the underlyingdielectric layer 110 b. Starting fromFIG. 1B , thesilicon layer 110 a is omitted for simplicity. - Next, in one embodiment, the method comprises the step of forming a gate
dielectric layer 120 on top of thesilicon layer 110 c. In one embodiment, the gatedielectric layer 120 can comprise silicon dioxide and can be formed by thermally oxidizing atop surface 112 of thesilicon layer 110 c. - Next, in one embodiment, a
gate layer 130 is formed on top of the gatedielectric layer 120. In one embodiment, thegate layer 130 can comprise poly-silicon. Next, in one embodiment, a hard maskdielectric layer 140 is formed on top of the poly-silicon layer 130. In one embodiment, hard maskdielectric layer 140 can comprise silicon dioxide and can be formed by, illustratively, chemical vapor deposition (i.e., CVD). Then, in one embodiment, aphotoresist layer 150 is formed on top of the hard maskdielectric layer 140. - Next, in one embodiment, the
photoresist layer 150 is patterned to become the patternedphotoresist layer 150′ by, illustratively, photolithography (i.e., the regions of thephotoresist layer 150 represented by the dashed lines are removed). - Next, in one embodiment, the patterned
photoresist layer 150′ can be used as a mask to etch the hard maskdielectric layer 140 and then thegate layer 130 so as to form the hard maskdielectric region 140′ and thegate region 130′, respectively. In other words, the regions of the hard maskdielectric layer 140 and thegate layer 130 represented by the dashed lines are removed. - Next, with reference to
FIG. 1B , in one embodiment, the method proceeds with an implantation step of using theregions 130′, 140′, and 150′ as a mask to implant nitrogen in atop layer 114 of the underlyingdielectric layer 110 b. As a result,regions top layer 114 are doped with nitrogen except for a separatingdielectric region 114 c directly beneath theregions 130′, 140′, and 150′. In general, any dopants can be used here instead of nitrogen provided that thedoped regions dielectric layer 110 b. - Next, with reference to
FIG. 1C , in one embodiment, the patternedphotoresist layer 150′ (FIG. 1B ) can be removed, and anitride layer 150 can be blanket-deposited on top of thestructure 100. - Next, with reference to
FIG. 1D , in one embodiment, the method can proceed with an anisotropic etching step that removes most of thenitride layer 150 and leavesnitride spacers gate stack 130′,140′ (that comprises thegate region 130′ and the hard maskdielectric region 140′). In one embodiment, the anisotropic etching step can be RIE (Reactive Ion Etching). Next, in one embodiment, an oxide (e.g., SiO2)layer 160 can be blanket-deposited on thestructure 100 by, illustratively, CVD. - Next, in one embodiment, the
gate stack 130′,140′ can be used as a mask to implant germanium in atop layer 116 of thesilicon layer 110 c. As a result, dopedregions top layer 116 are doped with germanium except for aregion 116 c directly beneath thegate stack 130′,140′. In general, any dopants can be used here instead of germanium provided that the resultingsilicon regions silicon layer 110 c. - Next, with reference to
FIG. 1E , in one embodiment,nitride spacers gate stack 130′,140′ (that now includes a portion of theoxide layer 160 that covers thegate stack 130′,140′). In one embodiment, thenitride spacers structure 100 and then etching back. - Next, in one embodiment, the method proceeds with an implantation step (represented by
arrow 117 a′) of implanting germanium in thesilicon layer 110 c at an angle such that the resultingdoped region 117 a is deeper than thedoped region 116 a and extends under thenitride spacer 170 a. Then, in one embodiment, the method proceeds with an implantation step (represented by arrow 117 b′) of implanting germanium in thesilicon layer 110 c at an angle such that the resulting doped region 117 b is deeper than thedoped region 116 b and extends under thenitride spacer 170 b. Thearrows 117 a′ and 117 b′ also indicate the respective directions of germanium bombardments. - Next, in one embodiment, the method proceeds with an implantation step (represented by arrow 118) of implanting germanium vertically in the
silicon layer 110 c such that the resultingdoped regions doped regions 117 a and 117 b, respectively. Thearrow 118 also indicates the direction of germanium bombardment. Starting fromFIG. 1F , thedoped regions doped region 119 a. Similarly, the dopedregions region 119 b. - Next, with reference to
FIG. 1F , in one embodiment,oxide spacers nitride spacers oxide spacers structure 100 and then etching back. As a result, a top region of theoxide layer 160 is etched away, and thenitride spacers regions oxide layer 160 is reduced to theoxide regions gate dielectric layer 120 is reduced togate dielectric region 120′. - Next, with reference to
FIG. 1G , in one embodiment, the method proceeds with an etching step of anisotropically etching away (illustratively, using RIE) silicon regions exposed to the atmosphere while leaving essentially intact other regions comprising other materials such as oxide and nitride. As a result,regions silicon layer 110 c are removed. - Next, in one embodiment, the nitrogen-doped
regions - Next, with reference to
FIG. 1H , in one embodiment, silicon is epitaxially grown from thesilicon layer 110 c (including the dopedregions top surfaces - Next, in one embodiment, the resulting
silicon layer 110 c is anisotropically etched back (illustratively, using RIE) totop surfaces 194 a and 194 b, respectively. In one embodiment, thetop surfaces 194 a and 194 b of the resultingsilicon layer 110 c after etching back are below the bottom surfaces 195 a and 195 b (FIG. 1G ) of the germanium-dopedregions - Next, in one embodiment, an anneal process can be performed to diffuse germanium in the germanium-doped
regions silicon layer 110 c. - Next, with reference to
FIG. 1I , in one embodiment, the germanium-dopedregions FIG. 1H ) of thesilicon layer 110 c can be removed (illustratively, by wet etching) while leaving essentially intact other regions of thesilicon layer 110 c that are not doped with germanium. - Next, in one embodiment, an S/D implantation step can be performed to form S/
D regions silicon layer 110 c. In one embodiment, an S/D anneal step can be performed after the S/D implantation step. - Next, with reference to
FIG. 1J , in one embodiment, the method proceeds with a step of anisotropically etching (illustratively, using RIE) the exposednitride regions FIG. 1I ). As a result, thenitride spacers nitride regions oxide regions FIG. 1I ). As a result, the etch rate for thenitride regions nitride spacers nitride spacers nitride regions - Next, in one embodiment, the method proceeds with a step of anisotropically etching (illustratively, using RIE) the exposed
oxide regions FIG. 1I ). As a result, the hard maskdielectric region 140′ is removed, while theoxide regions oxide spacers 160 a′ and 160 b′, respectively. - Next, in one embodiment, a halo implantation step (represented by an
arrow 220 a′) can be performed to form ahalo region 220 a. Next, in one embodiment, another halo implantation step (represented by anarrow 220 b′) can be performed to form ahalo region 220 b. Thearrows 220 a′ and 220 b′ also indicate the respective directions of halo ion bombardments. - Next, in one embodiment, an extension implantation step (represented by arrows 230) can be performed to form
extension regions arrow 230 also indicates the direction of extension ion bombardments. - Next, in one embodiment, a halo and extension anneal step can be performed to anneal the resulting
halo regions extension regions - Next, with reference to
FIG. 1K , in one embodiment,oxide spacers oxide spacers 160 a′ and 160 b′, respectively. In one embodiment, theoxide spacers structure 100 and then etching back. Now, thegate region 130′ and thegate dielectric region 120′ can be collectively referred to as thegate stack 120′,130′ of thestructure 100. - In summary, the method for forming lowered S/
D transistor 100 starts out with aplanar silicon layer 110 c (FIG. 1A ). Then, thesilicon regions FIG. 1H ) are doped with germanium so that they can be removed later (FIG. 1I ) without affecting other silicon regions of thesilicon layer 110 c. As a result, the transistor 100 (FIG. 1K ) has lowered S/D regions top surfaces D regions top surface 242 of the channel region 240). Considering a path from thegate region 130′ to the S/D region 210 a through thenitride spacer 150 a, theoxide spacers 160 a′ and 240 a, because of the lowered S/D region 210 a, the path is extended when it goes through theoxide spacer 240 a. As a result, the out-fringing capacitance between thegate region 130′ to the S/D region 210 a is reduced. For a similar reason, the out-fringing capacitance between thegate region 130′ and the S/D region 210 b is also reduced. - To form the separating
dielectric region 114 c (FIG. 1C ), theoxide regions underlying dielectric layer 110 b are doped with nitrogen so that theoxide regions FIG. 1G ) and replaced by epi-silicon (epi=epitaxially grown) as shown inFIG. 1H . As a result, the separatingdielectric region 114 c is disposed between the S/D regions FIG. 1K ). Because of the separatingdielectric region 114 c, the channel region 240 (immediately beneath thegate dielectric region 120′) is thinner. As a result, short channel effects are improved. - While particular embodiments of the present invention have been described herein for purposes of illustration, many modifications and changes will become apparent to those skilled in the art. Accordingly, the appended claims are intended to encompass all such modifications and changes as fall within the true spirit and scope of this invention.
Claims (20)
Priority Applications (3)
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US10/904,660 US20060108651A1 (en) | 2004-11-22 | 2004-11-22 | Lowered Source/Drain Transistors |
CN200510115133A CN100578810C (en) | 2004-11-22 | 2005-11-10 | Lowered source electrode/drain electrode transistors and method for producing the same |
US12/367,764 US7732288B2 (en) | 2004-11-22 | 2009-02-09 | Method for fabricating a semiconductor structure |
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US10/904,660 US20060108651A1 (en) | 2004-11-22 | 2004-11-22 | Lowered Source/Drain Transistors |
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US12/367,764 Division US7732288B2 (en) | 2004-11-22 | 2009-02-09 | Method for fabricating a semiconductor structure |
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US10/904,660 Abandoned US20060108651A1 (en) | 2004-11-22 | 2004-11-22 | Lowered Source/Drain Transistors |
US12/367,764 Active US7732288B2 (en) | 2004-11-22 | 2009-02-09 | Method for fabricating a semiconductor structure |
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US8598003B2 (en) * | 2009-12-21 | 2013-12-03 | Intel Corporation | Semiconductor device having doped epitaxial region and its methods of fabrication |
US9941388B2 (en) * | 2014-06-19 | 2018-04-10 | Globalfoundries Inc. | Method and structure for protecting gates during epitaxial growth |
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US20030025135A1 (en) * | 2001-07-17 | 2003-02-06 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method of manufacturing same |
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US6495402B1 (en) * | 2001-02-06 | 2002-12-17 | Advanced Micro Devices, Inc. | Semiconductor-on-insulator (SOI) device having source/drain silicon-germanium regions and method of manufacture |
DE10353772B4 (en) * | 2003-11-18 | 2008-12-18 | Austriamicrosystems Ag | Process for the production of transistor structures with LDD |
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2004
- 2004-11-22 US US10/904,660 patent/US20060108651A1/en not_active Abandoned
-
2005
- 2005-11-10 CN CN200510115133A patent/CN100578810C/en not_active Expired - Fee Related
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2009
- 2009-02-09 US US12/367,764 patent/US7732288B2/en active Active
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US6010936A (en) * | 1996-11-27 | 2000-01-04 | Lg Semicon Co., Ltd. | Semiconductor device fabrication method |
US5994747A (en) * | 1998-02-13 | 1999-11-30 | Texas Instruments-Acer Incorporated | MOSFETs with recessed self-aligned silicide gradual S/D junction |
US6414353B1 (en) * | 1998-08-07 | 2002-07-02 | Mitsubishi Denki Kabushiki Kaisha | TFT with partially depleted body |
US6214679B1 (en) * | 1999-12-30 | 2001-04-10 | Intel Corporation | Cobalt salicidation method on a silicon germanium film |
US6437404B1 (en) * | 2000-08-10 | 2002-08-20 | Advanced Micro Devices, Inc. | Semiconductor-on-insulator transistor with recessed source and drain |
US6465313B1 (en) * | 2001-07-05 | 2002-10-15 | Advanced Micro Devices, Inc. | SOI MOSFET with graded source/drain silicide |
US20030025135A1 (en) * | 2001-07-17 | 2003-02-06 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method of manufacturing same |
US6927110B2 (en) * | 2002-10-04 | 2005-08-09 | Seiko Epson Corporation | Method of manufacturing a semiconductor device |
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CN100578810C (en) | 2010-01-06 |
US7732288B2 (en) | 2010-06-08 |
US20090142894A1 (en) | 2009-06-04 |
CN1790739A (en) | 2006-06-21 |
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