US20050285193A1 - Semiconductor device and method of manufacturing same - Google Patents

Semiconductor device and method of manufacturing same Download PDF

Info

Publication number
US20050285193A1
US20050285193A1 US11/081,538 US8153805A US2005285193A1 US 20050285193 A1 US20050285193 A1 US 20050285193A1 US 8153805 A US8153805 A US 8153805A US 2005285193 A1 US2005285193 A1 US 2005285193A1
Authority
US
United States
Prior art keywords
layer
semiconductor
spaces
sige
gate electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/081,538
Inventor
Sung-young Lee
Dong-Suk Shin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Assigned to SAMSUNG ELECTRONICS CO., LTD. reassignment SAMSUNG ELECTRONICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LEE, SUNG-YOUNG, SHIN, DONG-SUK
Publication of US20050285193A1 publication Critical patent/US20050285193A1/en
Priority to US12/015,646 priority Critical patent/US7989296B2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78639—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a drain or source connected to a bulk conducting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/78654—Monocrystalline silicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
    • H01L29/78687—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys with a multilayer structure or superlattice structure

Definitions

  • the present invention relates generally to a semiconductor device and a method of manufacturing the same. More particularly, the invention relates to a semiconductor device comprising a metal oxide semiconductor (MOS) transistor and a method of manufacturing the same.
  • MOS metal oxide semiconductor
  • Fully depleted silicon-on-insulator (FD-SOI) technology has been widely used to create high speed, low power logic circuits.
  • FD-SOI technology reduces parasitic capacitances associated with source, drain, and channel regions of semiconductor circuits, thereby allowing the circuits to operate at higher speeds.
  • FD-SOI technology reduces the amount of leakage current occurring at source and drain junctions of the circuits, thereby lowering associated power consumption.
  • shallow source/drain regions are readily implemented using FD-SOI technology, thus allowing the short channel effect to be readily constrained and thereby improving the scalability of the circuits.
  • CMOS complementary metal-oxide semiconductor
  • a mechanical stress engineering technique According to the mechanical stress engineering technique, a local stress is applied to a channel region so as to control the carrier (electron or hole) mobility ( ⁇ ) within a semiconductor material. Where the carrier mobility increases, the switching characteristics of the device are improved, thus enabling the manufacture of higher-speed devices.
  • the present invention provides a semiconductor device capable of improving carrier mobility by applying a local stress to a channel region while maintaining advantages of an SOI device, such as the ability to constrain short channel effects and reduce junction resistance.
  • the present invention provides a method of manufacturing a semiconductor device in which a highly integrated semiconductor device having an improved short channel effect and reduced junction capacitance, as well as a device being capable of constraining a substrate floating effect may be implemented at a relatively low cost.
  • a semiconductor device comprising a gate electrode formed on a semiconductor substrate, an active region containing spaces formed below the gate electrode, a channel region formed between the gate electrode and the spaces, and source and drain regions formed on both sides of the gate electrode within the active region.
  • a method of manufacturing a semiconductor device comprises forming a gate electrode on a semiconductor substrate, forming spaces in an active region below the gate electrode, forming a channel region between the gate electrode and the spaces, and forming source and gate regions on both sides of the gate electrode within the active region.
  • the short channel effect is constrained and junction resistance is reduced by forming the spaces in the active region below the gate electrode. Furthermore, it effectively addresses the substrate floating effect which occurs in devices using SOI technology. Furthermore, the invention makes it possible to implement the mechanical stress engineering technique to the channel region to increase carrier mobility.
  • FIGS. 1A through 1M are cross-sectional views illustrating a method of manufacturing a semiconductor device according to one embodiment of the present invention
  • FIGS. 2A through 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention.
  • FIGS. 3A through 3C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to still another embodiment of the present invention.
  • FIGS. 4A through 4C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to still another embodiment of the present invention.
  • FIGS. 5A through 5C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to still another embodiment of the present invention.
  • FIGS. 6A through 6C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to a sixth embodiment of the present invention.
  • FIGS. 1A through 1M are cross-sectional views illustrating a method of manufacturing a semiconductor device according to one embodiment of the present invention.
  • a first silicon germanium (SiGe) layer 102 is formed on a bulk semiconductor substrate 100 such as a silicon substrate.
  • First SiGe layer 102 is generally formed to a thickness of about 10 to 100 nm using a selective epitaxial growth technology.
  • a silicon (Si) layer 104 is then formed on first SiGe layer 102 to a thickness of about 5 to 50 nm.
  • an active region is defined by forming a device isolation region 106 on semiconductor substrate 100 using a conventional isolation method such as a trench isolation method. In other words, the active region is delimited on either side by device isolation region 106 .
  • first insulating spacers 118 are formed on sidewalls of gate electrode 114 .
  • first insulating spacers 118 comprise a silicon nitride layer 118 a , a silicon oxide layer 118 b , or a combination thereof.
  • an Si layer 104 , first SiGe layer 102 and semiconductor substrate 100 are partially etched to form a recess region 120 using hard mask 116 , first insulating spacers 118 and device isolation region 106 as an etching mask.
  • first SiGe layer 102 sidewalls of Si layer 104
  • device isolation region 106 sidewalls of device isolation region 106 are exposed.
  • a portion of Si layer 104 remaining below gate electrode 114 acts as a channel region for a transistor.
  • an insulating material is deposited on the structure having recess region 120 and an etch-back process is performed to form second insulating spacers 122 covering sidewalls of first SiGe layer 102 , sidewalls of Si layer 104 and sidewalls of first insulating spacers 118 , which are exposed in or above recess region 120 .
  • Second insulating spacers 122 are also formed on sidewalls of device isolation region 106 .
  • second insulating spacers 122 are formed of a silicon oxide layer, a silicon nitride layer, or a combination thereof.
  • second insulating spacers 122 are formed of a silicon oxide layer.
  • a second SiGe layer 132 is formed on semiconductor substrate 100 in recess region 120 .
  • Second SiGe layer 132 is formed to a thickness of about 10 to 100 nm using a selective epitaxial growth technology.
  • second SiGe layer 132 has the same thickness as first SiGe layer 102 .
  • a Ge concentration in second SiGe layer 132 is equal to a Ge concentration in first SiGe layer 102 .
  • a semiconductor layer 134 is formed on second SiGe layer 132 using a selective epitaxial growth technology.
  • Semiconductor layer 134 is formed of a different material from second SiGe layer 132 .
  • semiconductor layer 134 may be formed of Si or SiC. Where semiconductor layer 134 is formed of SiC, the carrier mobility in an negative metal-oxide semiconductor (NMOS) device can be improved by locally applying a tensile stress to the channel region formed by Si layer 104 .
  • NMOS negative metal-oxide semiconductor
  • Semiconductor layer 134 is formed to a thickness sufficient to completely fill recess region 120 . As shown in FIG. 1G , semiconductor layer 134 typically has a thickness such that semiconductor layer 134 partially covers an upper surface of device isolation region 106 . As a result, semiconductor layer 134 generally protects a corner portion of device isolation region 106 .
  • second insulating spacers 122 etched and thereby removed. Consequently, the sidewalls of first and second SiGe layers 102 and 132 are exposed through spaces 136 between Si layer 104 and semiconductor layer 134 .
  • first and second SiGe layers 102 and 132 are selectively removed to form spaces 140 below Si layer 104 and semiconductor layer 134 , respectively.
  • First and second SiGe layers 102 and 132 are generally removed using a wet etching process or an isotropic plasma etching process.
  • the plasma etching process may employ, for example, an etchant comprised of a mixture of HNO 3 , H 2 O 2 , and HF.
  • Si is epitaxially grown from Si layer 104 and semiconductor layer 134 using a selective epitaxial growth technology. As a result, Si layer 104 and semiconductor layer 134 are joined together by a region “A”.
  • an extension region 152 and a halo ion implantation region 154 are formed in semiconductor layer 134 and Si layer 104 using a conventional ion implantation process using hard mask 116 as an ion implantation mask.
  • third insulating spacers 156 covering silicon oxide layer 118 b are formed on the sidewalls of gate electrode 114 .
  • Third insulating spacers 156 are usually formed of either a silicon oxide layer, a silicon nitride layer, or a combination thereof.
  • third insulating spacers 156 are formed of a silicon oxide layer.
  • Source and drain regions 158 are then formed in semiconductor layer 134 and Si layer 104 .
  • Source and drain regions 158 are typically formed using a conventional ion implantation process using hard mask 116 and third insulating spacers 156 as an ion implantation mask.
  • metal silicide layers 162 and 164 are formed on upper surfaces of gate electrode 114 and source and drain regions 158 using a conventional silicide deposition process.
  • Metal silicide layers 162 and 164 contribute to reduced surface resistance and contact resistance for contacts in the semiconductor device.
  • Metal silicide layers 162 and 164 are typically formed of cobalt silicide, nickel silicide, titanium silicide, hafnium silicide, platinum silicide, or tungsten silicide. In some instances, the formation of metal silicide layers 162 and 164 can be omitted.
  • spaces 140 are extended to completely overlap the channel region and source and drain regions 158 . Accordingly, as in the case where a SOI substrate is used, the short channel effect is readily constrained and junction capacitance is reduced.
  • FIGS. 2A through 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention.
  • FIGS. 2A through 2C is substantially similar to the embodiment illustrated in FIGS. 1A through 1M .
  • One difference, however, is that spaces 140 formed in the active region below gate electrode 114 are filled with insulating materials.
  • spaces 140 are formed in an active region of a semiconductor substrate 100 in the manner described in relation to FIGS. 1A through 11 .
  • An insulating material is deposited to fill spaces 140 and an etch-back process is performed to expose sidewalls of Si layer 104 . Consequently, spaces 140 are filled by an insulating layer 240 .
  • Insulating layer 240 is typically formed of an oxide layer or a nitride layer.
  • Si is epitaxially grown from Si layer 104 and semiconductor layer 134 in the manner described in relation to FIG. 1J , thereby joining Si layer 104 and semiconductor layer 134 with a region “B”.
  • a transistor is formed in the manner described in relation to FIGS. 1K through 1M .
  • insulating layer 240 is extended to completely overlap the channel region and source and drain regions 158 . Accordingly, as in the case where a SOI substrate is used, the short channel effect is readily constrained and junction capacitance is reduced.
  • FIGS. 3A through 3C are cross-sectional views illustrating a method of fabricating a semiconductor device according to still another embodiment of the present invention.
  • FIGS. 3A through 3C is substantially similar to the method illustrated in FIGS. 1A through 1M .
  • One difference, however, is that the spaces formed on the active region below gate electrode 114 are extended to only a portion of the active region.
  • spaces 136 exposing the sidewalls of first and second SiGe layers 102 and 132 are formed on semiconductor substrate 100 in the manner described in relation to FIGS. 1A through 1H .
  • First and second SiGe layers 102 and 132 exposed through spaces 136 are partially removed to form spaces 340 below Si layer 104 and semiconductor layer 134 .
  • Portions of second SiGe layer 132 adjacent to second insulating spacers 122 are prevented from being removed by controlling the amount of time used to etch first and second SiGe layers 102 and 132 .
  • Si is epitaxially grown from Si layer 104 and semiconductor layer 134 in the manner described in relation to FIG. 1J , thereby joining Si layer 104 and semiconductor layer 134 with a region “C”.
  • a transistor is formed in the manner described in relation to FIGS. 1K through 1M .
  • spaces 340 are extended to completely overlap the channel region and to partially overlap source and drain regions 158 .
  • spaces 340 formed in the active region below gate electrode 114 are extended cover only a portion of the active region.
  • a portion of second SiGe layer 132 adjacent to second insulating spacers 122 still remains between semiconductor substrate 100 and semiconductor layer 134 . Accordingly, the length of spaces 340 is limited by the portion of second SiGe layer 132 remaining between semiconductor substrate 100 and source and drain regions 158 . Due to second SiGe layer 132 , a substrate floating effect is prevented from occurring in a MOS transistor.
  • FIGS. 4A through 4C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to still another embodiment of the present invention.
  • FIGS. 4A is substantially similar to the method illustrated in FIGS. 3A through 3C . However, one difference is that spaces 340 formed in the active region below gate electrode 114 are filled with an insulating material.
  • Insulating layer 440 typically comprises an oxide layer or a nitride layer.
  • Si is epitaxially grown from Si layer 104 and semiconductor layer 134 in the manner described in relation to FIG. 1J , thereby joining Si layer 104 and semiconductor layer 134 with a region “D”.
  • a transistor is formed in the manner described in relation to FIGS. 1K through 1M .
  • FIGS. 5A through 5E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to still another embodiment of the present invention.
  • FIGS. 5A through 5E is substantially similar to the method illustrated in FIGS. 1A through 1M .
  • One difference, however, is that spaces are only formed below the channel region but not in other parts of the active region.
  • second insulating spacers 122 are formed in the manner described in relation to FIGS. 1A through 1E .
  • a semiconductor layer 534 is then formed on semiconductor substrate 100 in recess region 120 .
  • semiconductor layer 534 is formed of materials whose composition is different from that of first SiGe layer 102 .
  • semiconductor layer 534 is typically formed of Si, SiC or SiGe. Where semiconductor layer 534 is formed of SiC, the carrier mobility in a NMOS device is readily improved by locally applying a tensile stress to the channel region formed by Si layer 104 .
  • semiconductor layer 534 is formed of SiGe
  • the carrier mobility in a positive metal-oxide semiconductor (PMOS) device is readily improved by locally applying a tensile stress to the channel region formed by Si layer 104 .
  • semiconductor layer 534 is formed of SiGe, it preferably has a Ge concentration lower than the Ge concentration of first SiGe layer 102 .
  • Semiconductor layer 534 is formed to a thickness sufficient to fill recess region 120 . As shown in FIG. 5A , semiconductor layer 534 typically has a thickness such that it partially covers an upper surface of device isolation region 106 , thereby protecting a corner portion of device isolation region 106 .
  • second insulating spacers 122 and silicon oxide layer 118 b are selectively etched and removed in the manner described in relation to FIG. 1H . Consequently, spaces 136 are formed between Si layer 104 and semiconductor layer 534 . Sidewalls of first SiGe layer 102 are exposed through spaces 136 .
  • first SiGe layer 102 is selectively removed to form spaces 540 below Si layer 104 in the manner described in relation to FIG. 1I .
  • semiconductor layer 534 is formed of SiGe
  • the Ge concentration of first SiGe layer 102 is typically higher than that of semiconductor layer 534 , as described in relation to FIG. 5A . Accordingly, even where semiconductor layer 534 is formed of SiGe, first SiGe layer 102 can be selectively removed under the condition that it has a high etch selectivity relative to semiconductor layer 534 .
  • Si is epitaxially grown from Si layer 104 and semiconductor layer 534 in the same manner described in relation to FIG. 1J , thereby joining Si layer 104 and semiconductor layer 534 with a region “E”. Consequently, spaces 540 remain only below the channel region formed by Si layer 104 in the active region.
  • extension region 152 and halo ion implantation region 154 are formed in semiconductor layer 534 and Si layer 104 below gate electrode 114 in the manner described in relation to FIGS. 1K through 1M .
  • Third insulating spacers 156 and source and drain regions 158 are then formed.
  • metal silicide layers 162 and 164 are formed on gate electrode 114 and source and drain regions 158 . In this manner, the formation of a transistor is completed.
  • FIGS. 6A through 6C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to still another embodiment of the present invention.
  • FIGS. 6A through 6C is substantially similar to the method illustrated in FIGS. 5A through 5E .
  • One difference, however, is that spaces 540 formed below the channel region formed by Si layer 104 are filled with an insulating material.
  • spaces 540 are formed below Si layer 104 in the manner described in relation to FIGS. 5A through 5C .
  • An insulating material is deposited on semiconductor substrate 100 to fill spaces 540 and an etch-back process is performed until the sidewalls of Si layer 104 are exposed. Consequently, spaces 540 are filled with an insulating layer 640 .
  • Insulating layer 640 is typically formed of an oxide layer or a nitride layer.
  • Si is epitaxially grown from Si layer 104 and semiconductor layer 534 in the manner described in relation to FIG. 5D , thereby joining Si layer 104 and semiconductor layer 534 with a region “F”.
  • a transistor is formed in the manner described in relation to FIG. 5E .
  • the short channel effect is constrained and junction resistance is reduced by forming spaces in the active region below the gate electrode of a MOS transistor.
  • the present invention avoids the problem of the substrate floating effect that occurs in the SOI substrate. Further, it is possible to implement the technique whereby local stress is applied to the channel region. Accordingly, where the present invention is applied to the manufacture of very large scale integrated semiconductor devices, the performance of the device is improved by employing a structure which increases carrier mobility. In addition, the highly-integrated semiconductor devices can be manufactured at a low cost relative to those using SOI technology.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A semiconductor device and related method of manufacture are disclosed. The semiconductor device comprises a gate electrode formed on a semiconductor substrate, an active region containing spaces formed below the gate electrode, a channel region formed between the gate electrode and the spaces, and source and drain regions formed on opposite sides of the gate electrode within the active region. The spaces are formed by etching a semiconductor layer formed below the gate electrode in the active region.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates generally to a semiconductor device and a method of manufacturing the same. More particularly, the invention relates to a semiconductor device comprising a metal oxide semiconductor (MOS) transistor and a method of manufacturing the same.
  • A claim of priority is made to Korean Patent Application No. 10-2004-0049004 filed on Jun. 28, 2004, the disclosure of which is hereby incorporated by reference in its entirety.
  • 2. Description of the Related Art
  • Fully depleted silicon-on-insulator (FD-SOI) technology has been widely used to create high speed, low power logic circuits. Using FD-SOI technology reduces parasitic capacitances associated with source, drain, and channel regions of semiconductor circuits, thereby allowing the circuits to operate at higher speeds. In addition, FD-SOI technology reduces the amount of leakage current occurring at source and drain junctions of the circuits, thereby lowering associated power consumption. Furthermore, shallow source/drain regions are readily implemented using FD-SOI technology, thus allowing the short channel effect to be readily constrained and thereby improving the scalability of the circuits.
  • Unfortunately, however, a substrate floating effect may occur in MOS transistors formed on an SOI substrate where an element in a channel region assumes a floating state electric potential. Furthermore, where a buried oxide layer (BOX) is formed below a silicon substrate, a self-heating problem often occurs in devices formed on the silicon layer. As a result, the range of applications where SOI technology can be used is restricted by the kinds of circuits to be formed.
  • As complementary metal-oxide semiconductor (CMOS) technology has continued to shrink in size, a variety of attempts to improve the performance of transistors with short channel lengths have been made. Among these attempts, a mechanical stress engineering technique has been proposed. According to the mechanical stress engineering technique, a local stress is applied to a channel region so as to control the carrier (electron or hole) mobility (μ) within a semiconductor material. Where the carrier mobility increases, the switching characteristics of the device are improved, thus enabling the manufacture of higher-speed devices.
  • Unfortunately, it is difficult to apply local stress to SOI devices because the silicon layer formed on the buried oxide layer (BOX) is too thin. In addition, cost poses an obstacle to the manufacture of devices using SOI technology because SOI wafers are extremely expensive.
    • SUMMARY OF THE INVENTION
  • The present invention provides a semiconductor device capable of improving carrier mobility by applying a local stress to a channel region while maintaining advantages of an SOI device, such as the ability to constrain short channel effects and reduce junction resistance.
  • In addition, the present invention provides a method of manufacturing a semiconductor device in which a highly integrated semiconductor device having an improved short channel effect and reduced junction capacitance, as well as a device being capable of constraining a substrate floating effect may be implemented at a relatively low cost.
  • According to one embodiment of the present invention, a semiconductor device is provided. The semiconductor device comprises a gate electrode formed on a semiconductor substrate, an active region containing spaces formed below the gate electrode, a channel region formed between the gate electrode and the spaces, and source and drain regions formed on both sides of the gate electrode within the active region.
  • According to another embodiment of the present invention, a method of manufacturing a semiconductor device is provided. The method comprises forming a gate electrode on a semiconductor substrate, forming spaces in an active region below the gate electrode, forming a channel region between the gate electrode and the spaces, and forming source and gate regions on both sides of the gate electrode within the active region.
  • According to the present invention, the short channel effect is constrained and junction resistance is reduced by forming the spaces in the active region below the gate electrode. Furthermore, it effectively addresses the substrate floating effect which occurs in devices using SOI technology. Furthermore, the invention makes it possible to implement the mechanical stress engineering technique to the channel region to increase carrier mobility.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The invention is described below in relation to several embodiments illustrated in the accompanying drawings. Throughout the drawings like reference numbers indicate like exemplary elements, components, or steps and the thickness of various layers has been exaggerated for clarity. In the drawings:
  • FIGS. 1A through 1M are cross-sectional views illustrating a method of manufacturing a semiconductor device according to one embodiment of the present invention;
  • FIGS. 2A through 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention;
  • FIGS. 3A through 3C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to still another embodiment of the present invention;
  • FIGS. 4A through 4C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to still another embodiment of the present invention;
  • FIGS. 5A through 5C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to still another embodiment of the present invention; and,
  • FIGS. 6A through 6C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to a sixth embodiment of the present invention.
    • DESCRIPTION OF THE EXEMPLARY EMBODIMENTS
  • Exemplary embodiments of the invention are described below with reference to the corresponding drawings. These embodiments are presented as teaching examples. The actual scope of the invention is defined by the claims that follow.
  • FIGS. 1A through 1M are cross-sectional views illustrating a method of manufacturing a semiconductor device according to one embodiment of the present invention.
  • Referring to FIG. 1A, a first silicon germanium (SiGe) layer 102 is formed on a bulk semiconductor substrate 100 such as a silicon substrate. First SiGe layer 102 is generally formed to a thickness of about 10 to 100 nm using a selective epitaxial growth technology. A silicon (Si) layer 104 is then formed on first SiGe layer 102 to a thickness of about 5 to 50 nm.
  • Referring to FIG. 1B, an active region is defined by forming a device isolation region 106 on semiconductor substrate 100 using a conventional isolation method such as a trench isolation method. In other words, the active region is delimited on either side by device isolation region 106.
  • Referring to FIG. 1C, a gate insulating layer 112 and a gate electrode 114 are formed on Si layer 104 using a hard mask 116 formed of an insulating material. First insulating spacers 118 are formed on sidewalls of gate electrode 114. According to selected embodiments of the invention, first insulating spacers 118 comprise a silicon nitride layer 118 a, a silicon oxide layer 118 b, or a combination thereof.
  • Referring to FIG. 1D, an Si layer 104, first SiGe layer 102 and semiconductor substrate 100 are partially etched to form a recess region 120 using hard mask 116, first insulating spacers 118 and device isolation region 106 as an etching mask. In recess region 120, sidewalls of first SiGe layer 102, sidewalls of Si layer 104, and sidewalls of device isolation region 106 are exposed. A portion of Si layer 104 remaining below gate electrode 114 acts as a channel region for a transistor.
  • Referring to FIG. 1E, an insulating material is deposited on the structure having recess region 120 and an etch-back process is performed to form second insulating spacers 122 covering sidewalls of first SiGe layer 102, sidewalls of Si layer 104 and sidewalls of first insulating spacers 118, which are exposed in or above recess region 120. Second insulating spacers 122 are also formed on sidewalls of device isolation region 106. According to selected embodiments of the invention, second insulating spacers 122 are formed of a silicon oxide layer, a silicon nitride layer, or a combination thereof. Preferably, second insulating spacers 122 are formed of a silicon oxide layer.
  • Referring to FIG. 1F, a second SiGe layer 132 is formed on semiconductor substrate 100 in recess region 120. Second SiGe layer 132 is formed to a thickness of about 10 to 100 nm using a selective epitaxial growth technology. Preferably, second SiGe layer 132 has the same thickness as first SiGe layer 102. Also, preferably, a Ge concentration in second SiGe layer 132 is equal to a Ge concentration in first SiGe layer 102.
  • Referring to FIG. 1G, a semiconductor layer 134 is formed on second SiGe layer 132 using a selective epitaxial growth technology. Semiconductor layer 134 is formed of a different material from second SiGe layer 132. For example, semiconductor layer 134 may be formed of Si or SiC. Where semiconductor layer 134 is formed of SiC, the carrier mobility in an negative metal-oxide semiconductor (NMOS) device can be improved by locally applying a tensile stress to the channel region formed by Si layer 104.
  • Semiconductor layer 134 is formed to a thickness sufficient to completely fill recess region 120. As shown in FIG. 1G, semiconductor layer 134 typically has a thickness such that semiconductor layer 134 partially covers an upper surface of device isolation region 106. As a result, semiconductor layer 134 generally protects a corner portion of device isolation region 106.
  • Referring to FIG. 1H, second insulating spacers 122 etched and thereby removed. Consequently, the sidewalls of first and second SiGe layers 102 and 132 are exposed through spaces 136 between Si layer 104 and semiconductor layer 134.
  • Referring to FIG. 11, first and second SiGe layers 102 and 132 are selectively removed to form spaces 140 below Si layer 104 and semiconductor layer 134, respectively. First and second SiGe layers 102 and 132 are generally removed using a wet etching process or an isotropic plasma etching process. The plasma etching process may employ, for example, an etchant comprised of a mixture of HNO3, H2O2, and HF.
  • Referring to FIG. 1J, Si is epitaxially grown from Si layer 104 and semiconductor layer 134 using a selective epitaxial growth technology. As a result, Si layer 104 and semiconductor layer 134 are joined together by a region “A”.
  • Referring to FIG. 1K, an extension region 152 and a halo ion implantation region 154 are formed in semiconductor layer 134 and Si layer 104 using a conventional ion implantation process using hard mask 116 as an ion implantation mask.
  • Referring to FIG. 1L, third insulating spacers 156 covering silicon oxide layer 118 b are formed on the sidewalls of gate electrode 114. Third insulating spacers 156 are usually formed of either a silicon oxide layer, a silicon nitride layer, or a combination thereof. Preferably, third insulating spacers 156 are formed of a silicon oxide layer.
  • Source and drain regions 158 are then formed in semiconductor layer 134 and Si layer 104. Source and drain regions 158 are typically formed using a conventional ion implantation process using hard mask 116 and third insulating spacers 156 as an ion implantation mask.
  • Referring to FIG. 1M, hard mask 116 is removed from gate electrode 114 and then metal silicide layers 162 and 164 are formed on upper surfaces of gate electrode 114 and source and drain regions 158 using a conventional silicide deposition process. Metal silicide layers 162 and 164 contribute to reduced surface resistance and contact resistance for contacts in the semiconductor device. Metal silicide layers 162 and 164 are typically formed of cobalt silicide, nickel silicide, titanium silicide, hafnium silicide, platinum silicide, or tungsten silicide. In some instances, the formation of metal silicide layers 162 and 164 can be omitted.
  • According to selected embodiments of the present invention, spaces 140 are extended to completely overlap the channel region and source and drain regions 158. Accordingly, as in the case where a SOI substrate is used, the short channel effect is readily constrained and junction capacitance is reduced.
  • FIGS. 2A through 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention.
  • The embodiment illustrated in FIGS. 2A through 2C is substantially similar to the embodiment illustrated in FIGS. 1A through 1M. One difference, however, is that spaces 140 formed in the active region below gate electrode 114 are filled with insulating materials.
  • Referring to FIG. 2A, spaces 140 are formed in an active region of a semiconductor substrate 100 in the manner described in relation to FIGS. 1A through 11. An insulating material is deposited to fill spaces 140 and an etch-back process is performed to expose sidewalls of Si layer 104. Consequently, spaces 140 are filled by an insulating layer 240. Insulating layer 240 is typically formed of an oxide layer or a nitride layer.
  • Referring to FIG. 2B, Si is epitaxially grown from Si layer 104 and semiconductor layer 134 in the manner described in relation to FIG. 1J, thereby joining Si layer 104 and semiconductor layer 134 with a region “B”.
  • Referring to FIG. 2C, a transistor is formed in the manner described in relation to FIGS. 1K through 1M.
  • According to selected embodiments of the present invention, insulating layer 240 is extended to completely overlap the channel region and source and drain regions 158. Accordingly, as in the case where a SOI substrate is used, the short channel effect is readily constrained and junction capacitance is reduced.
  • FIGS. 3A through 3C are cross-sectional views illustrating a method of fabricating a semiconductor device according to still another embodiment of the present invention.
  • The method illustrated in FIGS. 3A through 3C is substantially similar to the method illustrated in FIGS. 1A through 1M. One difference, however, is that the spaces formed on the active region below gate electrode 114 are extended to only a portion of the active region.
  • Referring to FIG. 3A, spaces 136 exposing the sidewalls of first and second SiGe layers 102 and 132 are formed on semiconductor substrate 100 in the manner described in relation to FIGS. 1A through 1H. First and second SiGe layers 102 and 132 exposed through spaces 136 are partially removed to form spaces 340 below Si layer 104 and semiconductor layer 134. Portions of second SiGe layer 132 adjacent to second insulating spacers 122 are prevented from being removed by controlling the amount of time used to etch first and second SiGe layers 102 and 132.
  • Referring to FIG. 3B, Si is epitaxially grown from Si layer 104 and semiconductor layer 134 in the manner described in relation to FIG. 1J, thereby joining Si layer 104 and semiconductor layer 134 with a region “C”.
  • Referring to FIG. 3C, a transistor is formed in the manner described in relation to FIGS. 1K through 1M.
  • According to selected embodiments of the present invention, spaces 340 are extended to completely overlap the channel region and to partially overlap source and drain regions 158. In other words, spaces 340 formed in the active region below gate electrode 114 are extended cover only a portion of the active region. A portion of second SiGe layer 132 adjacent to second insulating spacers 122 still remains between semiconductor substrate 100 and semiconductor layer 134. Accordingly, the length of spaces 340 is limited by the portion of second SiGe layer 132 remaining between semiconductor substrate 100 and source and drain regions 158. Due to second SiGe layer 132, a substrate floating effect is prevented from occurring in a MOS transistor.
  • FIGS. 4A through 4C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to still another embodiment of the present invention.
  • The method illustrated in FIGS. 4A is substantially similar to the method illustrated in FIGS. 3A through 3C. However, one difference is that spaces 340 formed in the active region below gate electrode 114 are filled with an insulating material.
  • Referring to FIG. 4A, an insulating material is deposited to fill spaces 340 shown in FIG. 3A and an etch-back process is performed until sidewalls of Si layer 104 are exposed, thereby forming an insulating layer 440. Insulating layer 440 typically comprises an oxide layer or a nitride layer.
  • Referring to FIG. 4B, Si is epitaxially grown from Si layer 104 and semiconductor layer 134 in the manner described in relation to FIG. 1J, thereby joining Si layer 104 and semiconductor layer 134 with a region “D”.
  • Referring to FIG. 4C, a transistor is formed in the manner described in relation to FIGS. 1K through 1M.
  • FIGS. 5A through 5E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to still another embodiment of the present invention.
  • The method illustrated in FIGS. 5A through 5E is substantially similar to the method illustrated in FIGS. 1A through 1M. One difference, however, is that spaces are only formed below the channel region but not in other parts of the active region.
  • Referring to FIG. 5A, second insulating spacers 122 are formed in the manner described in relation to FIGS. 1A through 1E. A semiconductor layer 534 is then formed on semiconductor substrate 100 in recess region 120. Typically, semiconductor layer 534 is formed of materials whose composition is different from that of first SiGe layer 102. For example, semiconductor layer 534 is typically formed of Si, SiC or SiGe. Where semiconductor layer 534 is formed of SiC, the carrier mobility in a NMOS device is readily improved by locally applying a tensile stress to the channel region formed by Si layer 104. Where semiconductor layer 534 is formed of SiGe, the carrier mobility in a positive metal-oxide semiconductor (PMOS) device is readily improved by locally applying a tensile stress to the channel region formed by Si layer 104. Where semiconductor layer 534 is formed of SiGe, it preferably has a Ge concentration lower than the Ge concentration of first SiGe layer 102.
  • Semiconductor layer 534 is formed to a thickness sufficient to fill recess region 120. As shown in FIG. 5A, semiconductor layer 534 typically has a thickness such that it partially covers an upper surface of device isolation region 106, thereby protecting a corner portion of device isolation region 106.
  • Referring to FIG. 5B, second insulating spacers 122 and silicon oxide layer 118 b are selectively etched and removed in the manner described in relation to FIG. 1H. Consequently, spaces 136 are formed between Si layer 104 and semiconductor layer 534. Sidewalls of first SiGe layer 102 are exposed through spaces 136.
  • Referring to FIG. 5C, first SiGe layer 102 is selectively removed to form spaces 540 below Si layer 104 in the manner described in relation to FIG. 1I. Where semiconductor layer 534 is formed of SiGe, the Ge concentration of first SiGe layer 102 is typically higher than that of semiconductor layer 534, as described in relation to FIG. 5A. Accordingly, even where semiconductor layer 534 is formed of SiGe, first SiGe layer 102 can be selectively removed under the condition that it has a high etch selectivity relative to semiconductor layer 534.
  • Referring to FIG. 5D, Si is epitaxially grown from Si layer 104 and semiconductor layer 534 in the same manner described in relation to FIG. 1J, thereby joining Si layer 104 and semiconductor layer 534 with a region “E”. Consequently, spaces 540 remain only below the channel region formed by Si layer 104 in the active region.
  • Referring to FIG. 5E, extension region 152 and halo ion implantation region 154 are formed in semiconductor layer 534 and Si layer 104 below gate electrode 114 in the manner described in relation to FIGS. 1K through 1M. Third insulating spacers 156 and source and drain regions 158 are then formed. Where necessary, metal silicide layers 162 and 164 are formed on gate electrode 114 and source and drain regions 158. In this manner, the formation of a transistor is completed.
  • FIGS. 6A through 6C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to still another embodiment of the present invention.
  • The method illustrated in FIGS. 6A through 6C is substantially similar to the method illustrated in FIGS. 5A through 5E. One difference, however, is that spaces 540 formed below the channel region formed by Si layer 104 are filled with an insulating material.
  • Referring to FIG. 6A, spaces 540 are formed below Si layer 104 in the manner described in relation to FIGS. 5A through 5C. An insulating material is deposited on semiconductor substrate 100 to fill spaces 540 and an etch-back process is performed until the sidewalls of Si layer 104 are exposed. Consequently, spaces 540 are filled with an insulating layer 640. Insulating layer 640 is typically formed of an oxide layer or a nitride layer.
  • Referring to FIG. 6B, Si is epitaxially grown from Si layer 104 and semiconductor layer 534 in the manner described in relation to FIG. 5D, thereby joining Si layer 104 and semiconductor layer 534 with a region “F”.
  • Referring to FIG. 6C, a transistor is formed in the manner described in relation to FIG. 5E.
  • According to the present invention, the short channel effect is constrained and junction resistance is reduced by forming spaces in the active region below the gate electrode of a MOS transistor. In addition, the present invention avoids the problem of the substrate floating effect that occurs in the SOI substrate. Further, it is possible to implement the technique whereby local stress is applied to the channel region. Accordingly, where the present invention is applied to the manufacture of very large scale integrated semiconductor devices, the performance of the device is improved by employing a structure which increases carrier mobility. In addition, the highly-integrated semiconductor devices can be manufactured at a low cost relative to those using SOI technology.
  • The exemplary embodiments of the present invention described herein are teaching examples. Those of ordinary skill will understand that various changes in form and details may be made thereto without departing from the scope of the present invention as defined by the following claims.

Claims (21)

1. A semiconductor device, comprising:
a gate electrode formed on a semiconductor substrate;
an active region comprising spaces formed below the gate electrode;
a channel region formed between the gate electrode and the spaces; and,
source and drain regions respectively formed within the active region on opposite sides of the gate electrode.
2. The semiconductor device of claim 1, wherein the channel region comprises a silicon (Si) layer; and,
wherein the source and drain regions are formed of a Si layer, a silicon carbide (SiC) layer, or a silicon germanium (SiGe) layer.
3. The semiconductor device of claim 1, wherein the spaces extend to completely overlap the channel region and at least one of the source and drain regions.
4. The semiconductor device of claim 1, wherein the spaces extend to completely overlap the channel region, and at least partially overlap at least one of the source and drain regions.
5. The semiconductor device of claim 4, further comprising:
a semiconductor layer formed between the semiconductor substrate and the source and drain regions to define a length of the spaces.
6. The semiconductor device of claim 5, wherein the semiconductor layer comprises a SiGe layer.
7. The semiconductor device of claim 1, further comprising an insulating layer filling the spaces.
8. The semiconductor device of claim 7, wherein the insulating layer is formed of an oxide layer or a nitride layer.
9. A method of manufacturing a semiconductor device, comprising:
forming a first silicon germanium (SiGe) layer formed on a bulk semiconductor substrate;
forming a silicon (Si) layer on the first SiGe layer;
defining an active region on the semiconductor substrate;
sequentially forming a gate insulating layer and a gate electrode on the Si layer;
selectively removing portions of the Si layer and the first SiGe layer to form a recess region exposing the semiconductor substrate, the recess region being formed in the active region near the gate electrode;
forming a semiconductor layer within the recess region;
selectively removing the first SiGe layer to form spaces below the Si layer in the active region;
epitaxially growing Si, such that the Si layer and the semiconductor layer are joined; and,
forming source and drain regions in the semiconductor layer.
10. The method of claim 9, wherein the semiconductor layer comprises:
a first semiconductor layer formed from a second SiGe layer, and a second semiconductor layer formed from a Si layer or a SiC layer.
11. The method of claim 10, wherein Ge concentration in the second SiGe layer is substantially equal to Ge concentration in the first SiGe layer.
12. The method of claim 10, wherein the first semiconductor layer is selectively and simultaneously removed with the selective removal of the first SiGe layer; and
wherein the spaces extended from a lower portion of the Si layer to a lower portion of the second semiconductor layer.
13. The method of claim 12, wherein the first semiconductor layer is completely and simultaneously removed.
14. The method of claim 12, wherein the first semiconductor layer is partially simultaneously removed.
15. The method of claim 9, wherein the semiconductor layer is formed from a single layer comprising a Si layer, a SiC layer, or a SiGe layer.
16. The method of claim 15, wherein the semiconductor layer is not removed with the first SiGe layer.
17. The method of claim 9, wherein the spaces are formed only below the Si layer.
18. The method of claim 15, wherein the semiconductor layer is formed from a SiGe layer having a concentration of Ge which is lower than a concentration of Ge in the first SiGe layer.
19. The method of claim 9, further comprising:
forming an insulating layer to fill the spaces.
20. The method of claim 19, wherein the insulating layer is formed from an oxide layer or a nitride layer.
21. A method of manufacturing a semiconductor device, comprising:
forming a gate electrode on a semiconductor substrate;
forming spaces in an active region below the gate electrode;
forming a channel region between the gate electrode and the spaces; and,
forming source and gate regions on opposite sides of the gate electrode within the active region.
US11/081,538 2004-06-28 2005-03-17 Semiconductor device and method of manufacturing same Abandoned US20050285193A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US12/015,646 US7989296B2 (en) 2004-06-28 2008-01-17 Semiconductor device and method of manufacturing same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020040049004A KR100618839B1 (en) 2004-06-28 2004-06-28 Method for manufacturing semiconductor device
KR2004-49004 2004-06-28

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/015,646 Division US7989296B2 (en) 2004-06-28 2008-01-17 Semiconductor device and method of manufacturing same

Publications (1)

Publication Number Publication Date
US20050285193A1 true US20050285193A1 (en) 2005-12-29

Family

ID=35504717

Family Applications (2)

Application Number Title Priority Date Filing Date
US11/081,538 Abandoned US20050285193A1 (en) 2004-06-28 2005-03-17 Semiconductor device and method of manufacturing same
US12/015,646 Expired - Fee Related US7989296B2 (en) 2004-06-28 2008-01-17 Semiconductor device and method of manufacturing same

Family Applications After (1)

Application Number Title Priority Date Filing Date
US12/015,646 Expired - Fee Related US7989296B2 (en) 2004-06-28 2008-01-17 Semiconductor device and method of manufacturing same

Country Status (2)

Country Link
US (2) US20050285193A1 (en)
KR (1) KR100618839B1 (en)

Cited By (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070210301A1 (en) * 2006-03-09 2007-09-13 Jin-Ping Han Semiconductor devices and methods of manufacturing thereof
US20070228417A1 (en) * 2006-04-03 2007-10-04 Kabushiki Kaisha Toshiba Semiconductor device and method of fabricating the same
US20090166761A1 (en) * 2005-12-13 2009-07-02 Nxp B.V. Field effect transistor structure with an insulating layer at the junction
US20100213554A1 (en) * 2009-02-23 2010-08-26 I-Chang Wang Gate structure and method for trimming spacers
US8324059B2 (en) 2011-04-25 2012-12-04 United Microelectronics Corp. Method of fabricating a semiconductor structure
US8426284B2 (en) 2011-05-11 2013-04-23 United Microelectronics Corp. Manufacturing method for semiconductor structure
US8431460B2 (en) 2011-05-27 2013-04-30 United Microelectronics Corp. Method for fabricating semiconductor device
US8445363B2 (en) 2011-04-21 2013-05-21 United Microelectronics Corp. Method of fabricating an epitaxial layer
US8466502B2 (en) 2011-03-24 2013-06-18 United Microelectronics Corp. Metal-gate CMOS device
US8476169B2 (en) 2011-10-17 2013-07-02 United Microelectronics Corp. Method of making strained silicon channel semiconductor structure
US8481391B2 (en) 2011-05-18 2013-07-09 United Microelectronics Corp. Process for manufacturing stress-providing structure and semiconductor device with such stress-providing structure
WO2013113184A1 (en) * 2012-02-01 2013-08-08 中国科学院微电子研究所 Semiconductor structure and manufacturing method thereof
US8575043B2 (en) 2011-07-26 2013-11-05 United Microelectronics Corp. Semiconductor device and manufacturing method thereof
US8647941B2 (en) 2011-08-17 2014-02-11 United Microelectronics Corp. Method of forming semiconductor device
US8647953B2 (en) 2011-11-17 2014-02-11 United Microelectronics Corp. Method for fabricating first and second epitaxial cap layers
US20140042529A1 (en) * 2012-08-10 2014-02-13 Renesas Electronics Corporation Semiconductor device and manufactruing method of the same
US8664069B2 (en) 2012-04-05 2014-03-04 United Microelectronics Corp. Semiconductor structure and process thereof
US8674433B2 (en) 2011-08-24 2014-03-18 United Microelectronics Corp. Semiconductor process
US8691659B2 (en) 2011-10-26 2014-04-08 United Microelectronics Corp. Method for forming void-free dielectric layer
US8710632B2 (en) 2012-09-07 2014-04-29 United Microelectronics Corp. Compound semiconductor epitaxial structure and method for fabricating the same
US8709930B2 (en) 2011-11-25 2014-04-29 United Microelectronics Corp. Semiconductor process
US8716750B2 (en) 2011-07-25 2014-05-06 United Microelectronics Corp. Semiconductor device having epitaxial structures
US8754448B2 (en) 2011-11-01 2014-06-17 United Microelectronics Corp. Semiconductor device having epitaxial layer
US8753902B1 (en) 2013-03-13 2014-06-17 United Microelectronics Corp. Method of controlling etching process for forming epitaxial structure
US8765546B1 (en) 2013-06-24 2014-07-01 United Microelectronics Corp. Method for fabricating fin-shaped field-effect transistor
US8796695B2 (en) 2012-06-22 2014-08-05 United Microelectronics Corp. Multi-gate field-effect transistor and process thereof
US8835243B2 (en) 2012-05-04 2014-09-16 United Microelectronics Corp. Semiconductor process
US8853060B1 (en) 2013-05-27 2014-10-07 United Microelectronics Corp. Epitaxial process
US8866230B2 (en) 2012-04-26 2014-10-21 United Microelectronics Corp. Semiconductor devices
US8895396B1 (en) 2013-07-11 2014-11-25 United Microelectronics Corp. Epitaxial Process of forming stress inducing epitaxial layers in source and drain regions of PMOS and NMOS structures
US8951876B2 (en) 2012-06-20 2015-02-10 United Microelectronics Corp. Semiconductor device and manufacturing method thereof
US8981487B2 (en) 2013-07-31 2015-03-17 United Microelectronics Corp. Fin-shaped field-effect transistor (FinFET)
US9034705B2 (en) 2013-03-26 2015-05-19 United Microelectronics Corp. Method of forming semiconductor device
US9064893B2 (en) 2013-05-13 2015-06-23 United Microelectronics Corp. Gradient dopant of strained substrate manufacturing method of semiconductor device
US9076652B2 (en) 2013-05-27 2015-07-07 United Microelectronics Corp. Semiconductor process for modifying shape of recess
US9117925B2 (en) 2013-01-31 2015-08-25 United Microelectronics Corp. Epitaxial process
US9136348B2 (en) 2012-03-12 2015-09-15 United Microelectronics Corp. Semiconductor structure and fabrication method thereof
US9202914B2 (en) 2012-03-14 2015-12-01 United Microelectronics Corporation Semiconductor device and method for fabricating the same
US20170133460A1 (en) * 2015-11-09 2017-05-11 United Microelectronics Corp. Semiconductor structure and manufacturing method thereof
US20190363135A1 (en) * 2016-09-29 2019-11-28 Intel Corporation Resistive random access memory cell
CN110649036A (en) * 2018-06-27 2020-01-03 台湾积体电路制造股份有限公司 Bulk semiconductor substrate configured to exhibit semiconductor-on-insulator behavior

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7473594B2 (en) * 2006-07-25 2009-01-06 International Business Machines Corporation Raised STI structure and superdamascene technique for NMOSFET performance enhancement with embedded silicon carbon
US20080157200A1 (en) * 2006-12-27 2008-07-03 International Business Machines Corporation Stress liner surrounded facetless embedded stressor mosfet
KR100855977B1 (en) 2007-02-12 2008-09-02 삼성전자주식회사 Semiconductor device and methods for manufacturing the same
WO2009147559A1 (en) * 2008-06-02 2009-12-10 Nxp B.V. Local buried layer forming method and semiconductor device having such a layer
US8106468B2 (en) * 2008-06-20 2012-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Process for fabricating silicon-on-nothing MOSFETs
CN102299074B (en) * 2010-06-22 2013-04-17 中国科学院微电子研究所 Semiconductor device and forming method thereof
US8278200B2 (en) * 2011-01-24 2012-10-02 International Business Machines Corpration Metal-semiconductor intermixed regions
KR20130000212A (en) * 2011-06-22 2013-01-02 삼성전자주식회사 Semiconductor device and method of fabricating the same
US8524566B2 (en) * 2011-12-20 2013-09-03 GlobalFoundries, Inc. Methods for the fabrication of integrated circuits including back-etching of raised conductive structures
US9040394B2 (en) 2013-03-12 2015-05-26 Samsung Electronics Co., Ltd. Method for fabricating a semiconductor device
US9041062B2 (en) 2013-09-19 2015-05-26 International Business Machines Corporation Silicon-on-nothing FinFETs
US9224841B2 (en) 2014-01-23 2015-12-29 Globalfoundries Inc. Semiconductor fins on a trench isolation region in a bulk semiconductor substrate and a method of forming the semiconductor fins
US9093478B1 (en) 2014-04-11 2015-07-28 International Business Machines Corporation Integrated circuit structure with bulk silicon FinFET and methods of forming
US9941388B2 (en) * 2014-06-19 2018-04-10 Globalfoundries Inc. Method and structure for protecting gates during epitaxial growth
US9431536B1 (en) 2015-03-16 2016-08-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure with raised source/drain having cap element
DE102016119799B4 (en) * 2016-10-18 2020-08-06 Infineon Technologies Ag INTEGRATED CIRCUIT CONTAINING A CURVED CAVE AND PRODUCTION METHOD
US10461154B1 (en) * 2018-06-21 2019-10-29 International Business Machines Corporation Bottom isolation for nanosheet transistors on bulk substrate

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5240876A (en) * 1991-02-22 1993-08-31 Harris Corporation Method of fabricating SOI wafer with SiGe as an etchback film in a BESOI process
US20020149031A1 (en) * 2001-04-12 2002-10-17 Samsung Electronics Co., Ltd. Semiconductor device having gate all around type transistor and method of forming the same
US20030155572A1 (en) * 2002-02-19 2003-08-21 Min-Koo Han Thin film transistor and method for manufacturing thereof
US7019364B1 (en) * 1999-08-31 2006-03-28 Kabushiki Kaisha Toshiba Semiconductor substrate having pillars within a closed empty space
US7033868B2 (en) * 2003-09-24 2006-04-25 Fujitsu Limited Semiconductor device and method of manufacturing same

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3762136B2 (en) * 1998-04-24 2006-04-05 株式会社東芝 Semiconductor device
JP3527880B2 (en) * 2000-06-21 2004-05-17 シャープ株式会社 Semiconductor device and manufacturing method thereof
JP2003298047A (en) * 2002-04-02 2003-10-17 Takehide Shirato Semiconductor device and manufacturing method therefor
JP4277481B2 (en) * 2002-05-08 2009-06-10 日本電気株式会社 Semiconductor substrate manufacturing method and semiconductor device manufacturing method
KR100598098B1 (en) * 2004-02-06 2006-07-07 삼성전자주식회사 Metal-Oxide-Semiconductor Having Buried Insulation Region And Methods Of Fabricating The Same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5240876A (en) * 1991-02-22 1993-08-31 Harris Corporation Method of fabricating SOI wafer with SiGe as an etchback film in a BESOI process
US7019364B1 (en) * 1999-08-31 2006-03-28 Kabushiki Kaisha Toshiba Semiconductor substrate having pillars within a closed empty space
US20020149031A1 (en) * 2001-04-12 2002-10-17 Samsung Electronics Co., Ltd. Semiconductor device having gate all around type transistor and method of forming the same
US20030155572A1 (en) * 2002-02-19 2003-08-21 Min-Koo Han Thin film transistor and method for manufacturing thereof
US7033868B2 (en) * 2003-09-24 2006-04-25 Fujitsu Limited Semiconductor device and method of manufacturing same

Cited By (61)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090166761A1 (en) * 2005-12-13 2009-07-02 Nxp B.V. Field effect transistor structure with an insulating layer at the junction
US7923346B2 (en) * 2005-12-13 2011-04-12 Nxp B.V. Field effect transistor structure with an insulating layer at the junction
US7696019B2 (en) * 2006-03-09 2010-04-13 Infineon Technologies Ag Semiconductor devices and methods of manufacturing thereof
US20100136761A1 (en) * 2006-03-09 2010-06-03 Jin-Ping Han Semiconductor Devices and Methods of Manufacturing Thereof
US8647929B2 (en) * 2006-03-09 2014-02-11 Infineon Technologies Ag Semiconductor devices and methods of manufacturing thereof
US20070210301A1 (en) * 2006-03-09 2007-09-13 Jin-Ping Han Semiconductor devices and methods of manufacturing thereof
US20070228417A1 (en) * 2006-04-03 2007-10-04 Kabushiki Kaisha Toshiba Semiconductor device and method of fabricating the same
US20100213554A1 (en) * 2009-02-23 2010-08-26 I-Chang Wang Gate structure and method for trimming spacers
US9318571B2 (en) 2009-02-23 2016-04-19 United Microelectronics Corp. Gate structure and method for trimming spacers
US8466502B2 (en) 2011-03-24 2013-06-18 United Microelectronics Corp. Metal-gate CMOS device
US8592271B2 (en) 2011-03-24 2013-11-26 United Microelectronics Corp. Metal-gate CMOS device and fabrication method thereof
US8445363B2 (en) 2011-04-21 2013-05-21 United Microelectronics Corp. Method of fabricating an epitaxial layer
US8324059B2 (en) 2011-04-25 2012-12-04 United Microelectronics Corp. Method of fabricating a semiconductor structure
US8426284B2 (en) 2011-05-11 2013-04-23 United Microelectronics Corp. Manufacturing method for semiconductor structure
US8481391B2 (en) 2011-05-18 2013-07-09 United Microelectronics Corp. Process for manufacturing stress-providing structure and semiconductor device with such stress-providing structure
US8431460B2 (en) 2011-05-27 2013-04-30 United Microelectronics Corp. Method for fabricating semiconductor device
US8716750B2 (en) 2011-07-25 2014-05-06 United Microelectronics Corp. Semiconductor device having epitaxial structures
US8575043B2 (en) 2011-07-26 2013-11-05 United Microelectronics Corp. Semiconductor device and manufacturing method thereof
US8647941B2 (en) 2011-08-17 2014-02-11 United Microelectronics Corp. Method of forming semiconductor device
US8674433B2 (en) 2011-08-24 2014-03-18 United Microelectronics Corp. Semiconductor process
US8853740B2 (en) 2011-10-17 2014-10-07 United Microelectronics Corp. Strained silicon channel semiconductor structure
US8476169B2 (en) 2011-10-17 2013-07-02 United Microelectronics Corp. Method of making strained silicon channel semiconductor structure
US8691659B2 (en) 2011-10-26 2014-04-08 United Microelectronics Corp. Method for forming void-free dielectric layer
US8754448B2 (en) 2011-11-01 2014-06-17 United Microelectronics Corp. Semiconductor device having epitaxial layer
US8927376B2 (en) 2011-11-01 2015-01-06 United Microelectronics Corp. Semiconductor device and method of forming epitaxial layer
US8647953B2 (en) 2011-11-17 2014-02-11 United Microelectronics Corp. Method for fabricating first and second epitaxial cap layers
US8709930B2 (en) 2011-11-25 2014-04-29 United Microelectronics Corp. Semiconductor process
US8969164B2 (en) 2012-02-01 2015-03-03 Institute of Microelectronics, Chinese Academy of Sciences Semiconductor structure and method for manufacturing the same
CN103247624A (en) * 2012-02-01 2013-08-14 中国科学院微电子研究所 Semiconductor structure and manufacturing method thereof
WO2013113184A1 (en) * 2012-02-01 2013-08-08 中国科学院微电子研究所 Semiconductor structure and manufacturing method thereof
US9312359B2 (en) 2012-03-12 2016-04-12 United Microelectronics Corp. Semiconductor structure and fabrication method thereof
US9136348B2 (en) 2012-03-12 2015-09-15 United Microelectronics Corp. Semiconductor structure and fabrication method thereof
US9202914B2 (en) 2012-03-14 2015-12-01 United Microelectronics Corporation Semiconductor device and method for fabricating the same
US9443970B2 (en) 2012-03-14 2016-09-13 United Microelectronics Corporation Semiconductor device with epitaxial structures and method for fabricating the same
US8884346B2 (en) 2012-04-05 2014-11-11 United Microelectronics Corp. Semiconductor structure
US8664069B2 (en) 2012-04-05 2014-03-04 United Microelectronics Corp. Semiconductor structure and process thereof
US8866230B2 (en) 2012-04-26 2014-10-21 United Microelectronics Corp. Semiconductor devices
US8835243B2 (en) 2012-05-04 2014-09-16 United Microelectronics Corp. Semiconductor process
US8951876B2 (en) 2012-06-20 2015-02-10 United Microelectronics Corp. Semiconductor device and manufacturing method thereof
US9269811B2 (en) 2012-06-20 2016-02-23 United Microelectronics Corp. Spacer scheme for semiconductor device
US8796695B2 (en) 2012-06-22 2014-08-05 United Microelectronics Corp. Multi-gate field-effect transistor and process thereof
US8999793B2 (en) 2012-06-22 2015-04-07 United Microelectronics Corp. Multi-gate field-effect transistor process
US20140042529A1 (en) * 2012-08-10 2014-02-13 Renesas Electronics Corporation Semiconductor device and manufactruing method of the same
US9130039B2 (en) * 2012-08-10 2015-09-08 Renesas Electronics Corporation Semiconductor device and manufacturing method of the same
US9484456B2 (en) 2012-08-10 2016-11-01 Renesas Electronics Corporation Semiconductor device and manufacturing method of the same
US8710632B2 (en) 2012-09-07 2014-04-29 United Microelectronics Corp. Compound semiconductor epitaxial structure and method for fabricating the same
US9117925B2 (en) 2013-01-31 2015-08-25 United Microelectronics Corp. Epitaxial process
US8753902B1 (en) 2013-03-13 2014-06-17 United Microelectronics Corp. Method of controlling etching process for forming epitaxial structure
US9034705B2 (en) 2013-03-26 2015-05-19 United Microelectronics Corp. Method of forming semiconductor device
US9064893B2 (en) 2013-05-13 2015-06-23 United Microelectronics Corp. Gradient dopant of strained substrate manufacturing method of semiconductor device
US8853060B1 (en) 2013-05-27 2014-10-07 United Microelectronics Corp. Epitaxial process
US9263579B2 (en) 2013-05-27 2016-02-16 United Microelectronics Corp. Semiconductor process for modifying shape of recess
US9076652B2 (en) 2013-05-27 2015-07-07 United Microelectronics Corp. Semiconductor process for modifying shape of recess
US8765546B1 (en) 2013-06-24 2014-07-01 United Microelectronics Corp. Method for fabricating fin-shaped field-effect transistor
US8895396B1 (en) 2013-07-11 2014-11-25 United Microelectronics Corp. Epitaxial Process of forming stress inducing epitaxial layers in source and drain regions of PMOS and NMOS structures
US8981487B2 (en) 2013-07-31 2015-03-17 United Microelectronics Corp. Fin-shaped field-effect transistor (FinFET)
US20170133460A1 (en) * 2015-11-09 2017-05-11 United Microelectronics Corp. Semiconductor structure and manufacturing method thereof
US20190363135A1 (en) * 2016-09-29 2019-11-28 Intel Corporation Resistive random access memory cell
CN110649036A (en) * 2018-06-27 2020-01-03 台湾积体电路制造股份有限公司 Bulk semiconductor substrate configured to exhibit semiconductor-on-insulator behavior
US10672795B2 (en) * 2018-06-27 2020-06-02 Taiwan Semiconductor Manufacturing Co., Ltd. Bulk semiconductor substrate configured to exhibit semiconductor-on-insulator behavior
US11211283B2 (en) 2018-06-27 2021-12-28 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming a bulk semiconductor substrate configured to exhibit soi behavior

Also Published As

Publication number Publication date
KR100618839B1 (en) 2006-09-01
US7989296B2 (en) 2011-08-02
US20080132011A1 (en) 2008-06-05
KR20060000276A (en) 2006-01-06

Similar Documents

Publication Publication Date Title
US7989296B2 (en) Semiconductor device and method of manufacturing same
US9647118B2 (en) Device having EPI film in substrate trench
US7034362B2 (en) Double silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) structures
US7915100B2 (en) Hybrid orientation CMOS with partial insulation process
US7410859B1 (en) Stressed MOS device and method for its fabrication
US7687365B2 (en) CMOS structure for body ties in ultra-thin SOI (UTSOI) substrates
US7023057B2 (en) CMOS on hybrid substrate with different crystal orientations using silicon-to-silicon direct wafer bonding
US7425483B2 (en) Structure and method of fabricating a hybrid substrate for high-performance hybrid-orientation silicon-on-insulator CMOS devices
US7326601B2 (en) Methods for fabrication of a stressed MOS device
US7619300B2 (en) Super hybrid SOI CMOS devices
US10170475B2 (en) Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon region
US10038075B2 (en) Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon-germanium region
US20070102756A1 (en) FinFET transistor fabricated in bulk semiconducting material
US6406951B1 (en) Fabrication of fully depleted field effect transistor with raised source and drain in SOI technology
JP2008227026A (en) Manufacturing method of semiconductor device
US8389391B2 (en) Triple-gate transistor with reverse shallow trench isolation
US8017472B2 (en) CMOS devices having stress-altering material lining the isolation trenches and methods of manufacturing thereof
US7611937B2 (en) High performance transistors with hybrid crystal orientations
US7442612B2 (en) Nitride-encapsulated FET (NNCFET)
US6657261B2 (en) Ground-plane device with back oxide topography

Legal Events

Date Code Title Description
AS Assignment

Owner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OF

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LEE, SUNG-YOUNG;SHIN, DONG-SUK;REEL/FRAME:016388/0241

Effective date: 20050308

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION