US20050249025A1 - Method and System For A Variable Frequency SDRAM Controller - Google Patents
Method and System For A Variable Frequency SDRAM Controller Download PDFInfo
- Publication number
- US20050249025A1 US20050249025A1 US10/709,299 US70929904A US2005249025A1 US 20050249025 A1 US20050249025 A1 US 20050249025A1 US 70929904 A US70929904 A US 70929904A US 2005249025 A1 US2005249025 A1 US 2005249025A1
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- United States
- Prior art keywords
- clock
- frequency
- proper position
- signals
- low level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
Definitions
- SDRAM controller becomes a fundamental block of the ASIC design for a digital system.
- a new method to control the SDRAM is presented here, in which a non-regular frequency clock or control signals are involved to best fit timing requirement of a standard SDRAM. As a result, the most efficient timing to access a SDRAM is achieved.
- the conventional way to control a SDRAM is using a fix frequency clock as reference, generating all clock-based control signals such as RAS_, CAS_, MA according to this reference clock (see FIG. 1 ).
- the fix frequency is constrained and decided by both system bandwidth requirement and working frequency of the logic circuit within an ASIC.
- the cycle time Tcyc (1/Frequency) is used as the basic unit to generate all control signals.
- These control signals seen by the SDRAM must be an integer multiple-cycled pulse in unit of Tcyc, since a fix frequency is fed to the SDRAM as a reference clock.
- the invention provides a method for providing a variable frequency clock for a SDRAM.
- the method comprises the following steps: (1) receiving a clock with a fixed frequency and a plurality of signals, wherein each the signal is an interlace combination of a plurality of high level signals and a plurality of low levels signals; (2) extracting a plurality of proper positions from the signals, wherein each low level of each the signal corresponds to a proper position; and (3) amending the frequency of the clock such that each the proper position corresponds to a rising edge of the clock.
- each the proper position could located at the center of corresponding the low level; each the proper position could be located at a safety region around the center of corresponding the low level; and each the proper position could be located at a safety region inside corresponding the low level.
- the step of amending the frequency of the clock is performed by the following steps chosen from the group consisting of the following: multiply frequency, divide frequency, mix the clock with at least one higher frequency clock, using doubled edges of the clock, using and the combination thereof.
- the invention also provides a system for providing a variable frequency clock for a SDRAM.
- the system comprises the following: (1) a receiver for receiving a clock with a fixed frequency and a plurality of signals, wherein each the signal is an interlace combination of a plurality of high level signals and a plurality of low levels signals; (2) an extractor for extracting a plurality of proper positions from the signals, wherein each low level of each the signal corresponds to a proper position; and (3) an amender for amending the frequency of the clock such that each the proper position corresponds to a rising edge of the clock.
- the extractor could locate each the proper position at the center of corresponding the low level; the extractor could locate each the proper position at a safety region around the center of corresponding the low level; and the extractor also could locate each the proper position at a safety region inside corresponding the low level.
- the amender is a combination of the parts chosen from the group consisting of the following: frequency multiplier, frequency divider, mixer that receive the clock and at least one higher frequency clock, and the combination thereof.
- FIG. 1 Block Diagram of Regular Frequency Control of SDRAM
- FIG. 2 Examples of Standard SDRAM Timing, A Regular Frequency Clock is Used
- FIG. 3 Block Diagram of Variable Frequency Control of SDRAM.
- FIG. 4 Examples of Revised SDRAM Timing, A Variable Frequency Clock is Used.
- variable Frequency Control of SDRAM For example, a variable frequency clock source is generated specifically by some elaborate logic circuit (see FIG. 3 ). This circuit is designed so that non-integer multiple-cycled pulse (in unit of Tcyc) can be seen by the SDRAM.
- the key point of proposed scheme is to provide higher resolution clock by using either doubled edges of the original clock or higher internal frequency clock as new reference.
- the newly created clock, along with other control signals, are built-in in ASIC to output best fitting timing to SDRAM.
- the conquered problems and advantages of the invention could be briefly described as the following.
- the proposed method uses logic circuit to generate variable frequency clock and, according to it, creates related control signals to optimize the access timing toward SDRAM.
- the variable frequency clocking method removes the limitation on integer-multiple of timing implementation on control signals of SDRAM, thus achieves a more optimized and efficient SDRAM access.
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Dram (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
A method for providing a variable frequency clock for a SDRAM. First, receiving a clock with a fixed frequency and a plurality of signals, wherein each the signal is an interlace combination of a plurality of high level signals and a plurality of low levels signals. Second, extracting a plurality of proper positions from the signals, wherein each low level of each the signal corresponds to a proper position. Third, amending the frequency of the clock such that each the proper position corresponds to a rising edge of the clock.
Description
- 1. Field of the Invention
- Use of SDRAM is nowadays a very popular feature of the system in which large external buffer is necessary. Therefore, the SDRAM controller becomes a fundamental block of the ASIC design for a digital system. A new method to control the SDRAM is presented here, in which a non-regular frequency clock or control signals are involved to best fit timing requirement of a standard SDRAM. As a result, the most efficient timing to access a SDRAM is achieved.
- 2. Description of the Prior Art
- The conventional way to control a SDRAM is using a fix frequency clock as reference, generating all clock-based control signals such as RAS_, CAS_, MA according to this reference clock (see
FIG. 1 ). This is a readily easy and straightforward way to use SDRAM. The fix frequency is constrained and decided by both system bandwidth requirement and working frequency of the logic circuit within an ASIC. To meet some SDRAM's timing parameters given in its specification, the cycle time Tcyc (1/Frequency) is used as the basic unit to generate all control signals. These control signals seen by the SDRAM must be an integer multiple-cycled pulse in unit of Tcyc, since a fix frequency is fed to the SDRAM as a reference clock. Resolution of Tcyc may not be fine enough to generate the best fitting control waveforms to the SDRAM. Therefore, some extra cycle(s) may be accumulated during a read/write access of the SDRAM and it does reduce efficiency of the SDRAM.FIG. 2 shows an example that we design timing parameters tRCD=2*Tcyc, tRP=2*Tcyc and tRC=6*Tcyc to meet minimum timing requirement of tRCDmin=1.4*Tcyc, tPRmin=1.4*Tcyc and tRCmin=5*Tcyc. - The invention provides a method for providing a variable frequency clock for a SDRAM. The method comprises the following steps: (1) receiving a clock with a fixed frequency and a plurality of signals, wherein each the signal is an interlace combination of a plurality of high level signals and a plurality of low levels signals; (2) extracting a plurality of proper positions from the signals, wherein each low level of each the signal corresponds to a proper position; and (3) amending the frequency of the clock such that each the proper position corresponds to a rising edge of the clock. Herein, each the proper position could located at the center of corresponding the low level; each the proper position could be located at a safety region around the center of corresponding the low level; and each the proper position could be located at a safety region inside corresponding the low level. Further, the step of amending the frequency of the clock is performed by the following steps chosen from the group consisting of the following: multiply frequency, divide frequency, mix the clock with at least one higher frequency clock, using doubled edges of the clock, using and the combination thereof.
- The invention also provides a system for providing a variable frequency clock for a SDRAM. The system comprises the following: (1) a receiver for receiving a clock with a fixed frequency and a plurality of signals, wherein each the signal is an interlace combination of a plurality of high level signals and a plurality of low levels signals; (2) an extractor for extracting a plurality of proper positions from the signals, wherein each low level of each the signal corresponds to a proper position; and (3) an amender for amending the frequency of the clock such that each the proper position corresponds to a rising edge of the clock. Herein, the extractor could locate each the proper position at the center of corresponding the low level; the extractor could locate each the proper position at a safety region around the center of corresponding the low level; and the extractor also could locate each the proper position at a safety region inside corresponding the low level. Further, the amender is a combination of the parts chosen from the group consisting of the following: frequency multiplier, frequency divider, mixer that receive the clock and at least one higher frequency clock, and the combination thereof.
- The foregoing aspects and many of the attendant advantages of the present invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:
-
FIG. 1 . Block Diagram of Regular Frequency Control of SDRAM; -
FIG. 2 . Examples of Standard SDRAM Timing, A Regular Frequency Clock is Used; -
FIG. 3 . Block Diagram of Variable Frequency Control of SDRAM; and -
FIG. 4 . Examples of Revised SDRAM Timing, A Variable Frequency Clock is Used. - In the following, some preferred embodiments of the invention would be described in greater detail. Nevertheless, it should be recognized that the present invention could be practiced in a wider range in other embodiments beside those explicitly described, and the scope of the present invention is not limited by these expressed embodiments but specified in the accompanying claims.
- One main character of the invention is “Variable Frequency Control of SDRAM. For example, a variable frequency clock source is generated specifically by some elaborate logic circuit (see
FIG. 3 ). This circuit is designed so that non-integer multiple-cycled pulse (in unit of Tcyc) can be seen by the SDRAM. The key point of proposed scheme is to provide higher resolution clock by using either doubled edges of the original clock or higher internal frequency clock as new reference. The newly created clock, along with other control signals, are built-in in ASIC to output best fitting timing to SDRAM.FIG. 4 shows an example that we design timing parameters tRCD=1.5*Tcyc (>tRCDmin=1.4*Tcyc), tRP=1.5*Tcyc (>tRPmin=1.4*Tcyc) and tRC=5*Tcyc (≧tRCmin=5*Tcyc) to optimize timing of control signals over SDRAM. Saving of 0.5*Tcyc in tRCD and 0.5*Tcyc in tRP together to make 1*Tcyc saving in tRC. - The conquered problems and advantages of the invention could be briefly described as the following. The proposed method uses logic circuit to generate variable frequency clock and, according to it, creates related control signals to optimize the access timing toward SDRAM. The variable frequency clocking method removes the limitation on integer-multiple of timing implementation on control signals of SDRAM, thus achieves a more optimized and efficient SDRAM access.
- Of course, it is to be understood that the present invention is not limited by these disclosed embodiments. Various modification and similar changes are still possible within the spirit of the present invention. In this way, the scope of the present invention should be defined by the appended claims.
Claims (10)
1. A method for providing a variable frequency clock for a SDRAM, comprising:
receiving a clock with a fixed frequency and a plurality of signals, wherein each said signal is an interlace combination of a plurality of high level signals and a plurality of low levels signals;
extracting a plurality of proper positions from said signals, wherein each low level of each said signal corresponds to a proper position; and
amending the frequency of said clock such that each said proper position corresponds to a rising edge of said clock.
2. The method of claim 1 , wherein each said proper position is located at the center of corresponding said low level.
3. The method of claim 1 , wherein each said proper position is located at a safety region around the center of corresponding said low level.
4. The method of claim 1 , wherein each said proper position is located at a safety region inside corresponding said low level.
5. The method of claim 1 , wherein the step of amending the frequency of said clock is performed by the following steps chosen from the group consisting of the following: multiply frequency, divide frequency, mix said clock with at least one higher frequency clock, using doubled edges of the clock, using and the combination thereof.
6. A system for providing a variable frequency clock for a SDRAM, comprising:
a receiver for receiving a clock with a fixed frequency and a plurality of signals, wherein each said signal is an interlace combination of a plurality of high level signals and a plurality of low levels signals;
an extractor for extracting a plurality of proper positions from said signals, wherein each low level of each said signal corresponds to a proper position; and
an amender for amending the frequency of said clock such that each said proper position corresponds to a rising edge of said clock.
7. The system of claim 1 , wherein said extractor locates each said proper position at the center of corresponding said low level.
8. The system of claim 1 , wherein said extractor locates each said proper position at a safety region around the center of corresponding said low level.
9. The system of claim 1 , wherein said extractor locates each said proper position at a safety region inside corresponding said low level.
10. The system of claim 1 , wherein said amender is a combination of the parts chosen from the group consisting of the following: frequency multiplier, frequency divider, mixer that receive said clock and at least one higher frequency clock, and the combination thereof.
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/709,299 US20050249025A1 (en) | 2004-04-27 | 2004-04-27 | Method and System For A Variable Frequency SDRAM Controller |
TW094113419A TWI280588B (en) | 2004-04-27 | 2005-04-27 | Apparatus and method for generating a variable-frequency clock |
CNB2005100712577A CN100565704C (en) | 2004-04-27 | 2005-04-27 | Produce the apparatus and method of variable clock pulse |
US11/162,972 US7136323B2 (en) | 2004-04-27 | 2005-09-29 | Apparatus and method for generating a variable-frequency clock |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/709,299 US20050249025A1 (en) | 2004-04-27 | 2004-04-27 | Method and System For A Variable Frequency SDRAM Controller |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/162,972 Continuation-In-Part US7136323B2 (en) | 2004-04-27 | 2005-09-29 | Apparatus and method for generating a variable-frequency clock |
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US20050249025A1 true US20050249025A1 (en) | 2005-11-10 |
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Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
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US10/709,299 Abandoned US20050249025A1 (en) | 2004-04-27 | 2004-04-27 | Method and System For A Variable Frequency SDRAM Controller |
US11/162,972 Expired - Lifetime US7136323B2 (en) | 2004-04-27 | 2005-09-29 | Apparatus and method for generating a variable-frequency clock |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
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US11/162,972 Expired - Lifetime US7136323B2 (en) | 2004-04-27 | 2005-09-29 | Apparatus and method for generating a variable-frequency clock |
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Country | Link |
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US (2) | US20050249025A1 (en) |
CN (1) | CN100565704C (en) |
TW (1) | TWI280588B (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
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US8407411B2 (en) * | 2010-06-28 | 2013-03-26 | Wuxi Vimicro Corporation | Operation frequency adjusting system and method |
CN112309445B (en) * | 2019-08-01 | 2023-10-13 | 群联电子股份有限公司 | Memory interface circuit, memory storage device and signal generation method |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3173313D1 (en) * | 1980-09-25 | 1986-02-06 | Toshiba Kk | Clock synchronization signal generating circuit |
US4893271A (en) * | 1983-11-07 | 1990-01-09 | Motorola, Inc. | Synthesized clock microcomputer with power saving |
US4819164A (en) * | 1983-12-12 | 1989-04-04 | Texas Instruments Incorporated | Variable frequency microprocessor clock generator |
US4623846A (en) * | 1985-02-14 | 1986-11-18 | Motorola, Inc. | Constant duty cycle, frequency programmable clock generator |
JPH0387909A (en) * | 1989-05-10 | 1991-04-12 | Seiko Epson Corp | Information processor and microprocessor |
US5528307A (en) * | 1991-07-18 | 1996-06-18 | Canon Kabushiki Kaisha | Clock generator |
JP3277603B2 (en) * | 1993-05-19 | 2002-04-22 | 富士通株式会社 | Semiconductor storage device |
US5752011A (en) * | 1994-06-20 | 1998-05-12 | Thomas; C. Douglas | Method and system for controlling a processor's clock frequency in accordance with the processor's temperature |
US6167529A (en) * | 1997-12-30 | 2000-12-26 | Intel Corporation | Instruction dependent clock scheme |
JP3935274B2 (en) * | 1998-09-18 | 2007-06-20 | 富士通株式会社 | Clock switching circuit |
US6507247B2 (en) * | 2001-02-27 | 2003-01-14 | Corrent Corporation | Circuit and method for generating a variable frequency clock signal |
JP2002328744A (en) * | 2001-04-27 | 2002-11-15 | Fujitsu Ltd | Semiconductor integrated circuit device |
-
2004
- 2004-04-27 US US10/709,299 patent/US20050249025A1/en not_active Abandoned
-
2005
- 2005-04-27 CN CNB2005100712577A patent/CN100565704C/en not_active Expired - Fee Related
- 2005-04-27 TW TW094113419A patent/TWI280588B/en not_active IP Right Cessation
- 2005-09-29 US US11/162,972 patent/US7136323B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
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US20060050602A1 (en) | 2006-03-09 |
US7136323B2 (en) | 2006-11-14 |
TW200535866A (en) | 2005-11-01 |
CN100565704C (en) | 2009-12-02 |
CN1697080A (en) | 2005-11-16 |
TWI280588B (en) | 2007-05-01 |
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AS | Assignment |
Owner name: VIA TECHNOLOGIES, INC., TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LIN, KEVIN;CHANG, ALEX;REEL/FRAME:014537/0174 Effective date: 20040401 |
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STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |
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AS | Assignment |
Owner name: TIAN HOLDINGS, LLC, DELAWARE Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:VIA TECHNOLOGIES, INC.;REEL/FRAME:020246/0057 Effective date: 20071207 |