US20050225364A1 - High speed low power input buffer - Google Patents
High speed low power input buffer Download PDFInfo
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- US20050225364A1 US20050225364A1 US11/148,739 US14873905A US2005225364A1 US 20050225364 A1 US20050225364 A1 US 20050225364A1 US 14873905 A US14873905 A US 14873905A US 2005225364 A1 US2005225364 A1 US 2005225364A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
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Abstract
The input buffer circuit includes an input stage providing a switching point voltage based on a predetermined switching point set between a first and second reference voltages that maximizes the high and low noise margins of the input buffer. The input buffer circuit further includes an output stage. The output stage is coupled to the input stage. The output stage receives the switching point voltage from the input stage and amplifies the switching point voltage to a full logic level voltage.
Description
- This patent application is a continuation of U.S. patent application Ser. No. 10/627,536, filed Jul. 25, 2003, which is a divisional of U.S. patent application Ser. No. 10/174,206, filed on Jun. 17, 2002, now issued as U.S. Pat. No. 6,600,343, which is a divisional of U.S. patent application Ser. No. 09/649,555, filed on Aug. 28, 2000, now issued as U.S. Pat. No. 6,407,588. These applications are incorporated herein by reference.
- The present invention relates generally to integrated circuits. More particularly, it pertains to differential amplifiers including input buffers.
- Differential amplifiers are commonly used in memory devices as input buffers to couple data signals between a memory array and data terminals of the memory devices. Generally, one common problem with these input buffers is the setting of a switching point voltage to maximize the switching response of the input buffers. Switching point voltage refers to the point at which the input and output voltages are transitioning from a high state-to-low state or a low state-to-high state. If the switching point voltage goes too high, the bits of data coming out of the input buffer will have a good low noise margin, but will not have a high noise margin similarly, if the switching point voltage goes too low, the bits of data will have a good high noise margin, but will not have a good low noise margin. If the switching point voltage is too high or too low, the bits of data coming out of the input buffer can be distorted. For example, if we were to input a voltage in a digital wave form having a sloping rise and fall times like a triangular wave, and if the switching point voltage is too high or too low, the bits of data coming out of the input buffer can be of varying widths and can cause timing problems in the input buffer.
- Thus, there is a need for an input buffer that can automatically establish a switching point voltage that maximizes the high and low noise margins of an integrated circuit. There is also a need for input buffers used in memories of computers to transfer data at a faster rate using low power. Therefore, there is also a need for a low power high-speed input buffer that is capable of operating at high speeds, while using low power.
- The input buffer of the present invention provides, among other things, provides a mechanism to accurately establish a switching point voltage that maximizes the high and low noise margins of an integrated circuit, while using a low power. Also the input buffer is capable of operating at high speeds. According to one embodiment, the input buffer has an input stage providing a switching point voltage based on a predetermined switching point set between first and second reference voltages that maximizes the high and low noise margins of the input buffer. The input buffer further includes an output stage. The output stage is coupled to the input stage. The output stage receives the switching point voltage from the input stage and amplifies the switching point voltage to a full logic level voltage.
- These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims and their equivalents. Other aspects of the invention will be apparent on reading the following detailed description of the invention and viewing the drawings that form a part thereof.
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FIG. 1 is a schematic diagram illustrating generally one embodiment of an input buffer of the present invention. -
FIG. 2A is a timing diagram illustrating one embodiment of application of supply voltage to the input buffer circuit of the present invention. -
FIG. 2B is a timing diagram illustrating one embodiment of output voltage obtained from the input buffer circuit of the present invention when the supply voltage to the input buffer circuit is as shown inFIG. 2A . -
FIG. 3 is a timing diagram illustrating one embodiment of a current drawn by the input buffer of the present invention, when operating at 250 Mega Hertz. -
FIG. 4 is a graph illustrating one embodiment of current transfer characteristics of the input buffer of the present invention. -
FIG. 5 is a flow diagram illustrating a method of providing a switching point voltage from the input buffer of the present invention. -
FIG. 6 is an elevation view of one embodiment of a substrate containing semiconductor dies including the input buffer of the present invention. -
FIG. 7 is a block diagram of one embodiment of a circuit module including the input buffer of the present invention. -
FIG. 8 is a block diagram of one embodiment of a memory module including the input buffer of the present invention. -
FIG. 9 is a block diagram of one embodiment of an electronic system formed according to the teachings of the present invention. -
FIG. 10 is a block diagram of one embodiment of a memory system including the input buffer of the present invention. -
FIG. 11 is a block diagram of one embodiment of a computer system including the input buffer of the present invention. - In the following detailed description of the invention, reference is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. Moreover, it is to be understood that the various embodiments of the invention, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described in one embodiment may be included within other embodiments. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is designed only by the appended claims, along with the full scope of equivalents to which such claims are entitled.
- The transistors described herein are N-channel metal-oxide-semiconductor (NMOS) and P-channel metal-oxide-semiconductor (PMOS). A metal-oxide-semiconductor (MOS) transistor includes a gate, a first node (drain) and a second node (source). Since a MOS transistor is typically a symmetrical device, the true designation of “source” and “drain” is only possible once voltage is impressed on the terminals. The designations of source and drain herein should be interpreted, therefore, in the broadest sense.
- The embodiments of the present invention provide a mechanism to set a predetermined switching point for a switching point voltage which maximizes the high and low noise margins of an integrated circuit. Also the input buffer circuit of the present invention uses low power. This is because the differential amplifier of the present invention behaves like an inverter by drawing current only during switching. The present invention is capable of operating at high speeds to meet the needs of today's computers and computing circuitry which requires a memory that transfers data at a faster rate using low power. High operating speeds are achieved by not having the current source in series with the differential amplifier. Having current source in series with the differential amplifier, causes a slew rate limitation. To overcome the problem of slew rate limitation, the differential amplifier requires a large current source to charge-up quickly the input capacitance of a next stage, which is generally not desirable.
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FIG. 1 is a schematic diagram of one embodiment of an integrated circuit according to the teachings of the present invention. In particular,FIG. 1 illustrates aninput buffer circuit 100. Theinput buffer circuit 100 shown inFIG. 1 includes aninput stage 110 and anoutput stage 120. Theinput stage 110 includes a first pair of NMOS andPMOS transistors PMOS transistors NMOS transistors NMOS transistors output stage 120 includes a fifth pair of PMOS andNMOS transistors - Description of Connectivity of the Input Buffer Circuit:
- The first pair of NMOS and
PMOS transistors current sink node drain 159 of theNMOS transistor 130 is coupled to the firstcurrent source node 185, adrain 175 of thePMOS transistor 132 is coupled to the firstcurrent sink node 186. A 161 source of theNMOS transistor 130 is coupled to asource 173 of thePMOS transistor 132, and agate 174 of thePMOS transistor 132 is coupled to receive a second reference voltage (VL). - The second pair of NMOS and
PMOS transistors current source node 187 and a secondcurrent sink node 188, in which adrain 171 of theNMOS transistor 134 is couple to the secondcurrent source node 187, adrain 191 of thePMOS transistor 136 is coupled to the secondcurrent sink node 188, asource 194 of theNMOS transistor 134 is coupled to asource 189 of thePMOS transistor 136, agate 172 of theNMOS transistor 134 is coupled to receive a first reference voltage (VH), and thegates pair NMOS transistor 130 and the secondpair PMOS transistor 136 are coupled to each other and to a input terminal (VDD) to receive the supply voltage from a power source. VL and VH are effectively utilized in the present invention to maximize the switching point voltage. - The third pair of PMOS and
NMOS transistors current source node 185 and the firstcurrent sink node 186, in which asource 156 of thePMOS transistor 138 is coupled to the firstcurrent source node 185, adrain 158 of thePMOS transistor 138 is coupled to thedrain 159 of the firstpair NMOS transistor 130, adrain 176 of theNMOS transistor 140 is coupled to thedrain 175 of the firstpair PMOS transistor 132, and asource 178 of theNMOS transistor 140 is coupled to the firstcurrent sink node 186. - The fourth pair of PMOS and
NMOS transistors current source node 187 and the secondcurrent sink node 188, in which asource 168 of thePMOS transistor 142 is coupled to a secondcurrent source node 187, adrain 170 of thePMOS transistor 142 is coupled to thedrain 171 of the secondpair NMOS transistor 134, agate 169 of thePMOS transistor 142 is coupled to thegate 157 of the thirdpair PMOS transistor 138 and further thegates fourth PMOS transistors drain 159 of the firstpair NMOS transistor 130, adrain 192 of theNMOS transistor 144 is coupled to thedrain 191 of the secondpair PMOS transistor 136, asource 197 of theNMOS transistor 144 is coupled to the secondcurrent sink node 188, agate 193 of theNMOS transistor 144 is coupled to thegate 177 of the thirdpair NMOS transistor 140, thegate 177 of thethird PMOS transistor 140 and agate 193 of thePMOS transistor 144 are coupled to thedrain 191 of the secondpair PMOS transistor 136. - The fifth pair of PMOS and
NMOS transistors current source node 195 and a thirdcurrent sink node 196, wherein asource 179 of thePMOS transistor 150 is coupled to the thirdcurrent source node 195, agate 180 of thePMOS transistor 150 is coupled to thedrain 171 of the secondpair NMOS transistor 134 and further coupled to thedrain 170 of the fourthpair PMOS transistor 142. Further adrain 182 of theNMOS transistor 152 is coupled to adrain 181 of thePMOS transistor 150 and thedrain 182 of theNMOS transistor 152 and thedrain 181 of thePMOS transistor 150 are coupled to a output terminal (VOUT) to supply and to amplify the switching point voltage to a full logic level voltage, and agate 183 of theNMOS transistor 152 is coupled to thedrain 175 of the firstpair PMOS transistor 132 and further coupled to thedrain 176 of thirdpair NMOS transistor 140. - Description of Operation of the Input Buffer Circuit:
- In this example embodiment, the
input buffer circuit 100 including theNMOS transistors PMOS transistors FIG. 1 an input voltage is applied across two gate to source voltages. Thisinput buffer circuit 100 of the present invention is unlike a normal inverter. That is theinput buffer circuit 100 of the present invention is different in that an input voltage is applied parallel across the gate to source voltages. Applying the voltages across the gate to source voltages of the transistors provides an immunity from power supply voltage variations. - When the input voltage (VIN) to the
input buffer circuit 100 goes high (i.e., above the switching point voltage), the gate to source voltage ofNMOS transistor 130 increases and source to gate voltage ofPMOS transistor 132 increases, this in-turn causes the current to increase inPMOS transistor 138,NMOS transistor 130,PMOS transistor 132, andNMOS transistor 140. This causes the voltage across the gate ofNMOS transistor 152 to increase and the output to go low. Also when the input voltage is high, the source to gate voltage ofPMOS transistor 136 and gate to source voltage ofNMOS transistor 134 decreases. This causes the current inPMOS transistor 142 andNMOS transistor 144 to go to zero. This will cause the current to go throughPMOS transistor 138,NMOS transistor 130, andPMOS transistor 132. This will in-turn cause the current decrease throughNMOS transistor 140 and charge-up the gate ofNMOS transistor 152. One of ordinary skill in the art will understand that the opposite occurs when the VIN goes low (i.e., goes below the switching point voltage). Essentially, in operation, theinput buffer circuit 100 takes a low level input voltage (such as 100 millivolts peak to peak) and amplifies the input voltage to a full logic level output voltage (VOUT). Also theinput buffer circuit 100 of the present invention effectively utilizes the VL and VH to maximize the switching point voltageFIGS. 2A and 2B show timing diagrams 200 and 210 illustrating one embodiment of switching point voltage output obtained from theinput buffer circuit 100 shown inFIG. 1 . The timing diagram 200 inFIG. 2A , shows the application of the supply voltage (VDD) to theinput buffer circuit 100. In the embodiment shown inFIG. 2A , the VDD switches from 0.5 to 1.0 volts, and has a switching point voltage of around 0.75. volts. The timing diagram 210 shown inFIG. 2B , shows the output voltage (VOUT) obtained from theoutput stage 120 of theinput buffer circuit 100 when applying the VDD as shown in the timing diagram 200 ofFIG. 2A . Timing diagrams 200 and 210 clearly show that the input stage and the output stage of the novelinput buffer circuit 100 amplifies the VDD and the switching point voltage to a full logic level voltage. -
FIG. 3 is a timing diagram 300 illustrating one embodiment of current draw by theinput buffer circuit 100 of thepresent invention 300 when operating at 250 Mega Hertz. The timing diagram 300 shows that theinput buffer circuit 100 essentially draws current only during switching.FIG. 3 shows current drawn asspikes 310 during switching and then drawing no current the rest of the time to conserve power. This timing diagram 300 shows that theinput buffer circuit 100 ofFIG. 1 uses low power by behaving like a conventional inverter and drawing current only during switching. However the novelinput buffer circuit 100 of this present invention offers better noise immunity by having a more accurate/effective switching point voltage. -
FIG. 4 is agraph 400 illustrating one embodiment of current versus voltage behavior of the input buffer according to the teachings of the present invention. One of ordinary skill in the art will understand that when VDD is applied to theinput buffer circuit 100, the voltage across the first pair oftransistors transistors NMOS transistor 130 andPMOS transistor 132 are turned-on, andPMOS transistor 136 andNMOS transistor 134 are turned-off. This in-turn causes the current ID1 (represents current drawn across first and third pair oftransistors FIG. 1 ) to increase exponentially and current ID2 (represents current drawn across second and fourth pair oftransistors FIG. 1 ) to decrease exponentially, as shown inFIG. 4 . One of ordinary skill in the art will understand that the opposite occurs when the voltage across the first pair of transistors decreases and the voltage across the second pair oftransistors input buffer circuit 100 of the present invention operates like a self-biased class AB input, where neither of the output currents ID1 and ID2 is zero as long as their magnitude remains less than the current through the fifth pair of PMOS andNMOS transistors -
FIG. 5 shows a method of providing a switching point voltage using theinput buffer circuit 100 of the present invention.Method 500 begins withstep 510 by determining available first and second reference voltages (VH and VL) to theinput buffer circuit 100. After determining the available VH and VL voltages, thenext step 520 in the process includes computing a switching point voltage based on the available VH and VL voltages to maximize high and low noise margins of theinput buffer circuit 100. In one embodiment, the switching point voltage is computed based on the average of the first and second reference voltages ((VH+VL)/2). Thenext step 530 in the process includes setting the switching point voltage by sizing the transistors in theinput buffer circuit 100, to provide the computed switching point voltage. In one embodiment, sizing the transistors in theinput buffer circuit 100 includes selecting appropriate reference voltages based on using standard size transistors. In another embodiment, sizing the transistors in theinput buffer circuit 100 includes using standard reference voltages VDD and ground. In one embodiment, the first reference voltage is set to VDD. In one embodiment, the second reference voltage is set to zero by coupling the gate of thePMOS transistor 132 of theinput stage 110 to ground. In another embodiment, providing a first reference voltage includes using a standard supply voltage VDD and sizing the transistors in theinput buffer circuit 100 to obtain a desired switching point voltage. - With reference to
FIG. 6 , in one embodiment, asemiconductor die 610 is produced from asilicon wafer 600. A die is an individual pattern, typically rectangular, on a substrate that contains circuitry to perform a specific function. A semiconductor wafer will typically contain a repeated pattern of such dies containing the same functionality. According to the teaching of the present invention, die 610 contains circuitry for the inventive input buffer, as discussed above.Die 610 may further contain additional circuitry to extend to such complex devices as a monolithic processor with multiple functionality.Die 610 is typically packaged in a protective casing (not shown) with leads extending therefrom (not shown) providing access to the circuitry of the die for unilateral or bilateral communication and control. - As shown in
FIG. 7 , two or more dies 710 may be combined, with or without protective casing, into acircuit module 700 to enhance or extend the functionality of an individual die 710-1. According to the teachings of the present invention at least one of the dies 710-1, 710-2, . . . , 710-N shown inFIG. 7 , includes buffer circuit of the present invention.Circuit module 700 may be a combination of dies 710-1 representing a variety of functions, or a combination of dies 710-1 containing the same functionality. Some examples of a circuit module include input buffer, memory modules, device drivers, power modules, communication modems, processor modules and application-specific modules and may include multi-layer, multi-chip modules.Circuit module 700 may be a sub-component of a variety of electronic systems, such as a clock, a television, a cell phone, a personal computer, an automobile, an industrial control system, an aircraft and others.Circuit module 700 will have a variety ofleads 710 extending therefrom providing unilateral or bilateral communication and control. -
FIG. 8 shows one embodiment of a circuit module asmemory module 800.Memory module 800 generally depicts a Single In-line Memory Module (SIMM) or Dual In-line Memory Module (DIMM). A SIMM or DIMM is generally a printed circuit board (PCB) or other support containing a series of memory devices including input buffer circuit according to the teaching of the present invention. While a SIMM will have a single in-line set of contacts or leads, a DIMM will have a set of leads on each side of the support with each set representing separate I/O signals.Memory module 800 contains multiple memory devices 810-1, 810-2, . . . , 810-N contained onsupport 815, the number depending upon the desired bus width and the desire for parity. According to the teachings of the present invention,memory module 800 include input buffer circuit of the present invention in a memory device 810-1, 810-2, . . . , 810-N on both sides ofsupport 815.Memory module 800 accepts a command signal from an external controller (not shown) on acommand link 820 and provides for data input and data output ondata links 830. Thecommand link 820 anddata links 830 are connected to leads 840 extending from thesupport 815.Leads 840 are shown for conceptual purposes and are not limited to the positions shown inFIG. 7 . -
FIG. 9 shows anelectronic system 900 includes one ormore circuit modules 800 as described inFIG. 8 .Electronic system 900 generally contains auser interface 910.User interface 910 provides a user of theelectronic system 900 with some form of control or observation of the results of theelectronic system 900. Some examples ofuser interface 910 include the keyboard, pointing device, monitor and printer of a personal computer; the tuning dial, display and speakers of a radio; the ignition switch and gas pedal of an automobile; and the card reader, keypad, display and currency dispenser of an automated teller machine.User interface 910 may further describe access ports 901-1, 901-2, . . . , 901-N provided toelectronic system 900. Access ports 901-1, 901-2, . . . , 901-N are used to connect anelectronic system 900 to the more tangible user interface components previously exemplified. One or more of thecircuit modules 800 includes the input buffer circuit according to the teachings of the present invention. One or more of the circuit modules may be a processor providing some form of manipulation, control or direction of inputs from or outputs touser interface 910, or of other information either preprogrammed into, or otherwise provided to,electronic system 900. As will be apparent from the lists of examples previously given,electronic system 900 will often contain certain mechanical components (not shown) in addition tocircuit modules 800 including an input buffer circuit according to the teachings of the present invention anduser interface 910. It will be appreciated that the one ormore circuit modules 800 inelectronic system 900 can be replaced by a single integrated circuit. Furthermore,electronic system 900 may be a sub-component of a larger electronic system. -
FIG. 10 shows one embodiment of an electronic system asmemory system 1000.Memory system 1000 contains one ormore memory modules 800 such as memory modules described in connection withFIG. 8 . One ormore memory modules 800 includes an input buffer circuit according to the teachings of the present invention and amemory controller 910.Memory controller 1010 provides and controls a bidirectional interface betweenmemory system 1000 and anexternal system bus 1020.Memory system 1000 accepts a command signal from theexternal bus 1020 and relays it to the one ormore memory modules 800 on acommand link 1030.Memory system 1000 provides for data input and data output between the one ormore memory modules 800 andexternal system bus 1020 ondata links 1040. -
FIG. 11 shows a further embodiment of an electronic system as acomputer system 1100.Computer system 1100 contains aprocessor 1110 and amemory system 1000 housed in acomputer unit 1105.Computer system 1100 is but one example of an electronic system containing another electronic system, i.e.memory system 1000, as a sub-component.Computer system 1100 optionally contains user interface components. Depicted inFIG. 11 are akeyboard 1120, apointing device 1130, amonitor 1140, aprinter 1150 and abulk storage device 1160. It will be appreciated that other components are often associated withcomputer system 1100 such as modems, device driver cards, additional storage devices, etc. It will further be appreciated that theprocessor 1110 andmemory system 1000 can include the input buffer circuit according to the teachings of the present invention.Computer system 1100 can be incorporated on a single integrated circuit. Such single package processing units reduce the communication time between the processor and the memory circuit. - An input buffer circuit is described which conveniently allows setting any predetermined switching point voltage to provide a switching point voltage that maximizes high and low noise margins of an integrated circuit. The input buffer of the present invention is capable of operating at high speeds while using low power. The input buffer circuit is self-biasing and automatically adjusts to process variations. In one embodiment, the input buffer has an input stage providing a switching point voltage based on a predetermined switching point set between a first and second reference voltages that maximizes the high and low noise margins of the input buffer. The input stage is further coupled to an output stage. The output stage receives the switching point voltage from the input stage and amplifies the switching point voltage to a full logic level voltage.
- It is to be understood that the above description is intended to be illustrative, and not restrictive. Many other embodiments will be apparent to those of skill in the art upon reading and understanding the above description. The scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.
Claims (29)
1. A method of operating an input buffer, comprising:
applying a first source voltage to a drain of a first NMOS transistor and applying a first sink voltage to a drain of a first PMOS transistor;
applying an input voltage higher than a switching point to a gate of the first NMOS transistor and to a gate of the first PMOS transistor;
increasing a gate to source voltage of the first NMOS transistor and increasing a source to gate voltage of a second PMOS transistor having a low reference voltage connected to the gate;
increasing current flow through the first NMOS, the second PMOS transistor, and to a second sink voltage; and
increasing the voltage to a gate of a second NMOS transistor and connecting an output of the input buffer to a third sink voltage.
2. The method of operating an input buffer of claim 1 , wherein the first sink voltage and the second sink voltage are the same voltage.
3. The method of operating an input buffer of claim 1 , wherein the third sink voltage is a ground voltage level.
4. The method of operating an input buffer of claim 1 , wherein first and second sink voltages are higher than the third sink voltage.
5. The method of operating an input buffer of claim 1 , wherein a difference between the first source voltage and the first sink voltage is less than 100 millivolts.
6. A method of operating an input buffer, comprising:
applying a first source voltage to a drain of a first NMOS transistor;
applying a first sink voltage to a drain of a first PMOS transistor;
applying an input voltage lower than a switching point to a gate of the first NMOS transistor and to a gate of the first PMOS transistor;
decreasing a gate to source voltage of the first PMOS transistor and decreasing a source to gate voltage of a third NMOS transistor having a high reference voltage connected to the gate;
increasing current flow between the drain of the third NMOS transistor and a second source voltage through the first PMOS transistor to the first sink voltage; and
decreasing a voltage to a gate of a second PMOS transistor and connecting an output of the input buffer to a third source voltage.
7. The method of operating an input buffer of claim 6 , wherein the first source voltage and the second source voltage are the same voltage.
8. The method of operating an input buffer of claim 6 , wherein the third source voltage is a power supply voltage level.
9. The method of operating an input buffer of claim 6 , wherein first and second source voltages are lower than the third source voltage.
10. The method of operating an input buffer of claim 6 , wherein a difference between the first source voltage and the first sink voltage is less than 100 millivolts.
11. The method of operating an input buffer of claim 6 , wherein applying an input voltage includes setting the switching point voltage by sizing the first and second NMOS transistors and the first and second PMOS transistors.
12. A method of operating an input buffer, comprising:
applying a first source voltage to a drain of a first NMOS transistor and applying a first sink voltage to a drain of a first PMOS transistor;
applying an input voltage to a gate of the first NMOS transistor and to a gate of the first PMOS transistor, wherein the input voltage is applied across the gate to drain of each of the first NMOS and first PMOS transistor;
wherein applying an input voltage higher than a switching point increases a gate to source voltage of the first NMOS transistor and increases a source to gate voltage of a second PMOS transistor having a low reference voltage connected to the gate;
resulting in increased current flow in a third PMOS transistor connected between the drain of the first NMOS transistor and the first source voltage and having a gate connected to the drain of the first NMOS transistor;
resulting in a current increase in the first NMOS transistor, the second PMOS transistor, and a second NMOS transistor connected between the source of the second PMOS transistor and a second sink voltage, and having a gate connected to a drain of the first PMOS transistor; and
resulting in an increase in the voltage to a gate of a third NMOS transistor and connecting an output of the input buffer to a third sink voltage; and
wherein applying an input voltage lower than the switching point decreases a gate to source voltage of the first PMOS transistor and decreases a source to gate voltage of a fourth NMOS transistor having a high reference voltage connected to the gate;
resulting in increased current flow in a fourth PMOS transistor connected between the drain of the fourth NMOS transistor and a second source voltage and having a gate connected to the drain of the first NMOS transistor;
resulting in a current increase in the first PMOS transistor, a fifth NMOS transistor connected between a drain of the first PMOS transistor and a second sink voltage and having a gate connected to the drain of the first PMOS transistor; and
resulting in a decrease in the voltage to a gate of a fifth PMOS transistor and connecting the output of the input buffer to a third source voltage.
13. The method of operating an input buffer of claim 12 , wherein the third sink voltage is a ground reference voltage level.
14. The method of operating an input buffer of claim 12 , wherein the third source voltage is a supply voltage level.
15. The method of operating an input buffer of claim 12 , wherein the first and second source voltages are the same voltage.
16. The method of operating an input buffer of claim 12 , wherein the first and second sink voltages are the same voltage.
17. The method of operating an input buffer of claim 12 , wherein the first and second source voltages are lower than the third source voltage level.
18. The method of operating an input buffer of claim 12 , wherein the first and second sink voltages are higher than the third sink voltage level.
19. The method of operating an input buffer of claim 12 , wherein the first and second source voltages are the same voltage and lower than the third source voltage, and the first and second sink voltages are the same voltage and higher than the third sink voltage level.
20. The method of operating an input buffer of claim 19 , wherein a difference between the first and second source voltage level and the first and second sink voltage level is 100 millivolts and is less than a difference between the third source voltage level and the third sink voltage level.
21. The method of operating an input buffer of claim 12 , wherein the high and the low reference voltages are selected to set the switching point to an average of the first source voltage level and the first sink voltage level.
22. A method of operating an input buffer, comprising:
applying an input voltage having a voltage range between a high input logic level and a low input logic level of less than 100 millivolts to a first CMOS pair connected between a first source voltage level and a first sink voltage level;
wherein the first CMOS pair are cross coupled source to source to a second CMOS pair connected between a second source voltage level and a second sink voltage level;
wherein the second CMOS pair includes a high reference voltage communicating with a gate of a NMOS transistor of the second CMOS pair, and a low reference voltage communicating with a gate of a PMOS transistor of the second CMOS pair;
a drain of the PMOS transistor of the second CMOS pair communicating with a gate of a NMOS transistor communicating between a ground voltage and an output terminal of a third CMOS pair, and a drain of a NMOS transistor of the second CMOS pair communication with a gate of a PMOS transistor communicating between a supply voltage and the output terminal of the third CMOS pair; and
inverting and amplifying the input voltage logic level as an output logic level ranging between a high output logic level and a low output logic level of approximately 1000 millivolts.
23. The method of operating an input buffer of claim 22 , wherein the high and the low reference voltages are selected to set a logic switching point between the low input logic level and the high input logic level to an average of the first source voltage level and the first sink voltage level.
24. The method of operating an input buffer of claim 22 , wherein the first and second source voltages are lower than the supply voltage level.
25. The method of operating an input buffer of claim 22 , wherein the first and second sink voltages are higher than the ground voltage level.
26. The method of operating an input buffer of claim 22 , wherein the first and second source voltages are substantially equal to each other.
27. The method of operating an input buffer of claim 22 , wherein the first and second sink voltages are substantially equal to each other.
28. The method of operating an input buffer of claim 22 , wherein the source of a PMOS transistor of the first CMOS pair is connected to a source of the NMOS transistor of the second CMOS pair.
29. The method of operating an input buffer of claim 22 , wherein the source of a NMOS transistor of the first CMOS pair is connected to a source of the PMOS transistor of the second CMOS pair.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US11/148,739 US20050225364A1 (en) | 2000-08-28 | 2005-06-09 | High speed low power input buffer |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
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US09/649,555 US6407588B1 (en) | 2000-08-28 | 2000-08-28 | High speed low power input buffer |
US10/174,206 US6600343B2 (en) | 2000-08-28 | 2002-06-17 | High speed low power input buffer |
US10/627,536 US6914454B2 (en) | 2000-08-28 | 2003-07-25 | High speed low power input buffer |
US11/148,739 US20050225364A1 (en) | 2000-08-28 | 2005-06-09 | High speed low power input buffer |
Related Parent Applications (1)
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US10/627,536 Continuation US6914454B2 (en) | 2000-08-28 | 2003-07-25 | High speed low power input buffer |
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US20050225364A1 true US20050225364A1 (en) | 2005-10-13 |
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US09/649,555 Expired - Lifetime US6407588B1 (en) | 2000-08-28 | 2000-08-28 | High speed low power input buffer |
US10/174,206 Expired - Lifetime US6600343B2 (en) | 2000-08-28 | 2002-06-17 | High speed low power input buffer |
US10/627,536 Expired - Lifetime US6914454B2 (en) | 2000-08-28 | 2003-07-25 | High speed low power input buffer |
US11/148,739 Abandoned US20050225364A1 (en) | 2000-08-28 | 2005-06-09 | High speed low power input buffer |
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US09/649,555 Expired - Lifetime US6407588B1 (en) | 2000-08-28 | 2000-08-28 | High speed low power input buffer |
US10/174,206 Expired - Lifetime US6600343B2 (en) | 2000-08-28 | 2002-06-17 | High speed low power input buffer |
US10/627,536 Expired - Lifetime US6914454B2 (en) | 2000-08-28 | 2003-07-25 | High speed low power input buffer |
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US20080082319A1 (en) * | 2006-09-29 | 2008-04-03 | Intel Corporation | Apparatus, System and Method for Buffering Audio Data to Allow Low Power States in a Processing System During Audio Playback |
US20150194195A1 (en) * | 2014-01-03 | 2015-07-09 | Samsung Electronics Co., Ltd. | Self bias buffer circuit and memory device including the same |
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US20070183228A1 (en) * | 2005-10-27 | 2007-08-09 | Washburn Robert D | Control signal interface circuit for computer memory modules |
US7512019B2 (en) * | 2005-11-02 | 2009-03-31 | Micron Technology, Inc. | High speed digital signal input buffer and method using pulsed positive feedback |
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US9379693B2 (en) * | 2014-01-03 | 2016-06-28 | Samsung Electronics Co., Ltd. | Self bias buffer circuit and memory device including the same |
Also Published As
Publication number | Publication date |
---|---|
US20020149399A1 (en) | 2002-10-17 |
US6600343B2 (en) | 2003-07-29 |
US6914454B2 (en) | 2005-07-05 |
US6407588B1 (en) | 2002-06-18 |
US20040017231A1 (en) | 2004-01-29 |
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