US20050116290A1 - Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers - Google Patents
Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers Download PDFInfo
- Publication number
- US20050116290A1 US20050116290A1 US10/725,850 US72585003A US2005116290A1 US 20050116290 A1 US20050116290 A1 US 20050116290A1 US 72585003 A US72585003 A US 72585003A US 2005116290 A1 US2005116290 A1 US 2005116290A1
- Authority
- US
- United States
- Prior art keywords
- orientation
- single crystal
- soi substrate
- substrate structure
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 144
- 239000004065 semiconductor Substances 0.000 title claims abstract description 143
- 238000005280 amorphization Methods 0.000 title claims abstract description 22
- 238000001953 recrystallisation Methods 0.000 title claims abstract description 20
- 239000013078 crystal Substances 0.000 title claims description 89
- 238000000034 method Methods 0.000 claims abstract description 73
- 238000002955 isolation Methods 0.000 claims description 35
- 239000000463 material Substances 0.000 claims description 13
- 238000005468 ion implantation Methods 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 10
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 5
- 229910052681 coesite Inorganic materials 0.000 claims description 5
- 229910052906 cristobalite Inorganic materials 0.000 claims description 5
- 229910052734 helium Inorganic materials 0.000 claims description 5
- 239000012212 insulator Substances 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 229910052682 stishovite Inorganic materials 0.000 claims description 5
- 229910052905 tridymite Inorganic materials 0.000 claims description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 4
- 229910000927 Ge alloy Inorganic materials 0.000 claims description 4
- 229910000673 Indium arsenide Inorganic materials 0.000 claims description 4
- 229910003811 SiGeC Inorganic materials 0.000 claims description 4
- 229910045601 alloy Inorganic materials 0.000 claims description 4
- 239000000956 alloy Substances 0.000 claims description 4
- 229910052786 argon Inorganic materials 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 150000001875 compounds Chemical class 0.000 claims description 4
- 229910052732 germanium Inorganic materials 0.000 claims description 4
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 claims description 4
- 229910003465 moissanite Inorganic materials 0.000 claims description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims description 4
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 4
- 229910021488 crystalline silicon dioxide Inorganic materials 0.000 claims description 3
- 239000003989 dielectric material Substances 0.000 claims description 3
- 239000007789 gas Substances 0.000 claims description 3
- 229910052739 hydrogen Inorganic materials 0.000 claims description 3
- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- 150000004706 metal oxides Chemical class 0.000 claims description 3
- 229910052785 arsenic Inorganic materials 0.000 claims description 2
- 229910052796 boron Inorganic materials 0.000 claims description 2
- 229910052799 carbon Inorganic materials 0.000 claims description 2
- 239000004020 conductor Substances 0.000 claims description 2
- 229910052743 krypton Inorganic materials 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 229910052751 metal Inorganic materials 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims description 2
- 150000004767 nitrides Chemical class 0.000 claims description 2
- 229910052581 Si3N4 Inorganic materials 0.000 claims 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims 1
- 239000000126 substance Substances 0.000 claims 1
- 238000000137 annealing Methods 0.000 description 8
- 235000012431 wafers Nutrition 0.000 description 7
- 239000007943 implant Substances 0.000 description 5
- 238000010849 ion bombardment Methods 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 5
- 238000002513 implantation Methods 0.000 description 3
- -1 silicon nitrides Chemical class 0.000 description 3
- 229910004205 SiNX Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 108091006149 Electron carriers Proteins 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 230000002209 hydrophobic effect Effects 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229910021426 porous silicon Inorganic materials 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02609—Crystal orientation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76275—Vertical isolation by bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
- H01L27/1207—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
- H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/78654—Monocrystalline silicon transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
Definitions
- the present invention relates to high-performance complementary metal oxide semiconductor (CMOS) circuits in which carrier mobility is enhanced by utilizing different semiconductor surface orientations for p-type field effect transistors (FETs) and n-type FETs. More particularly, the present invention relates to methods for fabricating planar substrate structures with different surface crystal orientations, and to the hybrid-orientation substrate structures produced by such methods.
- CMOS complementary metal oxide semiconductor
- CMOS circuits of current semiconductor technology comprise n-type FETs (nFETs), which utilize electron carriers for their operation, and p-type FETs (pFETs), which utilize hole carriers for their operation.
- CMOS circuits are typically fabricated on semiconductor wafers having a single crystal orientation. In particular, most of today's semiconductor devices are built on Si having a ( 100 ) surface orientation.
- hole mobility can be about 2 to 4 times higher on a 110 -oriented Si wafer than on a standard 100 -oriented Si wafer. It would therefore be desirable to create a hybrid-orientation substrate comprising 100 -oriented Si (where nFETs would be formed) and 110 -oriented Si (where pFETs would be formed).
- Planar hybrid substrate structures with different surface orientations have been described previously (see, for example, co-assigned U.S. application Ser. No. 10/696,634, filed Oct. 29, 2003, and co-assigned U.S. application Ser. No. 10/250,241, filed Jun. 17, 2003).
- FIGS. 1A-1E show, in cross section view, some prior art examples of planar hybrid-orientation semiconductor substrate structures comprising bulk semiconductor substrate 10 , dielectric trench isolation regions 20 , semiconductor regions 30 with a first surface orientation (e.g., j′k′l′), and semiconductor region 40 with a second surface orientation (e.g., jkl).
- semiconductor regions 30 and 40 are both directly on bulk substrate 10 , with semiconductor region 40 and bulk substrate 10 having the same orientation.
- the structure of FIG. 1B differs from that of FIG. 1A only in that semiconductor regions 30 are on buried oxide (BOX) layer 50 instead of directly on bulk substrate 10 .
- the structures of FIGS. 1C-1E differ from those of FIGS. 1A-1B by the thickness of BOX layers 50 and 50 ′ and by the depth of trench isolation structures 20 and 20 ′.
- FIGS. 2A-2B show, in cross section view, previous examples of how integrated CMOS circuits comprising at least one pFET on a ( 110 ) crystallographic plane of Si and at least one nFET on a ( 100 ) crystallographic plane of Si may be advantageously disposed on the hybrid-orientation substrate structure of FIG. 1B .
- a bulk Si substrate 120 with 100 orientation has regions 130 of 110 -oriented Si on BOX layer 140 , and regions 150 of regrown 100 -oriented Si on bulk substrate 120 .
- pFET devices 170 are disposed on 110 -oriented regions 130 and nFET devices 180 are disposed on 100 -oriented regions 150 .
- FIG. 1A shows, in cross section view, previous examples of how integrated CMOS circuits comprising at least one pFET on a ( 110 ) crystallographic plane of Si and at least one nFET on a ( 100 ) crystallographic plane of Si may be advantageously disposed on the hybrid-orientation substrate structure of FIG.
- a bulk Si substrate 180 with 110 orientation has regions 190 of 100 -oriented Si on a BOX layer 140 and regions 200 of regrown 110 -oriented Si on bulk substrate 180 .
- pFET devices 210 are disposed on 110 -oriented regions 180 and nFET devices 220 are disposed on 100 -oriented regions 190 .
- FIGS. 3A-3I show, in cross section view, the steps of a prior art method used to form the structure of FIG 1 B.
- FIG. 3A shows the starting Si substrate 250
- FIG. 3B shows substrate 250 after formation of BOX layer 260 and silicon-on-insulator (SiOI) device layer 270 .
- Si substrate 250 may be 110 - (or 100 -) oriented, and SiOI device layer 270 would be 100 - (or 110 -) oriented.
- SiOI layer 270 may be formed by bonding or other methods.
- protective dielectric (preferably SiN x ) layer 280 After depositing protective dielectric (preferably SiN x ) layer 280 to form the structure of FIG.
- SiOI device layer 270 and BOX layer 260 are removed in selected areas to form openings 290 extending to Si substrate 250 , as shown in FIG. 3D . Openings 290 are lined with a dielectric (preferably SiN x ) which is then etched to form sidewall spacers 300 , as shown in FIG. 3E .
- a dielectric preferably SiN x
- epitaxial Si 310 is selectively grown in openings 290 to produce the structure of FIG. 3F , which is planarized back to form the structure of FIG. 3G .
- Protective dielectric 280 is then removed by a process such as polishing to form the structure of FIG. 3H with coplanar, differently oriented Si device layers 310 (on bulk Si substrate 250 ) and 320 (on BOX layer 260 ).
- FIG. 3I shows the completed substrate structure after shallow trench isolation areas 330 have been formed in the structure of FIG. 3H .
- the structure of FIG. 4 may be produced by replacing Si substrate 250 in FIG. 3A with a SiOI substrate 400 comprising substrate 410 , BOX layer 420 , and Si layer 430 to produce differently oriented single crystal regions 320 with a first orientation and 440 with a second orientation matching that of semiconductor layer 430 .
- the use of two BOX layers adds extra complexity to the process and produces structures where one of the hybrid orientations is significantly thicker than the other (a disadvantage when both layers need to be thin).
- planar hybrid-orientation semiconductor substrate structures especially planar hybrid-orientation semiconductor-on-insulator (SOI) substrate structures wherein the differently oriented semiconductors are disposed on a common BOX layer.
- SOI semiconductor-on-insulator
- the term “clearly defined” is used herein to denote that the surface regions of a given surface orientation are macroscopic and not merely single grains of polycrystalline Si.
- ICs integrated circuits
- the sides of the regions selected for amorphization and templated recrystallization would typically be isolated from adjacent crystalline regions, for example, by trenches.
- the trenches may be formed and filled before amorphization, formed and filled between amorphization and recrystallization, or formed after amorphization and filled after recrystallization.
- the basic steps above are incorporated into a method for forming a planar hybrid-orientation SiOI substrate structure.
- a 100 -oriented Si substrate is used for the first, lower layer of the bilayer template stack and a 110 -oriented Si layer for the second, upper layer of the bilayer template stack.
- the uppermost portion of the template stack is amorphized in selected areas to a depth that ends in the underlying 100 -oriented Si substrate.
- the amorphized Si regions are then recrystallized into 100 -oriented Si, using the underlying 100 -oriented Si as a template.
- a buried oxide (BOX) layer is formed by oxygen implantation and annealing (e.g., a “Separation by Implantation of Oxygen” or SIMOX process).
- the basic steps above are incorporated into a another method to form a planar hybrid-orientation SiOI substrate structure.
- a 110 -oriented SiOI layer on a BOX layer is used for the first, lower layer of a bilayer template stack, and a 100 -oriented Si layer is used for the second, upper layer of a bilayer template stack.
- the lowermost portion of the bilayer template stack is then amorphized in selected areas from the BOX layer up to a depth ending in the upper template layer.
- the amorphized Si regions are then recrystallized into 100 -orientated Si, using the upper 100 -oriented Si layer as a template.
- the uppermost portion of the bilayer template is then removed by a process such as polishing to leave coplanar surface regions of 110 -oriented Si (in the untreated areas) and 100 -oriented Si (in the treated areas).
- the basic steps of the present invention can be easily adapted in whole or in part to form planar hybrid-orientation semiconductor structures on different substrates (e.g., bulk, thin or thick BOX, insulating or high resistivity substrates), or to form planar hybrid-orientation semiconductor substrate structures having three or more surface orientations.
- substrates e.g., bulk, thin or thick BOX, insulating or high resistivity substrates
- planar hybrid-orientation semiconductor substrate structures having three or more surface orientations.
- Yet another aspect of the present invention provides integrated circuits on the planar hybrid-orientation semiconductor substrates of this invention, wherein the integrated circuits comprise pFETs on a ( 110 ) crystallographic plane and nFETs on a ( 100 ) crystallographic plane.
- FIGS. 1A-1E show, in cross section view, some examples of prior art planar hybrid-orientation semiconductor substrate structures, wherein the first of two semiconductor orientations is disposed directly on a bulk semiconductor substrate and the second of two semiconductor orientations is disposed either on the substrate ( FIGS. 1A and 1C ), partially insulated from the substrate by a thin BOX layer ( FIG. 1E ), or fully insulated from the substrate by a thick BOX layer (FIGS. 1 B and 1 D);
- FIGS. 2A-2B show, in cross section view, prior art examples of how the hybrid-orientation substrate structure of FIG. 1B might form the basis of integrated circuits comprising at least one pFET on a 110 -oriented single crystal Si region and at least one nFET on a 100 -oriented single crystal Si region;
- FIGS. 3A-3I show, in cross section view, the steps of the basic prior art method used to form the structures of FIGS. 1A-1E , illustrated for the case of FIG. 1B ;
- FIG. 4 shows, in cross section view, a prior art example of a planar hybrid-orientation semiconductor substrate structure wherein both of two differently oriented single crystal Si regions are disposed on buried insulator layers;
- FIGS. 5A-5B show, in cross section view, two preferred SOI embodiments of the hybrid-orientation substrates of the present invention
- FIG. 6 shows, in cross section view, how a hybrid-orientation substrate structure of the present invention can be used to form the basis of an integrated circuit comprising at least one pFET on a ( 110 ) Si crystallographic plane and at least one nFET on a ( 100 ) Si crystallographic plane.
- FIGS. 7A-7G show, in cross section view, the basic steps underlying the methods of the present invention, illustrated for the case of upper layer amorphization and lower layer templating;
- FIGS. 8A-8G show, in cross section view, a first preferred method to produce the structure of FIG. 5A of the present invention
- FIG. 9A-9F show, in cross section view, a second preferred method to produce the structure of FIG. 5B of the present invention.
- FIGS. 10A-10I show, in cross section view, different embodiments of the hybrid-orientation substrates that may be produced by the methods of the present invention.
- FIGS. 5A-5B show, in cross section view, two preferred embodiments of hybrid-orientation substrates that can be fabricated by the methods of the present invention.
- Hybrid-orientation substrate 450 of FIG. 5A and hybrid-orientation substrate 460 of FIG. 5B both comprise first single crystal semiconductor regions 470 with a first orientation, and second single crystal semiconductor regions 480 with a second orientation different from the first orientation.
- Semiconductor regions 470 and 480 have approximately the same thickness and are disposed on the same BOX layer 490 .
- the term “BOX” denotes a buried oxide region. Although this terminology is specifically used here, the present invention is not limited to merely buried oxides. Instead, various insulating layers can be used; the various insulating layers are described in greater detail hereinbelow.
- trench isolation regions 500 are separated by dielectric trench isolation regions 500 , which are shown as having the same depth and stopping on BOX layer 490 .
- trench isolation regions 500 may be shallower (so as not to reach BOX layer 490 ), deeper (so as to extend past BOX layer 490 ), or of non-equal depths, as desired.
- the structures of FIGS. 5A and 5B differ from each other only in the particulars of substrates 510 and 520 .
- Substrate 510 in FIG. 5A is a semiconductor having an epitaxial relationship to single crystal semiconductor region 480
- substrate 520 in FIG. 5B has no particular restrictions other than being compatible with whatever subsequent processing it will be subjected to.
- the hybrid-orientation substrate structures of FIGS. 5A-5B may be incorporated as the substrates for integrated circuits comprising at least one pFET on a ( 110 ) crystallographic plane and at least one nFET on a ( 100 ) crystallographic plane.
- FIG. 6 illustrates an exemplary integrated circuit on a Si version of the hybrid-orientation substrate structure of FIG. 5B , in cross section view.
- Substrate 520 has single crystal 110 -oriented Si regions 530 and single crystal 100 -oriented Si regions 540 , separated by isolation regions 500 on BOX layer 490 .
- pFET devices 170 are disposed on 110 -oriented regions 530 and nFET devices 180 are disposed on 100 -oriented regions 540 . For clarity, dopings are not shown.
- the FETs shown in FIG. 6 can be fabricated on the structure shown in FIG. 5A using techniques that are well known to those skilled in the art.
- the 110 and 100 crystal orientations of layers 540 and 530 are reversed.
- the pFET devices 170 would still be fabricated atop the 110 -oriented regions and the nFET devices 180 would be fabricated atop the 100 -oriented surface.
- the present invention also provides new methods for forming planar hybrid-orientation semiconductor substrate structures. Common to all methods are three basic steps, by which the orientation of selected semiconductor regions may be changed from an original orientation to a desired orientation:
- FIGS. 7A-7D These steps are illustrated in FIGS. 7A-7D for the case of upper layer amorphization and bottom layer templating. Although this embodiment is shown, the present invention also contemplates methods in which the bottom layer is amorphized and recrystallization is templated from the top layer.
- FIG. 7A shows initial SOI substrate 580 comprising base substrate 520 , BOX layer 490 , and single crystal SOI layer 590 with a first orientation.
- SOI layer 590 may be formed by bonding or by any other method known to the art.
- FIG. 7B shows bilayer template stack 600 comprising SOI layer 590 as a lower template layer with a first orientation and single crystal semiconductor layer 610 as an upper template layer with a second orientation different from the first orientation. Layer 610 would typically be formed by bonding.
- FIG. 7C shows the structure of FIG. 7B after ion bombardment 620 in selected areas creates localized amorphized regions 630 .
- Localized amorphized regions 630 extend from the top surface of upper template layer 610 down to interface 640 , located within lower template layer 590 .
- Selected area ion bombardment 620 would typically be effected by blanket ion bombardment in combination with a patterned mask.
- FIG. 7D shows the structure of FIG. 7C after localized amorphized regions 630 have been recrystallized (starting at interface 640 , using lower layer 590 as a template) to form single crystal semiconductor region 650 .
- Non-amorphized upper template layer regions 610 ′ (with the second crystal orientation) and recrystallized region 650 (with the first crystal orientation) now comprise planar hybrid-orientation substrate 650 with surface A-B comprising at least two clearly defined single-crystal semiconductor regions with different surface orientations.
- the sides of the region(s) 630 selected for amorphization and templated recrystallization would typically be at least partially isolated from adjacent crystalline regions, for example, by trenches.
- the trenches may be formed and filled before amorphization, formed and filled between amorphization and recrystallization, or formed after amorphization and filled after recrystallization.
- Trench formation would typically be effected by a process such as reactive ion etching (RIE) through a mask.
- RIE reactive ion etching
- FIGS. 7E-7G show examples of three geometries for isolation trenches.
- isolation trenches 660 extend through the upper template layer, but do not extend past the amorphization depth. In this case, some templating from side interfaces 670 may occur.
- isolation trenches 680 extend past the amorphization depth, but not all the way to BOX layer 490
- isolation trenches 690 extend all the way to BOX layer 490 .
- isolation trenches may not be necessary if the recrystallization rate of the desired crystal orientation is much faster than recrystallization templated from competing undesired crystal orientations.
- the recrystallization rates of Si-implant-amorphized single crystal Si samples has been reported to be three times faster for 100 -oriented Si than for 110 -oriented Si [see, for example, L. Csepregi et al., J. Appl. Phys. 49 3096 (1978)].
- the fact that different semiconductor orientations can differ in their recrystallization rates should also be considered when designing the template layer stacks and process flows.
- the layer of a bilayer template stack having the slower-growing orientation would preferably be the one that is amorphized, whereas the layer with the faster-growing orientation would preferably be the one from which the recyrstallization is templated.
- FIGS. 8A-8G the basic steps of FIGS. 7A-7D are incorporated into a method for forming a planar hybrid-orientation SiOI substrate structure similar to structure 450 of FIG. 5A .
- isolation trenches are not shown.
- FIG. 8A shows 100 -oriented Si substrate 700 comprising the first, lower layer of the template stack;
- FIG. 8B shows the substrate 700 after addition of 110 -oriented Si layer 710 comprising the second, upper layer of the template stack.
- Layer 710 would typically be formed by bonding.
- FIG. 8C shows the structure of FIG. 8B being subjected to ion bombardment 720 in selected areas to create the structure of FIG. 8D with localized amorphized regions 730 extending from the top surface of template layer 710 to a depth ending in substrate 700 .
- FIG. 8E shows the structure of FIG. 8D after localized amorphized regions 730 have been recrystallized (using 100 -oriented Si substrate 700 as a template) to form single crystal 100 -oriented Si region(s) 740 .
- Non-amorphized 110 -oriented Si regions 710 ′ and recrystallized 100 -oriented Si region(s) 740 now comprise bulk planar hybrid-orientation substrate 750 with surface A-B comprising at least two clearly defined single-crystal semiconductor regions with different surface orientations.
- FIGS. 8F-8G A SIMOX process is then used to create a BOX layer, as shown in FIGS. 8F-8G .
- FIG. 8F shows the structure of FIG. 8E being exposed to blanket oxygen ion implantation 760 used to create buried O-rich layer 770 .
- O-rich layer 770 preferably contains the original interface between layers 700 and 710 , and is converted into BOX layer 780 of FIG. 8G by the appropriate annealing steps.
- FIGS. 9A-9F the basic steps of FIGS. 7A-7D are incorporated into yet another method to form a planar hybrid-orientation SiOI substrate structure similar to structure 460 of FIG. 5B .
- FIG. 9A shows initial SiOI substrate 800 comprising base substrate 520 , BOX layer 490 , and 110 -oriented single crystal Si layer 810 .
- Si layer 810 may be formed by bonding or by any other method known to the art.
- FIG. 9B shows bilayer template stack 820 comprising 110 -oriented Si layer 810 as a lower template layer and single crystal 100 -oriented Si layer 830 as an upper template layer. Layer 830 would typically be formed by bonding.
- FIG. 9C shows the structure of FIG.
- FIG. 9B being subjected to ion bombardment 840 in selected areas to create the structure of FIG. 9D with buried localized amorphized regions 850 .
- Localized amorphized regions 850 extend from BOX layer 490 through lower template layer 810 and partially into upper template layer 830 .
- the areas selected for amorphization and templated recrystallization would typically be isolated from adjacent crystalline regions by trenches (not shown) to minimize the possibility of lateral templating.
- FIG. 9E shows the structure of FIG. 9D after localized amorphized regions 850 have been recrystallized, using upper template layer 810 as a template, to form 100 -oriented single crystal Si regions 860 .
- Upper template layer 810 is then removed by a process such as polishing (or oxidation followed by wet etchback) to leave coplanar 110 -oriented single-crystal Si regions 810 ′ and 100 -oriented single-crystal Si regions 860 disposed on common BOX layer 490 .
- FIGS. 8A-8G may equally well be employed with the orientations of substrate 700 and upper template layer 710 reversed, i.e., with substrate 700 comprising a 110 -oriented Si wafer instead of a 100 -oriented Si wafer, and upper template layer 710 comprising a single crystal layer of 100 -oriented Si instead of a single crystal layer of 110 -oriented Si.
- the method of FIGS. 9A-9F may be employed with the orientations of lower template layer 810 and upper template layer 830 reversed, i.e., with lower template layer 810 being 100 -oriented Si instead of 110 -oriented Si and upper template layer 830 being 110 -oriented Si instead of 100 -oriented Si.
- the structures and methods of the present invention may be employed using semiconductors other than Si, as will be described in more detail below.
- FIGS. 10A-10I show, in cross section view, different embodiments of the hybrid-orientation substrates that may be produced by the methods of the present invention.
- FIG. 10A shows “bulk” planar hybrid-orientation semiconductor substrate structure 900 comprising first single crystal semiconductor regions 910 with a first orientation, and second single crystal semiconductor regions 920 with a second orientation different from the first orientation, but identical to the orientation of substrate 930 .
- Planar hybrid-orientation semiconductor substrate structure 940 of FIG. 10B is similar to structure 900 of FIG. 10A , but has trench isolation regions 950 separating single crystal semiconductor regions 910 and 920 .
- Planar hybrid-orientation semiconductor substrate structure 960 of FIG. 10C is similar to structure 900 of FIG. 10A . However, substrate 930 has been replaced with substrate 980 , which may or not be epitaxially related to semiconductor region 920 . Structure 960 also comprises BOX layer 970 under semiconductor regions 910 and 920 , and residuals 990 of second semiconductor material with the second orientation remaining under first semiconductor regions 910 . Planar hybrid-orientation semiconductor substrate structure 1000 of FIG. 10D is similar to structure 960 of FIG. 10C , except that semiconductor region 920 is epitaxially related to semiconductor substrate 930 , and BOX layer 970 is located above interface 1010 between first single crystal semiconductor regions 910 and substrate 930 .
- Planar hybrid-orientation semiconductor substrate structures 1020 and 1030 of FIGS. 10E-10F are identical to structures 1000 and 940 of FIGS. 10A-10B , except that semiconductor substrate 930 has been replaced by insulating substrate 1040 .
- Planar hybrid-orientation semiconductor substrate structures 1050 and 1060 of FIGS. 10G-10H are similar to structure 960 of FIG. 10C , but have trench isolation regions 950 .
- trench isolation regions 950 extend below interface 1070 between first single crystal semiconductor regions 910 and residuals 990 , but do not reach BOX layer 970 .
- trench isolation regions 950 extend to BOX layer 970 .
- Planar hybrid-orientation semiconductor substrate structure 1080 of FIG. 10I comprises three differently oriented single crystal semiconductor regions 910 , 920 , and 1090 , separated by trench isolation regions 950 extending to BOX layer 970 .
- Planar hybrid-orientation semiconductor substrate structures with three or more surface orientations may be produced by the localized amorphization and recrystallization methods of this invention by using a multilayer template stack instead of a bilayer template stack.
- FIGS. 5A-5B and FIGS. 10A-10I may be produced by using various permutations of the basic steps of the invention with or without additional steps.
- a planar hybrid-orientation structure resembling 460 of FIG. 5B may be produced from the structure of FIG. 10H by the additional steps of amorphizing residuals 990 of second semiconductor material 920 and recrystallizing the amorphized regions using single crystal region 910 as a template.
- the semiconductor substrates and single crystal semiconductor regions of the present invention may be selected from a wide range of semiconductor materials.
- substrates 510 , 520 , 700 , 930 and 980 , and differently oriented first and second semiconductor regions 470 , 610 ′, 910 , and 480 , 650 , and 920 may be selected from the group including Si, SiC, SiGe, SiGeC, Ge alloys, Ge, C, GaAs, InAs, InP as well as other III-V or II-VI compound semiconductors.
- Layered combinations or alloys of the aforementioned semiconductor materials for example, Si layers on SiGe
- First and second semiconductor regions may be strained, unstrained, or a combination of strained and unstrained layers can be used. The crystallographic orientations would typically be selected from the group including ( 110 ), ( 111 ), and ( 100 ).
- first and second single crystal semiconductor regions 470 , 610 ′, 910 , and 480 , 650 , and 920 is typically from about 1 to about 500 nm, with a thickness from about 10 to about 100 nm being more typical.
- the thickness of substrates 510 , 520 , 700 , 930 , and 980 would typically be between 5 and 1000 ⁇ m, and most typically be about 600 ⁇ m.
- BOX layers and insulating substrates 1040 may be selected from a wide range of dielectric materials, including, but not limited to the group including SiO 2 , crystalline SiO 2 , SiO 2 containing nitrogen or other elements, silicon nitrides, metal oxides (e.g., Al 2 O 3 ), insulating metal nitrides (e.g., AlN), highly thermally conductive materials such as crystalline diamond.
- BOX thicknesses may range from about 2 nm to about 500 nm, with preferable thicknesses typically being in the range from about 50 to about 150 nm.
- Bonding methods for forming the template stack may include any methods known to those skilled in the art (see, for example, Q. Y. Tong et al. [in Semiconductor Wafer Bonding: Science and Technology (John Wiley, 1998)] and co-pending and co-assigned U.S. application Ser. No. 10/696,634, filed Oct. 29, 2003, and co-pending and co-assigned U.S. application Ser. No. 10/250,241, filed Jun. 17, 2003). The contents of each of the above mentioned co-assigned U.S. applications are incorporated herein by reference.
- Differently oriented semiconductor surfaces to be bonded are preferably hydrophobic (rather than hydrophilic) for the cleanest possible interfaces, since impurities in the amorphized regions will typically impede the progress of the recrystallization.
- very thin oxides at the bonded interface may be tolerable if the oxide can be made to assume a discontinuous, islanded morphology by suitable annealing (see, for example, P. McCann et al. [“An investigation into interfacial oxide in direct silicon bonding,” 6th Int. Symp. on Semiconductor Wafer Bonding, San Francisco, Sep. 2-7, 2001]).
- Wafer separation/removal after bonding may be accomplished by grinding or etching the wafer away (preferably making use of an etch stop layer), or by making use of a mechanically weak interface layer created at earlier steps in processing.
- mechanically weak interface layers include porous Si (see, for example, Epitaxial Layer Transfer (ELTRAN) described by K. Sakaguchi et al. in Solid State Technology, June 2000] and ion-implanted H-containing bubbles (see, for example, Smart Cut process, described in U.S. Pat. No. 5,374,564 by M. Bruel, which issued Dec. 20, 1994, and U.S. Pat. No. 5,882,987 by K. V. Srikrishnan, which issued Mar. 16, 1999).
- ETRAN Epitaxial Layer Transfer
- H-containing bubbles see, for example, Smart Cut process, described in U.S. Pat. No. 5,374,564 by M. Bruel, which issued Dec. 20, 1994, and U.S. Pat. No. 5,882,98
- Amorphization would typically be effected by ion implantation.
- the optimum ion implantation conditions will depend on the materials of the template layers, the thickness of the template layers, and position (upper or lower) of the stack layer being amorphized. Any ion species known to those skilled in the art may be used, including but not limited to: Si, Ge, Ar, C, O, N, H, He, Kr, Xe, P, B, As, etc.
- Ions for the amorphization are preferably Si or Ge.
- Lighter ions such as H and He are typically less effective at amorphization.
- Ion implantation may be performed at temperatures ranging from cryogenic to several hundred ° C. above nominal room temperature.
- nominal room temperature it is meant a temperature from about 20° to about 40° C. Regions not being amorphized would typically be protected from ion implantation by a patterned mask (for example, patterned photoresist for a room temperature implantation process). Implants may be performed with or without “screen oxide” layers and may be performed with multiple implants at different energies if a sufficiently uniformly amorphized region cannot be easily achieved with a single implant. The required implant dose depends on the implanting species, the semiconductor being implanted, and the thickness of the layer needing to be amorphized.
- Si implanted at cryogenic temperatures at 50, 100, 150, and 200 keV with a total dose of 6E15/cm 2 was found to be sufficient to amorphize the top 400 nm of 100 -oriented and 110 -oriented Si (see, for example, L. Csepregi et al.).
- much lower doses for example, 5E14/cm 2 at 40 keV
- Recrystallization of localized amorphous regions 630 , 730 , and 850 is typically effected by annealing at temperatures from about 200° to about 1300° C., preferably from about 400° to about 900° C., and more preferably from about 400° and 600° C., for a time period sufficient to bring about the desired recrystallization. This time period will depend on the orientation of the template layer, on the thickness of the amorphized region to be recrystallized, on the presence of implanted and other impurities in the amorphized layer, and possibly on the sharpness of the interface between the implanted and unimplanted regions.
- Annealing may be performed in a furnace or by rapid thermal annealing. In other embodiments, annealing may be performed using a laser anneal or a spike anneal.
- the annealing ambient would typically be selected from the group of gases including N 2 , Ar, He, H 2 and mixtures of these gases.
- any conventional ion implant step and annealing step that can be used in forming a buried insulating layer can be employed.
- any conventional SIMOX process can be used in producing a buried oxide layer in the structures shown in FIGS. 8F-8G .
- hybrid-orientation substrates of the invention may incorporate additional overlayers (such as epitaxially grown semiconductors or additional bonded layers), removal or etchback of certain surface features (for example, recessing one or more of the single crystal semiconductor regions or trench isolations), and/or specialized doping profiles, if such substrate features are desired for the subsequently fabricated devices.
- additional overlayers such as epitaxially grown semiconductors or additional bonded layers
- removal or etchback of certain surface features for example, recessing one or more of the single crystal semiconductor regions or trench isolations
- specialized doping profiles if such substrate features are desired for the subsequently fabricated devices.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Element Separation (AREA)
- Thin Film Transistor (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
- The present invention relates to high-performance complementary metal oxide semiconductor (CMOS) circuits in which carrier mobility is enhanced by utilizing different semiconductor surface orientations for p-type field effect transistors (FETs) and n-type FETs. More particularly, the present invention relates to methods for fabricating planar substrate structures with different surface crystal orientations, and to the hybrid-orientation substrate structures produced by such methods.
- The CMOS circuits of current semiconductor technology comprise n-type FETs (nFETs), which utilize electron carriers for their operation, and p-type FETs (pFETs), which utilize hole carriers for their operation. CMOS circuits are typically fabricated on semiconductor wafers having a single crystal orientation. In particular, most of today's semiconductor devices are built on Si having a (100) surface orientation.
- It is known that electrons have a high mobility in Si with a (100) surface orientation and that holes have high mobility in Si with a (110) surface orientation. In fact, hole mobility can be about 2 to 4 times higher on a 110-oriented Si wafer than on a standard 100-oriented Si wafer. It would therefore be desirable to create a hybrid-orientation substrate comprising 100-oriented Si (where nFETs would be formed) and 110-oriented Si (where pFETs would be formed).
- Planar hybrid substrate structures with different surface orientations have been described previously (see, for example, co-assigned U.S. application Ser. No. 10/696,634, filed Oct. 29, 2003, and co-assigned U.S. application Ser. No. 10/250,241, filed Jun. 17, 2003).
-
FIGS. 1A-1E show, in cross section view, some prior art examples of planar hybrid-orientation semiconductor substrate structures comprisingbulk semiconductor substrate 10, dielectrictrench isolation regions 20,semiconductor regions 30 with a first surface orientation (e.g., j′k′l′), andsemiconductor region 40 with a second surface orientation (e.g., jkl). In the structure ofFIG. 1A ,semiconductor regions bulk substrate 10, withsemiconductor region 40 andbulk substrate 10 having the same orientation. The structure ofFIG. 1B differs from that ofFIG. 1A only in thatsemiconductor regions 30 are on buried oxide (BOX)layer 50 instead of directly onbulk substrate 10. The structures ofFIGS. 1C-1E differ from those ofFIGS. 1A-1B by the thickness ofBOX layers trench isolation structures -
FIGS. 2A-2B show, in cross section view, previous examples of how integrated CMOS circuits comprising at least one pFET on a (110) crystallographic plane of Si and at least one nFET on a (100) crystallographic plane of Si may be advantageously disposed on the hybrid-orientation substrate structure ofFIG. 1B . InFIG. 2A , abulk Si substrate 120 with 100 orientation hasregions 130 of 110-oriented Si onBOX layer 140, andregions 150 of regrown 100-oriented Si onbulk substrate 120.pFET devices 170 are disposed on 110-orientedregions 130 andnFET devices 180 are disposed on 100-orientedregions 150. InFIG. 2B , abulk Si substrate 180 with 110 orientation hasregions 190 of 100-oriented Si on aBOX layer 140 andregions 200 of regrown 110-oriented Si onbulk substrate 180.pFET devices 210 are disposed on 110-orientedregions 180 andnFET devices 220 are disposed on 100-orientedregions 190. -
FIGS. 3A-3I show, in cross section view, the steps of a prior art method used to form the structure of FIG 1B. Specifically,FIG. 3A shows the startingSi substrate 250, andFIG. 3B showssubstrate 250 after formation ofBOX layer 260 and silicon-on-insulator (SiOI)device layer 270.Si substrate 250 may be 110- (or 100-) oriented, andSiOI device layer 270 would be 100- (or 110-) oriented. SiOIlayer 270 may be formed by bonding or other methods. After depositing protective dielectric (preferably SiNx)layer 280 to form the structure ofFIG. 3C ,SiOI device layer 270 andBOX layer 260 are removed in selected areas to formopenings 290 extending toSi substrate 250, as shown inFIG. 3D .Openings 290 are lined with a dielectric (preferably SiNx) which is then etched to formsidewall spacers 300, as shown inFIG. 3E . Next,epitaxial Si 310 is selectively grown inopenings 290 to produce the structure ofFIG. 3F , which is planarized back to form the structure ofFIG. 3G . Protective dielectric 280 is then removed by a process such as polishing to form the structure ofFIG. 3H with coplanar, differently oriented Si device layers 310 (on bulk Si substrate 250) and 320 (on BOX layer 260).FIG. 3I shows the completed substrate structure after shallowtrench isolation areas 330 have been formed in the structure ofFIG. 3H . - However, for many applications, it would be desirable to have both of the differently oriented Si regions on a BOX. Such structures are possible, but not easy, to produce by variations of the method of
FIGS. 3A-3I . For example, the structure ofFIG. 4 may be produced by replacingSi substrate 250 inFIG. 3A with aSiOI substrate 400 comprisingsubstrate 410,BOX layer 420, andSi layer 430 to produce differently orientedsingle crystal regions 320 with a first orientation and 440 with a second orientation matching that ofsemiconductor layer 430. However, the use of two BOX layers adds extra complexity to the process and produces structures where one of the hybrid orientations is significantly thicker than the other (a disadvantage when both layers need to be thin). In addition, selective epitaxial Si growth can be tricky; defects are likely to nucleate on the sides of sidewall spacers 300 (shown inFIGS. 3E-3F ), especially whenopenings 290 are small (e.g., less than 500 nm in diameter). - In view of the above, it would be desirable to have simpler and better methods (i.e., those that do not require epitaxial regrowth) to form planar hybrid-orientation semiconductor substrate structures, especially planar hybrid-orientation semiconductor-on-insulator (SOI) substrate structures wherein the differently oriented semiconductors are disposed on a common BOX layer.
- In addition, it would be desirable to have integrated electrical circuits on such planar hybrid-orientation SOI substrates wherein the electrical circuits comprise pFETs on a (110) crystallographic plane and nFETs on a (100) crystallographic plane.
- It is therefore an object of the present invention to provide a planar hybrid-orientation SOI substrate structure with a surface comprising at least two clearly defined single-crystal semiconductor regions with different surface orientations, wherein the differently oriented semiconductor regions are disposed on a common BOX layer. The term “clearly defined” is used herein to denote that the surface regions of a given surface orientation are macroscopic and not merely single grains of polycrystalline Si.
- It is a related object of the present invention to provide methods for fabricating such a planar hybrid-orientation semiconductor substrate structure.
- It is a further object of the present invention to provide methods for fabricating similar hybrid-orientation semiconductor substrate structures on a variety of support layers.
- It is yet another object of the present invention to provide integrated circuits (ICs) on the hybrid-orientation substrates of the present invention, wherein the ICs comprise pFETs on a (110) crystallographic plane and nFETs on a (100) crystallographic plane.
- In accordance with the above listed and other objects, new methods are provided for forming a variety of planar hybrid-orientation semiconductor substrate structures. Common to all methods are three basic steps, by which the orientation of selected semiconductor regions may be changed from an original orientation to a desired orientation:
-
- forming a bilayer template layer stack comprising a first, lower single crystal semiconductor layer (or substrate) having a first orientation and a second, upper (typically bonded) single crystal semiconductor layer having a second orientation different from the first;
- amorphizing one of the layers of the bilayer template stack in selected areas (by ion implantation through a mask, for example) to form localized amorphized regions; and
- recrystallizing the localized amorphized regions using the non-amorphized layer of the stack as a template, thereby changing the orientation in the localized amorphized regions from an original orientation to a desired orientation.
- To minimize the possibility of lateral templating, the sides of the regions selected for amorphization and templated recrystallization would typically be isolated from adjacent crystalline regions, for example, by trenches. The trenches may be formed and filled before amorphization, formed and filled between amorphization and recrystallization, or formed after amorphization and filled after recrystallization.
- In one embodiment of the present invention, the basic steps above are incorporated into a method for forming a planar hybrid-orientation SiOI substrate structure. A 100-oriented Si substrate is used for the first, lower layer of the bilayer template stack and a 110-oriented Si layer for the second, upper layer of the bilayer template stack. The uppermost portion of the template stack is amorphized in selected areas to a depth that ends in the underlying 100-oriented Si substrate. The amorphized Si regions are then recrystallized into 100-oriented Si, using the underlying 100-oriented Si as a template. Following these steps of patterned amorphization and recrystallization, which leave surface regions of 100-oriented Si in the treated areas and surface regions of 110-oriented Si in the untreated areas, a buried oxide (BOX) layer is formed by oxygen implantation and annealing (e.g., a “Separation by Implantation of Oxygen” or SIMOX process).
- In another embodiment of the present invention, the basic steps above are incorporated into a another method to form a planar hybrid-orientation SiOI substrate structure. In this method, a 110-oriented SiOI layer on a BOX layer is used for the first, lower layer of a bilayer template stack, and a 100-oriented Si layer is used for the second, upper layer of a bilayer template stack. The lowermost portion of the bilayer template stack is then amorphized in selected areas from the BOX layer up to a depth ending in the upper template layer. The amorphized Si regions are then recrystallized into 100-orientated Si, using the upper 100-oriented Si layer as a template. The uppermost portion of the bilayer template is then removed by a process such as polishing to leave coplanar surface regions of 110-oriented Si (in the untreated areas) and 100-oriented Si (in the treated areas).
- The basic steps of the present invention can be easily adapted in whole or in part to form planar hybrid-orientation semiconductor structures on different substrates (e.g., bulk, thin or thick BOX, insulating or high resistivity substrates), or to form planar hybrid-orientation semiconductor substrate structures having three or more surface orientations.
- Yet another aspect of the present invention provides integrated circuits on the planar hybrid-orientation semiconductor substrates of this invention, wherein the integrated circuits comprise pFETs on a (110) crystallographic plane and nFETs on a (100) crystallographic plane.
- These and other features, aspects, and advantages will be more readily apparent and better understood from the following detailed description of the invention, in which:
-
FIGS. 1A-1E show, in cross section view, some examples of prior art planar hybrid-orientation semiconductor substrate structures, wherein the first of two semiconductor orientations is disposed directly on a bulk semiconductor substrate and the second of two semiconductor orientations is disposed either on the substrate (FIGS. 1A and 1C ), partially insulated from the substrate by a thin BOX layer (FIG. 1E ), or fully insulated from the substrate by a thick BOX layer (FIGS. 1B and 1D); -
FIGS. 2A-2B show, in cross section view, prior art examples of how the hybrid-orientation substrate structure ofFIG. 1B might form the basis of integrated circuits comprising at least one pFET on a 110-oriented single crystal Si region and at least one nFET on a 100-oriented single crystal Si region; -
FIGS. 3A-3I show, in cross section view, the steps of the basic prior art method used to form the structures ofFIGS. 1A-1E , illustrated for the case ofFIG. 1B ; -
FIG. 4 shows, in cross section view, a prior art example of a planar hybrid-orientation semiconductor substrate structure wherein both of two differently oriented single crystal Si regions are disposed on buried insulator layers; -
FIGS. 5A-5B show, in cross section view, two preferred SOI embodiments of the hybrid-orientation substrates of the present invention; -
FIG. 6 shows, in cross section view, how a hybrid-orientation substrate structure of the present invention can be used to form the basis of an integrated circuit comprising at least one pFET on a (110) Si crystallographic plane and at least one nFET on a (100) Si crystallographic plane. -
FIGS. 7A-7G show, in cross section view, the basic steps underlying the methods of the present invention, illustrated for the case of upper layer amorphization and lower layer templating; -
FIGS. 8A-8G show, in cross section view, a first preferred method to produce the structure ofFIG. 5A of the present invention; -
FIG. 9A-9F show, in cross section view, a second preferred method to produce the structure ofFIG. 5B of the present invention; and -
FIGS. 10A-10I show, in cross section view, different embodiments of the hybrid-orientation substrates that may be produced by the methods of the present invention. - The present invention, which provides planar hybrid-orientation SOI substrate structures and methods of fabricating the same, will now be described in greater detail by referring to the drawings that accompany the present application.
-
FIGS. 5A-5B show, in cross section view, two preferred embodiments of hybrid-orientation substrates that can be fabricated by the methods of the present invention. Hybrid-orientation substrate 450 ofFIG. 5A and hybrid-orientation substrate 460 ofFIG. 5B both comprise first singlecrystal semiconductor regions 470 with a first orientation, and second singlecrystal semiconductor regions 480 with a second orientation different from the first orientation.Semiconductor regions same BOX layer 490. The term “BOX” denotes a buried oxide region. Although this terminology is specifically used here, the present invention is not limited to merely buried oxides. Instead, various insulating layers can be used; the various insulating layers are described in greater detail hereinbelow. -
Semiconductor regions trench isolation regions 500, which are shown as having the same depth and stopping onBOX layer 490. However, in some embodiments of the present invention,trench isolation regions 500 may be shallower (so as not to reach BOX layer 490), deeper (so as to extend past BOX layer 490), or of non-equal depths, as desired. The structures ofFIGS. 5A and 5B differ from each other only in the particulars ofsubstrates Substrate 510 inFIG. 5A is a semiconductor having an epitaxial relationship to singlecrystal semiconductor region 480, whereassubstrate 520 inFIG. 5B has no particular restrictions other than being compatible with whatever subsequent processing it will be subjected to. - The hybrid-orientation substrate structures of
FIGS. 5A-5B may be incorporated as the substrates for integrated circuits comprising at least one pFET on a (110) crystallographic plane and at least one nFET on a (100) crystallographic plane.FIG. 6 illustrates an exemplary integrated circuit on a Si version of the hybrid-orientation substrate structure ofFIG. 5B , in cross section view.Substrate 520 has single crystal 110-orientedSi regions 530 and single crystal 100-orientedSi regions 540, separated byisolation regions 500 onBOX layer 490.pFET devices 170 are disposed on 110-orientedregions 530 andnFET devices 180 are disposed on 100-orientedregions 540. For clarity, dopings are not shown. - The FETs shown in
FIG. 6 can be fabricated on the structure shown inFIG. 5A using techniques that are well known to those skilled in the art. In some embodiments, the 110 and 100 crystal orientations oflayers pFET devices 170 would still be fabricated atop the 110-oriented regions and thenFET devices 180 would be fabricated atop the 100-oriented surface. - The present invention also provides new methods for forming planar hybrid-orientation semiconductor substrate structures. Common to all methods are three basic steps, by which the orientation of selected semiconductor regions may be changed from an original orientation to a desired orientation:
-
- forming a bilayer template layer stack comprising a first, lower single crystal semiconductor layer (or substrate) having a first orientation and a second, upper (typically bonded) single crystal semiconductor layer having a second orientation different from the first;
- amorphizing one of the layers of the bilayer template stack in selected areas (by ion implantation through a mask, for example) to form localized amorphized regions; and
- recrystallizing the localized amorphized regions using the non-amorphized layer of the stack as a template, thereby changing the orientation in the localized amorphized regions from an original orientation to a desired orientation.
- These steps are illustrated in
FIGS. 7A-7D for the case of upper layer amorphization and bottom layer templating. Although this embodiment is shown, the present invention also contemplates methods in which the bottom layer is amorphized and recrystallization is templated from the top layer. -
FIG. 7A showsinitial SOI substrate 580 comprisingbase substrate 520,BOX layer 490, and singlecrystal SOI layer 590 with a first orientation.SOI layer 590 may be formed by bonding or by any other method known to the art.FIG. 7B showsbilayer template stack 600 comprisingSOI layer 590 as a lower template layer with a first orientation and singlecrystal semiconductor layer 610 as an upper template layer with a second orientation different from the first orientation.Layer 610 would typically be formed by bonding.FIG. 7C shows the structure ofFIG. 7B afterion bombardment 620 in selected areas creates localizedamorphized regions 630. Localizedamorphized regions 630 extend from the top surface ofupper template layer 610 down tointerface 640, located withinlower template layer 590. Selectedarea ion bombardment 620 would typically be effected by blanket ion bombardment in combination with a patterned mask.FIG. 7D shows the structure ofFIG. 7C after localizedamorphized regions 630 have been recrystallized (starting atinterface 640, usinglower layer 590 as a template) to form singlecrystal semiconductor region 650. Non-amorphized uppertemplate layer regions 610′ (with the second crystal orientation) and recrystallized region 650 (with the first crystal orientation) now comprise planar hybrid-orientation substrate 650 with surface A-B comprising at least two clearly defined single-crystal semiconductor regions with different surface orientations. - To minimize the possibility of lateral templating, the sides of the region(s) 630 selected for amorphization and templated recrystallization would typically be at least partially isolated from adjacent crystalline regions, for example, by trenches. The trenches may be formed and filled before amorphization, formed and filled between amorphization and recrystallization, or formed after amorphization and filled after recrystallization. Trench formation would typically be effected by a process such as reactive ion etching (RIE) through a mask.
-
FIGS. 7E-7G show examples of three geometries for isolation trenches. InFIG. 7E ,isolation trenches 660 extend through the upper template layer, but do not extend past the amorphization depth. In this case, some templating fromside interfaces 670 may occur. InFIG. 7F ,isolation trenches 680 extend past the amorphization depth, but not all the way to BOXlayer 490, and inFIG. 7G ,isolation trenches 690 extend all the way to BOXlayer 490. However, isolation trenches may not be necessary if the recrystallization rate of the desired crystal orientation is much faster than recrystallization templated from competing undesired crystal orientations. For example, the recrystallization rates of Si-implant-amorphized single crystal Si samples has been reported to be three times faster for 100-oriented Si than for 110-oriented Si [see, for example, L. Csepregi et al., J. Appl. Phys. 49 3096 (1978)]. - The fact that different semiconductor orientations can differ in their recrystallization rates should also be considered when designing the template layer stacks and process flows. The layer of a bilayer template stack having the slower-growing orientation would preferably be the one that is amorphized, whereas the layer with the faster-growing orientation would preferably be the one from which the recyrstallization is templated.
- In one embodiment of the invention, shown in
FIGS. 8A-8G , the basic steps ofFIGS. 7A-7D are incorporated into a method for forming a planar hybrid-orientation SiOI substrate structure similar to structure 450 ofFIG. 5A . For simplicity, isolation trenches are not shown.FIG. 8A shows 100-orientedSi substrate 700 comprising the first, lower layer of the template stack;FIG. 8B shows thesubstrate 700 after addition of 110-orientedSi layer 710 comprising the second, upper layer of the template stack.Layer 710 would typically be formed by bonding. -
FIG. 8C shows the structure ofFIG. 8B being subjected toion bombardment 720 in selected areas to create the structure ofFIG. 8D with localizedamorphized regions 730 extending from the top surface oftemplate layer 710 to a depth ending insubstrate 700.FIG. 8E shows the structure ofFIG. 8D after localizedamorphized regions 730 have been recrystallized (using 100-orientedSi substrate 700 as a template) to form single crystal 100-oriented Si region(s) 740. Non-amorphized 110-orientedSi regions 710′ and recrystallized 100-oriented Si region(s) 740 now comprise bulk planar hybrid-orientation substrate 750 with surface A-B comprising at least two clearly defined single-crystal semiconductor regions with different surface orientations. - A SIMOX process is then used to create a BOX layer, as shown in
FIGS. 8F-8G .FIG. 8F shows the structure ofFIG. 8E being exposed to blanketoxygen ion implantation 760 used to create buried O-rich layer 770. O-rich layer 770 preferably contains the original interface betweenlayers BOX layer 780 ofFIG. 8G by the appropriate annealing steps. - In another embodiment of the present invention, shown in
FIGS. 9A-9F , the basic steps ofFIGS. 7A-7D are incorporated into yet another method to form a planar hybrid-orientation SiOI substrate structure similar to structure 460 ofFIG. 5B . Specifically,FIG. 9A showsinitial SiOI substrate 800 comprisingbase substrate 520,BOX layer 490, and 110-oriented singlecrystal Si layer 810.Si layer 810 may be formed by bonding or by any other method known to the art.FIG. 9B showsbilayer template stack 820 comprising 110-orientedSi layer 810 as a lower template layer and single crystal 100-orientedSi layer 830 as an upper template layer.Layer 830 would typically be formed by bonding.FIG. 9C shows the structure ofFIG. 9B being subjected toion bombardment 840 in selected areas to create the structure ofFIG. 9D with buried localizedamorphized regions 850. Localizedamorphized regions 850 extend fromBOX layer 490 throughlower template layer 810 and partially intoupper template layer 830. As mentioned above, the areas selected for amorphization and templated recrystallization would typically be isolated from adjacent crystalline regions by trenches (not shown) to minimize the possibility of lateral templating.FIG. 9E shows the structure ofFIG. 9D after localizedamorphized regions 850 have been recrystallized, usingupper template layer 810 as a template, to form 100-oriented singlecrystal Si regions 860.Upper template layer 810 is then removed by a process such as polishing (or oxidation followed by wet etchback) to leave coplanar 110-oriented single-crystal Si regions 810′ and 100-oriented single-crystal Si regions 860 disposed oncommon BOX layer 490. - It should be noted that the method of
FIGS. 8A-8G may equally well be employed with the orientations ofsubstrate 700 andupper template layer 710 reversed, i.e., withsubstrate 700 comprising a 110-oriented Si wafer instead of a 100-oriented Si wafer, andupper template layer 710 comprising a single crystal layer of 100-oriented Si instead of a single crystal layer of 110-oriented Si. Likewise, the method ofFIGS. 9A-9F may be employed with the orientations oflower template layer 810 andupper template layer 830 reversed, i.e., withlower template layer 810 being 100-oriented Si instead of 110-oriented Si andupper template layer 830 being 110-oriented Si instead of 100-oriented Si. More generally, the structures and methods of the present invention may be employed using semiconductors other than Si, as will be described in more detail below. -
FIGS. 10A-10I show, in cross section view, different embodiments of the hybrid-orientation substrates that may be produced by the methods of the present invention.FIG. 10A shows “bulk” planar hybrid-orientationsemiconductor substrate structure 900 comprising first singlecrystal semiconductor regions 910 with a first orientation, and second singlecrystal semiconductor regions 920 with a second orientation different from the first orientation, but identical to the orientation ofsubstrate 930. Planar hybrid-orientationsemiconductor substrate structure 940 ofFIG. 10B is similar to structure 900 ofFIG. 10A , but hastrench isolation regions 950 separating singlecrystal semiconductor regions - Planar hybrid-orientation
semiconductor substrate structure 960 ofFIG. 10C is similar to structure 900 ofFIG. 10A . However,substrate 930 has been replaced withsubstrate 980, which may or not be epitaxially related tosemiconductor region 920.Structure 960 also comprisesBOX layer 970 undersemiconductor regions residuals 990 of second semiconductor material with the second orientation remaining underfirst semiconductor regions 910. Planar hybrid-orientationsemiconductor substrate structure 1000 ofFIG. 10D is similar to structure 960 ofFIG. 10C , except thatsemiconductor region 920 is epitaxially related tosemiconductor substrate 930, andBOX layer 970 is located aboveinterface 1010 between first singlecrystal semiconductor regions 910 andsubstrate 930. - Planar hybrid-orientation
semiconductor substrate structures FIGS. 10E-10F are identical tostructures FIGS. 10A-10B , except thatsemiconductor substrate 930 has been replaced by insulatingsubstrate 1040. - Planar hybrid-orientation
semiconductor substrate structures FIGS. 10G-10H are similar to structure 960 ofFIG. 10C , but havetrench isolation regions 950. Instructure 1050 ofFIG. 10G ,trench isolation regions 950 extend belowinterface 1070 between first singlecrystal semiconductor regions 910 andresiduals 990, but do not reachBOX layer 970. Instructure 1060 ofFIG. 10H ,trench isolation regions 950 extend to BOXlayer 970. - Planar hybrid-orientation
semiconductor substrate structure 1080 ofFIG. 10I comprises three differently oriented singlecrystal semiconductor regions trench isolation regions 950 extending toBOX layer 970. Planar hybrid-orientation semiconductor substrate structures with three or more surface orientations may be produced by the localized amorphization and recrystallization methods of this invention by using a multilayer template stack instead of a bilayer template stack. - Structures like those of
FIGS. 5A-5B andFIGS. 10A-10I may be produced by using various permutations of the basic steps of the invention with or without additional steps. For example, a planar hybrid-orientation structure resembling 460 ofFIG. 5B may be produced from the structure ofFIG. 10H by the additional steps ofamorphizing residuals 990 ofsecond semiconductor material 920 and recrystallizing the amorphized regions usingsingle crystal region 910 as a template. - The semiconductor substrates and single crystal semiconductor regions of the present invention may be selected from a wide range of semiconductor materials. For example,
substrates second semiconductor regions - The thickness of first and second single
crystal semiconductor regions substrates - BOX layers and insulating
substrates 1040 may be selected from a wide range of dielectric materials, including, but not limited to the group including SiO2, crystalline SiO2, SiO2 containing nitrogen or other elements, silicon nitrides, metal oxides (e.g., Al2O3), insulating metal nitrides (e.g., AlN), highly thermally conductive materials such as crystalline diamond. BOX thicknesses may range from about 2 nm to about 500 nm, with preferable thicknesses typically being in the range from about 50 to about 150 nm. - Bonding methods for forming the template stack may include any methods known to those skilled in the art (see, for example, Q. Y. Tong et al. [in Semiconductor Wafer Bonding: Science and Technology (John Wiley, 1998)] and co-pending and co-assigned U.S. application Ser. No. 10/696,634, filed Oct. 29, 2003, and co-pending and co-assigned U.S. application Ser. No. 10/250,241, filed Jun. 17, 2003). The contents of each of the above mentioned co-assigned U.S. applications are incorporated herein by reference.
- Differently oriented semiconductor surfaces to be bonded are preferably hydrophobic (rather than hydrophilic) for the cleanest possible interfaces, since impurities in the amorphized regions will typically impede the progress of the recrystallization. However, very thin oxides at the bonded interface may be tolerable if the oxide can be made to assume a discontinuous, islanded morphology by suitable annealing (see, for example, P. McCann et al. [“An investigation into interfacial oxide in direct silicon bonding,” 6th Int. Symp. on Semiconductor Wafer Bonding, San Francisco, Sep. 2-7, 2001]). Wafer separation/removal after bonding may be accomplished by grinding or etching the wafer away (preferably making use of an etch stop layer), or by making use of a mechanically weak interface layer created at earlier steps in processing. Examples of mechanically weak interface layers include porous Si (see, for example, Epitaxial Layer Transfer (ELTRAN) described by K. Sakaguchi et al. in Solid State Technology, June 2000] and ion-implanted H-containing bubbles (see, for example, Smart Cut process, described in U.S. Pat. No. 5,374,564 by M. Bruel, which issued Dec. 20, 1994, and U.S. Pat. No. 5,882,987 by K. V. Srikrishnan, which issued Mar. 16, 1999).
- Amorphization would typically be effected by ion implantation. The optimum ion implantation conditions will depend on the materials of the template layers, the thickness of the template layers, and position (upper or lower) of the stack layer being amorphized. Any ion species known to those skilled in the art may be used, including but not limited to: Si, Ge, Ar, C, O, N, H, He, Kr, Xe, P, B, As, etc. Ions for the amorphization are preferably Si or Ge. Lighter ions such as H and He are typically less effective at amorphization. Ion implantation may be performed at temperatures ranging from cryogenic to several hundred ° C. above nominal room temperature. By “nominal room temperature” it is meant a temperature from about 20° to about 40° C. Regions not being amorphized would typically be protected from ion implantation by a patterned mask (for example, patterned photoresist for a room temperature implantation process). Implants may be performed with or without “screen oxide” layers and may be performed with multiple implants at different energies if a sufficiently uniformly amorphized region cannot be easily achieved with a single implant. The required implant dose depends on the implanting species, the semiconductor being implanted, and the thickness of the layer needing to be amorphized. Si implanted at cryogenic temperatures at 50, 100, 150, and 200 keV with a total dose of 6E15/cm2 was found to be sufficient to amorphize the top 400 nm of 100-oriented and 110-oriented Si (see, for example, L. Csepregi et al.). However, much lower doses (for example, 5E14/cm2 at 40 keV) can amorphize Si when the implanted ion is Ge and surface region to be amorphized is thinner than 50-100 nm.
- Recrystallization of localized
amorphous regions - When a buried insulating is created in the structure following the recrystallizing step, any conventional ion implant step and annealing step that can be used in forming a buried insulating layer can be employed. For example, any conventional SIMOX process can be used in producing a buried oxide layer in the structures shown in
FIGS. 8F-8G . - Several embodiments of the present invention, together with modifications thereof, have been described in detail herein and illustrated in the accompanying drawings, it will be evident that various further modifications are possible without departing from the scope of the invention. In particular, it should be emphasized that while most of the substrate structures, circuits, and methods of this invention have been illustrated for the case of a small number of single crystal regions having two different orientations, the invention applies equally well to methods for providing and structures comprising large pluralities of such single crystal regions. Furthermore, the hybrid-orientation substrates of the invention may incorporate additional overlayers (such as epitaxially grown semiconductors or additional bonded layers), removal or etchback of certain surface features (for example, recessing one or more of the single crystal semiconductor regions or trench isolations), and/or specialized doping profiles, if such substrate features are desired for the subsequently fabricated devices. Nothing in the above specification is intended to limit the invention more narrowly than the appended claims. The examples given are intended only to be illustrative rather than exclusive.
Claims (55)
Priority Applications (8)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/725,850 US20050116290A1 (en) | 2003-12-02 | 2003-12-02 | Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers |
CNB2004100923713A CN100505273C (en) | 2003-12-02 | 2004-11-09 | Planar substrate with blended orientations and its forming method |
TW093134666A TWI328286B (en) | 2003-12-02 | 2004-11-12 | Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers |
KR1020067010604A KR100961800B1 (en) | 2003-12-02 | 2004-11-30 | Planar substrate with selected semiconductor crystal orientations formed by localized amorphzation and recrystallization of stacked template layeres |
EP04812491A EP1702350A2 (en) | 2003-12-02 | 2004-11-30 | Planar substrate with selected semiconductor crystal orientations formed by localized amorphzation and recrystallization of stacked template layers |
JP2006542666A JP5063114B2 (en) | 2003-12-02 | 2004-11-30 | Method for forming planar hybrid alignment substrate |
PCT/US2004/039970 WO2005057631A2 (en) | 2003-12-02 | 2004-11-30 | Planar substrate with selected semiconductor crystal orientations formed by localized amorphzation and recrystallization of stacked template layers |
US11/566,579 US7785939B2 (en) | 2003-12-02 | 2006-12-04 | Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/725,850 US20050116290A1 (en) | 2003-12-02 | 2003-12-02 | Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/566,579 Division US7785939B2 (en) | 2003-12-02 | 2006-12-04 | Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers |
Publications (1)
Publication Number | Publication Date |
---|---|
US20050116290A1 true US20050116290A1 (en) | 2005-06-02 |
Family
ID=34620372
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/725,850 Abandoned US20050116290A1 (en) | 2003-12-02 | 2003-12-02 | Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers |
US11/566,579 Expired - Fee Related US7785939B2 (en) | 2003-12-02 | 2006-12-04 | Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/566,579 Expired - Fee Related US7785939B2 (en) | 2003-12-02 | 2006-12-04 | Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers |
Country Status (7)
Country | Link |
---|---|
US (2) | US20050116290A1 (en) |
EP (1) | EP1702350A2 (en) |
JP (1) | JP5063114B2 (en) |
KR (1) | KR100961800B1 (en) |
CN (1) | CN100505273C (en) |
TW (1) | TWI328286B (en) |
WO (1) | WO2005057631A2 (en) |
Cited By (114)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050280121A1 (en) * | 2004-06-21 | 2005-12-22 | International Business Machines Corporation | Hybrid substrate technology for high-mobility planar and multiple-gate MOSFETs |
US20060006423A1 (en) * | 2002-09-30 | 2006-01-12 | Renesas Technology Corpo. | Semiconductor wafer and manufacturing method thereof |
US20060024931A1 (en) * | 2004-07-29 | 2006-02-02 | International Business Machines Corporation | Dual SIMOX hybrid orientation technology (HOT) substrates |
US20060060925A1 (en) * | 2004-09-17 | 2006-03-23 | International Business Machines Corporation | Semiconductor device structure with active regions having different surface directions and methods |
US20060113629A1 (en) * | 2004-11-30 | 2006-06-01 | Andy Wei | Technique for forming a substrate having crystalline semiconductor regions of different characteristics located above a crystalline bulk substrate |
US20060118918A1 (en) * | 2004-12-08 | 2006-06-08 | Advanced Micro Devices, Inc. | Semiconductor device and method of making semiconductor device comprising multiple stacked hybrid orientation layers |
US20060154429A1 (en) * | 2005-01-07 | 2006-07-13 | International Business Machines Corporation | Method for fabricating low-defect-density changed orientation Si |
US20060175659A1 (en) * | 2005-02-07 | 2006-08-10 | International Business Machines Corporation | A cmos structure for body ties in ultra-thin soi (utsoi) substrates |
US20060226491A1 (en) * | 2005-04-06 | 2006-10-12 | International Business Machines Corporation | Inverted multilayer semiconductor device assembly |
US20060231892A1 (en) * | 2005-04-14 | 2006-10-19 | International Business Machines Corporation | Enhanced silicon-on-insulator (SOI) transistors and methods of making enhanced SOI transistors |
US20060276011A1 (en) * | 2005-06-01 | 2006-12-07 | International Business Machines Corporation | Amorphization/templated recrystallization method for hybrid orientation substrates |
US20060286778A1 (en) * | 2005-06-21 | 2006-12-21 | International Business Machines Corporation | Method of manufacturing dual orientation wafers |
WO2007020287A1 (en) * | 2005-08-19 | 2007-02-22 | International Business Machines Corporation | Dual trench isolation for cmos with hybrid orientations |
US20070096148A1 (en) * | 2005-10-31 | 2007-05-03 | Jan Hoentschel | Embedded strain layer in thin soi transistors and a method of forming the same |
US20070105274A1 (en) * | 2005-11-01 | 2007-05-10 | Massachusetts Institute Of Technology | Monolithically integrated semiconductor materials and devices |
US20070102769A1 (en) * | 2005-11-08 | 2007-05-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dual SOI structure |
WO2007053382A1 (en) * | 2005-10-31 | 2007-05-10 | Advanced Micro Devices, Inc. | An embedded strain layer in thin soi transistors and a method of forming the same |
US20070138578A1 (en) * | 2005-12-19 | 2007-06-21 | International Business Machines Corporation | Metal oxynitride as a pFET material |
US20070138563A1 (en) * | 2005-12-16 | 2007-06-21 | International Business Machines Corporation | Dual metal gate self-aligned integration |
US20070148921A1 (en) * | 2005-12-23 | 2007-06-28 | Jiang Yan | Mixed orientation semiconductor device and method |
US20070145373A1 (en) * | 2005-07-15 | 2007-06-28 | International Business Machines Corporation | Epitaxial imprinting |
US20070148838A1 (en) * | 2005-12-28 | 2007-06-28 | International Business Machines Corporation | Metal gate CMOS with at least a single gate metal and dual gate dielectrics |
US20070145481A1 (en) * | 2005-12-22 | 2007-06-28 | Armin Tilke | Silicon-on-insulator chip having multiple crystal orientations |
US20070173008A1 (en) * | 2006-01-20 | 2007-07-26 | International Business Machines Corporation | Introduction of metal impurity to change workfunction of conductive electrodes |
US20070190745A1 (en) * | 2006-02-10 | 2007-08-16 | Sadaka Mariam G | Method to selectively form regions having differing properties and structure |
US20070202635A1 (en) * | 2006-02-27 | 2007-08-30 | Ellis-Monaghan John J | Multi-orientation semiconductor-on-insulator (soi) substrate, and method of fabricating same |
US20070275537A1 (en) * | 2006-05-25 | 2007-11-29 | International Business Machines Corporation | Formation of improved soi substrates using bulk semiconductor wafers |
US20070281446A1 (en) * | 2006-05-31 | 2007-12-06 | Winstead Brian A | Dual surface SOI by lateral epitaxial overgrowth |
US20080050890A1 (en) * | 2005-06-16 | 2008-02-28 | International Business Machines Corporation | Hybrid oriented substrates and crystal imprinting methods for forming such hybrid oriented substrates |
US20080048269A1 (en) * | 2006-08-25 | 2008-02-28 | International Business Machines Corporation | Method of fabricating structure for integrated circuit incorporating hybrid orientation technology and trench isolation regions |
US20080048286A1 (en) * | 2005-06-16 | 2008-02-28 | Hsu Louis L | Coplanar silicon-on-insulator (soi) regions of different crystal orientations and methods of making the same |
US20080064160A1 (en) * | 2006-09-07 | 2008-03-13 | International Business Machines Corporation | Cmos devices incorporating hybrid orientation technology (hot) with embedded connectors |
US20080087961A1 (en) * | 2006-10-11 | 2008-04-17 | International Business Machines Corporation | Method of reducing stacking faults through annealing |
US20080146006A1 (en) * | 2005-06-16 | 2008-06-19 | International Business Machines Corporation | Crystal imprinting methods for fabricating substrates with thin active silicon layers |
US20080164572A1 (en) * | 2006-12-21 | 2008-07-10 | Covalent Materials Corporation | Semiconductor substrate and manufacturing method thereof |
US20080169535A1 (en) * | 2007-01-12 | 2008-07-17 | International Business Machines Corporation | Sub-lithographic faceting for mosfet performance enhancement |
JP2008177529A (en) * | 2006-12-21 | 2008-07-31 | Covalent Materials Corp | Semiconductor substrate and method for manufacturing the same |
US20080188046A1 (en) * | 2007-02-05 | 2008-08-07 | Infineon Technologies North America Corp. | Method and Apparatus For Manufacturing A Semiconductor |
US20080191292A1 (en) * | 2007-02-12 | 2008-08-14 | International Business Machines Corporation | METAL GATES WITH LOW CHARGE TRAPPING AND ENHANCED DIELECTRIC RELIABILITY CHARACTERISTICS FOR HIGH-k GATE DIELECTRIC STACKS |
US20080220595A1 (en) * | 2007-03-11 | 2008-09-11 | Chien-Ting Lin | Method for fabricating a hybrid orientation substrate |
US20080224182A1 (en) * | 2006-04-18 | 2008-09-18 | International Business Machines Corporation | Trench-edge-defect-free recrystallization by edge-angle-optimized solid phase epitaxy: method and applications to hybrid orientation substrates |
FR2913815A1 (en) * | 2007-06-06 | 2008-09-19 | Soitec Silicon On Insulator | Hybrid substrate manufacturing method for telecommunication network, involves forming dielectric/polymer layer on structure, assembling layer with support substrates, and eliminating initial substrate until buried layer is eliminated |
US20080237809A1 (en) * | 2007-03-29 | 2008-10-02 | United Microelectronics Corp. | Method of fabricating hybrid orientation substrate and structure of the same |
US20080248626A1 (en) * | 2007-04-05 | 2008-10-09 | International Business Machines Corporation | Shallow trench isolation self-aligned to templated recrystallization boundary |
US20080258222A1 (en) * | 2007-04-20 | 2008-10-23 | International Business Machines Corporation | Design Structure Incorporating a Hybrid Substrate |
US20080258181A1 (en) * | 2007-04-20 | 2008-10-23 | Ethan Harrison Cannon | Hybrid Substrates and Methods for Forming Such Hybrid Substrates |
US20080258254A1 (en) * | 2007-04-20 | 2008-10-23 | Stmicroelectronics (Crolles 2) Sas | Process for realizing an integrated electronic circuit with two active layer portions having different crystal orientations |
US20080268587A1 (en) * | 2007-04-30 | 2008-10-30 | Sadaka Mariam G | Inverse slope isolation and dual surface orientation integration |
WO2008148882A2 (en) * | 2007-06-06 | 2008-12-11 | S.O.I.Tec Silicon On Insulator Technologies | Method for producing hybrid components |
US20080303090A1 (en) * | 2007-06-05 | 2008-12-11 | International Business Machines Corporation | Super hybrid soi cmos devices |
US20090008725A1 (en) * | 2007-07-03 | 2009-01-08 | International Business Machines Corporation | Method for deposition of an ultra-thin electropositive metal-containing cap layer |
EP2015349A1 (en) * | 2007-07-11 | 2009-01-14 | Commissariat A L'energie Atomique | Method of manufacturing a semiconductor-on-insulator substrate for microelectronics and optoelectronics |
US20090032842A1 (en) * | 2007-08-02 | 2009-02-05 | Lagally Max G | Nanomembrane structures having mixed crystalline orientations and compositions |
US20090090939A1 (en) * | 2007-10-09 | 2009-04-09 | International Business Machines Corporation | Self-assembled sidewall spacer |
US20090093133A1 (en) * | 2007-10-09 | 2009-04-09 | International Business Machines Corporation | Self-assembled sidewall spacer |
US20090108301A1 (en) * | 2007-10-30 | 2009-04-30 | International Business Machines Corporation | Hybrid orientation semiconductor structure with reduced boundary defects and method of forming same |
US20090108302A1 (en) * | 2007-10-31 | 2009-04-30 | International Business Machines Corporation | Multiple crystallographic orientation semiconductor structures |
US20090130817A1 (en) * | 2007-11-16 | 2009-05-21 | Angelo Pinto | Method to eliminate re-crystallization border defects generated during solid phase epitaxy of a dsb substrate |
US20090140294A1 (en) * | 2007-11-30 | 2009-06-04 | Hemant Adhikari | hetero-structured, inverted-t field effect transistor |
WO2009128776A1 (en) * | 2008-04-15 | 2009-10-22 | Vallin Oerjan | Hybrid wafers with hybrid-oriented layer |
US20090298258A1 (en) * | 2005-01-07 | 2009-12-03 | International Business Machines Corporation | QUASI-HYDROPHOBIC Si-Si WAFER BONDING USING HYDROPHILIC Si SURFACES AND DISSOLUTION OF INTERFACIAL BONDING OXIDE |
US20100044758A1 (en) * | 2008-08-25 | 2010-02-25 | International Business Machines Corporation | Cmos with channel p-finfet and channel n-finfet having different crystalline orientations and parallel fins |
US20100068643A1 (en) * | 2008-09-17 | 2010-03-18 | Fuji Xerox Co., Ltd. | Electrostatic-image-developing toner, process for producing electrostatic-image-developing toner, electrostatic image developer, and image-forming apparatus |
WO2010049654A1 (en) * | 2008-10-31 | 2010-05-06 | Commissariat A L'energie Atomique | Method for producing a hybrid substrate with an embedded electrically insulating continuous layer |
US20100155788A1 (en) * | 2006-03-15 | 2010-06-24 | Shaheen Mohamad A | Formation of a multiple crystal orientation substrate |
US7785939B2 (en) | 2003-12-02 | 2010-08-31 | International Business Machines Corporation | Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers |
EP2224476A1 (en) * | 2009-02-27 | 2010-09-01 | Commissariat à l'Énergie Atomique et aux Énergies Alternatives | Method for manufacturing a hybrid substrate by partial re-crystallisation of a mixed layer |
US7833849B2 (en) | 2005-12-30 | 2010-11-16 | International Business Machines Corporation | Method of fabricating a semiconductor structure including one device region having a metal gate electrode located atop a thinned polygate electrode |
US20100330810A1 (en) * | 2009-06-24 | 2010-12-30 | International Business Machines Corporation | Method for removing threshold voltage adjusting layer with external acid diffusion process |
US20110042751A1 (en) * | 2009-08-18 | 2011-02-24 | International Business Machines Corporation | Thermal dual gate oxide device integration |
US20110068396A1 (en) * | 2009-09-24 | 2011-03-24 | International Business Machines Corporation | METHOD AND STRUCTURE FOR FORMING HIGH-PERFOMANCE FETs WITH EMBEDDED STRESSORS |
US20110081754A1 (en) * | 2009-10-06 | 2011-04-07 | International Business Machines Corporation | Methods for obtaining gate stacks with tunable threshold voltage and scaling |
US20110089495A1 (en) * | 2009-10-20 | 2011-04-21 | International Business Machines Corporation | Application of cluster beam implantation for fabricating threshold voltage adjusted fets |
WO2011051109A1 (en) | 2009-10-28 | 2011-05-05 | International Business Machines Corporation | BI-LAYER nFET EMBEDDED STRESSOR ELEMENT AND INTEGRATION TO ENHANCE DRIVE CURRENT |
US20110129983A1 (en) * | 2008-01-28 | 2011-06-02 | Nxp B.V. | Method for fabricating a dual-orientation group-iv semiconductor substrate |
US20110147881A1 (en) * | 2009-12-22 | 2011-06-23 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Hybrid substrate with improved isolation and simplified method for producing a hybrid substrate |
US20110163385A1 (en) * | 2010-01-07 | 2011-07-07 | International Business Machines Corporation | Asymmetric fet including sloped threshold voltage adjusting material layer and method of fabricating same |
US20110221003A1 (en) * | 2010-03-09 | 2011-09-15 | International Business Machines Corporation | MOSFETs WITH REDUCED CONTACT RESISTANCE |
US20110227130A1 (en) * | 2007-06-29 | 2011-09-22 | International Business Machines Corporation | Structures and methods of forming sige and sigec buried layer for soi/sige technology |
WO2012078225A1 (en) | 2010-12-06 | 2012-06-14 | International Business Machines Corporation | STRUCTURE AND METHOD FOR Vt TUNING AND SHORT CHANNEL CONTROL WITH HIGH K/METAL GATE MOSFETs |
US8236660B2 (en) | 2010-04-21 | 2012-08-07 | International Business Machines Corporation | Monolayer dopant embedded stressor for advanced CMOS |
US8299535B2 (en) | 2010-06-25 | 2012-10-30 | International Business Machines Corporation | Delta monolayer dopants epitaxy for embedded source/drain silicide |
US8299530B2 (en) | 2010-03-04 | 2012-10-30 | International Business Machines Corporation | Structure and method to fabricate pFETS with superior GIDL by localizing workfunction |
US20130001706A1 (en) * | 2011-06-28 | 2013-01-03 | International Business Machines Corporation | Method and Structure for Low Resistive Source and Drain Regions in a Replacement Metal Gate Process Flow |
US8361889B2 (en) | 2010-07-06 | 2013-01-29 | International Business Machines Corporation | Strained semiconductor-on-insulator by addition and removal of atoms in a semiconductor-on-insulator |
TWI402943B (en) * | 2005-12-14 | 2013-07-21 | Freescale Semiconductor Inc | Soi active layer with different surface orientation |
US8536656B2 (en) | 2011-01-10 | 2013-09-17 | International Business Machines Corporation | Self-aligned contacts for high k/metal gate process flow |
US8564063B2 (en) | 2010-12-07 | 2013-10-22 | United Microelectronics Corp. | Semiconductor device having metal gate and manufacturing method thereof |
US8609550B2 (en) | 2011-09-08 | 2013-12-17 | Synopsys, Inc. | Methods for manufacturing integrated circuit devices having features with reduced edge curvature |
US8643115B2 (en) | 2011-01-14 | 2014-02-04 | International Business Machines Corporation | Structure and method of Tinv scaling for high κ metal gate technology |
US8659054B2 (en) | 2010-10-15 | 2014-02-25 | International Business Machines Corporation | Method and structure for pFET junction profile with SiGe channel |
CN103745952A (en) * | 2013-12-25 | 2014-04-23 | 上海新傲科技股份有限公司 | Preparation method for mixed crystal substrate with insulation buried layer |
US8735265B2 (en) | 2010-04-09 | 2014-05-27 | Samsung Electronics Co., Ltd. | Methods of selectively forming silicon-on-insulator structures using selective expitaxial growth process |
EP2782119A1 (en) * | 2013-03-21 | 2014-09-24 | STMicroelectronics (Crolles 2) SAS | Method for locally modifying the strains in a SOI substrate, in particular a FD SOI substrate and corresponding device |
US8951868B1 (en) | 2013-11-05 | 2015-02-10 | International Business Machines Corporation | Formation of functional gate structures with different critical dimensions using a replacement gate process |
US8962417B2 (en) | 2010-10-15 | 2015-02-24 | International Business Machines Corporation | Method and structure for pFET junction profile with SiGe channel |
US8999791B2 (en) | 2013-05-03 | 2015-04-07 | International Business Machines Corporation | Formation of semiconductor structures with variable gate lengths |
US9059095B2 (en) | 2013-04-22 | 2015-06-16 | International Business Machines Corporation | Self-aligned borderless contacts using a photo-patternable dielectric material as a replacement contact |
US9064808B2 (en) * | 2011-07-25 | 2015-06-23 | Synopsys, Inc. | Integrated circuit devices having features with reduced edge curvature and methods for manufacturing the same |
US20150206971A1 (en) * | 2004-12-01 | 2015-07-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid Fin Field-Effect Transistor Structures and Related Methods |
US9093425B1 (en) | 2014-02-11 | 2015-07-28 | International Business Machines Corporation | Self-aligned liner formed on metal semiconductor alloy contacts |
US20150311109A1 (en) * | 2014-04-29 | 2015-10-29 | International Business Machines Corporation | CHANNEL SiGe DEVICES WITH MULTIPLE THRESHOLD VOLTAGES ON HYBRID ORIENTED SUBSTRATES, AND METHODS OF MANUFACTURING SAME |
US9184290B2 (en) | 2014-04-02 | 2015-11-10 | International Business Machines Corporation | Method of forming well-controlled extension profile in MOSFET by silicon germanium based sacrificial layer |
US9214567B2 (en) | 2013-09-06 | 2015-12-15 | Globalfoundries Inc. | Nanowire compatible E-fuse |
US9293375B2 (en) | 2014-04-24 | 2016-03-22 | International Business Machines Corporation | Selectively grown self-aligned fins for deep isolation integration |
US9331076B2 (en) | 2014-05-02 | 2016-05-03 | International Business Machines Corporation | Group III nitride integration with CMOS technology |
US9412840B1 (en) | 2015-05-06 | 2016-08-09 | International Business Machines Corporation | Sacrificial layer for replacement metal semiconductor alloy contact formation |
US9595525B2 (en) | 2014-02-10 | 2017-03-14 | International Business Machines Corporation | Semiconductor device including nanowire transistors with hybrid channels |
US20180330989A1 (en) * | 2014-07-18 | 2018-11-15 | International Business Machines Corporation | Techniques for Creating a Local Interconnect Using a SOI Wafer |
US11011411B2 (en) * | 2019-03-22 | 2021-05-18 | International Business Machines Corporation | Semiconductor wafer having integrated circuits with bottom local interconnects |
US11139402B2 (en) | 2018-05-14 | 2021-10-05 | Synopsys, Inc. | Crystal orientation engineering to achieve consistent nanowire shapes |
US11264458B2 (en) | 2019-05-20 | 2022-03-01 | Synopsys, Inc. | Crystal orientation engineering to achieve consistent nanowire shapes |
US11401162B2 (en) * | 2017-12-28 | 2022-08-02 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Method for transferring a useful layer into a supporting substrate |
US20230067984A1 (en) * | 2021-08-27 | 2023-03-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices and methods of manufacturing thereof |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7235433B2 (en) * | 2004-11-01 | 2007-06-26 | Advanced Micro Devices, Inc. | Silicon-on-insulator semiconductor device with silicon layers having different crystal orientations and method of forming the silicon-on-insulator semiconductor device |
US7521307B2 (en) * | 2006-04-28 | 2009-04-21 | International Business Machines Corporation | CMOS structures and methods using self-aligned dual stressed layers |
US20080128821A1 (en) * | 2006-12-04 | 2008-06-05 | Texas Instruments Incorporated | Semiconductor Device Manufactured Using Passivation of Crystal Domain Interfaces in Hybrid Orientation Technology |
CN102790084B (en) * | 2011-05-16 | 2016-03-16 | 中国科学院上海微系统与信息技术研究所 | Germanium and III-V mix coplanar soi semiconductor structure and preparation method thereof |
FR2983342B1 (en) * | 2011-11-30 | 2016-05-20 | Soitec Silicon On Insulator | METHOD FOR MANUFACTURING A HETEROSTRUCTURE LIMITING THE DEFECT FORMATION AND HETEROSTRUCTURE THUS OBTAINED |
CN102768982A (en) * | 2012-07-06 | 2012-11-07 | 上海新傲科技股份有限公司 | Method for preparing mixed crystallographic direction substrate with insulating buried layer |
CN102768983A (en) * | 2012-07-12 | 2012-11-07 | 上海新傲科技股份有限公司 | Method for preparing mixed crystal orientation substrate with insulating buried layer |
JP2014093319A (en) * | 2012-10-31 | 2014-05-19 | Toshiba Corp | Semiconductor device and method for manufacturing the same |
CN103871813A (en) * | 2012-12-14 | 2014-06-18 | 中国科学院微电子研究所 | Method for improving uniformity of semiconductor ion implantation |
US9666493B2 (en) | 2015-06-24 | 2017-05-30 | International Business Machines Corporation | Semiconductor device structure with 110-PFET and 111-NFET curent flow direction |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4385937A (en) * | 1980-05-20 | 1983-05-31 | Tokyo Shibaura Denki Kabushiki Kaisha | Regrowing selectively formed ion amorphosized regions by thermal gradient |
US4768076A (en) * | 1984-09-14 | 1988-08-30 | Hitachi, Ltd. | Recrystallized CMOS with different crystal planes |
US4816893A (en) * | 1987-02-24 | 1989-03-28 | Hughes Aircraft Company | Low leakage CMOS/insulator substrate devices and method of forming the same |
US5384473A (en) * | 1991-10-01 | 1995-01-24 | Kabushiki Kaisha Toshiba | Semiconductor body having element formation surfaces with different orientations |
US6172381B1 (en) * | 1997-06-20 | 2001-01-09 | Advanced Micro Devices, Inc. | Source/drain junction areas self aligned between a sidewall spacer and an etched lateral sidewall |
US6774390B2 (en) * | 2002-02-22 | 2004-08-10 | Kabushiki Kaisha Toshiba | Semiconductor device |
US20040195646A1 (en) * | 2003-04-04 | 2004-10-07 | Yee-Chia Yeo | Silicon-on-insulator chip with multiple crystal orientations |
US6815278B1 (en) * | 2003-08-25 | 2004-11-09 | International Business Machines Corporation | Ultra-thin silicon-on-insulator and strained-silicon-direct-on-insulator with hybrid crystal orientations |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60154548A (en) * | 1984-01-24 | 1985-08-14 | Fujitsu Ltd | Manufacture of semiconductor device |
US4659392A (en) * | 1985-03-21 | 1987-04-21 | Hughes Aircraft Company | Selective area double epitaxial process for fabricating silicon-on-insulator structures for use with MOS devices and integrated circuits |
EP0228624B1 (en) * | 1985-12-19 | 1993-04-21 | Sumitomo Electric Industries, Ltd. | field effect transistor |
US4775641A (en) * | 1986-09-25 | 1988-10-04 | General Electric Company | Method of making silicon-on-sapphire semiconductor devices |
US4863877A (en) * | 1987-11-13 | 1989-09-05 | Kopin Corporation | Ion implantation and annealing of compound semiconductor layers |
JPH01162362A (en) * | 1987-12-18 | 1989-06-26 | Fujitsu Ltd | Manufacture of semiconductor device |
JPH01162376A (en) * | 1987-12-18 | 1989-06-26 | Fujitsu Ltd | Manufacture of semiconductor device |
JPH03285351A (en) * | 1990-04-02 | 1991-12-16 | Oki Electric Ind Co Ltd | Cmis semiconductor device and manufacture thereof |
JPH04372166A (en) * | 1991-06-21 | 1992-12-25 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
FR2681472B1 (en) * | 1991-09-18 | 1993-10-29 | Commissariat Energie Atomique | PROCESS FOR PRODUCING THIN FILMS OF SEMICONDUCTOR MATERIAL. |
JP3156878B2 (en) * | 1992-04-30 | 2001-04-16 | 株式会社東芝 | Semiconductor device and method of manufacturing the same |
US5554562A (en) * | 1995-04-06 | 1996-09-10 | Advanced Micro Devices, Inc. | Advanced isolation scheme for deep submicron technology |
US5882987A (en) * | 1997-08-26 | 1999-03-16 | International Business Machines Corporation | Smart-cut process for the production of thin semiconductor material films |
JP4521542B2 (en) * | 1999-03-30 | 2010-08-11 | ルネサスエレクトロニクス株式会社 | Semiconductor device and semiconductor substrate |
EP1073112A1 (en) * | 1999-07-26 | 2001-01-31 | STMicroelectronics S.r.l. | Process for the manufacturing of a SOI wafer by oxidation of buried cavities |
US6229187B1 (en) * | 1999-10-20 | 2001-05-08 | Advanced Micro Devices, Inc. | Field effect transistor with non-floating body and method for forming same on a bulk silicon wafer |
US6407425B1 (en) * | 2000-09-21 | 2002-06-18 | Texas Instruments Incorporated | Programmable neuron MOSFET on SOI |
US6782759B2 (en) * | 2001-07-09 | 2004-08-31 | Nartron Corporation | Anti-entrapment system |
US7329923B2 (en) * | 2003-06-17 | 2008-02-12 | International Business Machines Corporation | High-performance CMOS devices on hybrid crystal oriented substrates |
US7023055B2 (en) * | 2003-10-29 | 2006-04-04 | International Business Machines Corporation | CMOS on hybrid substrate with different crystal orientations using silicon-to-silicon direct wafer bonding |
US20050116290A1 (en) | 2003-12-02 | 2005-06-02 | De Souza Joel P. | Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers |
-
2003
- 2003-12-02 US US10/725,850 patent/US20050116290A1/en not_active Abandoned
-
2004
- 2004-11-09 CN CNB2004100923713A patent/CN100505273C/en not_active Expired - Fee Related
- 2004-11-12 TW TW093134666A patent/TWI328286B/en not_active IP Right Cessation
- 2004-11-30 WO PCT/US2004/039970 patent/WO2005057631A2/en active Application Filing
- 2004-11-30 EP EP04812491A patent/EP1702350A2/en not_active Withdrawn
- 2004-11-30 KR KR1020067010604A patent/KR100961800B1/en not_active IP Right Cessation
- 2004-11-30 JP JP2006542666A patent/JP5063114B2/en not_active Expired - Fee Related
-
2006
- 2006-12-04 US US11/566,579 patent/US7785939B2/en not_active Expired - Fee Related
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4385937A (en) * | 1980-05-20 | 1983-05-31 | Tokyo Shibaura Denki Kabushiki Kaisha | Regrowing selectively formed ion amorphosized regions by thermal gradient |
US4768076A (en) * | 1984-09-14 | 1988-08-30 | Hitachi, Ltd. | Recrystallized CMOS with different crystal planes |
US4816893A (en) * | 1987-02-24 | 1989-03-28 | Hughes Aircraft Company | Low leakage CMOS/insulator substrate devices and method of forming the same |
US5384473A (en) * | 1991-10-01 | 1995-01-24 | Kabushiki Kaisha Toshiba | Semiconductor body having element formation surfaces with different orientations |
US6172381B1 (en) * | 1997-06-20 | 2001-01-09 | Advanced Micro Devices, Inc. | Source/drain junction areas self aligned between a sidewall spacer and an etched lateral sidewall |
US6774390B2 (en) * | 2002-02-22 | 2004-08-10 | Kabushiki Kaisha Toshiba | Semiconductor device |
US20040195646A1 (en) * | 2003-04-04 | 2004-10-07 | Yee-Chia Yeo | Silicon-on-insulator chip with multiple crystal orientations |
US6815278B1 (en) * | 2003-08-25 | 2004-11-09 | International Business Machines Corporation | Ultra-thin silicon-on-insulator and strained-silicon-direct-on-insulator with hybrid crystal orientations |
Cited By (304)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080032486A1 (en) * | 2002-09-30 | 2008-02-07 | Renesas Technology Corp. | Semiconductor wafer and manufacturing method thereof |
US20060006423A1 (en) * | 2002-09-30 | 2006-01-12 | Renesas Technology Corpo. | Semiconductor wafer and manufacturing method thereof |
US7291542B2 (en) * | 2002-09-30 | 2007-11-06 | Renesas Technology Corp. | Semiconductor wafer and manufacturing method thereof |
US20080032487A1 (en) * | 2002-09-30 | 2008-02-07 | Renesas Technology Corp. | Semiconductor wafer and manufacturing method thereof |
US7785939B2 (en) | 2003-12-02 | 2010-08-31 | International Business Machines Corporation | Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers |
US20050280121A1 (en) * | 2004-06-21 | 2005-12-22 | International Business Machines Corporation | Hybrid substrate technology for high-mobility planar and multiple-gate MOSFETs |
CN101310386B (en) * | 2004-06-21 | 2013-03-06 | 微软公司 | Hybrid substrate technology for high-mobility planar and multiple-gate mosfets |
US7291886B2 (en) * | 2004-06-21 | 2007-11-06 | International Business Machines Corporation | Hybrid substrate technology for high-mobility planar and multiple-gate MOSFETs |
US20080020521A1 (en) * | 2004-06-21 | 2008-01-24 | International Business Machines Corporation | Hybrid substrate technology for high-mobility planar and multiple-gate mosfets |
US7485506B2 (en) * | 2004-06-21 | 2009-02-03 | International Business Machines Corporation | Hybrid substrate technology for high-mobility planar and multiple-gate MOSFETS |
US7253034B2 (en) | 2004-07-29 | 2007-08-07 | International Business Machines Corporation | Dual SIMOX hybrid orientation technology (HOT) substrates |
US20060024931A1 (en) * | 2004-07-29 | 2006-02-02 | International Business Machines Corporation | Dual SIMOX hybrid orientation technology (HOT) substrates |
US7354806B2 (en) * | 2004-09-17 | 2008-04-08 | International Business Machines Corporation | Semiconductor device structure with active regions having different surface directions and methods |
US20060060925A1 (en) * | 2004-09-17 | 2006-03-23 | International Business Machines Corporation | Semiconductor device structure with active regions having different surface directions and methods |
US7381624B2 (en) * | 2004-11-30 | 2008-06-03 | Advanced Micro Devices, Inc. | Technique for forming a substrate having crystalline semiconductor regions of different characteristics located above a crystalline bulk substrate |
US20060113629A1 (en) * | 2004-11-30 | 2006-06-01 | Andy Wei | Technique for forming a substrate having crystalline semiconductor regions of different characteristics located above a crystalline bulk substrate |
US20150206971A1 (en) * | 2004-12-01 | 2015-07-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid Fin Field-Effect Transistor Structures and Related Methods |
US9293582B2 (en) * | 2004-12-01 | 2016-03-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid fin field-effect transistor structures and related methods |
US20060118918A1 (en) * | 2004-12-08 | 2006-06-08 | Advanced Micro Devices, Inc. | Semiconductor device and method of making semiconductor device comprising multiple stacked hybrid orientation layers |
US7422956B2 (en) * | 2004-12-08 | 2008-09-09 | Advanced Micro Devices, Inc. | Semiconductor device and method of making semiconductor device comprising multiple stacked hybrid orientation layers |
US8053330B2 (en) | 2005-01-07 | 2011-11-08 | International Business Machines Corporation | Quasi-hydrophobic Si-Si wafer bonding using hydrophilic Si surfaces and dissolution of interfacial bonding oxide |
US7550369B2 (en) | 2005-01-07 | 2009-06-23 | International Business Machines Corporation | Method for fabricating low-defect-density changed orientation Si |
US20060154429A1 (en) * | 2005-01-07 | 2006-07-13 | International Business Machines Corporation | Method for fabricating low-defect-density changed orientation Si |
US7285473B2 (en) | 2005-01-07 | 2007-10-23 | International Business Machines Corporation | Method for fabricating low-defect-density changed orientation Si |
US20080057684A1 (en) * | 2005-01-07 | 2008-03-06 | International Business Machines Corporation | METHOD FOR FABRICATING LOW-DEFECT-DENSITY CHANGED ORIENTATION Si |
US20090298258A1 (en) * | 2005-01-07 | 2009-12-03 | International Business Machines Corporation | QUASI-HYDROPHOBIC Si-Si WAFER BONDING USING HYDROPHILIC Si SURFACES AND DISSOLUTION OF INTERFACIAL BONDING OXIDE |
US8138061B2 (en) | 2005-01-07 | 2012-03-20 | International Business Machines Corporation | Quasi-hydrophobic Si-Si wafer bonding using hydrophilic Si surfaces and dissolution of interfacial bonding oxide |
US20080248615A1 (en) * | 2005-02-07 | 2008-10-09 | International Business Machines Corporation | Cmos structure for body ties in ultra-thin soi (utsoi) substrates |
US20060175659A1 (en) * | 2005-02-07 | 2006-08-10 | International Business Machines Corporation | A cmos structure for body ties in ultra-thin soi (utsoi) substrates |
US7687365B2 (en) | 2005-02-07 | 2010-03-30 | International Business Machines Corporation | CMOS structure for body ties in ultra-thin SOI (UTSOI) substrates |
US7547917B2 (en) | 2005-04-06 | 2009-06-16 | International Business Machines Corporation | Inverted multilayer semiconductor device assembly |
US20060226491A1 (en) * | 2005-04-06 | 2006-10-12 | International Business Machines Corporation | Inverted multilayer semiconductor device assembly |
US7250351B2 (en) * | 2005-04-14 | 2007-07-31 | International Business Machines Corporation | Enhanced silicon-on-insulator (SOI) transistors and methods of making enhanced SOI transistors |
US20060231892A1 (en) * | 2005-04-14 | 2006-10-19 | International Business Machines Corporation | Enhanced silicon-on-insulator (SOI) transistors and methods of making enhanced SOI transistors |
WO2006130360A2 (en) | 2005-06-01 | 2006-12-07 | International Business Machines Corporation | Improved amorphization/templated recrystallization method for hybrid orientation substrates |
US7960263B2 (en) | 2005-06-01 | 2011-06-14 | International Business Machines Corporation | Amorphization/templated recrystallization method for hybrid orientation substrates |
US7291539B2 (en) * | 2005-06-01 | 2007-11-06 | International Business Machines Corporation | Amorphization/templated recrystallization method for hybrid orientation substrates |
WO2006130360A3 (en) * | 2005-06-01 | 2007-06-14 | Ibm | Improved amorphization/templated recrystallization method for hybrid orientation substrates |
US7547616B2 (en) | 2005-06-01 | 2009-06-16 | International Business Machines Corporation | Laser processing method for trench-edge-defect-free solid phase epitaxy in confined geometrics |
EP1886342A4 (en) * | 2005-06-01 | 2011-06-15 | Ibm | Improved amorphization/templated recrystallization method for hybrid orientation substrates |
US20060275971A1 (en) * | 2005-06-01 | 2006-12-07 | International Business Machines Corporation | Laser processing method for trench-edge-defect-free solid phase epitaxy in confined geometrics |
US20060276011A1 (en) * | 2005-06-01 | 2006-12-07 | International Business Machines Corporation | Amorphization/templated recrystallization method for hybrid orientation substrates |
US7691733B2 (en) | 2005-06-01 | 2010-04-06 | International Business Machines Corporation | Laser processing method for trench-edge-defect-free solid phase epitaxy in confined geometrics |
EP1886342A2 (en) * | 2005-06-01 | 2008-02-13 | International Business Machines Corporation | Improved amorphization/templated recrystallization method for hybrid orientation substrates |
US20080108204A1 (en) * | 2005-06-01 | 2008-05-08 | International Business Machines Corporation | Amorphization/templated recrystallization method for hybrid orientation substrates |
US20080286917A1 (en) * | 2005-06-01 | 2008-11-20 | International Business Machines Corporation | Laser processing method for trench-edge-defect-free solid phase epitaxy in confined geometrics |
US20100203708A1 (en) * | 2005-06-01 | 2010-08-12 | International Business Machines Corporation | Amorphization/templated recrystallization method for hybrid orientation substrates |
US7704852B2 (en) | 2005-06-01 | 2010-04-27 | International Business Machines Corporation | Amorphization/templated recrystallization method for hybrid orientation substrates |
US20080048286A1 (en) * | 2005-06-16 | 2008-02-28 | Hsu Louis L | Coplanar silicon-on-insulator (soi) regions of different crystal orientations and methods of making the same |
US20080283920A1 (en) * | 2005-06-16 | 2008-11-20 | International Business Machines Corporation | Hybrid oriented substrates and crystal imprinting methods for forming such hybrid oriented substrates |
US7651929B2 (en) | 2005-06-16 | 2010-01-26 | International Business Machines Corporation | Hybrid oriented substrates and crystal imprinting methods for forming such hybrid oriented substrates |
US7525121B2 (en) | 2005-06-16 | 2009-04-28 | International Business Machines Corporation | Coplanar silicon-on-insulator (SOI) regions of different crystal orientations and methods of making the same |
US7875960B2 (en) | 2005-06-16 | 2011-01-25 | International Business Machines Corporation | Hybrid oriented substrates and crystal imprinting methods for forming such hybrid oriented substrates |
US20080050890A1 (en) * | 2005-06-16 | 2008-02-28 | International Business Machines Corporation | Hybrid oriented substrates and crystal imprinting methods for forming such hybrid oriented substrates |
US7803700B2 (en) | 2005-06-16 | 2010-09-28 | International Business Machines Corporation | Crystal imprinting methods for fabricating substrates with thin active silicon layers |
US20080146006A1 (en) * | 2005-06-16 | 2008-06-19 | International Business Machines Corporation | Crystal imprinting methods for fabricating substrates with thin active silicon layers |
US7799609B2 (en) | 2005-06-21 | 2010-09-21 | International Business Machines Corporation | Method of manufacturing dual orientation wafers |
US7344962B2 (en) * | 2005-06-21 | 2008-03-18 | International Business Machines Corporation | Method of manufacturing dual orientation wafers |
US20060286778A1 (en) * | 2005-06-21 | 2006-12-21 | International Business Machines Corporation | Method of manufacturing dual orientation wafers |
US20080096370A1 (en) * | 2005-06-21 | 2008-04-24 | International Business Machines Corporation | Method of manufacturing dual orientation wafers |
US20070145373A1 (en) * | 2005-07-15 | 2007-06-28 | International Business Machines Corporation | Epitaxial imprinting |
CN100466267C (en) * | 2005-07-15 | 2009-03-04 | 国际商业机器公司 | Semiconductor structure and its production method |
US7732865B2 (en) * | 2005-07-15 | 2010-06-08 | International Business Machines Corporation | Epitaxial imprinting |
WO2007020287A1 (en) * | 2005-08-19 | 2007-02-22 | International Business Machines Corporation | Dual trench isolation for cmos with hybrid orientations |
GB2445511B (en) * | 2005-10-31 | 2009-04-08 | Advanced Micro Devices Inc | An embedded strain layer in thin soi transistors and a method of forming the same |
WO2007053382A1 (en) * | 2005-10-31 | 2007-05-10 | Advanced Micro Devices, Inc. | An embedded strain layer in thin soi transistors and a method of forming the same |
US7399663B2 (en) | 2005-10-31 | 2008-07-15 | Advanced Micro Devices, Inc. | Embedded strain layer in thin SOI transistors and a method of forming the same |
US20070096148A1 (en) * | 2005-10-31 | 2007-05-03 | Jan Hoentschel | Embedded strain layer in thin soi transistors and a method of forming the same |
GB2445511A (en) * | 2005-10-31 | 2008-07-09 | Advanced Micro Devices Inc | An embedded strain layer in thin soi transistors and a method of forming the same |
KR101290819B1 (en) | 2005-10-31 | 2013-07-30 | 글로벌파운드리즈 인크. | An embedded strain layer in thin soi transistor and a method of forming the same |
US20090242935A1 (en) * | 2005-11-01 | 2009-10-01 | Massachusetts Institute Of Technology | Monolithically integrated photodetectors |
US20070105335A1 (en) * | 2005-11-01 | 2007-05-10 | Massachusetts Institute Of Technology | Monolithically integrated silicon and III-V electronics |
US20070105274A1 (en) * | 2005-11-01 | 2007-05-10 | Massachusetts Institute Of Technology | Monolithically integrated semiconductor materials and devices |
US8012592B2 (en) | 2005-11-01 | 2011-09-06 | Massachuesetts Institute Of Technology | Monolithically integrated semiconductor materials and devices |
US8120060B2 (en) * | 2005-11-01 | 2012-02-21 | Massachusetts Institute Of Technology | Monolithically integrated silicon and III-V electronics |
US7705370B2 (en) | 2005-11-01 | 2010-04-27 | Massachusetts Institute Of Technology | Monolithically integrated photodetectors |
US7986029B2 (en) * | 2005-11-08 | 2011-07-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dual SOI structure |
US20070102769A1 (en) * | 2005-11-08 | 2007-05-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dual SOI structure |
TWI402943B (en) * | 2005-12-14 | 2013-07-21 | Freescale Semiconductor Inc | Soi active layer with different surface orientation |
US20070138563A1 (en) * | 2005-12-16 | 2007-06-21 | International Business Machines Corporation | Dual metal gate self-aligned integration |
US20090283830A1 (en) * | 2005-12-16 | 2009-11-19 | International Business Machines Corporation | Dual metal gate self-aligned integration |
US7872317B2 (en) | 2005-12-16 | 2011-01-18 | International Business Machines Corporation | Dual metal gate self-aligned integration |
US7569466B2 (en) | 2005-12-16 | 2009-08-04 | International Business Machines Corporation | Dual metal gate self-aligned integration |
US7436034B2 (en) | 2005-12-19 | 2008-10-14 | International Business Machines Corporation | Metal oxynitride as a pFET material |
US7776701B2 (en) | 2005-12-19 | 2010-08-17 | International Business Machines Corporation | Metal oxynitride as a pFET material |
US20070138578A1 (en) * | 2005-12-19 | 2007-06-21 | International Business Machines Corporation | Metal oxynitride as a pFET material |
US20080299730A1 (en) * | 2005-12-19 | 2008-12-04 | International Business Machines Corporation | METAL OXYNITRIDE AS A pFET MATERIAL |
DE102006060886B4 (en) * | 2005-12-22 | 2017-05-24 | Infineon Technologies Ag | SOI arrangement with multiple crystal orientations and associated SOI device and related manufacturing methods |
US10217812B2 (en) * | 2005-12-22 | 2019-02-26 | Infineon Technologies Ag | Silicon-on-insulator chip having multiple crystal orientations |
US20070145481A1 (en) * | 2005-12-22 | 2007-06-28 | Armin Tilke | Silicon-on-insulator chip having multiple crystal orientations |
US8319285B2 (en) | 2005-12-22 | 2012-11-27 | Infineon Technologies Ag | Silicon-on-insulator chip having multiple crystal orientations |
US20130082350A1 (en) * | 2005-12-22 | 2013-04-04 | Infineon Technologies Ag | Silicon-on-insulator chip having multiple crystal orientations |
US8530355B2 (en) | 2005-12-23 | 2013-09-10 | Infineon Technologies Ag | Mixed orientation semiconductor device and method |
DE102006060887B4 (en) * | 2005-12-23 | 2009-10-01 | Infineon Technologies Ag | Method for producing a mixed orientation semiconductor device |
US20070148921A1 (en) * | 2005-12-23 | 2007-06-28 | Jiang Yan | Mixed orientation semiconductor device and method |
US9607986B2 (en) | 2005-12-23 | 2017-03-28 | Infineon Technologies Ag | Mixed orientation semiconductor device and method |
US7666732B2 (en) | 2005-12-28 | 2010-02-23 | International Business Machines Corporation | Method of fabricating a metal gate CMOS with at least a single gate metal and dual gate dielectrics |
US7709902B2 (en) | 2005-12-28 | 2010-05-04 | International Business Machines Corporation | Metal gate CMOS with at least a single gate metal and dual gate dielectrics |
US20090008720A1 (en) * | 2005-12-28 | 2009-01-08 | International Business Machines Corporation | Metal gate cmos with at least a single gate metal and dual gate dielectrics |
US20070148838A1 (en) * | 2005-12-28 | 2007-06-28 | International Business Machines Corporation | Metal gate CMOS with at least a single gate metal and dual gate dielectrics |
US8569844B2 (en) | 2005-12-28 | 2013-10-29 | International Business Machines Corporation | Metal gate CMOS with at least a single gate metal and dual gate dielectrics |
US20090008719A1 (en) * | 2005-12-28 | 2009-01-08 | International Business Machines Corporation | Metal gate cmos with at least a single gate metal and dual gate dielectrics |
US7432567B2 (en) | 2005-12-28 | 2008-10-07 | International Business Machines Corporation | Metal gate CMOS with at least a single gate metal and dual gate dielectrics |
US7833849B2 (en) | 2005-12-30 | 2010-11-16 | International Business Machines Corporation | Method of fabricating a semiconductor structure including one device region having a metal gate electrode located atop a thinned polygate electrode |
US7750418B2 (en) | 2006-01-20 | 2010-07-06 | International Business Machines Corporation | Introduction of metal impurity to change workfunction of conductive electrodes |
US20070173008A1 (en) * | 2006-01-20 | 2007-07-26 | International Business Machines Corporation | Introduction of metal impurity to change workfunction of conductive electrodes |
WO2007087127A2 (en) | 2006-01-20 | 2007-08-02 | International Business Machines Corporation | Introduction of metal impurity to change workfunction of conductive electrodes |
US7425497B2 (en) | 2006-01-20 | 2008-09-16 | International Business Machines Corporation | Introduction of metal impurity to change workfunction of conductive electrodes |
US20070190745A1 (en) * | 2006-02-10 | 2007-08-16 | Sadaka Mariam G | Method to selectively form regions having differing properties and structure |
US7285452B2 (en) * | 2006-02-10 | 2007-10-23 | Sadaka Mariam G | Method to selectively form regions having differing properties and structure |
US7531392B2 (en) * | 2006-02-27 | 2009-05-12 | International Business Machines Corporation | Multi-orientation semiconductor-on-insulator (SOI) substrate, and method of fabricating same |
US20070202635A1 (en) * | 2006-02-27 | 2007-08-30 | Ellis-Monaghan John J | Multi-orientation semiconductor-on-insulator (soi) substrate, and method of fabricating same |
US20100155788A1 (en) * | 2006-03-15 | 2010-06-24 | Shaheen Mohamad A | Formation of a multiple crystal orientation substrate |
US7999319B2 (en) * | 2006-04-18 | 2011-08-16 | International Business Machines Corporation | Trench-edge-defect-free recrystallization by edge-angle-optimized solid phase epitaxy: method and applications to hybrid orientation substrates |
US20080224182A1 (en) * | 2006-04-18 | 2008-09-18 | International Business Machines Corporation | Trench-edge-defect-free recrystallization by edge-angle-optimized solid phase epitaxy: method and applications to hybrid orientation substrates |
US8268698B2 (en) | 2006-05-25 | 2012-09-18 | International Business Machines Corporation | Formation of improved SOI substrates using bulk semiconductor wafers |
US20090039461A1 (en) * | 2006-05-25 | 2009-02-12 | International Business Machines Corporation | Formation of improved soi substrates using bulk semiconductor wafers |
US7932158B2 (en) | 2006-05-25 | 2011-04-26 | International Business Machines Corporation | Formation of improved SOI substrates using bulk semiconductor wafers |
US20070275537A1 (en) * | 2006-05-25 | 2007-11-29 | International Business Machines Corporation | Formation of improved soi substrates using bulk semiconductor wafers |
US7452784B2 (en) * | 2006-05-25 | 2008-11-18 | International Business Machines Corporation | Formation of improved SOI substrates using bulk semiconductor wafers |
US20070281446A1 (en) * | 2006-05-31 | 2007-12-06 | Winstead Brian A | Dual surface SOI by lateral epitaxial overgrowth |
US7435639B2 (en) | 2006-05-31 | 2008-10-14 | Freescale Semiconductor, Inc. | Dual surface SOI by lateral epitaxial overgrowth |
US20080048269A1 (en) * | 2006-08-25 | 2008-02-28 | International Business Machines Corporation | Method of fabricating structure for integrated circuit incorporating hybrid orientation technology and trench isolation regions |
US8237247B2 (en) | 2006-09-07 | 2012-08-07 | International Business Machines Corporation | CMOS devices incorporating hybrid orientation technology (HOT) with embedded connectors |
US20090321794A1 (en) * | 2006-09-07 | 2009-12-31 | International Business Machines Corporation | Cmos devices incorporating hybrid orientation technology (hot) with embedded connectors |
US8513779B2 (en) | 2006-09-07 | 2013-08-20 | International Business Machines Corporation | CMOS devices incorporating hybrid orientation technology (HOT) with embedded connectors |
US7595232B2 (en) | 2006-09-07 | 2009-09-29 | International Business Machines Corporation | CMOS devices incorporating hybrid orientation technology (HOT) with embedded connectors |
US20080064160A1 (en) * | 2006-09-07 | 2008-03-13 | International Business Machines Corporation | Cmos devices incorporating hybrid orientation technology (hot) with embedded connectors |
US20100283089A1 (en) * | 2006-10-11 | 2010-11-11 | International Business Machines Corporation | Method of reducing stacking faults through annealing |
US7956417B2 (en) | 2006-10-11 | 2011-06-07 | International Business Machines Corporation | Method of reducing stacking faults through annealing |
US20080087961A1 (en) * | 2006-10-11 | 2008-04-17 | International Business Machines Corporation | Method of reducing stacking faults through annealing |
US7820501B2 (en) | 2006-10-11 | 2010-10-26 | International Business Machines Corporation | Decoder for a stationary switch machine |
JP2008177529A (en) * | 2006-12-21 | 2008-07-31 | Covalent Materials Corp | Semiconductor substrate and method for manufacturing the same |
US20080164572A1 (en) * | 2006-12-21 | 2008-07-10 | Covalent Materials Corporation | Semiconductor substrate and manufacturing method thereof |
US20080169535A1 (en) * | 2007-01-12 | 2008-07-17 | International Business Machines Corporation | Sub-lithographic faceting for mosfet performance enhancement |
KR101489304B1 (en) * | 2007-02-05 | 2015-02-11 | 삼성전자 주식회사 | Method and Apparatus for Manufacturing a Semiconductor |
US20080188046A1 (en) * | 2007-02-05 | 2008-08-07 | Infineon Technologies North America Corp. | Method and Apparatus For Manufacturing A Semiconductor |
US8016941B2 (en) * | 2007-02-05 | 2011-09-13 | Infineon Technologies Ag | Method and apparatus for manufacturing a semiconductor |
US20080191292A1 (en) * | 2007-02-12 | 2008-08-14 | International Business Machines Corporation | METAL GATES WITH LOW CHARGE TRAPPING AND ENHANCED DIELECTRIC RELIABILITY CHARACTERISTICS FOR HIGH-k GATE DIELECTRIC STACKS |
US20100044805A1 (en) * | 2007-02-12 | 2010-02-25 | International Business Machines Corporation | METAL GATES WITH LOW CHARGE TRAPPING AND ENHANCED DIELECTRIC RELIABILITY CHARACTERISTICS FOR HIGH-k GATE DIELECTRIC STACKS |
US7611979B2 (en) | 2007-02-12 | 2009-11-03 | International Business Machines Corporation | Metal gates with low charge trapping and enhanced dielectric reliability characteristics for high-k gate dielectric stacks |
US20080254604A1 (en) * | 2007-03-11 | 2008-10-16 | Chien-Ting Lin | Method for fabricating a hybrid orientation substrate |
US20080220595A1 (en) * | 2007-03-11 | 2008-09-11 | Chien-Ting Lin | Method for fabricating a hybrid orientation substrate |
US7682932B2 (en) | 2007-03-11 | 2010-03-23 | United Microelectronics Corp. | Method for fabricating a hybrid orientation substrate |
US7608522B2 (en) | 2007-03-11 | 2009-10-27 | United Microelectronics Corp. | Method for fabricating a hybrid orientation substrate |
US20080237809A1 (en) * | 2007-03-29 | 2008-10-02 | United Microelectronics Corp. | Method of fabricating hybrid orientation substrate and structure of the same |
US9034102B2 (en) | 2007-03-29 | 2015-05-19 | United Microelectronics Corp. | Method of fabricating hybrid orientation substrate and structure of the same |
US20080248626A1 (en) * | 2007-04-05 | 2008-10-09 | International Business Machines Corporation | Shallow trench isolation self-aligned to templated recrystallization boundary |
WO2008128897A3 (en) * | 2007-04-20 | 2008-12-11 | Ibm | Hybrid substrates and methods for forming such hybrid substrates |
US7750406B2 (en) | 2007-04-20 | 2010-07-06 | International Business Machines Corporation | Design structure incorporating a hybrid substrate |
US20080258181A1 (en) * | 2007-04-20 | 2008-10-23 | Ethan Harrison Cannon | Hybrid Substrates and Methods for Forming Such Hybrid Substrates |
US20080258222A1 (en) * | 2007-04-20 | 2008-10-23 | International Business Machines Corporation | Design Structure Incorporating a Hybrid Substrate |
US7651902B2 (en) * | 2007-04-20 | 2010-01-26 | International Business Machines Corporation | Hybrid substrates and methods for forming such hybrid substrates |
US7579254B2 (en) | 2007-04-20 | 2009-08-25 | Stmicroelectronics (Crolles 2) Sas | Process for realizing an integrated electronic circuit with two active layer portions having different crystal orientations |
FR2915318A1 (en) * | 2007-04-20 | 2008-10-24 | St Microelectronics Crolles 2 | METHOD OF MAKING AN ELECTRONIC CIRCUIT INTEGRATED WITH TWO PORTIONS OF ACTIVE LAYERS HAVING DIFFERENT CRYSTALLINE ORIENTATIONS |
US20080258254A1 (en) * | 2007-04-20 | 2008-10-23 | Stmicroelectronics (Crolles 2) Sas | Process for realizing an integrated electronic circuit with two active layer portions having different crystal orientations |
US7575968B2 (en) | 2007-04-30 | 2009-08-18 | Freescale Semiconductor, Inc. | Inverse slope isolation and dual surface orientation integration |
US20080268587A1 (en) * | 2007-04-30 | 2008-10-30 | Sadaka Mariam G | Inverse slope isolation and dual surface orientation integration |
US20090212329A1 (en) * | 2007-06-05 | 2009-08-27 | International Business Machines Corporation | Super hybrid soi cmos devices |
US7547641B2 (en) * | 2007-06-05 | 2009-06-16 | International Business Machines Corporation | Super hybrid SOI CMOS devices |
US20080303090A1 (en) * | 2007-06-05 | 2008-12-11 | International Business Machines Corporation | Super hybrid soi cmos devices |
US7619300B2 (en) | 2007-06-05 | 2009-11-17 | International Business Machines Corporation | Super hybrid SOI CMOS devices |
KR101525611B1 (en) * | 2007-06-06 | 2015-06-03 | 꼼미사리아 아 레네르지 아또미끄 에 오 에네르지 알떼르나띠브스 | Method for producing hybrid components |
WO2008148882A2 (en) * | 2007-06-06 | 2008-12-11 | S.O.I.Tec Silicon On Insulator Technologies | Method for producing hybrid components |
US20110163410A1 (en) * | 2007-06-06 | 2011-07-07 | S.O.I.Tec Silicon On Insulator Technologies | Method for producing hybrid components |
US8871607B2 (en) * | 2007-06-06 | 2014-10-28 | S.O.I. Tec Silicon On Insulator Technologies | Method for producing hybrid components |
WO2008148882A3 (en) * | 2007-06-06 | 2009-07-23 | Soitec Silicon On Insulator | Method for producing hybrid components |
FR2917235A1 (en) * | 2007-06-06 | 2008-12-12 | Soitec Silicon On Insulator | METHOD FOR PRODUCING HYBRID COMPONENTS |
FR2913815A1 (en) * | 2007-06-06 | 2008-09-19 | Soitec Silicon On Insulator | Hybrid substrate manufacturing method for telecommunication network, involves forming dielectric/polymer layer on structure, assembling layer with support substrates, and eliminating initial substrate until buried layer is eliminated |
US20110227130A1 (en) * | 2007-06-29 | 2011-09-22 | International Business Machines Corporation | Structures and methods of forming sige and sigec buried layer for soi/sige technology |
US9087925B2 (en) * | 2007-06-29 | 2015-07-21 | International Business Machines Corporation | Si and SiGeC on a buried oxide layer on a substrate |
US20090008725A1 (en) * | 2007-07-03 | 2009-01-08 | International Business Machines Corporation | Method for deposition of an ultra-thin electropositive metal-containing cap layer |
US20090294876A1 (en) * | 2007-07-03 | 2009-12-03 | International Business Machines Corporation | Method for deposition of an ultra-thin electropositive metal-containing cap layer |
US20090017602A1 (en) * | 2007-07-11 | 2009-01-15 | Commissariat A L'energie Atomique | Method for manufacturing a semiconductor-on-insulator substrate for microelectronics and optoelectronics |
EP2015349A1 (en) * | 2007-07-11 | 2009-01-14 | Commissariat A L'energie Atomique | Method of manufacturing a semiconductor-on-insulator substrate for microelectronics and optoelectronics |
FR2918793A1 (en) * | 2007-07-11 | 2009-01-16 | Commissariat Energie Atomique | METHOD OF MANUFACTURING A SEMICONDUCTOR-OVER-INSULATION SUBSTRATE FOR MICROELECTRONICS AND OPTOELECTRONICS. |
US7648893B2 (en) | 2007-07-11 | 2010-01-19 | Commissariat A L'energie Atomique | Method for manufacturing a semiconductor-on-insulator substrate for microelectronics and optoelectronics |
US8803195B2 (en) | 2007-08-02 | 2014-08-12 | Wisconsin Alumni Research Foundation | Nanomembrane structures having mixed crystalline orientations and compositions |
US20090032842A1 (en) * | 2007-08-02 | 2009-02-05 | Lagally Max G | Nanomembrane structures having mixed crystalline orientations and compositions |
US20090093133A1 (en) * | 2007-10-09 | 2009-04-09 | International Business Machines Corporation | Self-assembled sidewall spacer |
US7808020B2 (en) | 2007-10-09 | 2010-10-05 | International Business Machines Corporation | Self-assembled sidewall spacer |
US8105960B2 (en) | 2007-10-09 | 2012-01-31 | International Business Machines Corporation | Self-assembled sidewall spacer |
US20090090939A1 (en) * | 2007-10-09 | 2009-04-09 | International Business Machines Corporation | Self-assembled sidewall spacer |
US8236636B2 (en) | 2007-10-30 | 2012-08-07 | International Business Machines Corporation | Hybrid orientation semiconductor structure with reduced boundary defects and method of forming same |
US20090108301A1 (en) * | 2007-10-30 | 2009-04-30 | International Business Machines Corporation | Hybrid orientation semiconductor structure with reduced boundary defects and method of forming same |
US7863712B2 (en) * | 2007-10-30 | 2011-01-04 | International Business Machines Corporation | Hybrid orientation semiconductor structure with reduced boundary defects and method of forming same |
US20110086473A1 (en) * | 2007-10-30 | 2011-04-14 | International Business Machines Corporation | Hybrid orientation semiconductor structure with reduced boundary defects and method of forming same |
WO2009056471A1 (en) * | 2007-10-30 | 2009-05-07 | International Business Machines Corporation | Hybrid orientation semiconductor structure with reduced boundary defects and method of forming same |
US7993990B2 (en) | 2007-10-31 | 2011-08-09 | International Business Machines Corporation | Multiple crystallographic orientation semiconductor structures |
US7696573B2 (en) | 2007-10-31 | 2010-04-13 | International Business Machines Corporation | Multiple crystallographic orientation semiconductor structures |
US20100197118A1 (en) * | 2007-10-31 | 2010-08-05 | International Business Machines Corporation | Multiple crystallographic orientation semiconductor structures |
US20090108302A1 (en) * | 2007-10-31 | 2009-04-30 | International Business Machines Corporation | Multiple crystallographic orientation semiconductor structures |
US8043947B2 (en) | 2007-11-16 | 2011-10-25 | Texas Instruments Incorporated | Method to eliminate re-crystallization border defects generated during solid phase epitaxy of a DSB substrate |
US20090130817A1 (en) * | 2007-11-16 | 2009-05-21 | Angelo Pinto | Method to eliminate re-crystallization border defects generated during solid phase epitaxy of a dsb substrate |
TWI450339B (en) * | 2007-11-30 | 2014-08-21 | Advanced Micro Devices Inc | A hetero-structured, inverted-t field effect transistor |
US8288756B2 (en) * | 2007-11-30 | 2012-10-16 | Advanced Micro Devices, Inc. | Hetero-structured, inverted-T field effect transistor |
US20090140294A1 (en) * | 2007-11-30 | 2009-06-04 | Hemant Adhikari | hetero-structured, inverted-t field effect transistor |
US20110129983A1 (en) * | 2008-01-28 | 2011-06-02 | Nxp B.V. | Method for fabricating a dual-orientation group-iv semiconductor substrate |
US8394704B2 (en) * | 2008-01-28 | 2013-03-12 | Nxp B.V. | Method for fabricating a dual-orientation group-IV semiconductor substrate |
WO2009128776A1 (en) * | 2008-04-15 | 2009-10-22 | Vallin Oerjan | Hybrid wafers with hybrid-oriented layer |
US8241970B2 (en) | 2008-08-25 | 2012-08-14 | International Business Machines Corporation | CMOS with channel P-FinFET and channel N-FinFET having different crystalline orientations and parallel fins |
US8723233B2 (en) | 2008-08-25 | 2014-05-13 | International Business Machines Corporation | CMOS with channel P-FinFET and channel N-FinFET having different crystalline orientations and parallel fins |
US8574969B2 (en) | 2008-08-25 | 2013-11-05 | International Business Machines Corporation | CMOS with channel P-FinFET and channel N-FinFET having different crystalline orientations and parallel fins |
US8563369B2 (en) | 2008-08-25 | 2013-10-22 | International Business Machines Corporation | CMOS with channel P-FinFET and channel N-FinFET having different crystalline orientations and parallel fins |
US20100044758A1 (en) * | 2008-08-25 | 2010-02-25 | International Business Machines Corporation | Cmos with channel p-finfet and channel n-finfet having different crystalline orientations and parallel fins |
US8722470B2 (en) | 2008-08-25 | 2014-05-13 | International Business Machines Corporation | CMOS with channel p-FinFET and channel n-FinFET having different crystalline orientations and parallel fins |
US20100068643A1 (en) * | 2008-09-17 | 2010-03-18 | Fuji Xerox Co., Ltd. | Electrostatic-image-developing toner, process for producing electrostatic-image-developing toner, electrostatic image developer, and image-forming apparatus |
FR2938117A1 (en) * | 2008-10-31 | 2010-05-07 | Commissariat Energie Atomique | METHOD FOR PRODUCING A HYBRID SUBSTRATE HAVING AN ELECTRICALLY INSULATING CONTINUOUS LAYER BURIED |
WO2010049654A1 (en) * | 2008-10-31 | 2010-05-06 | Commissariat A L'energie Atomique | Method for producing a hybrid substrate with an embedded electrically insulating continuous layer |
US20110207293A1 (en) * | 2008-10-31 | 2011-08-25 | Thomas Signamarcheix | Method of producing a hybrid substrate having a continuous buried eectrically insulating layer |
US8318555B2 (en) | 2008-10-31 | 2012-11-27 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Method of producing a hybrid substrate having a continuous buried electrically insulating layer |
EP2224476A1 (en) * | 2009-02-27 | 2010-09-01 | Commissariat à l'Énergie Atomique et aux Énergies Alternatives | Method for manufacturing a hybrid substrate by partial re-crystallisation of a mixed layer |
US20100221891A1 (en) * | 2009-02-27 | 2010-09-02 | Franck Fournel | Method of producing a hybrid substrate by partial recrystallization of a mixed layer |
US8841202B2 (en) | 2009-02-27 | 2014-09-23 | Commissariat A L'energie Atomique | Method of producing a hybrid substrate by partial recrystallization of a mixed layer |
FR2942674A1 (en) * | 2009-02-27 | 2010-09-03 | Commissariat Energie Atomique | PROCESS FOR PRODUCING A HYBRID SUBSTRATE BY PARTIAL RECRYSTALLIZATION OF A MIXED LAYER |
US20100330810A1 (en) * | 2009-06-24 | 2010-12-30 | International Business Machines Corporation | Method for removing threshold voltage adjusting layer with external acid diffusion process |
US8227307B2 (en) | 2009-06-24 | 2012-07-24 | International Business Machines Corporation | Method for removing threshold voltage adjusting layer with external acid diffusion process |
US20110042751A1 (en) * | 2009-08-18 | 2011-02-24 | International Business Machines Corporation | Thermal dual gate oxide device integration |
US8105892B2 (en) | 2009-08-18 | 2012-01-31 | International Business Machines Corporation | Thermal dual gate oxide device integration |
US20110068396A1 (en) * | 2009-09-24 | 2011-03-24 | International Business Machines Corporation | METHOD AND STRUCTURE FOR FORMING HIGH-PERFOMANCE FETs WITH EMBEDDED STRESSORS |
DE112010002895T5 (en) | 2009-09-24 | 2012-06-21 | International Business Machines Corporation | Method and structure for forming high performance FETs with embedded stressors |
US8022488B2 (en) | 2009-09-24 | 2011-09-20 | International Business Machines Corporation | High-performance FETs with embedded stressors |
US7943458B2 (en) | 2009-10-06 | 2011-05-17 | International Business Machines Corporation | Methods for obtaining gate stacks with tunable threshold voltage and scaling |
US20110081754A1 (en) * | 2009-10-06 | 2011-04-07 | International Business Machines Corporation | Methods for obtaining gate stacks with tunable threshold voltage and scaling |
US20110089495A1 (en) * | 2009-10-20 | 2011-04-21 | International Business Machines Corporation | Application of cluster beam implantation for fabricating threshold voltage adjusted fets |
US8288222B2 (en) | 2009-10-20 | 2012-10-16 | International Business Machines Corporation | Application of cluster beam implantation for fabricating threshold voltage adjusted FETs |
US8492848B2 (en) | 2009-10-20 | 2013-07-23 | International Business Machines Corporation | Application of cluster beam implantation for fabricating threshold voltage adjusted FETs |
US8557652B2 (en) | 2009-10-20 | 2013-10-15 | International Business Machines Corporation | Application of cluster beam implantation for fabricating threshold voltage adjusted FETs |
WO2011051109A1 (en) | 2009-10-28 | 2011-05-05 | International Business Machines Corporation | BI-LAYER nFET EMBEDDED STRESSOR ELEMENT AND INTEGRATION TO ENHANCE DRIVE CURRENT |
US20110147881A1 (en) * | 2009-12-22 | 2011-06-23 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Hybrid substrate with improved isolation and simplified method for producing a hybrid substrate |
EP2339616A1 (en) * | 2009-12-22 | 2011-06-29 | Commissariat à l'Énergie Atomique et aux Énergies Alternatives | Hybrid substrate with improved insulation and method for simplified production of a hybrid substrate |
US8936993B2 (en) | 2009-12-22 | 2015-01-20 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Hybrid substrate with improved isolation and simplified method for producing a hybrid substrate |
FR2954584A1 (en) * | 2009-12-22 | 2011-06-24 | Commissariat Energie Atomique | HYBRID SUBSTRATE WITH IMPROVED INSULATION AND METHOD FOR SIMPLIFIED REALIZATION OF A HYBRID SUBSTRATE |
EP4047642A1 (en) * | 2009-12-22 | 2022-08-24 | Commissariat à l'Energie Atomique et aux Energies Alternatives | Hybrid substrate with improved insulation |
US8629022B2 (en) | 2010-01-07 | 2014-01-14 | International Business Machines Corporation | Asymmetric FET including sloped threshold voltage adjusting material layer and method of fabricating same |
US20110163385A1 (en) * | 2010-01-07 | 2011-07-07 | International Business Machines Corporation | Asymmetric fet including sloped threshold voltage adjusting material layer and method of fabricating same |
US8445974B2 (en) | 2010-01-07 | 2013-05-21 | International Business Machines Corporation | Asymmetric FET including sloped threshold voltage adjusting material layer and method of fabricating same |
US8299530B2 (en) | 2010-03-04 | 2012-10-30 | International Business Machines Corporation | Structure and method to fabricate pFETS with superior GIDL by localizing workfunction |
US20110221003A1 (en) * | 2010-03-09 | 2011-09-15 | International Business Machines Corporation | MOSFETs WITH REDUCED CONTACT RESISTANCE |
US8450807B2 (en) | 2010-03-09 | 2013-05-28 | International Business Machines Corporation | MOSFETs with reduced contact resistance |
US9356119B2 (en) | 2010-03-09 | 2016-05-31 | Globalfoundries Inc. | MOSFETs with reduced contact resistance |
US8735265B2 (en) | 2010-04-09 | 2014-05-27 | Samsung Electronics Co., Ltd. | Methods of selectively forming silicon-on-insulator structures using selective expitaxial growth process |
DE112011101433T5 (en) | 2010-04-21 | 2013-03-28 | International Business Machines Corporation | Embedded dopant monolayer stressor for advanced CMOS semiconductors |
US8421191B2 (en) | 2010-04-21 | 2013-04-16 | International Business Machines Corporation | Monolayer dopant embedded stressor for advanced CMOS |
US8236660B2 (en) | 2010-04-21 | 2012-08-07 | International Business Machines Corporation | Monolayer dopant embedded stressor for advanced CMOS |
DE112011101433B4 (en) * | 2010-04-21 | 2019-01-24 | Globalfoundries Inc. | Embedded dopant monolayer stressor for advanced CMOS semiconductors |
DE112011101378B4 (en) | 2010-06-25 | 2018-12-27 | Globalfoundries Inc. | Epitaxy of delta monolayer dopants for embedded source / drain silicide |
US8299535B2 (en) | 2010-06-25 | 2012-10-30 | International Business Machines Corporation | Delta monolayer dopants epitaxy for embedded source/drain silicide |
US8361889B2 (en) | 2010-07-06 | 2013-01-29 | International Business Machines Corporation | Strained semiconductor-on-insulator by addition and removal of atoms in a semiconductor-on-insulator |
US8962417B2 (en) | 2010-10-15 | 2015-02-24 | International Business Machines Corporation | Method and structure for pFET junction profile with SiGe channel |
US8659054B2 (en) | 2010-10-15 | 2014-02-25 | International Business Machines Corporation | Method and structure for pFET junction profile with SiGe channel |
US8466473B2 (en) | 2010-12-06 | 2013-06-18 | International Business Machines Corporation | Structure and method for Vt tuning and short channel control with high k/metal gate MOSFETs |
WO2012078225A1 (en) | 2010-12-06 | 2012-06-14 | International Business Machines Corporation | STRUCTURE AND METHOD FOR Vt TUNING AND SHORT CHANNEL CONTROL WITH HIGH K/METAL GATE MOSFETs |
US8765591B2 (en) | 2010-12-07 | 2014-07-01 | United Microelectronics Corp. | Semiconductor device having metal gate and manufacturing method thereof |
US8564063B2 (en) | 2010-12-07 | 2013-10-22 | United Microelectronics Corp. | Semiconductor device having metal gate and manufacturing method thereof |
US8536656B2 (en) | 2011-01-10 | 2013-09-17 | International Business Machines Corporation | Self-aligned contacts for high k/metal gate process flow |
US9059134B2 (en) | 2011-01-10 | 2015-06-16 | International Business Machines Corporation | Self-aligned contacts for high k/metal gate process flow |
US9006837B2 (en) | 2011-01-14 | 2015-04-14 | International Business Machines Corporation | Structure and method of Tinv scaling for high k metal gate technology |
US8643115B2 (en) | 2011-01-14 | 2014-02-04 | International Business Machines Corporation | Structure and method of Tinv scaling for high κ metal gate technology |
US9087784B2 (en) | 2011-01-14 | 2015-07-21 | International Business Machines Corporation | Structure and method of Tinv scaling for high k metal gate technology |
US8432002B2 (en) * | 2011-06-28 | 2013-04-30 | International Business Machines Corporation | Method and structure for low resistive source and drain regions in a replacement metal gate process flow |
US20130001706A1 (en) * | 2011-06-28 | 2013-01-03 | International Business Machines Corporation | Method and Structure for Low Resistive Source and Drain Regions in a Replacement Metal Gate Process Flow |
US9064808B2 (en) * | 2011-07-25 | 2015-06-23 | Synopsys, Inc. | Integrated circuit devices having features with reduced edge curvature and methods for manufacturing the same |
US10256293B2 (en) * | 2011-07-25 | 2019-04-09 | Synopsys, Inc. | Integrated circuit devices having features with reduced edge curvature and methods for manufacturing the same |
TWI555055B (en) * | 2011-07-25 | 2016-10-21 | 希諾皮斯股份有限公司 | Integrated circuit devices having features with reduced edge curvature and methods for manufacturing the same |
US20170373136A1 (en) * | 2011-07-25 | 2017-12-28 | Synopsys, Inc. | Integrated Circuit Devices Having Features With Reduced Edge Curvature and Methods for Manufacturing the Same |
US9786734B2 (en) | 2011-07-25 | 2017-10-10 | Synopsys, Inc. | Integrated circuit devices having features with reduced edge curvature and methods for manufacturing the same |
US8609550B2 (en) | 2011-09-08 | 2013-12-17 | Synopsys, Inc. | Methods for manufacturing integrated circuit devices having features with reduced edge curvature |
US10032859B2 (en) | 2011-09-08 | 2018-07-24 | Synopsys, Inc. | Methods for manufacturing integrated circuit devices having features with reduced edge curvature |
US9379183B2 (en) | 2011-09-08 | 2016-06-28 | Synopsys, Inc. | Methods for manufacturing integrated circuit devices having features with reduced edge curvature |
US9152750B2 (en) | 2011-09-08 | 2015-10-06 | Synopsys, Inc. | Methods for manufacturing integrated circuit devices having features with reduced edge curvature |
US10381478B2 (en) | 2013-03-21 | 2019-08-13 | Stmicroelectronics (Crolles 2) Sas | Method of localized modification of the stresses in a substrate of the SOI type, in particular FD SOI type, and corresponding device |
EP2782119A1 (en) * | 2013-03-21 | 2014-09-24 | STMicroelectronics (Crolles 2) SAS | Method for locally modifying the strains in a SOI substrate, in particular a FD SOI substrate and corresponding device |
FR3003685A1 (en) * | 2013-03-21 | 2014-09-26 | St Microelectronics Crolles 2 | METHOD FOR LOCALLY MODIFYING THE CONSTRAINTS IN A SOI SUBSTRATE, IN PARTICULAR FD SO SO, AND CORRESPONDING DEVICE |
US9653538B2 (en) | 2013-03-21 | 2017-05-16 | Stmicroelectronics (Crolles 2) Sas | Method of localized modification of the stresses in a substrate of the SOI type, in particular FD SOI type, and corresponding device |
US9059095B2 (en) | 2013-04-22 | 2015-06-16 | International Business Machines Corporation | Self-aligned borderless contacts using a photo-patternable dielectric material as a replacement contact |
US9240326B2 (en) | 2013-04-22 | 2016-01-19 | Globalfoundries Inc. | Self-aligned borderless contacts using a photo-patternable dielectric material as a replacement contact |
US8999791B2 (en) | 2013-05-03 | 2015-04-07 | International Business Machines Corporation | Formation of semiconductor structures with variable gate lengths |
US9466567B2 (en) | 2013-09-06 | 2016-10-11 | Globalfoundries Inc. | Nanowire compatible E-fuse |
US9214567B2 (en) | 2013-09-06 | 2015-12-15 | Globalfoundries Inc. | Nanowire compatible E-fuse |
US8951868B1 (en) | 2013-11-05 | 2015-02-10 | International Business Machines Corporation | Formation of functional gate structures with different critical dimensions using a replacement gate process |
CN103745952A (en) * | 2013-12-25 | 2014-04-23 | 上海新傲科技股份有限公司 | Preparation method for mixed crystal substrate with insulation buried layer |
US9595525B2 (en) | 2014-02-10 | 2017-03-14 | International Business Machines Corporation | Semiconductor device including nanowire transistors with hybrid channels |
US9859369B2 (en) | 2014-02-10 | 2018-01-02 | International Business Machines Corporation | Semiconductor device including nanowire transistors with hybrid channels |
US9293554B2 (en) | 2014-02-11 | 2016-03-22 | Globalfoundries Inc. | Self-aligned liner formed on metal semiconductor alloy contacts |
US9093425B1 (en) | 2014-02-11 | 2015-07-28 | International Business Machines Corporation | Self-aligned liner formed on metal semiconductor alloy contacts |
US9184290B2 (en) | 2014-04-02 | 2015-11-10 | International Business Machines Corporation | Method of forming well-controlled extension profile in MOSFET by silicon germanium based sacrificial layer |
US9293375B2 (en) | 2014-04-24 | 2016-03-22 | International Business Machines Corporation | Selectively grown self-aligned fins for deep isolation integration |
US10312259B2 (en) | 2014-04-29 | 2019-06-04 | International Business Machines Corporation | Channel SiGe devices with multiple threshold voltages on hybrid oriented substrates, and methods of manufacturing same |
US9490161B2 (en) * | 2014-04-29 | 2016-11-08 | International Business Machines Corporation | Channel SiGe devices with multiple threshold voltages on hybrid oriented substrates, and methods of manufacturing same |
US20150311109A1 (en) * | 2014-04-29 | 2015-10-29 | International Business Machines Corporation | CHANNEL SiGe DEVICES WITH MULTIPLE THRESHOLD VOLTAGES ON HYBRID ORIENTED SUBSTRATES, AND METHODS OF MANUFACTURING SAME |
US9362281B2 (en) | 2014-05-02 | 2016-06-07 | International Business Machines Corporation | Group III nitride integration with CMOS technology |
US9660069B2 (en) | 2014-05-02 | 2017-05-23 | International Business Machines Corporation | Group III nitride integration with CMOS technology |
US9564526B2 (en) | 2014-05-02 | 2017-02-07 | International Business Machines Corporation | Group III nitride integration with CMOS technology |
US9331076B2 (en) | 2014-05-02 | 2016-05-03 | International Business Machines Corporation | Group III nitride integration with CMOS technology |
US20180330989A1 (en) * | 2014-07-18 | 2018-11-15 | International Business Machines Corporation | Techniques for Creating a Local Interconnect Using a SOI Wafer |
US10699955B2 (en) * | 2014-07-18 | 2020-06-30 | Elpis Technologies Inc. | Techniques for creating a local interconnect using a SOI wafer |
US9412840B1 (en) | 2015-05-06 | 2016-08-09 | International Business Machines Corporation | Sacrificial layer for replacement metal semiconductor alloy contact formation |
US11401162B2 (en) * | 2017-12-28 | 2022-08-02 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Method for transferring a useful layer into a supporting substrate |
US11139402B2 (en) | 2018-05-14 | 2021-10-05 | Synopsys, Inc. | Crystal orientation engineering to achieve consistent nanowire shapes |
US11011411B2 (en) * | 2019-03-22 | 2021-05-18 | International Business Machines Corporation | Semiconductor wafer having integrated circuits with bottom local interconnects |
US11264458B2 (en) | 2019-05-20 | 2022-03-01 | Synopsys, Inc. | Crystal orientation engineering to achieve consistent nanowire shapes |
US20230067984A1 (en) * | 2021-08-27 | 2023-03-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices and methods of manufacturing thereof |
US11854816B2 (en) * | 2021-08-27 | 2023-12-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices and methods of manufacturing thereof |
Also Published As
Publication number | Publication date |
---|---|
US7785939B2 (en) | 2010-08-31 |
TWI328286B (en) | 2010-08-01 |
KR20060130572A (en) | 2006-12-19 |
CN100505273C (en) | 2009-06-24 |
EP1702350A2 (en) | 2006-09-20 |
WO2005057631A3 (en) | 2007-05-10 |
JP2007535802A (en) | 2007-12-06 |
JP5063114B2 (en) | 2012-10-31 |
KR100961800B1 (en) | 2010-06-08 |
WO2005057631A2 (en) | 2005-06-23 |
TW200529423A (en) | 2005-09-01 |
CN1630087A (en) | 2005-06-22 |
US20080108184A1 (en) | 2008-05-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7785939B2 (en) | Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers | |
US9355887B2 (en) | Dual trench isolation for CMOS with hybrid orientations | |
US7060585B1 (en) | Hybrid orientation substrates by in-place bonding and amorphization/templated recrystallization | |
US7402466B2 (en) | Strained silicon CMOS on hybrid crystal orientations | |
US7364958B2 (en) | CMOS on hybrid substrate with different crystal orientations using silicon-to-silicon direct wafer bonding | |
US6830962B1 (en) | Self-aligned SOI with different crystal orientation using wafer bonding and SIMOX processes | |
US7253034B2 (en) | Dual SIMOX hybrid orientation technology (HOT) substrates | |
JP2007533119A (en) | Silicon devices on Si: C-OI and SGOI and manufacturing methods | |
US7732865B2 (en) | Epitaxial imprinting | |
US7531392B2 (en) | Multi-orientation semiconductor-on-insulator (SOI) substrate, and method of fabricating same | |
US20110086473A1 (en) | Hybrid orientation semiconductor structure with reduced boundary defects and method of forming same | |
JP2005136410A (en) | Cmos on hybrid substrate with different crystal orientations formed by employing silicon-to-silicon direct wafer bonding | |
JP2004296744A (en) | Process for fabricating semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:DE SOUZA, JOEL P.;OTT, JOHN A.;REZNICEK, ALEXANDER;AND OTHERS;REEL/FRAME:014759/0778 Effective date: 20031126 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. 2 LLC, NEW YORK Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:036550/0001 Effective date: 20150629 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GLOBALFOUNDRIES U.S. 2 LLC;GLOBALFOUNDRIES U.S. INC.;REEL/FRAME:036779/0001 Effective date: 20150910 |