US20050099219A1 - Setting multiple chip parameters using one IC terminal - Google Patents
Setting multiple chip parameters using one IC terminal Download PDFInfo
- Publication number
- US20050099219A1 US20050099219A1 US11/014,093 US1409304A US2005099219A1 US 20050099219 A1 US20050099219 A1 US 20050099219A1 US 1409304 A US1409304 A US 1409304A US 2005099219 A1 US2005099219 A1 US 2005099219A1
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- Prior art keywords
- circuit
- parameter
- terminal
- resistor
- voltage
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1731—Optimisation thereof
- H03K19/1732—Optimisation thereof by limitation or reduction of the pin/gate ratio
Abstract
A method for setting multiple chip parameters using one IC terminal is described. The chip comprises a first circuit coupled to the pin for setting a first parameter. A second circuit coupled to the pin sets a second parameter. In addition, a third circuit coupled to the pin sets a third parameter of the chip.
Description
- The present invention pertains to the field of integrated circuit design. More particularly, the present invention relates to a method to improve cost efficiency by conserving integrated circuit terminals.
- Integrated circuit (IC) terminals are used to transfer input and output signals to and from a chip. These input and output signals may include data, clock signals, and power terminals. Moreover, signals used to control impedance, termination, slew rate, equalization, voltage swing, and reference voltages on the IC may be set and monitored through the IC terminals.
- Packaging bumps or pins are examples of IC terminals. Whether bumps or pins are implemented depends primarily on the packaging technology chosen. Regardless of which packaging technology implemented, each IC terminal is typically used to set only one parameter of the IC. For example, a programming resistor that sets the impedance of a driver may be set using a pin. Another pin may be used to set a reference voltage for a differential receiver.
- The embodiments of the present invention are illustrated by way of example and not in the figures of the accompanying drawings, in which like references indicate similar elements and in which:
-
FIG. 1 shows a flowchart for setting multiple voltages on an integrated circuit; -
FIG. 2 shows on embodiment of a system for setting multiple chip parameters using a single IC terminal; -
FIG. 3 shows one embodiment of a circuit for setting a first parameter; -
FIG. 4 shows one embodiment of a circuit for setting a second parameter; and -
FIG. 5 shows one embodiment of a circuit for setting a third parameter. - In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be understood by those skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention.
- A method that allows a user to set multiple parameters of an IC through a single IC terminal helps to reduce costs by minimizing the number of required IC terminals. If the IC terminals are predetermined, the ability to set multiple parameters using a single IC terminal enables more parameters of the IC to be adjusted for circuit improvements. For one embodiment of the invention,
FIG. 1 shows a flowchart for setting multiple variables using a single pin. Inoperation 100, a first internal circuit on an IC is coupled to an external circuit. The first circuit will be described in further detail below and inFIG. 3 . The external circuit may be a voltage source coupled to a voltage divider that comprises a first resistor and a second resistor. The external circuit may provide the first circuit with an input voltage. From the measured input voltage and the known values of the first and second resistors, the first circuit uses a first equation to calculate and set a first parameter inoperation 110. The first parameter may be a termination resistance. - Next, in operation 120, a logic circuit or switch on the IC may be used to couple a second internal circuit to the external circuit. The second circuit will be described in further detail below and in
FIG. 4 . The external circuit may provide the second circuit with an input voltage. From the measured input voltage and the known values of the first and second resistors, the second circuit uses a second equation to calculate and set a second parameter inoperation 130. The second parameter may be an equalization current. -
Operation 140 determines if the user wishes to set a third parameter of the IC. If the user does not wish to set a third parameter, the process is terminated inoperation 190. Otherwise,operation 150 couples a third internal circuit of the IC to the external circuit. For this embodiment, a capacitor and a third resistor may be added to the existing voltage divider structure. The third circuit will be described in further detail below and inFIG. 5 . The external circuit may provide the third circuit with an input voltage. Using the measured input voltage and the known values of the first, second, and third resistors, the third circuit uses a third equation to calculate a variable in operation 160. The variable may be a peak voltage value of the third circuit. The detected peak voltage may be converted to a digital number using a translation circuitry such as an analog-to-digital (A/D) converter. A third parameter may then be set in operation 170 using the digital number generated by the A/D converter. For example, the digital number may set a slew rate (rise time) of an input/output (I/O) buffer. The I/O buffer may have a plurality of drivers of different sizes. The slew rate setting of the I/O buffer may be adjusted by turning on drivers of a specific size. Thus, the slew rate setting of the I/O buffer depends on which drivers are turned on by the digital number. Finally, the process is terminated inoperation 190. - Because the external circuit is comprised of linear elements, the external circuit may be represented as a Thevenin voltage and resistance for DC operation. The external circuit and the internal circuits form a linear network. Therefore, two variables may be used to set two parameters. By measuring the network in two DC configurations, the values of the Thevenin voltage and resistance may be observed. The first configuration may be achieved by
operation 100 when the external circuit is coupled to the first circuit. The first circuit operated in open circuit mode may provide the Thevenin voltage. The second situation may be achieved by operation 120 when the external circuit is coupled to the second circuit. The second circuit operated in continuity mode may provide the Thevenin resistance. The derivations for the two parameters are described in further detail below. - To measure a third variable for setting a third parameter, an AC signal may be applied to the linear network. Any capacitively coupled path functions as an open circuit for DC signals. The third variable may be an effective Thevenin impedance when the AC signal is applied. The derivation for the third parameter is described in further detail below in equation
- For another embodiment of the invention, the external circuit used to set the first, the second, and the third parameters of
FIG. 1 are coupled to the first, the second, and the third circuits through a packaging bump rather than a pin. -
FIG. 2 depicts a system for setting multiple variables of anIC 200 using a single IC terminal. The system comprises anexternal circuit 210, a circuit to selectparameter setting circuits 220, a firstparameter setting circuit 230, a secondparameter setting circuit 240, and a thirdparameter setting circuit 250.Circuit 230,circuit 240, andcircuit 250 are used for setting a first, a second, and a third parameter of the IC.External circuit 210 is used to provide an input tocircuit 230,circuit 240, andcircuit 250. Theexternal circuit 210 is coupled to theIC 200 through asingle pin 205. Depending on the packaging technology of the chip,pin 205 may be implemented as a bump. -
Circuit 220 initially couples theexternal circuit 210 to thecircuit 230 to set the first parameter. After the first parameter has been set,circuit 220 then couples theexternal circuit 210 tocircuit 240 to set the second parameter. After the second parameter is set,circuit 220 then couples theexternal circuit 210 tocircuit 250 to set the third parameter. - For one embodiment of the invention,
circuit 220 is a decoder. For another embodiment of the invention,circuit 220 is a counter. For yet another embodiment of the invention,circuit 220 is a multiplexer. - For another embodiment of the invention, a first internal circuit may be used to set the first and second parameters and a second internal circuit may be used to set the third parameter. For yet another embodiment of the invention, a first internal circuit may be used to set the first, second, and third parameters.
-
FIG. 3 depicts an embodiment of thecircuit 230 for setting a first parameter ofIC 200. Thecircuit 230 comprises adifferential amplifier 350, atermination resistor 340, and acircuit 360 for adjusting the termination resistor based upon the output of thedifferential amplifier 350. The differential amplifier compares an input voltage with a reference voltage, xVcc. The input voltage is obtained from an external circuit such as a voltage divider comprising a DC voltage source (Vcc) 310,resistor 320, andresistor 330. The value of the input voltage is a function ofVcc 310,resistor 320,resistor 330, andresistor 340. - The magnitude of reference voltage, xVcc, may be a fraction of
Vcc 310. Thecircuit 360 calculates and sets thetermination resistor 340 such that the voltage drop across thetermination resistor 340 is approximately equal to xVcc. The following equation expresses the relationship between the voltage drop across thetermination resistor 340 and xVcc, whereinresistor 320 is R1,resistor 330 is R2, andresistor 340 is RT: - Because the values for R1, R2, Vcc, and xVcc are known, RT is the only unknown variable and may be readily solved. Note that in order for
circuit 230 to function as a linear circuit, thetermination resistor 340 may be limited to a range of possible values defined byresistors -
FIG. 4 depicts an embodiment of acircuit 240 for setting a second parameter ofIC 200. Thecircuit 240 comprises adifferential amplifier 450, a DC voltage source (Vcc) 480, aresistor 440, acurrent source 470, and acircuit 460 for calculating and setting thecurrent source 470. - The
resistor 440 is coupled toVcc 480 andcurrent source 470. The resistance ofresistor 440 is approximately equal or a known fraction to the resistance oftermination resistor 340 ofcircuit 230. Thus, a proper setting oftermination resistor 340 also sets theresistor 440. The equalization current of thecurrent source 470 is determined bycircuit 460. Thecircuit 460 is coupled to thedifferential amplifier 450, which compares an input voltage with the voltage value at node M. The input voltage may be created by an external circuit. For example, the external circuit may compriseVcc 310,resistor 320, andresistor 330. For this embodiment of the invention,Vcc 310 is approximately equal toVcc 480. The output ofdifferential amplifier 450 is coupled to thecircuit 460.Circuit 460 sets thecurrent source 470 such that the voltage drop at node M is approximately equal to the input voltage provided by the external circuit. Therefore, the following equation may be derived, whereinresistor 320 is R1,resistor 330 is R2,resistor 440 is RT, and the equalization current acrosscurrent source 470 is leq: - RT was previously calculated in equation 1. Because the values for R1, R2, Vcc, and RT are known, leq is the only unknown variable and may be readily solved. The constraint of RT, as previously discussed, may be alternatively described by the equation:
RT*leq<Vcc−xVcc Equation 3. -
FIG. 5 depicts an embodiment of acircuit 250 for setting a third parameter ofIC 200. Thecircuit 250 comprises apeak detection circuit 560 coupled to slewrate setting circuit 565,resistor 540, and an external circuit. Theresistor 540 is coupled to anAC voltage source 550. Theslew setting circuit 565 is coupled to an I/O buffer circuit 505. The external circuit may compriseVcc 310,resistor 320,resistor 330,capacitor 570, andresistor 580. - The
peak detection circuit 560 calculates a peak voltage at node P. For one embodiment of the invention,voltage source 550 generates a pulsed signal having a maximum voltage of 0.5*Vcc and a minimum voltage of zero.Resistors capacitor 570 is sufficiently small compared to theresistors resistor 320 is R1,resistor 330 is R2, the fundamental frequency of the pulsed signal generated byvoltage source 550 is w, andcapacitor 570 is C:
Therefore, in an AC analysis, theresistor 580 appears in combination withresistors - Because
circuit 250 is a linear circuit that comprises both AC and DC components, the peak voltage (Vp) at node P may be calculated using superposition. Superposition involves algebraically adding the peak voltage due to the DC (Vp1) and the AC (Vp2) voltage sources. To solve for the DC equation,AC voltage source 550 is considered a short circuit having zero impedance, while thecapacitor 570 operates as an open circuit having infinite impedance. The following equation may be derived using current analysis, whereinresistor 320 is R1,resistor 330 is R2,resistor 580 is R3, andresistor 540 is Rout:
Equation 5 may be simplified and solved for Vp1 as follows: - To solve for the AC equation, the
capacitor 570 is treated as a short circuit having zero impedance and Vcc is replaced by a short to ground. As stated above, theAC voltage source 550 fluctuates between zero and 0.5Vcc. The following equation may be obtained using current analysis:
Vp2 may then be calculated from equation 8: - The peak voltage, Vp, at node P may be obtained by adding Vp1 and Vp2:
- Once
peak detection circuit 560 detects the peak voltage at node P, a slew rate setting circuit may set a rise time of a signal transmitted by I/O buffer circuit 505. The slew rate setting circuit may be implemented as a lookup table that determines the slew rate given a peak voltage. For one embodiment of the invention, a range of peak voltage values map to a corresponding slew rate setting. - For another embodiment of the invention, the
voltage source 550 may generate a maximum voltage value of 0.6*Vcc. Thecircuit 250, however, may have a limited feasibility voltage range for thevoltage source 550 in order to maintain its linear characteristics. The feasibility voltage range may be a function ofresistor 320,resistor 330, andresistor 540. The peak voltage is determined, in part, fromresistor 580. As a result, the slewrate setting circuit 565 may define the feasible voltage range, which may thereby be used to determine a suitable value forresistor 580. For example, ifresistor 320 is 40 ohms,resistor 330 is 200 ohms, andresistor 540 is 50 ohms, the slewrate setting circuit 565 may define the feasible voltage range to be between 0.5Vcc and 0.7Vcc. If a peak voltage of 0.6Vcc is desired, then the user may chooseresistor 580 to be approximately 20 ohms based on equation 10. - Successive parameters may incorporate more reference errors due to component tolerances. Therefore, it may be desirable to set the most crucial parameter first to minimize the programming components. The less crucial parameters may then be subsequently set.
- In the foregoing specification the invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modification and changes may be made thereto without departure from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than restrictive sense.
Claims (18)
1. A system, comprising:
an external circuit; and
an integrated circuit (IC) having an IC terminal, wherein the IC terminal couples the IC to the external circuit, wherein the IC terminal is used to set a first and a second parameter of the IC.
2. The system of claim 1 , wherein the IC comprises a first circuit that determines the value of the first parameter.
3. The system of claim 2 , wherein the IC comprises a second circuit that determines the value of the second parameter.
4. (canceled)
5. The system of claim 2 , further comprising:
a switch, wherein the switch couples the first circuit to the external circuit to set the first parameter.
6. The system of claim 1 , wherein the IC comprises an internal circuit that determines the value of the first and second parameters.
7. The system of claim 2 , wherein the first circuit comprises a differential amplifier that compares a voltage as received at the IC terminal with a reference voltage and generates an output value, wherein a logic circuit coupled to the differential amplifier sets the first parameter based on the output value.
8. A method, comprising:
coupling an external circuit having a DC Thevenin equivalent circuit to a terminal of an integrated circuit (IC); and
using the Thevenin voltage and resistance of the external circuit to set two parameters in the IC.
9-14. (canceled)
15. An integrated circuit (IC), comprising:
a means for setting a termination resistance of the IC using an IC terminal; and
a means for setting an equalization current of the IC using the IC terminal.
16. (canceled)
17. An integrated circuit (IC), comprising:
an IC terminal to couple to the IC to an external circuit; and
an internal circuit coupled to the IC terminal wherein the internal circuit sets a first parameter and a second parameter of the IC.
18. (canceled)
19. The IC of claim 17 , wherein the first parameter is a termination resistance.
20-21. (canceled)
22. The IC of claim 17 , wherein the IC terminal is a pin.
23. The IC of claim 17 , wherein the IC terminal is a bump.
24-30. (canceled)
Priority Applications (1)
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US11/014,093 US20050099219A1 (en) | 2002-12-27 | 2004-12-15 | Setting multiple chip parameters using one IC terminal |
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US10/330,598 US6922071B2 (en) | 2002-12-27 | 2002-12-27 | Setting multiple chip parameters using one IC terminal |
US11/014,093 US20050099219A1 (en) | 2002-12-27 | 2004-12-15 | Setting multiple chip parameters using one IC terminal |
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US10/330,598 Continuation US6922071B2 (en) | 2002-12-27 | 2002-12-27 | Setting multiple chip parameters using one IC terminal |
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US10/330,598 Expired - Fee Related US6922071B2 (en) | 2002-12-27 | 2002-12-27 | Setting multiple chip parameters using one IC terminal |
US11/014,093 Abandoned US20050099219A1 (en) | 2002-12-27 | 2004-12-15 | Setting multiple chip parameters using one IC terminal |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060038577A1 (en) * | 2004-08-20 | 2006-02-23 | Samsung Electronics Co., Ltd. | Methods and circuits for generating reference voltage |
CN103164635A (en) * | 2011-12-15 | 2013-06-19 | 中国银联股份有限公司 | Security information interactive system, security information interactive device and security information interactive method based on spreading parameter set |
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US6967591B1 (en) * | 2002-04-15 | 2005-11-22 | Linear Technology Corporation | Multi-bit digital input using a single pin |
US6894501B1 (en) * | 2002-05-21 | 2005-05-17 | Volterra Semiconductor, Inc. | Selecting multiple settings for an integrated circuit function using a single integrated circuit terminal |
DE102004017863B4 (en) * | 2004-04-13 | 2014-09-25 | Qimonda Ag | Circuit and method for determining a reference level for such a circuit |
US20080278346A1 (en) * | 2007-05-11 | 2008-11-13 | Eftimie Sabin A | Single-Pin Multi-Bit Digital Circuit Configuration |
JP5499808B2 (en) * | 2010-03-19 | 2014-05-21 | 富士通セミコンダクター株式会社 | Receiver circuit, receiver circuit control method, and receiver circuit test method |
GB2484524A (en) * | 2010-10-14 | 2012-04-18 | Powervation Ltd | Pin programming a power supply controller |
CN103246304B (en) * | 2012-02-06 | 2016-08-24 | 炬芯(珠海)科技有限公司 | A kind of sheet internal reference voltage generative circuit, generation chip and the method for generation |
WO2020076713A1 (en) * | 2018-10-09 | 2020-04-16 | Brian Kaczynski | Fundamental frequency detection using peak detectors with frequency-controlled decay time |
US20200111470A1 (en) * | 2018-10-09 | 2020-04-09 | Brian J. Kaczynski | Fundamental frequency detection using peak detectors with frequency-controlled decay time |
US10729002B2 (en) * | 2019-07-18 | 2020-07-28 | Intel Corporation | Device, system and method to mitigate signal noise in communications with a memory module |
CN111062184B (en) * | 2019-12-11 | 2020-12-01 | 四川大学 | Quick three-pin automatic impedance matching system |
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US5532616A (en) * | 1994-08-01 | 1996-07-02 | Texas Instruments Incorporated | On-chip series terminated CMOS(Bi-CMOS) driver |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE69434903T2 (en) * | 1993-11-29 | 2007-04-26 | Fujitsu Ltd., Kawasaki | Electronic system for terminating bus lines |
JP4676646B2 (en) * | 2001-05-11 | 2011-04-27 | ルネサスエレクトロニクス株式会社 | Impedance adjustment circuit and semiconductor device |
US6642741B2 (en) * | 2001-06-01 | 2003-11-04 | Tektronix, Inc. | Electronically adjustable integrated circuit input/output termination method and apparatus |
US6603329B1 (en) * | 2001-08-29 | 2003-08-05 | Altera Corporation | Systems and methods for on-chip impedance termination |
-
2002
- 2002-12-27 US US10/330,598 patent/US6922071B2/en not_active Expired - Fee Related
-
2004
- 2004-12-15 US US11/014,093 patent/US20050099219A1/en not_active Abandoned
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5532616A (en) * | 1994-08-01 | 1996-07-02 | Texas Instruments Incorporated | On-chip series terminated CMOS(Bi-CMOS) driver |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060038577A1 (en) * | 2004-08-20 | 2006-02-23 | Samsung Electronics Co., Ltd. | Methods and circuits for generating reference voltage |
US8344792B2 (en) * | 2004-08-20 | 2013-01-01 | Samsung Electronics Co., Ltd. | Methods and circuits for generating reference voltage |
CN103164635A (en) * | 2011-12-15 | 2013-06-19 | 中国银联股份有限公司 | Security information interactive system, security information interactive device and security information interactive method based on spreading parameter set |
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US20040124875A1 (en) | 2004-07-01 |
US6922071B2 (en) | 2005-07-26 |
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