US20050045987A1 - Integrated circuit package having inductance loop formed from same-pin-to-same-bonding-pad structure - Google Patents

Integrated circuit package having inductance loop formed from same-pin-to-same-bonding-pad structure Download PDF

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US20050045987A1
US20050045987A1 US10/927,014 US92701404A US2005045987A1 US 20050045987 A1 US20050045987 A1 US 20050045987A1 US 92701404 A US92701404 A US 92701404A US 2005045987 A1 US2005045987 A1 US 2005045987A1
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Prior art keywords
package
chip
conductor
input
bonding pad
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US10/927,014
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Yido Koo
Hyungki Huh
Kang Lee
Jeong-Woo Lee
Joonbae Park
Kyeongho Lee
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GCTS SEMICONDUCTOR Inc
GCT Semiconductor Inc
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GCT Semiconductor Inc
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Priority to US10/927,014 priority Critical patent/US20050045987A1/en
Assigned to GCTS SEMICONDUCTOR, INC. reassignment GCTS SEMICONDUCTOR, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KOO, YIDO, PARK, JOONBAE, HUH, HYUNGKI, LEE, JEONG-WOO, LEE, KYEONGHO, LEE, KANG YOON
Publication of US20050045987A1 publication Critical patent/US20050045987A1/en
Priority to US11/274,825 priority patent/US7952442B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/645—Inductive arrangements
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
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    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
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    • H01L2924/19041—Component type being a capacitor
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    • H01L2924/1901—Structure
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    • H01L2924/19042—Component type being an inductor
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    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Definitions

  • This invention generally relates to integrated circuits, and more particularly to an integrated circuit package having an inductance loop formed from at least one input/output pin of the package.
  • the inductor used for band-selection purposes is located off-package (i.e., is circuit-board mounted).
  • off-package or board-mounted inductors increases system costs.
  • connection problems may occur between the package and board which may adversely affect the reliability and performance of the PLL circuitry.
  • U.S. Pat. No. 6,323,735 forms an inductor entirely within the integrated circuit package containing the phase-locked loop circuitry. This is accomplished using conductive wires which connect bonding pads on the IC chip to a same bonding pad on the package substrate. The connection between the pads and wires forms an inductance loop which controls the operational frequency band of the PLL circuitry. Multiple bonding pads may be included on the package substrate to form inductor loops of varying length. The loops are then selectively activated to effect a change in operational frequency.
  • the approach taken in the '735 patent is undesirable for at least two reasons.
  • CMOS Frequency Synthesizer Design discloses a self-contained integrated circuit package containing an inductor loop. This loop is formed by connecting bonding wires between bonding pads on the IC chip and respective input/output pins of the IC package. The input/output pins are then connected by a third bonding wire. While this approach does not require the formation of special bonding pads on the package substrate, it is has at least two drawbacks that make it undesirable. First, like in the '735 patent, a bonding wire is used to connect the input/output pins. As previously noted, these wires are susceptible to damage during manufacture and/or use.
  • the input/output pins connected by the third bonding wire are located on opposite sides of the package.
  • the third wire must pass over the IC chip. This is undesirable because the wire could short certain portions of the chip circuitry and introduce noise and other interfering influences which substantially degrade chip performance.
  • An object of the present invention is to provide an integrated circuit package which is more economical and requires fewer processing steps to manufacture than conventional IC packages.
  • Another object of the present invention is to provide an integrated circuit package which is less susceptible to damage and noise which can degrade reliability and performance not only of the chip circuitry but also of the host system of the chip.
  • Another object of at least one embodiment of the present invention is to accomplish one or more of the aforementioned objects by reducing the number of bonding wires used to form the inductor loop compared with the number of wires used in conventional self-contained integrated circuits.
  • Another object of the present invention is to provide an integrated circuit package which does not require special bonding pads to be formed on the package substrate in order to form an inductor loop connected to the chip.
  • Another object of the present invention is to achieve one or more of the aforementioned objects by forming the inductor loop from at least one input/output pin of the package.
  • the semiconductor package comprises an integrated circuit chip and an inductor loop which is connected in a self-contained manner within the package.
  • This inductor loop is formed from a plurality of sub-loops.
  • the first sub-loop includes a first conductor which connects a bonding pad on the chip to an input/output pin of the package and a second conductor which connects the same bonding pad to the same pin.
  • the second sub-loop includes one of the first and second conductors and a third conductor connected between the pin and pad.
  • the conductors are preferably bonding wires.
  • the present invention is also an oscillator circuit which includes an active oscillator having two output nodes, an inductor loop coupled to the output nodes, and at least one capacitive circuit coupled to one of the output nodes.
  • the capacitive circuit includes a capacitor, a resistor, and a first switch and the resistor provides a bias voltage to the capacitor when the first switch is open.
  • the first switch couples and decouples the capacitor to the output nodes of the active oscillator.
  • the active oscillator and capacitive circuit are included in a semiconductor package which includes an integrated circuit chip.
  • the inductor loop When configured in this manner, the inductor loop includes a first conductor connecting a bonding pad on the chip to an input/output pin of the package and a second conductor connecting the bonding pad on the chip to the input/output pin of the package.
  • the first and second conductors may be bonding wires and the inductor loop may include at least a third conductor connecting the bonding pad on the chip to the input/output pin of the package.
  • the present invention provides an oscillator circuit as previously described but with a different inductor loop configuration.
  • This inductor loop includes has two sub-loops, the first of which includes a first conductor connecting a bonding pad on the chip to an input/output pin of the package and second conductor connecting the bonding pad on the chip to the input/output pin of the package.
  • the second sub-loop includes one of the first conductor and the second conductor and a third conductor connecting the bonding pad on the chip to the input/output pin of the package.
  • the first conductor and the second conductor are bonding wires.
  • FIG. 1 is a diagram showing a conventional integrated circuit package which is not self-contained.
  • FIG. 2 is a diagram showing a semiconductor package in accordance with a first embodiment of the present invention.
  • FIG. 3 is a diagram showing a semiconductor package in accordance with a second embodiment of the present invention.
  • the present invention is, in one respect, a semiconductor package having an integrated circuit chip and an inductor loop which is connected in a self-contained manner within the package.
  • the present invention is also a system which is at least partially controlled by the inductor loop of the semiconductor device mentioned above.
  • the system may be a communications system where the inductor loop is used to set a transmitter and/or RF carrier frequency or another type of system.
  • FIG. 2 shows a semiconductor package in accordance with a first embodiment of the present invention.
  • This package includes an integrated circuit chip 10 mounted on or within a package housing 11 .
  • the housing includes a substrate 12 for supporting the chip and a plurality of input/output (I/O) pins 13 formed on the substrate for electrically connecting the chip to one or more external circuits (not shown).
  • the substrate may be any type known and the I/O pins may be connected to the chip using any one of a variety of conventional attachment techniques, including but not limited to wire bonds and solder bumps.
  • packages of this type include lead frame packages, ball grid array (BGA) packages including those using tape automated bonding (FAB), pin grid array packages (PGA), thin small outline packages (TSOP), small outline J-lead packages (SOJ); small outline packages (SOP), and chip scale packages (CSP) to name a few.
  • BGA ball grid array
  • FAB tape automated bonding
  • PGA pin grid array packages
  • TSOP thin small outline packages
  • SOJ small outline J-lead packages
  • SOP small outline packages
  • CSP chip scale packages
  • the I/O pins may take any one of a variety of forms.
  • the pins are shown as external package leads disposed along a periphery of the package substrate.
  • the pins may be formed in other ways including but not limited to electrically conductive vias which extend through the package substrate to solder bump connections provided on an opposing side of the package.
  • the semiconductor package also includes an inductor loop 20 self-contained within the package.
  • the inductor loop may be formed from two conductors.
  • the first conductor 22 connects a first bonding pad 24 on the chip to a first input/output pin 26 of the package, and the second conductor 23 connects the same bonding pad to the same input/output pin.
  • the pin connects the two conductors to thereby complete the loop.
  • the first and second conductors are preferably bonding wires.
  • the inductor loop may be used to control one or more circuits on the integrated circuit chip.
  • the inductance value of the loop may be used to set an output frequency or frequency band of this circuit.
  • the length of the loop may be used to set other operational parameters of the chip.
  • the inductance value of the loop depends on its overall length. This length may be set in various ways to achieve the desired inductance value.
  • the length of the first and second conductors may be set to have specific lengths based on a loop length to be achieved.
  • the specific application of the inductor loop of the present invention may be adapted, for example, depending upon the parameters being set and the specific function to be performed by the integrated circuit.
  • FIG. 3 shows a semiconductor package in accordance with a second embodiment of the present invention.
  • This package includes an integrated circuit chip 100 mounted on or within a package housing 110 .
  • the housing includes a substrate 112 for supporting the chip and a plurality of input/output (I/O) pins 113 formed on the substrate for electrically connecting the chip to one or more external circuits (not shown).
  • the substrate may be made from a material and the I/O pins may be formed and connected in any of the ways noted in the discussion of the first embodiment.
  • the semiconductor package also includes an inductor loop 120 self-contained within the package.
  • the inductor loop is formed from two sub-loops.
  • the first sub-loop is formed by connecting a first conductor 122 between a bonding pad 124 on the chip and a first input/output pin 126 of the package and a second conductor 133 between the same bonding pad and package pin.
  • the second sub-loop is formed by one of the first and second conductors and at least a third conductor 23 connected between the same pad and pin.
  • the conductors are preferably bonding wires.
  • the inductor loop therefore has an effective length (and thus an inductance value) based on the sum of the two sub-loops.
  • additional conductors may be added between the pad and pin to increase the number of sub-loops comprising the inductor.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)

Abstract

An integrated circuit package includes an inductance loop formed from a connection of bonding wires and one or more input/output (I/O) package pins. In one embodiment, the inductance loop is formed from a first wire which connects a bonding pad on the integrated circuit chip to an I/O pin of the package and a second wire which connects the same bonding pad to the same pin. By forming the inductor loop within the limits of the integrated circuit package, a substantial reduction in space requirements is realized, which, in turn, promotes miniaturization.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • This invention generally relates to integrated circuits, and more particularly to an integrated circuit package having an inductance loop formed from at least one input/output pin of the package.
  • 2. Description of the Related Art
  • One perennial goal among circuit designers is to decrease the size of integrated circuits. This goal is largely driven by market demand for ever-smaller consumer electronics, communications devices, and display systems to mention a few. There are, however, a number of impediments that undermine this goal, one of which will now be discussed.
  • Many integrated circuits are not self-contained devices. To ensure proper operation, these circuits must therefore be connected to one or more external components through connections which do not involve the use of an IC package input/output pin. This is accomplished, for example, by connecting the integrated circuit chip 1 to an off-package component 2 using bonding wires 3, as shown in FIG. 1. The need to establish off-package connections increases the cost and complexity of the manufacturing process and therefore is considered highly undesirable. These connections also expose the integrated circuit to an increased risk of damage from external influences, which translate into degradation in reliability and performance.
  • One conventional integrated circuit requiring off-package connections is routinely used in the frequency synthesizer of mobile communications devices such as cellular phones. Because the phase noise specifications are so stringent in these devices, voltage-controlled oscillators in a phase-locked loop used to generate the frequencies are typically based on some resonant structure. Ceramic resonators and LC tank circuits are common examples. While details in the implementation of LC tank oscillators differ, the general resonant structure includes an inductor connected in parallel with a fixed capacitor (C) and a variable capacitor (Cx). In the absence of any losses, energy passes between the capacitors and the inductor at a frequency fout=(½π) [L(C+Cx)]−1/2, with the inductance value L selected to control the operating band of the device.
  • In an integrated circuit which includes the aforementioned frequency synthesizer, the inductor used for band-selection purposes is located off-package (i.e., is circuit-board mounted). The use of off-package or board-mounted inductors increases system costs. Moreover, connection problems may occur between the package and board which may adversely affect the reliability and performance of the PLL circuitry.
  • Attempts have been made to overcome the drawbacks of these conventional devices. One approach, disclosed in U.S. Pat. No. 6,323,735, forms an inductor entirely within the integrated circuit package containing the phase-locked loop circuitry. This is accomplished using conductive wires which connect bonding pads on the IC chip to a same bonding pad on the package substrate. The connection between the pads and wires forms an inductance loop which controls the operational frequency band of the PLL circuitry. Multiple bonding pads may be included on the package substrate to form inductor loops of varying length. The loops are then selectively activated to effect a change in operational frequency.
  • The approach taken in the '735 patent is undesirable for at least two reasons. First, in order to form the inductor loop completely within the IC package, the package substrate must be formed to include bonding pads separate from the input/output package pins. The need to form these special pads increases the cost and complexity of the manufacturing process. Second, in order to accommodate the bonding pads, the size of the integrated circuit substrate must be increased and as a result more circuit board space is consumed. These effects undermine the goal of increasing integration and miniaturization.
  • Another approach, disclosed in the text “Wireless CMOS Frequency Synthesizer Design,” by Craninckx, discloses a self-contained integrated circuit package containing an inductor loop. This loop is formed by connecting bonding wires between bonding pads on the IC chip and respective input/output pins of the IC package. The input/output pins are then connected by a third bonding wire. While this approach does not require the formation of special bonding pads on the package substrate, it is has at least two drawbacks that make it undesirable. First, like in the '735 patent, a bonding wire is used to connect the input/output pins. As previously noted, these wires are susceptible to damage during manufacture and/or use. Second, the input/output pins connected by the third bonding wire are located on opposite sides of the package. As a result, the third wire must pass over the IC chip. This is undesirable because the wire could short certain portions of the chip circuitry and introduce noise and other interfering influences which substantially degrade chip performance.
  • In view of the foregoing considerations, it is apparent that a need exists for an integrated circuit package which is more economical and requires fewer processing steps to manufacture than conventional IC packages, and which is also less susceptible to damage and noise which can degrade reliability and performance not only of the chip circuitry but also the host system of the chip. A need also exists for an integrated circuit package which is self-contained at least with respect to connection of an inductor loop connected to the chip, and which is able through this connection to achieve at least one of the aforementioned advantages.
    • SUMMARY OF THE INVENTION
  • An object of the present invention is to provide an integrated circuit package which is more economical and requires fewer processing steps to manufacture than conventional IC packages.
  • Another object of the present invention is to provide an integrated circuit package which is less susceptible to damage and noise which can degrade reliability and performance not only of the chip circuitry but also of the host system of the chip.
  • Another object of the present invention is to provide an integrated circuit package which is self-contained at least with respect to connection of an inductor loop to the IC chip and which is able through this connection to achieve at least one of the aforementioned advantages.
  • Another object of at least one embodiment of the present invention is to accomplish one or more of the aforementioned objects by reducing the number of bonding wires used to form the inductor loop compared with the number of wires used in conventional self-contained integrated circuits.
  • Another object of the present invention is to provide an integrated circuit package which does not require special bonding pads to be formed on the package substrate in order to form an inductor loop connected to the chip.
  • Another object of the present invention is to achieve one or more of the aforementioned objects by forming the inductor loop from at least one input/output pin of the package.
  • These and other objects and advantages of the present invention are achieved by providing a semiconductor package comprising an integrated circuit chip and an inductor loop which is connected in a self-contained manner within the package. This self-contained connection is accomplished by forming the loop from at least two conductors. The first conductor connects a bonding pad on the chip to an input/output pin of the package. The second conductor connects the same bonding pad on the chip to the same input/output pin of the package, thereby forming a loop. At least a third conductor may be added between the same pin and pad to increase the effective length of the inductor to thereby achieve a desired inductance. The conductors are preferably bonding wires.
  • In accordance with another embodiment, the semiconductor package comprises an integrated circuit chip and an inductor loop which is connected in a self-contained manner within the package. This inductor loop is formed from a plurality of sub-loops. The first sub-loop includes a first conductor which connects a bonding pad on the chip to an input/output pin of the package and a second conductor which connects the same bonding pad to the same pin. The second sub-loop includes one of the first and second conductors and a third conductor connected between the pin and pad. The conductors are preferably bonding wires.
  • The present invention is also an oscillator circuit which includes an active oscillator having two output nodes, an inductor loop coupled to the output nodes, and at least one capacitive circuit coupled to one of the output nodes. The capacitive circuit includes a capacitor, a resistor, and a first switch and the resistor provides a bias voltage to the capacitor when the first switch is open. The first switch couples and decouples the capacitor to the output nodes of the active oscillator. Preferably, the active oscillator and capacitive circuit are included in a semiconductor package which includes an integrated circuit chip. When configured in this manner, the inductor loop includes a first conductor connecting a bonding pad on the chip to an input/output pin of the package and a second conductor connecting the bonding pad on the chip to the input/output pin of the package. The first and second conductors may be bonding wires and the inductor loop may include at least a third conductor connecting the bonding pad on the chip to the input/output pin of the package.
  • In accordance with another embodiment, the present invention provides an oscillator circuit as previously described but with a different inductor loop configuration. This inductor loop includes has two sub-loops, the first of which includes a first conductor connecting a bonding pad on the chip to an input/output pin of the package and second conductor connecting the bonding pad on the chip to the input/output pin of the package. The second sub-loop includes one of the first conductor and the second conductor and a third conductor connecting the bonding pad on the chip to the input/output pin of the package. The first conductor and the second conductor are bonding wires.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a diagram showing a conventional integrated circuit package which is not self-contained.
  • FIG. 2 is a diagram showing a semiconductor package in accordance with a first embodiment of the present invention.
  • FIG. 3 is a diagram showing a semiconductor package in accordance with a second embodiment of the present invention.
    • DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • The present invention is, in one respect, a semiconductor package having an integrated circuit chip and an inductor loop which is connected in a self-contained manner within the package. The present invention is also a system which is at least partially controlled by the inductor loop of the semiconductor device mentioned above. The system may be a communications system where the inductor loop is used to set a transmitter and/or RF carrier frequency or another type of system. The various embodiments of the invention will now be discussed in seriatim below.
  • FIG. 2 shows a semiconductor package in accordance with a first embodiment of the present invention. This package includes an integrated circuit chip 10 mounted on or within a package housing 11. The housing includes a substrate 12 for supporting the chip and a plurality of input/output (I/O) pins 13 formed on the substrate for electrically connecting the chip to one or more external circuits (not shown). The substrate may be any type known and the I/O pins may be connected to the chip using any one of a variety of conventional attachment techniques, including but not limited to wire bonds and solder bumps. Examples of packages of this type include lead frame packages, ball grid array (BGA) packages including those using tape automated bonding (FAB), pin grid array packages (PGA), thin small outline packages (TSOP), small outline J-lead packages (SOJ); small outline packages (SOP), and chip scale packages (CSP) to name a few.
  • The I/O pins may take any one of a variety of forms. For example, the pins are shown as external package leads disposed along a periphery of the package substrate. However, if desired the pins may be formed in other ways including but not limited to electrically conductive vias which extend through the package substrate to solder bump connections provided on an opposing side of the package.
  • The semiconductor package also includes an inductor loop 20 self-contained within the package. The inductor loop may be formed from two conductors. The first conductor 22 connects a first bonding pad 24 on the chip to a first input/output pin 26 of the package, and the second conductor 23 connects the same bonding pad to the same input/output pin. In this embodiment, the pin connects the two conductors to thereby complete the loop. The first and second conductors are preferably bonding wires.
  • Once the inductor loop is formed, it may be used to control one or more circuits on the integrated circuit chip. For example, if the integrated circuit includes a phase-locked loop, the inductance value of the loop may be used to set an output frequency or frequency band of this circuit. Alternatively, the length of the loop may be used to set other operational parameters of the chip. The inductance value of the loop depends on its overall length. This length may be set in various ways to achieve the desired inductance value. For example, the length of the first and second conductors may be set to have specific lengths based on a loop length to be achieved. The specific application of the inductor loop of the present invention may be adapted, for example, depending upon the parameters being set and the specific function to be performed by the integrated circuit.
  • FIG. 3 shows a semiconductor package in accordance with a second embodiment of the present invention. This package includes an integrated circuit chip 100 mounted on or within a package housing 110. The housing includes a substrate 112 for supporting the chip and a plurality of input/output (I/O) pins 113 formed on the substrate for electrically connecting the chip to one or more external circuits (not shown). The substrate may be made from a material and the I/O pins may be formed and connected in any of the ways noted in the discussion of the first embodiment.
  • The semiconductor package also includes an inductor loop 120 self-contained within the package. The inductor loop is formed from two sub-loops. The first sub-loop is formed by connecting a first conductor 122 between a bonding pad 124 on the chip and a first input/output pin 126 of the package and a second conductor 133 between the same bonding pad and package pin. The second sub-loop is formed by one of the first and second conductors and at least a third conductor 23 connected between the same pad and pin. The conductors are preferably bonding wires. The inductor loop therefore has an effective length (and thus an inductance value) based on the sum of the two sub-loops. Those skilled in the art can appreciate that additional conductors may be added between the pad and pin to increase the number of sub-loops comprising the inductor.
  • A semiconductor package in accordance with any of the aforementioned embodiments may be used in any one of a variety of applications. One exemplary application is in a communication system where the inductor loop is used to set one or more parameters such as but not limited to an operating frequency. One illustrative embodiment of a voltage-controlled oscillator which may be included in such a communication system will now be described.
  • Other modifications and variations to the invention will be apparent to those skilled in the art from the foregoing disclosure. Thus, while only certain embodiments of the invention have been specifically described herein, it will be apparent that numerous modifications may be made thereto without departing from the spirit and scope of the invention.

Claims (12)

1. A semiconductor package, comprising:
an integrated circuit chip; and
an inductor loop including a first conductor connecting a bonding pad on the chip to an input/output pin of the package, and a second conductor connecting the bonding pad on the chip to the input/output pin of the package.
2. The semiconductor package of claim 1, wherein the first conductor and the second conductor are bonding wires.
3. The semiconductor package of claim 1, wherein the inductor loop includes at least a third conductor connecting the bonding pad on the chip to the input/output pin of the package.
4. A semiconductor package, comprising:
an integrated circuit chip; and
an inductor loop including:
(a) a first sub-loop which includes a first conductor connecting a bonding pad on the chip to an input/output pin of the package and second conductor connecting the bonding pad on the chip to the input/output pin of the package; and
(b) a second sub-loop which includes one of the first conductor and the second conductor and a third conductor connecting the bonding pad on the chip to the input/output pin of the package.
5. The semiconductor package of claim 4, wherein the first conductor and the second conductor are bonding wires.
6. A semiconductor package, comprising:
an integrated circuit chip including a phase-locked loop; and
an inductor loop having a length corresponding to an output frequency of the phase-locked loop, said inductor loop including a first conductor connecting a bonding pad on the chip to an input/output pin of the package, and a second conductor connecting the bonding pad on the chip to the input/output pin of the package.
7. The semiconductor package of claim 6, wherein the first conductor and the second conductor are bonding wires.
8. An oscillator circuit, comprising:
an active oscillator having two output nodes;
an inductor loop coupled to the output nodes; and
at least one capacitive circuit coupled to one of the output nodes, said capacitive circuit including a capacitor, a resistor, and a first switch, wherein said resistor provides a bias voltage to the capacitor when the first switch is open and wherein said first switch couples and decouples the capacitor to the output nodes of the active oscillator, and wherein the active oscillator and capacitive circuit are included in a semiconductor package which includes an integrated circuit chip, said inductor loop including a first conductor connecting a bonding pad on the chip to an input/output pin of the package and a second conductor connecting the bonding pad on the chip to the input/output pin of the package.
9. The oscillator circuit of claim 8, wherein the first conductor and the second conductor are bonding wires.
10. The oscillator circuit of claim 8, wherein the inductor loop includes at least a third conductor connecting the bonding pad on the chip to the input/output pin of the package.
11. An oscillator circuit, comprising:
an active oscillator having two output nodes;
an inductor loop coupled to the output nodes; and
at least one capacitive circuit coupled to one of the output nodes, said capacitive circuit including a capacitor, a resistor, and a first switch, wherein said resistor provides a bias voltage to the capacitor when the first switch is open and wherein said first switch couples and decouples the capacitor to the output nodes of the active oscillator, and wherein the active oscillator and capacitive circuit are included in a semiconductor package which includes an integrated circuit chip, said inductor loop including:
(a) a first sub-loop which includes a first conductor connecting a bonding pad on the chip to an input/output pin of the package and second conductor connecting the bonding pad on the chip to the input/output pin of the package; and
(b) a second sub-loop which includes one of the first conductor and the second conductor and a third conductor connecting the bonding pad on the chip to the input/output pin of the package.
12. The oscillator circuit of claim 11, wherein the first conductor and the second conductor are bonding wires.
US10/927,014 2003-08-28 2004-08-27 Integrated circuit package having inductance loop formed from same-pin-to-same-bonding-pad structure Abandoned US20050045987A1 (en)

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US7952442B2 (en) 2011-05-31
US20060081973A1 (en) 2006-04-20
TW200524123A (en) 2005-07-16

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