US20040145007A1 - Non-volatile semiconductor memory device and method of fabricating the same - Google Patents
Non-volatile semiconductor memory device and method of fabricating the same Download PDFInfo
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- US20040145007A1 US20040145007A1 US10/612,913 US61291303A US2004145007A1 US 20040145007 A1 US20040145007 A1 US 20040145007A1 US 61291303 A US61291303 A US 61291303A US 2004145007 A1 US2004145007 A1 US 2004145007A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
- H10B41/44—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a control gate layer also being used as part of the peripheral transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Definitions
- the present invention relates generally to non-volatile semiconductor memory devices and methods of fabricating the same and particularly to non-volatile semiconductor memory devices capable of providing improved electrical characteristics and methods of fabricating the same.
- Japanese Patent Laying-Open No. 8-64700 discloses in FIG. 3 a non-volatile semiconductor memory device including a semiconductor substrate having a main surface with predeterminedly spaced device isolating trenches internally provided with CVD oxide film forming an isolation oxide film. Between such isolation oxide films on the substrate's main surface a floating gate electrode is disposed with a tunnel oxide film posed therebetween. On the floating gate electrode a control gate electrode is disposed with an ONO film posed therebetween.
- the floating gate electrode has an upper surface having a protrusion and a depression reflecting a feature underlying the floating gate electrode.
- the ONO film can differ in thickness, quality and the like from the remainder or electric field concentration can occur. This results in the device having impaired electrical characteristics.
- the present invention contemplates a non-volatile semiconductor memory device exhibiting excellent electrical characteristics and a method of fabricating the same.
- the present non-volatile semiconductor memory device includes a semiconductor substrate, an isolation insulator, a floating electrode, an insulation film, and a control gate.
- the semiconductor substrate has a main surface provided with two spaced trenches.
- the isolation insulator fills the trench and has an upper surface with an end having a curvature protruding toward the semiconductor substrate.
- the floating electrode has a flat surface and extends from a main surface of the semiconductor substrate between the two trenches to the two isolation insulators.
- the insulation film extends from an upper surface of the floating electrode to a side surface of the floating gate overlying the isolation insulator.
- the control gate is disposed on the insulation film to extend from an upper surface of the floating electrode to a side surface of the floating electrode.
- the insulation film can be disposed on a flat upper surface of the floating electrode.
- the insulation film can be free from local variation in thickness, characteristics and the like.
- local electric field concentration can be reduced between the control electrode and the floating electrode.
- the reduced electrical field concentration can contribute to less impaired electrical characteristics of the semiconductor device.
- the isolation insulator having an upper surface with an end having a curvature protruding toward the semiconductor substrate, can prevent the floating electrode from having a lower portion with a protrusion having an apex of an acute angle. As a result, highly reliable and long-life semiconductor device can be implemented.
- the present semiconductor device fabrication method includes the steps of: providing a semiconductor substrate at a main surface with two spaced trenches; providing in the trench an isolation insulator having a protrusion protruding upper than a main surface of the semiconductor substrate; and isotropically etching away the protrusion partially to reduce the protrusion to be smaller in thickness than the trench.
- the method includes the steps of: after the step of isotropically etching, providing the semiconductor substrate at a main surface with a conductor film extending from a region located between the two isolation insulators to the isolation insulator; removing an upper surface layer of the conductor film to expose an upper portion of the isolation insulator to provide a floating electrode formed of the conductor film, having a flat upper surface and located between the isolation insulators; and etching away an upper portion of the isolation insulator adjacent to the floating electrode to expose a side surface of the floating electrode.
- photolithography can be dispensed with in providing a floating electrode between isolation insulators. Without photolithography, mask misalignment or the like is not introduced, and the floating electrode can be provided precisely in position as designed.
- FIG. 1 is a schematic cross section of the present semiconductor device in a first embodiment
- FIGS. 2 - 8 illustrate first to seventh steps, respectively, of a method of fabricating the FIG. 1 semiconductor device
- FIG. 9 is a schematic cross section of the present semiconductor device in a second embodiment
- FIG. 10 is a partially enlarged, schematic cross section of the FIG. 9 semiconductor device
- FIGS. 11 - 17 are schematic cross sections for illustrating first to seventh steps, respectively, of a method of fabricating the semiconductor device shown in FIGS. 9 and 10;
- FIG. 18 is a schematic cross section of the present semiconductor device in a third embodiment
- FIGS. 19 - 28 are schematic cross sections for illustrating first to tenth steps, respectively, of a method of fabricating the FIG. 18 semiconductor device
- FIG. 29 is a schematic cross section of the present semiconductor device in a fourth embodiment
- FIGS. 30 and 31 are schematic cross sections for illustrating first and second steps, respectively, of a method of fabricating the FIG. 29 semiconductor device
- FIG. 32 is a schematic cross section of the present semiconductor device in a fifth embodiment
- FIGS. 33 - 42 are schematic cross sections for illustrating first to tenth steps, respectively, of a method of fabricating the FIG. 32 semiconductor device
- FIGS. 43 - 46 are schematic cross sections for illustrating first to fourth steps, respectively, of the present semiconductor device fabrication method in a sixth embodiment.
- FIGS. 47 - 49 are reference diagrams for illustrating an effect of the FIG. 1 semiconductor device.
- FIG. 1 Reference will first be made to FIG. 1 to describe the present semiconductor device in a first embodiment.
- the present semiconductor device is a semiconductor memory device including a semiconductor substrate 1 having a main surface having a device formation region surrounded by an isolation oxide film.
- the semiconductor device in the device formation region includes spaced, conductive impurity diffusion regions (not shown) and in a region located between conductive impurity diffusion regions has a tunnel insulation film 6 a - 6 c overlying a main surface of semiconductor substrate 1 , a floating gate electrode 7 a - 7 c overlying the tunnel insulation film, an ONO film 8 overlying floating gate electrode 7 a - 7 c , and a control gate electrode 9 overlying ONO film 8 .
- the FIG. 1 semiconductor device is a non-volatile semiconductor memory device (so-called flash memory).
- semiconductor substrate 1 has a main surface provided with a trench 2 a , 2 b surrounding the device formation region.
- an oxide film 3 is disposed on the trench 2 a , 2 b internal wall surface.
- oxide film 3 is filled with a high density plasma-chemical vapor deposition (HDP-CVD) oxide film 4 .
- Oxide film 3 and HDP-CVD oxide film 4 form an isolation oxide film 5 a , 5 b .
- Isolation oxide film 5 a , 5 b has an upper surface having an end 33 curved to protrude downward (or toward semiconductor substrate 1 ).
- tunnel insulation film 6 a - 6 c On the semiconductor substrate 1 main surface in the device formation region tunnel insulation film 6 a - 6 c is provided.
- Floating gate electrode 7 a - 7 c extends from tunnel insulation film 6 a - 6 c to an end 33 of isolation oxide film 5 a , 5 b .
- insulative ONO film 8 On floating gate electrode 7 a - 7 c insulative ONO film 8 is disposed.
- ONO film 8 is a film formed of a stack of the three insulation film layers of an oxide film, a nitride film and an oxide film, as seen from floating gate electrode 7 a - 7 c .
- ONO film 8 extends from an upper surface of floating gate electrode 7 a - 7 c to a side surface of the electrode.
- ONO film 8 also extends from a side surface of floating gate electrode 7 a - 7 c to a portion of an upper surface of isolation oxide film 5 a , 5 b.
- Floating gate electrode 7 a - 7 c has an upper surface planarized to extend in a direction substantially parallel to the main surface of semiconductor substrate 1 .
- the floating gate electrode 7 a - 7 c upper surface has an end having a corner 31 having an apex of approximately 90°.
- control gate electrode 9 is disposed on ONO film 8 .
- Control gate electrode 9 extends from an upper surface of floating gate electrode 7 a - 7 c to a side surface of floating gate electrode 7 a - 7 c .
- isolation oxide film 5 a , 5 b may have a width L1 for example of 200 nm and between isolation oxide films 5 a and 5 b the device formation region may have a width L2 for example of 100 nm.
- the FIG. 1 semiconductor device is a non-volatile semiconductor memory device including semiconductor substrate 1 , isolation oxide film 5 a , 5 b serving as an isolating insulator, floating gate electrode 7 a - 7 c serving as a floating electrode, ONO film 8 serving as an insulation film, and control gate electrode 9 serving as a control electrode.
- Semiconductor substrate 1 has a main surface having two spaced trenches 2 a and 2 b . Isolating insulation film 5 a , 5 b fills trench 2 a , 2 b .
- Isolating insulation film 5 a , 5 b has an upper surface having an end region 33 curved to protrude toward semiconductor substrate 1 (downward).
- Floating gate electrode 7 b extends from between two trenches 2 a and 2 b on a main surface of semiconductor substrate 1 to two isolation oxide films 5 a , 5 b .
- Floating gate electrode 7 a - 7 c has a flat upper surface.
- ONO film 8 extends from an upper surface of floating gate electrode 7 a - 7 c to a side surface of floating gate electrode 7 a - 7 c located on isolation oxide film 5 a , 5 b .
- Control gate electrode 9 overlies ONO film 8 to extend from an upper surface of floating gate electrode 7 a - 7 c to a side surface of floating gate electrode 7 a - 7 c.
- ONO film 8 can overlie a flat upper surface of floating gate electrode 7 a - 7 c .
- the insulative ONO film 8 can be free of local variation in thickness, characteristics and the like. This can for example address a conventional problem caused at a portion corresponding to region 30 shown in FIG. 1:
- ONO film 8 free of variation for example in thickness can contribute to reduced local electrical field concentration occurring between control gate electrode 9 and floating gate electrode 7 a - 7 c .
- the reduced local electrical field concentration can in turn contribute to less impaired electrical characteristics of the semiconductor device.
- the semiconductor device can be highly reliable and have a long life.
- floating gate electrode 7 a - 7 c that extends to reach isolation oxide film 5 a , 5 b can have an increased surface area opposite control gate electrode 9 . Furthermore, arranging control gate electrode 9 extending from an upper surface of floating gate electrode 7 a - 7 c to a side surface of floating gate electrode 7 a - 7 c with ONO film 8 posed therebetween can increase a capacitance (C1) between control gate electrode 9 and floating gate electrode 7 a - 7 c and accordingly, a coupling ratio ( ⁇ ) proportional to capacitance (C1) provided between control gate electrode 9 and floating gate electrode 7 a - 7 c.
- Increasing coupling ratio ( ⁇ ) can decrease a voltage of a signal applied to control gate electrode 9 .
- the present semiconductor device can thus reduce a voltage of a signal applied to control gate electrode 9 .
- connection 32 a sidewall surface of trench 2 a , 2 b and a main surface of semiconductor substrate 1 that underlies floating gate electrode 7 a - 7 c may be connected at a portion (connection 32 ) allowing semiconductor substrate 1 to have a curved surface.
- connection 32 has an effect, as will be described hereinafter with reference to FIGS. 47 and 48.
- connection 40 As shown in FIG. 47, if a main surface of substrate 1 underlying floating gate 7 b and a sidewall surface of trench 2 a are connected at a portion (connection 40 ), pointed as indicated by a numeral 41 (i.e., connection 40 is not rounded) then at connection 40 insulation between floating gate electrode 7 b and semiconductor substrate 1 reduces. This is because at pointed portion 41 (an angled portion) electric field concentration occurs.
- FIG. 48 shows that at a connection 32 semiconductor substrate 1 has a rounded surface (i.e., such as shown in the FIG. 1 semiconductor device). This provides for a reduced possibility of connection 32 having electric field concentration, and hence improved insulation between floating gate electrode 7 b and semiconductor substrate 1 .
- the present semiconductor device includes insulation oxide film 5 a having an upper surface with end region 33 curved to protrude toward semiconductor substrate 1 (i.e., downward).
- FIG. 49 is a schematic, partially enlarged diagram of FIG. 1.
- the present semiconductor device including isolation oxide film 5 a having an upper surface with end regions 33 curved to protrude downward, allows an upper surface of HDP-CVD oxide film 4 , a constituent of isolation oxide film 5 a , and an upper surface of tunnel insulation film 6 b to form an angle ⁇ 2 larger than an angle ⁇ 1 formed by upper surfaces of HDP-CVD oxide film 4 and tunnel insulation film 6 b , respectively, in the FIG. 48 semiconductor device.
- HDP-CVD oxide film 4 has an upper surface with end region 33 substantially linear as seen in cross section. That is, as shown in FIG.
- floating gate electrode 7 b has a bottom protrusion 34 having an obtuse apex (angle ⁇ 2), rather than an acute angle.
- electric field concentration can be reduced (i.e., tunnel insulation film 6 b can be enhanced in insulation). The semiconductor device can thus be prevented from having reduced reliability and shorter longevity attributed to electric field concentration.
- FIG. 1 semiconductor device (a non-volatile semiconductor memory device) is fabricated, as will be described hereinafter with reference to FIGS. 2 - 8 .
- a silicon oxide film (not shown) is disposed on a main surface of semiconductor substrate 1 .
- a silicon nitride film (not shown) is disposed.
- photolithography is employed to provide a patterned resist film.
- This resist film is used as a mask in partially etching the silicon nitride and oxide films away.
- the resist pattern is then removed.
- Semiconductor substrate 1 thus has a main surface with patterned silicon oxide and nitride films 10 and 11 thereon (see FIG. 2). Silicon oxide and nitride films 10 and 11 are used as a mask in partially dry-etching semiconductor substrate 1 away. Alternatively, the substrate may be subjected to anisotropic etching other than dry etching.
- Semiconductor substrate 1 thus has a main surface provided with two spaced trenches 2 a and 2 b (as shown in FIG. 2.)
- Trench 2 a , 2 b then has an internal wall surface thermally oxidized to provide oxide film 3 (see FIG. 3). The structure shown in FIG. 3 is thus obtained. Note that oxide film 3 is introduced to alleviate etching-stress in semiconductor substrate 1 .
- HDP-CVD oxide film 4 is disposed to fill trench 2 a , 2 b and also extend to an upper surface of silicon nitride film 11 .
- CMP Chemical mechanical polishing
- This isotropic etching also exposes a main surface of semiconductor substrate 1 in the device formation region.
- This isotropically etching an upper, protruding portion of isolation oxide film 5 a , 5 b to partially remove it the width of protrusion is reduced to be smaller than that of trench 2 a , 2 b.
- tunnel insulation film 6 a - 6 c (see FIG. 7) is provided on a main surface of semiconductor substrate 1 in the device formation region.
- a polysilicon film 14 serving as a conductive film (see FIG. 7) is disposed to extend from tunnel insulation film 6 a - 6 c to isolation oxide film 5 a , 5 b .
- the step of reducing the width of a protrusion of isolation oxide film 5 a , 5 b to be smaller than that of trench 2 a , 2 b is followed by the step of disposing conductive, polysilicon film 14 extending from a region of a main surface of semiconductor substrate 1 located between two isolation oxide films 5 a and 5 b to isolation oxide film 5 a , 5 b.
- Polysilicon film 14 then has an upper surface layer chemically mechanically polished or subjected to a similar planarization process to have a portion removed. As a result, as shown in FIG. 7, polysilicon film 14 has an upper surface 16 receding, as indicated by an arrow 15 , to expose an upper surface of isolation oxide film 5 a , 5 b . Floating gate electrodes 7 a - 7 c separated by isolation oxide films 5 a and 5 b can thus be obtained.
- Conductive polysilicon film 14 thus has an upper surface layer removed to expose an upper portion of isolation oxide film 5 a , 5 b to form floating gate electrode 7 b formed of polysilicon film 14 , having a flat upper surface and also located between isolation oxide films 5 a and 5 b .
- polysilicon film 14 may be replaced with amorphous silicon film.
- isolation oxide film 5 a , 5 b has an upper portion isotropically etched away. It can be etched away with an etchant for example of hydrogen fluoride. As a result, as shown in FIG. 8, floating gate electrode 7 a - 7 c can have an exposed side surface. Thus an upper portion of isolation oxide film 5 a , 5 b that is adjacent to floating gate electrode 7 a - 7 c is etched away to provide floating gate electrode 7 a - 7 c with an exposed side surface.
- ONO film 8 is then provided to extend from upper and side surfaces of floating gate electrode 7 a - 7 c to an upper surface of isolation oxide film 5 a , 5 b (see FIG. 1). Then on ONO film 8 control gate electrode 9 (see FIG. 1) is disposed. As a result can be obtained a flash memory serving as a semiconductor device structured as shown in FIG. 1.
- FIGS. 2 - 8 semiconductor device fabrication method photolithography can be dispensed with and between isolation oxide films 5 a and 5 b floating gate electrode 7 a - 7 c can be formed in self alignment. Dispensing with photolithography and hence absence of mask misalignment allows floating gate electrode 7 a - 7 c to be more precisely positioned as designed. It can also help to form floating gate electrode 7 a - 7 c having a flat upper surface.
- isolation oxide film 5 a , 5 b having a protrusion smaller in width than trench 2 a , 2 b allows floating gate electrode 7 a - 7 c between isolation oxide films 5 a and 5 b to have an end overlying isolation oxide film 5 a , 5 b .
- This can help floating gate electrode 7 a - 7 c to have a width larger than that between trenches 2 a and 2 b .
- isolation oxide film 5 a , 5 b has an upper portion removed to allow floating gate electrode 7 a - 7 c to have an exposed side surface.
- control gate electrode 9 to extend from an upper surface of floating gate electrode 7 a - 7 c to the side surface thereof with ONO film 8 posed therebetween. This can in turn increase capacitance (C1) between control gate electrode 9 and floating gate electrode 7 a - 7 c . Consequently, coupling ratio (a) can be increased and the flash memory can operate with enhanced characteristics.
- FIGS. 9 and 10 With reference to FIGS. 9 and 10 the present semiconductor device in a second embodiment will be described. Note that FIG. 9 corresponds to FIG. 1.
- FIGS. 9 and 10 semiconductor device is basically similar in structure to the FIG. 1 semiconductor device, except the geometry of a boundary between isolation oxide film 5 a , 5 b and a device formation region of semiconductor substrate 1 , i.e., the geometry of an upper portion (an edge 17 ) of trench 2 a , 2 b .
- Edge 17 has a geometry, as will more specifically be described hereinafter with reference to FIG. 10.
- isolation oxide film 5 a has an end, or edge 17 , defined by a curved portion 19 providing a curvature connecting together a flat portion 18 defining a main surface of semiconductor substrate 1 and a liner portion 20 defining a side surface of trench 2 a .
- liner portion 20 is a substantially linear portion of the side surface of trench 2 a , as seen in a cross section of trench 2 a in a direction substantially perpendicular to the main surface of semiconductor substrate 1 .
- Curved portion 19 has a width L of 5 to 40 nm, more preferably 10 to 30 nm.
- the present semiconductor device in one example is characterized in configuration summarized as follows: the semiconductor device is a non-volatile semiconductor memory device having the FIG. 1 semiconductor memory device's characteristic configuration plus connection 32 between a sidewall surface of trench 2 a , 2 b and a main surface of semiconductor substrate 1 underlying floating gate electrode 7 a - 7 c that allows semiconductor substrate 1 to have a surface having a larger curvature.
- the semiconductor device thus configured can be as effective as the FIG. 1 semiconductor device and also more reliably prevent floating gate electrode 7 a - 7 c from having a lower surface with protrusion 34 located on connection 32 and having an acute apex ⁇ .
- protrusion 34 can be free from significant electric field concentration, which further ensures that the semiconductor device is free from impaired reliability and reduced lifetime attributed to electric field concentration.
- curved portion 19 a portion of a surface of semiconductor substrate 1 , curved as has been described above, has a width L of 5 to 40 nm as seen in a direction in which the semiconductor substrate 1 main surface extends.
- Curved portion 19 having width L numerically ranging as described above allows a flat main surface of semiconductor substrate 1 at a portion adjacent to trench 2 a , 2 b and also allows a sidewall surface of trench 2 a , 2 b and a main surface of semiconductor substrate 1 to be connected 32 with a sufficiently smooth curvature.
- FIGS. 9 and 10 semiconductor device (a non-volatile semiconductor device) is fabricated, as described hereinafter.
- a silicon oxide film (not shown) is disposed on a main surface of semiconductor substrate 1 (see FIG. 11) is disposed.
- a polysilicon film (not shown) is disposed on the silicon oxide film.
- the polysilicon film can have a thickness for example of no more than 40 nm. Furthermore, the polysilicon film's thickness is preferably 10 to 30 nm, more preferably 15 to 25 nm.
- a silicon nitride film (not shown) is disposed. The polysilicon film may be replaced with amorphous silicon film.
- semiconductor substrate 1 has a main surface underlying a film formed of a stack of silicon oxide film 10 , polysilicon film 21 and silicon nitride film 11 having an open pattern and serving as a mask layer.
- a mask layer is formed that is formed of a film formed of stacked layers including polysilicon film 21 serving as a buffer conductive film layer and has an open pattern on a region to be provided with two trenches 2 a , 2 b .
- Polysilicon film 21 is partially exposed at a side surface opposite to the open pattern.
- the film formed of stacked layers is used as a mask in anisotropically etching away a main surface of semiconductor substrate 1 partially.
- semiconductor substrate 1 has a main surface provided with two trenches 2 a , 2 b (see FIG. 11). The structure shown in FIG. 11 is thus obtained.
- trench 2 a , 2 b has an internal wall surface thermally oxidized to provide oxide film 3 (FIG. 12) serving as a first oxide film.
- the thermal oxidization step performed to provide the first oxide film also similarly oxidizes an end of polysilicon film 21 that faces trench 2 a , 2 b (FIG. 11). Consequently, as shown in FIG. 12, at edge 17 , located at an upper portion of trench 2 a , 2 b , in an interface between semiconductor substrate 1 and silicon nitride film 11 , silicon oxide film extends inward from an end facing trench 2 a , 2 b and a so-called bird's beak is formed. This bird's beak results in curved edge 17 of a surface of semiconductor substrate 1 in contact with oxide film 3 .
- trench 2 a , 2 b is filled. More specifically, on oxide film 3 HDP-CVD oxide film 4 serving as a second oxide film (see FIG. 13) is disposed. HDP-CVD oxide film 4 filling trench 2 a ; 2 b also extends to an upper surface of silicon nitride film 11 . As a result, the structure shown in FIG. 13 is obtained.
- HDP-CVD oxide film 4 (FIG. 13) is for example chemically mechanically polished to have an upper surface layer removed. As a result, a portion of HDP-CVD oxide film 4 overlying an upper surface of silicon nitride film 11 is removed and HDP-CVD oxide film 4 also has a flat upper surface 12 (see FIG. 14). The FIG. 14 structure is thus obtained.
- isolation oxide film 5 a , 5 b initially having a geometry as indicated by a broken line before it is etched, has a surface layer removed, as indicated by arrows. Isolation oxide film 5 a , 5 b having been etched has a geometry as indicated by a solid line. Furthermore, silicon oxide film 10 overlying a main surface of silicon substrate 1 (see FIG.
- isolation oxide film 5 a , 5 b is reduced to have a smaller width than trench 2 a , 2 b and a film formed of stacked layers serving as a mask layer (the film formed of stacked layers disposed on a main surface of semiconductor substrate 1 and including silicon oxide film 10 ) is also removed. As a result, the structure shown in FIG. 15 is obtained.
- semiconductor substrate 1 has a curved surface attributed to a bird's beak. This reduces charge concentration in the semiconductor device at edge 17 , as described later. Furthermore, isotropically etching the isolation oxide film, as shown in FIG. 15, can stabilize edge 17 in geometry. More specifically, if isolation oxide film 5 a , 5 b isotropically etched away as shown in FIG.
- edge 17 having a curved surface can contribute to relatively reduced, positional variation of an end of isolation oxide film 5 a , 5 b in a direction across a depth of semiconductor substrate 1 (i.e., that of a portion at which a main surface of semiconductor substrate 1 at edge 17 and an upper surface of isolation oxide film 5 a , 5 b contact each other).
- a silicon oxide film is disposed to serve as tunnel insulation film 6 a - 6 b (FIG. 16).
- tunnel insulation film 6 a - 6 c isolation oxide film 5 a , 5 b is buried under conductive polysilicon film 14 (FIG. 16).
- Polysilicon film 14 has an upper surface layer for example chemically, mechanically polished and thus removed away. As a result, as indicated in FIG. 16 by arrows, polysilicon film 14 has an upper surface 16 receding to a position indicated by a solid line.
- Isolation oxide film 5 a , 5 b accordingly has an upper surface exposed.
- polysilicon film 14 is separated by isolation oxide film 5 a , 5 b .
- polysilicon film 14 forms floating gate electrode 7 a - 7 c .
- the configuration shown in FIG. 16 is thus obtained.
- isolation oxide film 5 a , 5 b is wet-etched or similarly, isotropically etched to have an upper portion removed.
- floating gate electrode 7 a - 7 c has an exposed side surface. The structure as shown in FIG. 17 is thus obtained.
- ONO film 8 (FIG. 9) and control gate electrode 9 (FIG. 9) are disposed to obtain the semiconductor device shown in FIGS. 9 and 10.
- the semiconductor device is a non-volatile semiconductor memory device including a memory cell region provided with floating gate electrode 7 a - 7 c , control gate electrode 9 and the like, and a peripheral circuitry region provided with field effect transistors configured of gate electrodes 23 a , 23 b , gate insulation film 22 a , 22 b , and source/drain regions (not shown).
- the memory cell region has a structure similar to that of the present semiconductor device in the first embodiment shown in FIG. 1.
- semiconductor substrate 1 has a main surface provided with trench 2 c , 2 d .
- Trench 2 c , 2 d has an internal wall surface with oxide film 3 disposed thereon.
- oxide film 3 HDP-CVD oxide film 4 is disposed to fill trench 2 c , 2 d and also extend to a main surface of semiconductor substrate 1 .
- Oxide film 3 and HDP-CVD oxide film 4 form isolation oxide film 5 c , 5 d .
- Isolation oxide film 5 c , 5 d separates a device formation region, in which semiconductor substrate 1 has a main surface with gate insulation film 22 a , 22 b disposed thereon.
- gate insulation film 22 a , 22 b via a channel region underlying gate insulation film 22 a , 22 b , spaced source/drain regions (not shown) are provided opposite as seen in a direction perpendicular to the plane of FIG. 18.
- gate insulation film 22 a , 22 b On gate insulation film 22 a , 22 b gate electrode 23 a , 23 b is provided.
- a thickness T2 of isolation oxide film 5 c , 5 d in the peripheral circuitry region is larger than a thickness T1 of isolation oxide film 5 a , 5 b in the memory cell region.
- the FIG. 18 present semiconductor device in one example has a characteristic configuration summarized as follows: the semiconductor device is a non-volatile semiconductor memory device having the FIG. 1 semiconductor device's characteristic configuration, characterized in that semiconductor substrate 1 includes a memory cell region and a peripheral circuitry region.
- the memory cell region has formed therein a memory cell of flash memory including floating gate electrode 7 a - 7 c , ONO film 8 serving as an insulation film and control gate electrode 9 .
- the peripheral circuitry region is a region other than the memory cell region.
- the peripheral circuitry region has trench 2 c , 2 d provided in a main surface of semiconductor substrate 1 to serve as another trench.
- the semiconductor device further includes isolation oxide film 5 c , 5 d provided in trench 2 c , 2 d and serving another isolation insulator.
- thickness T2 of isolation oxide film 5 c , 5 d arranged in the peripheral circuitry region is larger than thickness T1 of isolation oxide film 5 a , 5 b arranged in the memory cell region and serving as isolation insulator.
- the semiconductor device thus configured can be as effective as the FIG. 1 semiconductor device and also increase isolation breakdown voltage, junction breakdown voltage of isolation oxide film 5 c , 5 d in the peripheral circuitry region. This is because isolation oxide film 5 c having large thickness T2 hardly allows an impurity introduced after the provision of gate electrode 23 a , 23 b to be introduced into semiconductor substrate 1 adjacent to isolation oxide film 5 c . As a result, the semiconductor device can provide increased reliability.
- FIG. 18 semiconductor device is fabricated, as described hereinafter.
- a silicon oxide film (not shown) is disposed.
- a silicon nitride film (not shown) is disposed.
- a patterned resist (not shown) is disposed. This resist film is used as a mask in dry-etching or similarly, anisotropically etching the silicon nitride and oxide films to remove the films partially. The resist film is then removed.
- semiconductor substrate 1 has a main surface underlying a silicon oxide film 10 (see FIG. 19) and a silicon nitride film 11 (see FIG. 19) having an open pattern. Silicon nitride and oxide films 11 and 10 are used as a mask in anisotropically etching a main surface of semiconductor substrate 1 to partially remove it. As a result, as shown in FIG. 19, semiconductor substrate 1 has a main surface provided with trench 2 a - 2 d . Thus the step of providing semiconductor substrate 1 at a main surface thereof with two trenches 2 a and 2 b and the step of providing the peripheral circuitry region at a main surface of semiconductor substrate 1 with different trenches 2 c , 2 d are simultaneously performed.
- trench 2 a - 2 d has an internal wall surface thermally oxidized to provide oxide film 3 (see FIG. 20) to provide such a structure as shown in FIG. 20.
- trench 2 a - 2 d is filled with HDP-CVD oxide film 4 .
- HDP-CVD oxide film 4 fills trench 2 a - 2 d and also extends to reach an upper surface of silicon nitride film 11 .
- HDP-CVD oxide film 4 is then chemically mechanically polished to have an upper surface layer thereof removed. This allows silicon nitride film 11 to have an upper surface exposed and HDP-CVD oxide film 4 to have a flat upper surface 12 , as shown in FIG. 22. As a result, trench 2 a - 2 d is internally provided with isolation oxide film 5 a - 5 d formed of oxide film 3 and HDP-CVD oxide film 4 .
- isolation oxide film 5 a , 5 b serving as an isolation insulator and the step of providing in trench 2 c , 2 d isolation oxide film 5 c , 5 d serving as another isolation insulator having a portion protruding upper than a main surface of semiconductor substrate 1 , are performed.
- Silicon nitride film 11 (see FIG. 22) is then wet-etched away. Then in the peripheral circuitry region on silicon oxide film 10 and isolation oxide film 5 c , 5 d a resist film 24 (see FIG. 23) is disposed to serve as a protection film. Then, similarly as has been shown in the FIG. 6 step, in the memory cell region isolation oxide film 5 a , 5 b has an upper portion wet-etched or similarly, isotropically etched to have a portion removed.
- isolation oxide film 5 a , 5 b has an upper portion etched to have a geometry, as shown in FIG. 23 by a broken line. Furthermore, at that time, in the device formation region, silicon oxide film 10 overlying a main surface of semiconductor substrate 1 is removed.
- Resist film 24 serving as a protection film can prevent the peripheral circuitry region from having isolation oxide film 5 c , 5 d etched away.
- thickness T2 of isolation oxide film 5 c , 5 d can be larger than thickness T1 of isolation oxide film 5 a , 5 b provided in the memory cell region (see FIG. 18).
- Polysilicon film 14 is them chemically mechanically polished to have an upper surface layer thereof removed. This allows isolation oxide film 5 a - 5 d to have an upper surface exposed and also polysilicon film 14 to have an upper surface 16 receding to a position indicated in FIG. 24 by a solid line. As a result, floating gate electrode 7 a - 7 c and a conductive layer 25 are provided divided by isolation oxide film 5 a - 5 d . Floating gate electrode 7 a - 7 c and conductor layer 25 have upper surface 16 planarized by the chemical mechanical polishing described above. The structure shown in FIG. 24 is thus obtained.
- peripheral circuitry region's resist film 24 (see FIG. 25) is removed.
- ONO film 8 is then disposed on upper and side surfaces of floating gate electrode 7 a - 7 c , an upper surface of isolation oxide film 5 a , 5 b , and upper surfaces of the peripheral circuitry region's isolation oxide film 5 c , 5 d and conductor layer 25 (see FIG. 26). As a result, the structure shown in FIG. 26 is obtained.
- gate insulation film 22 a , 22 b (see FIG. 28) is disposed in the peripheral circuitry region on substrate surface 26 (see FIG. 27). Then across the memory cell and peripheral circuitry regions on ONO film 8 (see FIG. 28) and gate insulation film 22 a , 22 b and on isolation oxide film 5 c , 5 d control gate electrode 9 is disposed. Then in the peripheral circuitry region on control gate electrode 9 a resist pattern is disposed and used as a mask in partially removing control gate electrode 9 to form gate electrode 23 a , 23 b as shown in FIG. 18. The resist film is then removed.
- FIG. 18 semiconductor device can be obtained.
- the semiconductor device is basically similar in structure to the FIG. 18 semiconductor device, except that in the FIG. 29 semiconductor device, isolation oxide film 5 a - 5 d has opposite edges 17 having a curvature similar to that of edge 17 of the FIGS. 9 and 10 semiconductor device.
- the FIG. 29 present semiconductor device in one example has the FIGS. 9 and 10 semiconductor device's characteristic-configuration and the FIG. 18 semiconductor device's characteristic configuration.
- the FIG. 29 semiconductor device can provide an effect similar to that provided by the configuration characteristic to the FIGS. 9 and 10 semiconductor device and that characteristic to the FIG. 18 semiconductor device.
- FIG. 29 semiconductor device is fabricated, as described hereinafter.
- a silicon oxide film (not shown) is disposed.
- a polysilicon film (not shown) is disposed.
- a silicon nitride film (not shown) is disposed.
- a patterned resist film is disposed on the silicon nitride film. This resist film is used as a mask in anisotropically etching the stack of the silicon nitride film, the polysilicon film and the silicon oxide film to partially remove it. The resist film is then removed.
- semiconductor substrate 1 has a main surface underlying a stack of silicon nitride film 11 (FIG. 30), polysilicon film 21 (FIG.
- semiconductor substrate 1 can have a main surface provided with trench 2 a - 2 d .
- the structure shown in FIG. 30 is thus obtained.
- trench 2 a - 2 d has an internal wall surface thermally oxidized to provide oxide film 3 (see FIG. 31).
- oxide film 3 see FIG. 31.
- FIGS. 21 - 28 steps of the present semiconductor fabrication method in the third embodiment are performed to obtain the FIG. 29 semiconductor device.
- the semiconductor device is basically similar in structure to the FIGS. 9 and 10 semiconductor device, except that isolation oxide film 5 a , 5 b provided in trench 2 a , 2 d having a width W smaller than that of trench 2 a , 2 d (FIG. 9) of the FIGS. 9 and 10 semiconductor device.
- the FIG. 32 semiconductor device has trench 2 a , 2 d having width W smaller than a minimum processing dimension in a photolithography process employed in fabricating the FIG. 32 semiconductor device. Furthermore, from a different point of view, in the FIG.
- an active region as compared to an active region's width Wa (a distance between trenches 2 a and 2 b ), an isolation width, or the trench 2 a , 2 b width W, is smaller. As such in a memory cell region an active region can effectively be used.
- semiconductor device edge 17 preferably has a curved portion with width L of 10 to 100 nm, more preferably 50 to 60 nm.
- the FIG. 32 present semiconductor device has a configuration similar to that characteristic to the FIGS. 9 and 10 semiconductor device and also has a characteristic configuration as described below: in the FIG. 32 semiconductor device, as seen in a direction of a length of floating gate electrode 7 a - 7 c , trench 2 a , 2 b has width W smaller than a minimum processing dimension in a photolithography process employed in forming trench 2 a , 2 b . In other words, as seen in the direction of the length of floating gate electrode 7 a - 7 c , trench 2 a , 2 b has width W smaller than width Wa of an active region corresponding to a distance between trenches 2 a and 2 b .
- a sidewall surface of trench 2 a , 2 b and a main surface of semiconductor substrate 1 underlying floating gate electrode 7 a - 7 c are connected by edge 17 allowing semiconductor substrate 1 to have a curved surface having width L of 10 to 100 nm as seen in a direction extending along a direction in which the semiconductor substrate 1 main surface extends.
- the semiconductor device thus configured can be as effective as the FIGS. 9 and 10 semiconductor device and also allows semiconductor substrate 1 to have a main surface occupied by trench 2 a , 2 b having a reduced area. This can provide an increased number of memory cells including floating gate electrode 7 a - 7 c , ONO film 8 and control gate 9 that are provided on a main surface of semiconductor substrate 1 per unit area.
- the semiconductor device thus allows increased degrees of integration.
- the connection located at an upper portion of trench 2 a , 2 b has a width (width L of a curved portion corresponding to a portion of a surface of the semiconductor substrate that is rounded) limited to the numerical range as described above.
- semiconductor substrate 1 can have a flat main surface and the trench 2 a , 2 b sidewall surface and the semiconductor substrate 1 main surface can be connected together by a portion having a sufficiently smoothly curved surface.
- FIG. 32 semiconductor device is fabricated, as described hereinafter.
- a silicon oxide film (not shown) is disposed on a main surface of semiconductor substrate 1 (see FIG. 33) is disposed.
- a silicon nitride film (not shown) is disposed on this silicon substrate film.
- photolithography is employed to provide a patterned resist film (not shown).
- This resist film is used as a mask in anisotropically etching the silicon nitride and oxide films to partially remove the films. Note that in anisotropically etching the films, semiconductor substrate 1 also has a main surface removed to some extent, overetched. The resist pattern is then removed. A stack of silicon nitride and oxide films 11 and 10 having an open pattern and serving as a mask layer is thus provided. As a result, the structure as shown in FIG. 33 is obtained.
- a TEOS oxide film or other similar oxide film (not shown) is disposed to extend from an upper surface of silicon nitride film 11 to an exposed main surface of semiconductor conductor substrate 1 .
- the oxide film is then anisotropically etched to be etched back to provide a sidewall oxide film 27 on a sidewall surface defining (or facing) an open pattern of silicon nitride and oxide films 11 and 10 .
- Silicon nitride and oxide films 11 and 10 stacked in layers and sidewall oxide film 27 are then used as a mask in anisotropically etching away a main surface of semiconductor substrate 1 partially.
- semiconductor substrate 1 has a main surface provided with trench 2 a , 2 b
- Trench 2 a , 2 b has a width smaller by that of sidewall oxide film 27 than that of the open pattern of silicon nitride and oxide films 11 and 10 (i.e., a distance defining the open pattern and extending between opposite sidewalls of silicon nitride and oxide films 11 and 10 ).
- the resist film used as an anisotropic etching mask to obtain the FIG. 35 structure has a pattern with a dimension corresponding approximately to a minimum processing dimension adopted in photolithography
- sidewall oxide film 27 allows trench 2 a , 2 b to have a width smaller than the minimum processing dimension adopted in photolithography.
- width W of trench 2 a , 2 b allows width W of trench 2 a , 2 b to be determined without any limitation imposed by the minimum processing dimension adopted in the photolithography employed to form the open pattern.
- a portion corresponding to a surface of semiconductor substrate 1 that is not covered with the film formed of stacked layers or sidewall oxide film 27 i.e., a portion corresponding to a surface of semiconductor substrate 1 that is anisotropically etched
- trench 2 a , 2 b can have a width smaller than the minimum processing dimension to allow the semiconductor device to be highly integrated.
- trench 2 a has an internal wall surface thermally oxidized to provide oxide film 3 (see FIG. 36). In doing so, an oxidation species disperses in sidewall oxide film 27 . This facilitates oxidation of semiconductor substrate 1 more at edge 17 than at a portion in a vicinity of a bottom wall of trench 2 a , 2 b . Thus at edge 17 semiconductor substrate 1 has a surface (an interface between semiconductor substrate 1 and oxide film 3 ) having a curvature.
- oxide film 3 (see FIG. 36) is disposed and then on oxide film 3 trench 2 a , 2 b is filled with HDP-CVD oxide film 4 (see FIG. 36).
- HDP-CVD oxide film 4 filling trench 2 a , 2 b further extends to reach an upper surface of silicon nitride film 11 .
- the structure as shown in FIG. 36 is thus obtained.
- HDP-CVD oxide film 4 (see FIG. 36) is chemically mechanically polished to planarize and thus remove a surface layer thereof.
- silicon nitride film 11 has an upper surface exposed and isolation oxide film 5 a , 5 b has a flat upper surface 12 .
- thermal phosphoric acid or a similar etchant is used to wet-etch silicon nitride film 11 (see FIG. 37) away. As a result, the structure as shown in FIG. 38 is obtained.
- tunnel insulation film 6 a - 6 c (see FIG. 40) is disposed.
- Polysilicon film 14 (see FIG. 40) is disposed on tunnel insulation film 6 a - 6 c , covering isolation oxide film 5 a , 5 b .
- FIG. 40 the structure as shown in FIG. 40 is obtained.
- Polysilicon film 14 (FIG. 40) is chemically mechanically polished to have a surface layer thereof partially removed.
- isolation oxide film 5 a , 5 b can have an exposed upper surface and floating gate electrode 7 a - 7 c (see FIG. 41) having a flat upper surface can also be formed.
- Floating gate electrode 7 a - 7 c are isolated by isolation oxide film 5 a , 5 b .
- the structure as shown in FIG. 41 is obtained.
- isolation oxide film 5 a , 5 b is wet-etched to have an upper portion thereof partially removed.
- floating gate electrode 7 a - 7 c has an exposed side surface.
- ONO film 8 (see FIG. 32) and control gate electrode 9 (see FIG. 32) are then provided to obtain such a semiconductor device as shown in FIG. 32.
- FIGS. 43 - 46 semiconductor device fabrication method can provide a semiconductor device similar in structure to the FIG. 32 semiconductor device.
- the semiconductor device fabrication method will be described.
- a silicon oxide film (not shown) is disposed on a main surface of semiconductor substrate 1 (see FIG. 43) a silicon oxide film (not shown) is disposed. On this silicon oxide film a polysilicon film (not shown) is disposed. On the polysilicon film a silicon nitride film (not shown) is disposed. On the silicon nitride film a patterned resist film (not shown) is disposed. This resist film is used as a mask in etching away the stack of the silicon nitride, polysilicon and silicon oxide films partially. The resist film is then removed. As a result, as shown in FIG. 43, there can be provided a film formed of a stack of silicon oxide film 10 , polysilicon film 21 and silicon nitride film 11 and having a pattern on a main surface of semiconductor substrate 1 .
- TEOS oxide film or any other similar oxide film (not shown) is then disposed to extend from an upper surface of silicon nitride film 11 to a main surface of silicon substrate 1 .
- the oxide film is anisotropically etched to have a portion removed.
- sidewall oxide film 27 is provided on a sidewall surface of silicon nitride film 11 , polysilicon film 21 and silicon oxide film 10 .
- Silicon nitride film 11 and sidewall oxide film 27 are then used as a mask in anisotropically etching a main surface of semiconductor substrate 1 to partially remove it, similarly as has been shown in the FIG. 35 step.
- semiconductor substrate 1 has a main surface provided with trench 2 a , 2 b .
- Trench 2 a , 2 b can have a width changed, as desired, by adjusting that of sidewall oxide film 27 , and, similarly as in the semiconductor fabrication method described in the fifth embodiment, when silicon nitride film 11 , polysilicon film 21 and silicon oxide film 10 stacked in a film provide opposite sidewall surfaces spaced by a distance approximately the same as a minimum processing dimension adopted in photolithography, sufficiently increasing sidewall oxide film 27 in width allows a width of trench 2 a , 2 b sufficiently smaller than the minimum processing dimension adopted in photolithography.
- trench 2 a , 2 b has an internal wall surface thermally oxidized to provide oxide film 3 (see FIG. 46).
- oxide film 3 As an oxidation species disperses throughout sidewall oxide film 27 , semiconductor substrate 1 is oxidized further than at the other portions.
- oxide film 3 is relatively increased in thickness and semiconductor substrate 1 has a smoothly curved surface.
- oxide film 3 HDP-CVD oxide film 4 is disposed to fill trench 2 a , 2 b and also extend to an upper surface of silicon nitride film 11 . As a result, the structure as shown in FIG. 46 is obtained.
- steps similar to the FIGS. 37 - 42 steps are performed to obtain a semiconductor device similar in structure to the FIG. 32 semiconductor device.
- FIGS. 43 - 46 semiconductor device fabrication method has the configurations characteristic to the semiconductor fabrication methods described in the second and fifth embodiments of the present invention. Thus it can be as effective as those described in the second and fifth embodiments.
Abstract
Description
- 1. Field of the Invention
- The present invention relates generally to non-volatile semiconductor memory devices and methods of fabricating the same and particularly to non-volatile semiconductor memory devices capable of providing improved electrical characteristics and methods of fabricating the same.
- 2. Description of the Background Art
- Conventionally as one example of semiconductor devices non-volatile semiconductor memory devices have been known (see Japanese Patent Laying-Open No. 8-64700 for example).
- Japanese Patent Laying-Open No. 8-64700 discloses in FIG. 3 a non-volatile semiconductor memory device including a semiconductor substrate having a main surface with predeterminedly spaced device isolating trenches internally provided with CVD oxide film forming an isolation oxide film. Between such isolation oxide films on the substrate's main surface a floating gate electrode is disposed with a tunnel oxide film posed therebetween. On the floating gate electrode a control gate electrode is disposed with an ONO film posed therebetween.
- In the above conventional non-volatile semiconductor memory device, however, the floating gate electrode has an upper surface having a protrusion and a depression reflecting a feature underlying the floating gate electrode. As such at the protrusion of the floating gate electrode (e.g., an end of the floating gate electrode) the ONO film can differ in thickness, quality and the like from the remainder or electric field concentration can occur. This results in the device having impaired electrical characteristics.
- The present invention contemplates a non-volatile semiconductor memory device exhibiting excellent electrical characteristics and a method of fabricating the same.
- The present non-volatile semiconductor memory device includes a semiconductor substrate, an isolation insulator, a floating electrode, an insulation film, and a control gate. The semiconductor substrate has a main surface provided with two spaced trenches. The isolation insulator fills the trench and has an upper surface with an end having a curvature protruding toward the semiconductor substrate. The floating electrode has a flat surface and extends from a main surface of the semiconductor substrate between the two trenches to the two isolation insulators. The insulation film extends from an upper surface of the floating electrode to a side surface of the floating gate overlying the isolation insulator. The control gate is disposed on the insulation film to extend from an upper surface of the floating electrode to a side surface of the floating electrode.
- Thus the insulation film can be disposed on a flat upper surface of the floating electrode. With the floating electrode having an upper surface free of protrusions and depressions, the insulation film can be free from local variation in thickness, characteristics and the like. With the insulation film free of variation for example in thickness, local electric field concentration can be reduced between the control electrode and the floating electrode. The reduced electrical field concentration can contribute to less impaired electrical characteristics of the semiconductor device. Furthermore, the isolation insulator having an upper surface with an end having a curvature protruding toward the semiconductor substrate, can prevent the floating electrode from having a lower portion with a protrusion having an apex of an acute angle. As a result, highly reliable and long-life semiconductor device can be implemented.
- The present semiconductor device fabrication method includes the steps of: providing a semiconductor substrate at a main surface with two spaced trenches; providing in the trench an isolation insulator having a protrusion protruding upper than a main surface of the semiconductor substrate; and isotropically etching away the protrusion partially to reduce the protrusion to be smaller in thickness than the trench. Furthermore the method includes the steps of: after the step of isotropically etching, providing the semiconductor substrate at a main surface with a conductor film extending from a region located between the two isolation insulators to the isolation insulator; removing an upper surface layer of the conductor film to expose an upper portion of the isolation insulator to provide a floating electrode formed of the conductor film, having a flat upper surface and located between the isolation insulators; and etching away an upper portion of the isolation insulator adjacent to the floating electrode to expose a side surface of the floating electrode.
- Thus photolithography can be dispensed with in providing a floating electrode between isolation insulators. Without photolithography, mask misalignment or the like is not introduced, and the floating electrode can be provided precisely in position as designed.
- The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
- In the drawings:
- FIG. 1 is a schematic cross section of the present semiconductor device in a first embodiment;
- FIGS.2-8 illustrate first to seventh steps, respectively, of a method of fabricating the FIG. 1 semiconductor device;
- FIG. 9 is a schematic cross section of the present semiconductor device in a second embodiment;
- FIG. 10 is a partially enlarged, schematic cross section of the FIG. 9 semiconductor device;
- FIGS.11-17 are schematic cross sections for illustrating first to seventh steps, respectively, of a method of fabricating the semiconductor device shown in FIGS. 9 and 10;
- FIG. 18 is a schematic cross section of the present semiconductor device in a third embodiment;
- FIGS.19-28 are schematic cross sections for illustrating first to tenth steps, respectively, of a method of fabricating the FIG. 18 semiconductor device;
- FIG. 29 is a schematic cross section of the present semiconductor device in a fourth embodiment;
- FIGS. 30 and 31 are schematic cross sections for illustrating first and second steps, respectively, of a method of fabricating the FIG. 29 semiconductor device;
- FIG. 32 is a schematic cross section of the present semiconductor device in a fifth embodiment;
- FIGS.33-42 are schematic cross sections for illustrating first to tenth steps, respectively, of a method of fabricating the FIG. 32 semiconductor device;
- FIGS.43-46 are schematic cross sections for illustrating first to fourth steps, respectively, of the present semiconductor device fabrication method in a sixth embodiment; and
- FIGS.47-49 are reference diagrams for illustrating an effect of the FIG. 1 semiconductor device.
- Hereinafter with reference to the drawings the present invention will be described in embodiments. Throughout the figures, like components are denoted by like reference characters.
- First Embodiment
- Reference will first be made to FIG. 1 to describe the present semiconductor device in a first embodiment.
- As shown in FIG. 1, the present semiconductor device is a semiconductor memory device including a
semiconductor substrate 1 having a main surface having a device formation region surrounded by an isolation oxide film. The semiconductor device in the device formation region includes spaced, conductive impurity diffusion regions (not shown) and in a region located between conductive impurity diffusion regions has a tunnel insulation film 6 a-6 c overlying a main surface ofsemiconductor substrate 1, a floating gate electrode 7 a-7 c overlying the tunnel insulation film, anONO film 8 overlying floating gate electrode 7 a-7 c, and acontrol gate electrode 9 overlyingONO film 8. The FIG. 1 semiconductor device is a non-volatile semiconductor memory device (so-called flash memory). - More specifically, as shown in FIG. 1,
semiconductor substrate 1 has a main surface provided with atrench trench oxide film 3 is disposed. Onoxide film 3trench oxide film 4.Oxide film 3 and HDP-CVD oxide film 4 form anisolation oxide film Isolation oxide film end 33 curved to protrude downward (or toward semiconductor substrate 1). - On the
semiconductor substrate 1 main surface in the device formation region tunnel insulation film 6 a-6 c is provided. Floating gate electrode 7 a-7 c extends from tunnel insulation film 6 a-6 c to anend 33 ofisolation oxide film insulative ONO film 8 is disposed. ONOfilm 8 is a film formed of a stack of the three insulation film layers of an oxide film, a nitride film and an oxide film, as seen from floating gate electrode 7 a-7 c. ONOfilm 8 extends from an upper surface of floating gate electrode 7 a-7 c to a side surface of the electrode. Furthermore,ONO film 8 also extends from a side surface of floating gate electrode 7 a-7 c to a portion of an upper surface ofisolation oxide film - Floating gate electrode7 a-7 c has an upper surface planarized to extend in a direction substantially parallel to the main surface of
semiconductor substrate 1. The floating gate electrode 7 a-7 c upper surface has an end having acorner 31 having an apex of approximately 90°. OnONO film 8control gate electrode 9 is disposed.Control gate electrode 9 extends from an upper surface of floating gate electrode 7 a-7 c to a side surface of floating gate electrode 7 a-7 c. Note thatisolation oxide film isolation oxide films - The above-described, present semiconductor device in one example has a characteristic configuration summarized as follows: the FIG. 1 semiconductor device is a non-volatile semiconductor memory device including
semiconductor substrate 1,isolation oxide film ONO film 8 serving as an insulation film, and controlgate electrode 9 serving as a control electrode.Semiconductor substrate 1 has a main surface having two spacedtrenches insulation film trench insulation film end region 33 curved to protrude toward semiconductor substrate 1 (downward). Floatinggate electrode 7 b extends from between twotrenches semiconductor substrate 1 to twoisolation oxide films ONO film 8 extends from an upper surface of floating gate electrode 7 a-7 c to a side surface of floating gate electrode 7 a-7 c located onisolation oxide film Control gate electrode 9 overliesONO film 8 to extend from an upper surface of floating gate electrode 7 a-7 c to a side surface of floating gate electrode 7 a-7 c. - Thus
ONO film 8 can overlie a flat upper surface of floating gate electrode 7 a-7 c. With floating gate electrode 7 a-7 c having an upper surface free of protrusions and depressions, theinsulative ONO film 8 can be free of local variation in thickness, characteristics and the like. This can for example address a conventional problem caused at a portion corresponding toregion 30 shown in FIG. 1:ONO film 8 free of variation for example in thickness can contribute to reduced local electrical field concentration occurring betweencontrol gate electrode 9 and floating gate electrode 7 a-7 c. The reduced local electrical field concentration can in turn contribute to less impaired electrical characteristics of the semiconductor device. As a result, the semiconductor device can be highly reliable and have a long life. - Furthermore, floating gate electrode7 a-7 c that extends to reach
isolation oxide film control gate electrode 9. Furthermore, arrangingcontrol gate electrode 9 extending from an upper surface of floating gate electrode 7 a-7 c to a side surface of floating gate electrode 7 a-7 c withONO film 8 posed therebetween can increase a capacitance (C1) betweencontrol gate electrode 9 and floating gate electrode 7 a-7 c and accordingly, a coupling ratio (α) proportional to capacitance (C1) provided betweencontrol gate electrode 9 and floating gate electrode 7 a-7 c. - Herein, coupling ratio (α) is represented by α=C1/(C1+C2), wherein C2 represents a capacitance between floating gate electrode7 a-7 c and
semiconductor substrate 1, and C1 represents a capacitance betweencontrol gate electrode 9 and floating gate electrode 7 a-7 c, as described above. Increasing coupling ratio (α) can decrease a voltage of a signal applied to controlgate electrode 9. The present semiconductor device can thus reduce a voltage of a signal applied to controlgate electrode 9. - Furthermore in the FIG. 1 semiconductor device a sidewall surface of
trench semiconductor substrate 1 that underlies floating gate electrode 7 a-7 c may be connected at a portion (connection 32) allowingsemiconductor substrate 1 to have a curved surface. Such aconnection 32 has an effect, as will be described hereinafter with reference to FIGS. 47 and 48. - As shown in FIG. 47, if a main surface of
substrate 1 underlying floatinggate 7 b and a sidewall surface oftrench 2 a are connected at a portion (connection 40), pointed as indicated by a numeral 41 (i.e.,connection 40 is not rounded) then atconnection 40 insulation between floatinggate electrode 7 b andsemiconductor substrate 1 reduces. This is because at pointed portion 41 (an angled portion) electric field concentration occurs. In contrast, FIG. 48 shows that at aconnection 32semiconductor substrate 1 has a rounded surface (i.e., such as shown in the FIG. 1 semiconductor device). This provides for a reduced possibility ofconnection 32 having electric field concentration, and hence improved insulation between floatinggate electrode 7 b andsemiconductor substrate 1. - Furthermore, as shown in FIG. 49, the present semiconductor device includes
insulation oxide film 5 a having an upper surface withend region 33 curved to protrude toward semiconductor substrate 1 (i.e., downward). Note that FIG. 49 is a schematic, partially enlarged diagram of FIG. 1. - As shown in FIG. 49, the present semiconductor device, including
isolation oxide film 5 a having an upper surface withend regions 33 curved to protrude downward, allows an upper surface of HDP-CVD oxide film 4, a constituent ofisolation oxide film 5 a, and an upper surface oftunnel insulation film 6 b to form an angle α2 larger than an angle α1 formed by upper surfaces of HDP-CVD oxide film 4 andtunnel insulation film 6 b, respectively, in the FIG. 48 semiconductor device. Note that in the FIG. 48 semiconductor device HDP-CVD oxide film 4 has an upper surface withend region 33 substantially linear as seen in cross section. That is, as shown in FIG. 49,region 33 that is curved to protrude downward, allows an upper surface of HDP-CVD oxide film 4 and that oftunnel insulation film 6 b to form large angle α2. As such in a vicinity ofconnection 32 floatinggate electrode 7 b has abottom protrusion 34 having an obtuse apex (angle α2), rather than an acute angle. Atprotrusion 34 having an apex of an obtuse angle, electric field concentration can be reduced (i.e.,tunnel insulation film 6 b can be enhanced in insulation). The semiconductor device can thus be prevented from having reduced reliability and shorter longevity attributed to electric field concentration. - The FIG. 1 semiconductor device (a non-volatile semiconductor memory device) is fabricated, as will be described hereinafter with reference to FIGS.2-8.
- Initially on a main surface of semiconductor substrate1 a silicon oxide film (not shown) is disposed. On the silicon oxide film a silicon nitride film (not shown) is disposed. On the silicon nitride and oxide films photolithography is employed to provide a patterned resist film. This resist film is used as a mask in partially etching the silicon nitride and oxide films away. The resist pattern is then removed.
Semiconductor substrate 1 thus has a main surface with patterned silicon oxide andnitride films nitride films etching semiconductor substrate 1 away. Alternatively, the substrate may be subjected to anisotropic etching other than dry etching.Semiconductor substrate 1 thus has a main surface provided with two spacedtrenches -
Trench oxide film 3 is introduced to alleviate etching-stress insemiconductor substrate 1. - Then, as shown in FIG. 4, on
oxide film 3trench CVD oxide film 4. HDP-CVD oxide film 4 is disposed to filltrench silicon nitride film 11. - Chemical mechanical polishing (CMP) is then employed to remove a portion of HDP-
CVD oxide film 4 overlying an upper surface ofsilicon nitride film 11 and also planarize anupper surface 12 of HDP-CVD oxide film 4 (see FIG. 5). Alternatively the CMP is replaced with a different planarization process. As a result,isolation oxide film CVD oxide film 4 anoxide film 3 can be obtained (FIG. 5). Thus, forming intrench semiconductor substrate 1 provides the structure shown in FIG. 5. - Wet-etching is then employed to remove silicon nitride film11 (see FIG. 5). In this wet etching, thermal phosphoric acid or the like can be used as etchant. Then as an etchant hydrogen fluoride or the like is employed to isotropically etch away an upper portion of HDP-
CVD oxide film 4 andoxide film 3 overlying a main surface of semiconductor substrate 1 (see FIG. 5), as shown in FIG. 6. Consequently, as indicated in FIG. 6 by a broken line,isolation oxide film isolation oxide film semiconductor substrate 1. This isotropic etching also exposes a main surface ofsemiconductor substrate 1 in the device formation region. Thus by isotropically etching an upper, protruding portion ofisolation oxide film trench - Then, on a main surface of
semiconductor substrate 1 in the device formation region, tunnel insulation film 6 a-6 c (see FIG. 7) is provided. Apolysilicon film 14 serving as a conductive film (see FIG. 7) is disposed to extend from tunnel insulation film 6 a-6 c toisolation oxide film isolation oxide film trench polysilicon film 14 extending from a region of a main surface ofsemiconductor substrate 1 located between twoisolation oxide films isolation oxide film -
Polysilicon film 14 then has an upper surface layer chemically mechanically polished or subjected to a similar planarization process to have a portion removed. As a result, as shown in FIG. 7,polysilicon film 14 has anupper surface 16 receding, as indicated by anarrow 15, to expose an upper surface ofisolation oxide film isolation oxide films Conductive polysilicon film 14 thus has an upper surface layer removed to expose an upper portion ofisolation oxide film gate electrode 7 b formed ofpolysilicon film 14, having a flat upper surface and also located betweenisolation oxide films polysilicon film 14 may be replaced with amorphous silicon film. - Then between floating gate electrodes7 a-7 c
isolation oxide film isolation oxide film -
ONO film 8 is then provided to extend from upper and side surfaces of floating gate electrode 7 a-7 c to an upper surface ofisolation oxide film ONO film 8 control gate electrode 9 (see FIG. 1) is disposed. As a result can be obtained a flash memory serving as a semiconductor device structured as shown in FIG. 1. - In the FIGS.2-8 semiconductor device fabrication method, photolithography can be dispensed with and between
isolation oxide films - Furthermore,
isolation oxide film trench isolation oxide films isolation oxide film trenches isolation oxide film control gate electrode 9 to extend from an upper surface of floating gate electrode 7 a-7 c to the side surface thereof withONO film 8 posed therebetween. This can in turn increase capacitance (C1) betweencontrol gate electrode 9 and floating gate electrode 7 a-7 c. Consequently, coupling ratio (a) can be increased and the flash memory can operate with enhanced characteristics. - Second Embodiment
- With reference to FIGS. 9 and 10 the present semiconductor device in a second embodiment will be described. Note that FIG. 9 corresponds to FIG. 1.
- The FIGS. 9 and 10 semiconductor device is basically similar in structure to the FIG. 1 semiconductor device, except the geometry of a boundary between
isolation oxide film semiconductor substrate 1, i.e., the geometry of an upper portion (an edge 17) oftrench Edge 17 has a geometry, as will more specifically be described hereinafter with reference to FIG. 10. - As shown in FIG. 10,
isolation oxide film 5 a has an end, oredge 17, defined by acurved portion 19 providing a curvature connecting together aflat portion 18 defining a main surface ofsemiconductor substrate 1 and aliner portion 20 defining a side surface oftrench 2 a. Note thatliner portion 20 is a substantially linear portion of the side surface oftrench 2 a, as seen in a cross section oftrench 2 a in a direction substantially perpendicular to the main surface ofsemiconductor substrate 1.Curved portion 19 has a width L of 5 to 40 nm, more preferably 10 to 30 nm. - As shown in FIGS. 9 and 10, the present semiconductor device in one example is characterized in configuration summarized as follows: the semiconductor device is a non-volatile semiconductor memory device having the FIG. 1 semiconductor memory device's characteristic configuration plus
connection 32 between a sidewall surface oftrench semiconductor substrate 1 underlying floating gate electrode 7 a-7 c that allowssemiconductor substrate 1 to have a surface having a larger curvature. - The semiconductor device thus configured can be as effective as the FIG. 1 semiconductor device and also more reliably prevent floating gate electrode7 a-7 c from having a lower surface with
protrusion 34 located onconnection 32 and having an acute apex β. As such,protrusion 34 can be free from significant electric field concentration, which further ensures that the semiconductor device is free from impaired reliability and reduced lifetime attributed to electric field concentration. - Furthermore, in the FIGS. 9 and 10 semiconductor device,
curved portion 19, a portion of a surface ofsemiconductor substrate 1, curved as has been described above, has a width L of 5 to 40 nm as seen in a direction in which thesemiconductor substrate 1 main surface extends. -
Curved portion 19 having width L numerically ranging as described above allows a flat main surface ofsemiconductor substrate 1 at a portion adjacent to trench 2 a, 2 b and also allows a sidewall surface oftrench semiconductor substrate 1 to be connected 32 with a sufficiently smooth curvature. - With reference to FIGS.11-17, the FIGS. 9 and 10 semiconductor device (a non-volatile semiconductor device) is fabricated, as described hereinafter.
- Initially on a main surface of semiconductor substrate1 (see FIG. 11) a silicon oxide film (not shown) is disposed. On the silicon oxide film a polysilicon film (not shown) is disposed. The polysilicon film can have a thickness for example of no more than 40 nm. Furthermore, the polysilicon film's thickness is preferably 10 to 30 nm, more preferably 15 to 25 nm. On the polysilicon film a silicon nitride film (not shown) is disposed. The polysilicon film may be replaced with amorphous silicon film.
- On the silicon nitride film a patterned resist film is disposed. The resist film is used as a mask in partially removing the silicon nitride film, the polysilicon film and the silicon oxide film. The resist film is then removed. As a result,
semiconductor substrate 1 has a main surface underlying a film formed of a stack ofsilicon oxide film 10,polysilicon film 21 andsilicon nitride film 11 having an open pattern and serving as a mask layer. Thus on a main surface of semiconductor substrate a mask layer is formed that is formed of a film formed of stacked layers includingpolysilicon film 21 serving as a buffer conductive film layer and has an open pattern on a region to be provided with twotrenches Polysilicon film 21 is partially exposed at a side surface opposite to the open pattern. - The film formed of stacked layers is used as a mask in anisotropically etching away a main surface of
semiconductor substrate 1 partially. As aresult semiconductor substrate 1 has a main surface provided with twotrenches - Then, similarly as described in the FIG. 3 step,
trench polysilicon film 21 that facestrench edge 17, located at an upper portion oftrench semiconductor substrate 1 andsilicon nitride film 11, silicon oxide film extends inward from anend facing trench curved edge 17 of a surface ofsemiconductor substrate 1 in contact withoxide film 3. - Then, similarly as described in the FIG. 4 step,
trench oxide film 3 HDP-CVD oxide film 4 serving as a second oxide film (see FIG. 13) is disposed. HDP-CVD oxide film 4filling trench 2 a; 2 b also extends to an upper surface ofsilicon nitride film 11. As a result, the structure shown in FIG. 13 is obtained. - Then, similarly as described in the FIG. 5 step, HDP-CVD oxide film4 (FIG. 13) is for example chemically mechanically polished to have an upper surface layer removed. As a result, a portion of HDP-
CVD oxide film 4 overlying an upper surface ofsilicon nitride film 11 is removed and HDP-CVD oxide film 4 also has a flat upper surface 12 (see FIG. 14). The FIG. 14 structure is thus obtained. - Wet-etching is then employed to remove silicon nitride film11 (FIG. 14) and the remaining polysilicon film 21 (FIG. 11). An etchant such as hydrofluoric acid is then used to isotropically etch away an upper portion of
isolation oxide film isolation oxide film Isolation oxide film silicon oxide film 10 overlying a main surface of silicon substrate 1 (see FIG. 11) is also etched away. Thus, a protrusion corresponding to an upper portion ofisolation oxide film trench semiconductor substrate 1 and including silicon oxide film 10) is also removed. As a result, the structure shown in FIG. 15 is obtained. - In doing so, at
edge 17 of an upper portion oftrench semiconductor substrate 1 has a curved surface attributed to a bird's beak. This reduces charge concentration in the semiconductor device atedge 17, as described later. Furthermore, isotropically etching the isolation oxide film, as shown in FIG. 15, can stabilizeedge 17 in geometry. More specifically, ifisolation oxide film isolation oxide film semiconductor substrate 1 atedge 17 and an upper surface ofisolation oxide film - Then, similarly as shown in the FIG. 7 step, on a main surface of
semiconductor substrate 1 in an active region a silicon oxide film is disposed to serve as tunnel insulation film 6 a-6 b (FIG. 16). Then on tunnel insulation film 6 a-6 cisolation oxide film Polysilicon film 14 has an upper surface layer for example chemically, mechanically polished and thus removed away. As a result, as indicated in FIG. 16 by arrows,polysilicon film 14 has anupper surface 16 receding to a position indicated by a solid line. -
Isolation oxide film polysilicon film 14 is separated byisolation oxide film polysilicon film 14 forms floating gate electrode 7 a-7 c. The configuration shown in FIG. 16 is thus obtained. - Then, similarly as has been described in the FIG. 8 step,
isolation oxide film - Thereafter, ONO film8 (FIG. 9) and control gate electrode 9 (FIG. 9) are disposed to obtain the semiconductor device shown in FIGS. 9 and 10.
- Third Embodiment
- With reference to FIG. 18, the present semiconductor device in a third embodiment will be described hereinafter.
- As shown in FIG. 18, the semiconductor device is a non-volatile semiconductor memory device including a memory cell region provided with floating gate electrode7 a-7 c,
control gate electrode 9 and the like, and a peripheral circuitry region provided with field effect transistors configured ofgate electrodes gate insulation film - In the peripheral circuitry region,
semiconductor substrate 1 has a main surface provided withtrench Trench oxide film 3 disposed thereon. Onoxide film 3 HDP-CVD oxide film 4 is disposed to filltrench semiconductor substrate 1.Oxide film 3 and HDP-CVD oxide film 4 formisolation oxide film Isolation oxide film semiconductor substrate 1 has a main surface withgate insulation film gate insulation film gate insulation film b gate electrode - As can be seen from FIG. 18, a thickness T2 of
isolation oxide film isolation oxide film - The FIG. 18 present semiconductor device in one example has a characteristic configuration summarized as follows: the semiconductor device is a non-volatile semiconductor memory device having the FIG. 1 semiconductor device's characteristic configuration, characterized in that
semiconductor substrate 1 includes a memory cell region and a peripheral circuitry region. In the FIG. 18 semiconductor device, the memory cell region has formed therein a memory cell of flash memory including floating gate electrode 7 a-7 c,ONO film 8 serving as an insulation film and controlgate electrode 9. The peripheral circuitry region is a region other than the memory cell region. The peripheral circuitry region hastrench semiconductor substrate 1 to serve as another trench. The semiconductor device further includesisolation oxide film trench semiconductor substrate 1, thickness T2 ofisolation oxide film isolation oxide film - The semiconductor device thus configured can be as effective as the FIG. 1 semiconductor device and also increase isolation breakdown voltage, junction breakdown voltage of
isolation oxide film isolation oxide film 5 c having large thickness T2 hardly allows an impurity introduced after the provision ofgate electrode semiconductor substrate 1 adjacent toisolation oxide film 5 c. As a result, the semiconductor device can provide increased reliability. - With reference to FIGS.19-28 the FIG. 18 semiconductor device is fabricated, as described hereinafter.
- Initially in the semiconductor substrate1 (see FIG. 19) at the memory cell and peripheral circuitry regions on a main surface of semiconductor substrate 1 a silicon oxide film (not shown) is disposed. On this silicon oxide film a silicon nitride film (not shown) is disposed. On the silicon nitride film a patterned resist (not shown) is disposed. This resist film is used as a mask in dry-etching or similarly, anisotropically etching the silicon nitride and oxide films to remove the films partially. The resist film is then removed.
- As a result,
semiconductor substrate 1 has a main surface underlying a silicon oxide film 10 (see FIG. 19) and a silicon nitride film 11 (see FIG. 19) having an open pattern. Silicon nitride andoxide films semiconductor substrate 1 to partially remove it. As a result, as shown in FIG. 19,semiconductor substrate 1 has a main surface provided with trench 2 a-2 d. Thus the step of providingsemiconductor substrate 1 at a main surface thereof with twotrenches semiconductor substrate 1 withdifferent trenches - Then, similarly as has been shown in the FIG. 3 step, trench2 a-2 d has an internal wall surface thermally oxidized to provide oxide film 3 (see FIG. 20) to provide such a structure as shown in FIG. 20.
- Then, as shown in FIG. 21, on
oxide film 3 trench 2 a-2 d is filled with HDP-CVD oxide film 4. HDP-CVD oxide film 4 fills trench 2 a-2 d and also extends to reach an upper surface ofsilicon nitride film 11. - HDP-
CVD oxide film 4 is then chemically mechanically polished to have an upper surface layer thereof removed. This allowssilicon nitride film 11 to have an upper surface exposed and HDP-CVD oxide film 4 to have a flatupper surface 12, as shown in FIG. 22. As a result, trench 2 a-2 d is internally provided with isolation oxide film 5 a-5 d formed ofoxide film 3 and HDP-CVD oxide film 4. Thus, the step of providingisolation oxide film trench isolation oxide film semiconductor substrate 1, are performed. - Silicon nitride film11 (see FIG. 22) is then wet-etched away. Then in the peripheral circuitry region on
silicon oxide film 10 andisolation oxide film isolation oxide film - As a result,
isolation oxide film silicon oxide film 10 overlying a main surface ofsemiconductor substrate 1 is removed. - Resist
film 24 serving as a protection film can prevent the peripheral circuitry region from havingisolation oxide film semiconductor substrate 1, thickness T2 ofisolation oxide film isolation oxide film - Then in the peripheral circuitry region resist film24 (see FIG. 23) and silicon oxide film 10 (see FIG. 23) overlying a main surface of
semiconductor substrate 1 are removed. Then in the memory cell and peripheral circuitry regions on an exposed main surface ofsemiconductor substrate 1 tunnel insulation film 6 a-6 e (see FIG. 24) is disposed. On tunnel insulation film 6 a-6 e isolation oxide film 5 a-5 d is buried by polysilicon film 14 (see FIG. 24). -
Polysilicon film 14 is them chemically mechanically polished to have an upper surface layer thereof removed. This allows isolation oxide film 5 a-5 d to have an upper surface exposed and alsopolysilicon film 14 to have anupper surface 16 receding to a position indicated in FIG. 24 by a solid line. As a result, floating gate electrode 7 a-7 c and aconductive layer 25 are provided divided by isolation oxide film 5 a-5 d. Floating gate electrode 7 a-7 c andconductor layer 25 haveupper surface 16 planarized by the chemical mechanical polishing described above. The structure shown in FIG. 24 is thus obtained. - Then in the peripheral circuitry region on
isolation oxide film conductor layer 25 resist film 24 (see FIG. 25) is disposed. The intermediate product is then wet etched to partially remove an upper portion ofisolation oxide film - Then the peripheral circuitry region's resist film24 (see FIG. 25) is removed.
ONO film 8 is then disposed on upper and side surfaces of floating gate electrode 7 a-7 c, an upper surface ofisolation oxide film isolation oxide film - Then in the peripheral circuitry region ONO film8 (see FIG. 26), conductor layer 25 (see FIG. 26) and
tunnel insulation film substrate surface 26 is exposed. - Then in the peripheral circuitry region on substrate surface26 (see FIG. 27)
gate insulation film gate insulation film isolation oxide film control gate electrode 9 is disposed. Then in the peripheral circuitry region on control gate electrode 9 a resist pattern is disposed and used as a mask in partially removingcontrol gate electrode 9 to formgate electrode - Thus the FIG. 18 semiconductor device can be obtained.
- Fourth Embodiment
- With reference to FIG. 29 the present semiconductor device in a fourth embodiment will be described.
- As shown in FIG. 29, the semiconductor device is basically similar in structure to the FIG. 18 semiconductor device, except that in the FIG. 29 semiconductor device, isolation oxide film5 a-5 d has
opposite edges 17 having a curvature similar to that ofedge 17 of the FIGS. 9 and 10 semiconductor device. - The FIG. 29 present semiconductor device in one example has the FIGS. 9 and 10 semiconductor device's characteristic-configuration and the FIG. 18 semiconductor device's characteristic configuration. As such, the FIG. 29 semiconductor device can provide an effect similar to that provided by the configuration characteristic to the FIGS. 9 and 10 semiconductor device and that characteristic to the FIG. 18 semiconductor device.
- With reference to FIGS. 30 and 31 the FIG. 29 semiconductor device is fabricated, as described hereinafter.
- Initially on a main surface of semiconductor substrate1 (see FIG. 30) a silicon oxide film (not shown) is disposed. On this silicon oxide film a polysilicon film (not shown) is disposed. On this polysilicon film a silicon nitride film (not shown) is disposed. On the silicon nitride film a patterned resist film is disposed. This resist film is used as a mask in anisotropically etching the stack of the silicon nitride film, the polysilicon film and the silicon oxide film to partially remove it. The resist film is then removed. As a result,
semiconductor substrate 1 has a main surface underlying a stack of silicon nitride film 11 (FIG. 30), polysilicon film 21 (FIG. 30) and silicon oxide film 10 (FIG. 30) having an open pattern. The stack of the layers is used as a mask in anisotropically etching a main surface ofsemiconductor substrate 1 to partially remove it. As a result, as shown in FIG. 30,semiconductor substrate 1 can have a main surface provided with trench 2 a-2 d. The structure shown in FIG. 30 is thus obtained. - Then in order to alleviate etching-stress in
semiconductor substrate 1 trench 2 a-2 d has an internal wall surface thermally oxidized to provide oxide film 3 (see FIG. 31). In doing so, with the existence ofpolysilicon film 21, atedge 17 located at an upper end of trench 2 a-2 d, similarly as has been shown in the FIG. 12 step, a bird's beak extends and consequentlysemiconductor substrate 1 has a surface curved. The structure shown in FIG. 31 is thus obtained. - Thereafter the FIGS.21-28 steps of the present semiconductor fabrication method in the third embodiment are performed to obtain the FIG. 29 semiconductor device.
- Fifth Embodiment
- With reference to FIG. 32, the present semiconductor device in a fifth embodiment will be described.
- As shown in FIG. 32, the semiconductor device is basically similar in structure to the FIGS. 9 and 10 semiconductor device, except that
isolation oxide film trench trench trench trenches trench - Furthermore in the FIG. 32
semiconductor device edge 17 preferably has a curved portion with width L of 10 to 100 nm, more preferably 50 to 60 nm. - The FIG. 32 present semiconductor device has a configuration similar to that characteristic to the FIGS. 9 and 10 semiconductor device and also has a characteristic configuration as described below: in the FIG. 32 semiconductor device, as seen in a direction of a length of floating gate electrode7 a-7 c,
trench trench trench trenches trench semiconductor substrate 1 underlying floating gate electrode 7 a-7 c are connected byedge 17 allowingsemiconductor substrate 1 to have a curved surface having width L of 10 to 100 nm as seen in a direction extending along a direction in which thesemiconductor substrate 1 main surface extends. - The semiconductor device thus configured can be as effective as the FIGS. 9 and 10 semiconductor device and also allows
semiconductor substrate 1 to have a main surface occupied bytrench ONO film 8 and controlgate 9 that are provided on a main surface ofsemiconductor substrate 1 per unit area. The semiconductor device thus allows increased degrees of integration. - Furthermore, in addition to
trench trench b semiconductor substrate 1 can have a flat main surface and thetrench semiconductor substrate 1 main surface can be connected together by a portion having a sufficiently smoothly curved surface. - With reference to FIGS.33-42 the FIG. 32 semiconductor device is fabricated, as described hereinafter.
- On a main surface of semiconductor substrate1 (see FIG. 33) a silicon oxide film (not shown) is disposed. On this silicon substrate film, a silicon nitride film (not shown) is disposed. On the silicon nitride film, photolithography is employed to provide a patterned resist film (not shown). This resist film is used as a mask in anisotropically etching the silicon nitride and oxide films to partially remove the films. Note that in anisotropically etching the films,
semiconductor substrate 1 also has a main surface removed to some extent, overetched. The resist pattern is then removed. A stack of silicon nitride andoxide films - Then, a TEOS oxide film or other similar oxide film (not shown) is disposed to extend from an upper surface of
silicon nitride film 11 to an exposed main surface ofsemiconductor conductor substrate 1. The oxide film is then anisotropically etched to be etched back to provide asidewall oxide film 27 on a sidewall surface defining (or facing) an open pattern of silicon nitride andoxide films - Silicon nitride and
oxide films sidewall oxide film 27 are then used as a mask in anisotropically etching away a main surface ofsemiconductor substrate 1 partially. As a result, as shown in FIG. 35,semiconductor substrate 1 has a main surface provided withtrench Trench sidewall oxide film 27 than that of the open pattern of silicon nitride andoxide films 11 and 10 (i.e., a distance defining the open pattern and extending between opposite sidewalls of silicon nitride andoxide films 11 and 10). As such, if the resist film used as an anisotropic etching mask to obtain the FIG. 35 structure has a pattern with a dimension corresponding approximately to a minimum processing dimension adopted in photolithography,sidewall oxide film 27 allowstrench - In other words, using as a mask the
sidewall oxide film 27 provided on a sidewall facing an open pattern of a film formed of stacked layers as a mask layer, allows width W oftrench sidewall oxide film 27 in width, a portion corresponding to a surface ofsemiconductor substrate 1 that is not covered with the film formed of stacked layers or sidewall oxide film 27 (i.e., a portion corresponding to a surface ofsemiconductor substrate 1 that is anisotropically etched) can be provided with a width smaller than the minimum processing dimension as described above. As a result,trench - Then, similarly as has been shown in the FIG. 3 step, in order for example to alleviate etching-stress in
semiconductor substrate 1,trench 2 a has an internal wall surface thermally oxidized to provide oxide film 3 (see FIG. 36). In doing so, an oxidation species disperses insidewall oxide film 27. This facilitates oxidation ofsemiconductor substrate 1 more atedge 17 than at a portion in a vicinity of a bottom wall oftrench edge 17semiconductor substrate 1 has a surface (an interface betweensemiconductor substrate 1 and oxide film 3) having a curvature. - Then oxide film3 (see FIG. 36) is disposed and then on
oxide film 3trench CVD oxide film 4filling trench silicon nitride film 11. The structure as shown in FIG. 36 is thus obtained. - HDP-CVD oxide film4 (see FIG. 36) is chemically mechanically polished to planarize and thus remove a surface layer thereof. As a result, as shown in FIG. 37,
silicon nitride film 11 has an upper surface exposed andisolation oxide film upper surface 12. - Then, thermal phosphoric acid or a similar etchant is used to wet-etch silicon nitride film11 (see FIG. 37) away. As a result, the structure as shown in FIG. 38 is obtained.
- Then, fluoric acid or a similar etchant is employed to isotropically etch away
sidewall oxide film 27 andisolation oxide film silicon oxide film 10 on a main surface ofsemiconductor substrate 1 is also removed. As a result, the structure as shown in FIG. 39 is obtained. - Then in a device formation region isolated by
isolation oxide film semiconductor substrate 1 tunnel insulation film 6 a-6 c (see FIG. 40) is disposed. Polysilicon film 14 (see FIG. 40) is disposed on tunnel insulation film 6 a-6 c, coveringisolation oxide film - Polysilicon film14 (FIG. 40) is chemically mechanically polished to have a surface layer thereof partially removed. As a result, as shown in FIG. 41,
isolation oxide film isolation oxide film - Then, similarly as has been shown in the FIG. 8 step,
isolation oxide film - ONO film8 (see FIG. 32) and control gate electrode 9 (see FIG. 32) are then provided to obtain such a semiconductor device as shown in FIG. 32.
- Sixth Embodiment
- The FIGS.43-46 semiconductor device fabrication method can provide a semiconductor device similar in structure to the FIG. 32 semiconductor device. Hereinafter with reference to FIGS. 43-46 the semiconductor device fabrication method will be described.
- Initially on a main surface of semiconductor substrate1 (see FIG. 43) a silicon oxide film (not shown) is disposed. On this silicon oxide film a polysilicon film (not shown) is disposed. On the polysilicon film a silicon nitride film (not shown) is disposed. On the silicon nitride film a patterned resist film (not shown) is disposed. This resist film is used as a mask in etching away the stack of the silicon nitride, polysilicon and silicon oxide films partially. The resist film is then removed. As a result, as shown in FIG. 43, there can be provided a film formed of a stack of
silicon oxide film 10,polysilicon film 21 andsilicon nitride film 11 and having a pattern on a main surface ofsemiconductor substrate 1. - TEOS oxide film or any other similar oxide film (not shown) is then disposed to extend from an upper surface of
silicon nitride film 11 to a main surface ofsilicon substrate 1. The oxide film is anisotropically etched to have a portion removed. As a result, as shown in FIG. 44,sidewall oxide film 27 is provided on a sidewall surface ofsilicon nitride film 11,polysilicon film 21 andsilicon oxide film 10. -
Silicon nitride film 11 andsidewall oxide film 27 are then used as a mask in anisotropically etching a main surface ofsemiconductor substrate 1 to partially remove it, similarly as has been shown in the FIG. 35 step. As a result, as shown in FIG. 45,semiconductor substrate 1 has a main surface provided withtrench Trench sidewall oxide film 27, and, similarly as in the semiconductor fabrication method described in the fifth embodiment, whensilicon nitride film 11,polysilicon film 21 andsilicon oxide film 10 stacked in a film provide opposite sidewall surfaces spaced by a distance approximately the same as a minimum processing dimension adopted in photolithography, sufficiently increasingsidewall oxide film 27 in width allows a width oftrench - Then in order to alleviate etching-stress of
semiconductor substrate 1trench edge 17, as an oxidation species disperses throughoutsidewall oxide film 27,semiconductor substrate 1 is oxidized further than at the other portions. As a result, atedge 17oxide film 3 is relatively increased in thickness andsemiconductor substrate 1 has a smoothly curved surface. Then onoxide film 3 HDP-CVD oxide film 4 is disposed to filltrench silicon nitride film 11. As a result, the structure as shown in FIG. 46 is obtained. - Then steps similar to the FIGS.37-42 steps are performed to obtain a semiconductor device similar in structure to the FIG. 32 semiconductor device.
- Thus the FIGS.43-46 semiconductor device fabrication method has the configurations characteristic to the semiconductor fabrication methods described in the second and fifth embodiments of the present invention. Thus it can be as effective as those described in the second and fifth embodiments.
- Although the present invention has been described and illustrate in detail, it is already understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.
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Also Published As
Publication number | Publication date |
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KR20040067796A (en) | 2004-07-30 |
CN1286179C (en) | 2006-11-22 |
US20090017594A1 (en) | 2009-01-15 |
CN1518110A (en) | 2004-08-04 |
KR100558722B1 (en) | 2006-03-10 |
JP2004228421A (en) | 2004-08-12 |
US6906378B2 (en) | 2005-06-14 |
TW200414514A (en) | 2004-08-01 |
US20050221559A1 (en) | 2005-10-06 |
TWI325171B (en) | 2010-05-21 |
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