US20040100844A1 - Differential charge transfer sense amplifier - Google Patents
Differential charge transfer sense amplifier Download PDFInfo
- Publication number
- US20040100844A1 US20040100844A1 US10/305,703 US30570302A US2004100844A1 US 20040100844 A1 US20040100844 A1 US 20040100844A1 US 30570302 A US30570302 A US 30570302A US 2004100844 A1 US2004100844 A1 US 2004100844A1
- Authority
- US
- United States
- Prior art keywords
- gate
- biased
- pmosfet
- pmosfets
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/065—Differential amplifiers of latching type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
Definitions
- the present invention relates to memory circuits, and more specifically, to sense amplifiers for SRAM (Static Random Access Memory).
- SRAM Static Random Access Memory
- microprocessor die 102 comprises many sub-blocks, such as arithmetic logic unit (ALU) 104 and on-die cache 106 .
- ALU arithmetic logic unit
- Microprocessor 102 may also communicate to other levels of cache, such as off-die cache 108 .
- Higher memory hierarchy levels, such as system memory 110 are accessed via host bus 112 and chipset 114 .
- other off-die functional units such as graphics accelerator 116 and network interface controller (NIC) 118 , to name just a few, may communicate with microprocessor 102 via appropriate busses or ports.
- NIC network interface controller
- SRAM Static Random Access Memory
- Other components in the computer system of FIG. 1 may also use SRAM to store data.
- the bit of information stored within a memory cell of a SRAM is read by sensing the voltage developed on two complementary bitlines.
- An example of a sense amplifier for sensing the bitline voltages is provided in FIG. 2.
- Complementary bitlines 202 and 204 are connected to the sense amplifier by column-select transistors 206 and 208 . These column-select transistors are turned ON by driving column-select line 210 LOW.
- pre-charge line 212 is driven LOW so that pMOSFETs 214 , 216 , and 218 charge bitlines 202 and 204 to V DD (HIGH).
- Transistors 220 , 222 , 224 , and 226 are cross-coupled inverters, which are enabled by driving enable line 228 HIGH.
- the selected memory cell will discharge one of the two complementary bitlines such that the pMOSFET in one of the two cross-coupled inverters switches ON, whereupon the cross-coupled inverters latch the data read from the selected memory cell.
- bitline 202 stays HIGH and bitline 204 goes LOW.
- bitlines are pre-charged HIGH
- pMOSFET 203 is ON
- nMOSFETs 222 and 226 are ON and their sources and drains are HIGH
- pMOSFETs 220 and 224 are OFF.
- pre-charge line 212 is driven HIGH
- enable line 228 is driven HIGH so that pMOSFET 230 switches OFF and nMOSFET 232 switches ON.
- bitline 202 Current will flow through bitline 202 from a HIGH (V DD ) potential to a LOW (V SS ) potential through nMOSFETs 222 and 232 for some time interval.
- the charge stored by the total capacitance connected to node 234 is discharged via bitline 204 to the memory cell and also the path comprising nMOSFET 226 and 232 .
- bitline 204 Eventually node 234 is discharged to the point where pMOSFET 220 starts to switch ON and nMOSFET 222 starts to switch OFF.
- Bitline 204 will continue to discharge LOW.
- FIG. 1 is a prior art computer system.
- FIG. 2 is a prior art sense amplifier for a SRAM.
- FIG. 3 is an embodiment of the present invention.
- a first supply rail 302 is at a voltage V DD
- a second supply rail 304 is at a voltage V SS , where V SS ⁇ V DD .
- supply rail is in general some kind of conductive material, such as a copper interconnect, power plane, doped polysilicon, or the integrated circuit substrate itself upon which the circuit of FIG. 3 is formed.
- the voltage V SS of supply rail 304 may not necessarily refer to the substrate voltage, and it may or may not necessarily be a ground voltage by which other voltages are referenced to.
- a bias circuit 306 provides a bias voltage V B to the gates of pMOSFETs 308 and 310 , where V SS ⁇ V B ⁇ (V DD ⁇
- Column-select line 344 for the selected memory cell is driven LOW so that column-select pMOSFETs 346 and 348 switch ON to connect the selected memory cell to the sense amplifier.
- pre-charge line 326 is LOW.
- pre-charge line 326 LOW With pre-charge line 326 LOW, pMOSFETs 328 , 330 , and 332 are ON to pre-charge HIGH bitlines 340 and 342 , the sources and drains of column-select transistors 346 and 348 , the sources of pMOSFETs 308 and 310 , and the interconnects therebetween. Also, pMOSFETs 334 , 336 , and 338 are ON to pre-charge HIGH the drains of pMOSFETs 308 and 310 , the sources of pMOSFETs 356 and 358 , and the interconnects therebetween.
- a first inverter comprises pMOSFET 312 and nMOSFET 314 , and pMOSFET 316 and nMOSFET 318 form a second inverter, where the first and second inverters are cross-coupled to form a latch.
- enable line 320 is HIGH to switch ON nMOSFETs 352 and 354 so that nodes 322 and 324 are LOW. (Nodes 322 and 324 may be viewed as either the input ports or the output ports of the cross-coupled first and second inverters.)
- pre-charge line 326 is driven HIGH so that pMOSFETs 328 , 330 , 332 , 334 , 336 , and 338 are OFF.
- enable line 320 is driven LOW so that nMOSFETs 352 and 354 switch OFF, pMOSFETs 356 and 358 switch ON to couple the selected memory cell to the nodes (ports) 322 and 324 of the latch, and pMOSFET 350 switches ON to enable the latch.
- nodes 322 and 324 are LOW but the bitlines have been charged HIGH.
- Both gate-biased pMOSFETs 308 and 310 are in their triode regions because their initial drain-to-source voltages are close to zero.
- a second capacitor defined by bitline 342 , the diffusion capacitances of pMOSFETs 348 and 310 , the interconnects between pMOSFETs 348 and 310 and between pMOSFETs 310 and 358 , the diffusion capacitance seen at the source of pMOSFET 358 , and the diffusion capacitances of other column-select transistors that may be connected to gate-biased pMOSFET 310 will store a second charge during the pre-charge phase.
- this second capacitor will start to discharge to V SS supply rail 304 via the selected memory cell, causing the voltage potential of the source of gate-biased pMOSFET 310 to fall. As this voltage potential approaches V B +
- enable line 320 is driven LOW to switch ON pMOSFETs 356 and 358 .
- the interval of time between driving pre-charge line 326 HIGH to end the pre-charge phase and driving enable line 320 LOW to begin the enable phase should, in a preferred embodiment, be at least that interval of time for which the voltage potential at the source of gate-biased pMOSFET 358 approaches V B +
- the capacitance of the third capacitor is much smaller than that of the first capacitor.
- the voltage at node 322 will initially rise much faster than that of node 324 .
- nMOSFET 318 will kick in, which will start to discharge node 324 , so that node 324 is eventually pulled to Vss and may not even have a chance to rise all the way to V DD C T3 /C L .
- bitline 342 As discussed above, as the voltage potential at the source of gate-biased pMOSFET 310 approaches V B +
- the speed of the charge transfer to node 322 increases with increasing first capacitance.
- the first capacitance increases as the number of bitlines multiplexed to the sense amplifier via column-select transistors increases.
- the speed of the sense amplifier of FIG. 3 is expected to increase as the number of multiplexed bitlines increases. This is in contrast to the prior art sense amplifier of FIG. 2, where its speed decreases as the number of multiplexed bitlines increases.
- latches other than that shown in FIG. 3 may be used.
- other types of pass transistors may be used in place of pMOSFETs 356 and 358 , or nMOSFETs 352 and 354 .
- a nMOSFET may be used in place of pMOSFET 356 or pMOSFET 358 , where the gate of the nMOSFET is driven so that the nMOSFET is OFF during the pre-charge phase and switches ON during the enable phase.
- a pMOSFET may be used in place of nMOSFET 352 or nMOSFET 354 , where the gate of the pMOSFET is driven so that the pMOSFET is ON during the pre-charge phase and switches OFF during the enable phase.
- pass transistor may be used in place of pMOSFET 356 , pMOSFET 358 , nMOSFET 352 , or nMOSFET 354 , provided it is understood that any pass transistors substituted for nMOSFETs 352 or 354 are ON during the pre-charge phase and OFF during the enable phase, and any pass transistors substituted for pMOSFETs 356 or 358 are OFF during the pre-charge phase and are ON during the enable phase.
Landscapes
- Static Random-Access Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
- The present invention relates to memory circuits, and more specifically, to sense amplifiers for SRAM (Static Random Access Memory).
- Consider a computer system, such as that illustrated in FIG. 1. In FIG. 1, microprocessor die102 comprises many sub-blocks, such as arithmetic logic unit (ALU) 104 and on-
die cache 106.Microprocessor 102 may also communicate to other levels of cache, such as off-die cache 108. Higher memory hierarchy levels, such assystem memory 110, are accessed viahost bus 112 andchipset 114. In addition, other off-die functional units, such asgraphics accelerator 116 and network interface controller (NIC) 118, to name just a few, may communicate withmicroprocessor 102 via appropriate busses or ports. - Advanced microprocessors use large SRAM (Static Random Access Memory)caches with fast read/write operations to store data and instructions. Other components in the computer system of FIG. 1 may also use SRAM to store data. The bit of information stored within a memory cell of a SRAM is read by sensing the voltage developed on two complementary bitlines. An example of a sense amplifier for sensing the bitline voltages is provided in FIG. 2.
Complementary bitlines select transistors select line 210 LOW. Before a read operation is performed, pre-chargeline 212 is driven LOW so thatpMOSFETs charge bitlines Transistors - After pre-charge, when the column-select transistors are ON and the cross-coupled inverters are enabled, the selected memory cell will discharge one of the two complementary bitlines such that the pMOSFET in one of the two cross-coupled inverters switches ON, whereupon the cross-coupled inverters latch the data read from the selected memory cell.
- The above may be explained in more detail as follows. Suppose the data stored in the memory cell is such that during a read operation,
bitline 202 stays HIGH andbitline 204 goes LOW. Initially, both bitlines are pre-charged HIGH, pMOSFET 203 is ON,nMOSFETs pMOSFETs line 212 is driven HIGH, and enable line 228 is driven HIGH so that pMOSFET 230 switches OFF and nMOSFET 232 switches ON. Current will flow throughbitline 202 from a HIGH (VDD) potential to a LOW (VSS) potential throughnMOSFETs node 234 is discharged viabitline 204 to the memory cell and also thepath comprising nMOSFET node 234 is discharged to the point where pMOSFET 220 starts to switch ON and nMOSFET 222 starts to switch OFF. Bitline 204 will continue to discharge LOW. - As discussed above, there is some portion of time for which current flows from the VDD potential to the VSS potential through
bitline 202. This results in wasted power. Also, a sufficient amount of charge must be dumped to ground so thatnode 234 is brought to the point where pMOSFET 220 starts to switch ON and nMOSFET 222 starts to switch OFF. In practice, to multiplex multiple bitlines to the sense amplifier, there will be multiple column-select pMOSFETs of thetype pMOSFET 204 connected tonode 234 which contributes to the total capacitance seen bynode 234. As this total capacitance increases, the evaluation time also increases, thereby slowing down the read operation. - In high performance microprocessors, it is desirable for caches to waste as little energy as possible during a read operation, and for the read operation to be fast.
- FIG. 1 is a prior art computer system.
- FIG. 2 is a prior art sense amplifier for a SRAM.
- FIG. 3 is an embodiment of the present invention.
- Before discussing the operation of the sense amplifier in FIG. 3, the three different voltages appearing in the circuit are discussed. A
first supply rail 302 is at a voltage VDD, and asecond supply rail 304 is at a voltage VSS, where VSS<VDD. It is to be understood that the term “supply rail” is in general some kind of conductive material, such as a copper interconnect, power plane, doped polysilicon, or the integrated circuit substrate itself upon which the circuit of FIG. 3 is formed. The voltage VSS ofsupply rail 304 may not necessarily refer to the substrate voltage, and it may or may not necessarily be a ground voltage by which other voltages are referenced to. A bias circuit 306 provides a bias voltage VB to the gates ofpMOSFETs pMOSFETs pMOSFETs pMOSFETs - Column-
select line 344 for the selected memory cell is driven LOW so that column-selectpMOSFETs line 326 is LOW. Withpre-charge line 326 LOW,pMOSFETs HIGH bitlines select transistors pMOSFETs pMOSFETs pMOSFETs pMOSFETs - A first inverter comprises pMOSFET312 and nMOSFET 314, and pMOSFET 316 and nMOSFET 318 form a second inverter, where the first and second inverters are cross-coupled to form a latch. During the pre-charge phase, enable
line 320 is HIGH to switch ONnMOSFETs nodes Nodes - After pre-charge, and before a read operation begins, pre-charge
line 326 is driven HIGH so thatpMOSFETs pre-charge line 326 is driven HIGH, enableline 320 is driven LOW so thatnMOSFETs pMOSFETs - To describe in more detail the operation of the embodiment in FIG. 3, and how the time interval between driving pre-charge
line 326 HIGH and driving enableline 320 LOW is determined, assume for the rest of the description that the stored information in the selected memory cell is such that the selected memorycell couples bitline 340 to VDD supply rail 302 andcouples bitline 342 to VSS supply rail 304. - At the end of the pre-charge phase,
nodes biased pMOSFETs bitline 340, the diffusion capacitances ofpMOSFETs pMOSFETs pMOSFETs pMOSFET 356, and the diffusion capacitances of other column-select transistors that may be connected to gate-biased pMOSFET 308, will store a first charge during the pre-charge phase. - Likewise, a second capacitor defined by
bitline 342, the diffusion capacitances ofpMOSFETs pMOSFETs pMOSFETs pMOSFET 358, and the diffusion capacitances of other column-select transistors that may be connected to gate-biased pMOSFET 310, will store a second charge during the pre-charge phase. When the pre-charge phase ends, this second capacitor will start to discharge to VSS supply rail 304 via the selected memory cell, causing the voltage potential of the source of gate-biased pMOSFET 310 to fall. As this voltage potential approaches VB+|VT|, gate-biased pMOSFET 310 will go into its sub-threshold region. This effectively cuts off most of the second capacitor from the source of pMOSFET 358. - When the voltage potential at the source of gate-
biased pMOSFET 358 approaches VB+|VT|, enableline 320 is driven LOW to switch ONpMOSFETs line 326 HIGH to end the pre-charge phase and driving enableline 320 LOW to begin the enable phase should, in a preferred embodiment, be at least that interval of time for which the voltage potential at the source of gate-biased pMOSFET 358 approaches VB+|VT| once pre-chargeline 326 has been driven HIGH. - When enable
line 320 is driven LOW to switch ONpMOSFET 356, most of the first charge will transfer tonode 322, thereby raising the voltage ofnode 322. A third capacitor defined by the diffusion capacitance seen at the source ofpMOSFET 358, the diffusion capacitance seen at the drain of gate-biased pMOSFET 310, and the capacitance due to that portion of the interconnect between the source ofpMOSFET 358 and the drain of gate-biased pMOSFET 310, will store a third charge during the pre-charge phase. When the pre-charge phase has ended and the enableline 320 is driven LOW to switch ONpMOSFET 358, the third capacitor will start to transfer some of the third charge tonode 324. This will start to raise the voltage atnode 324. - The capacitance of the third capacitor is much smaller than that of the first capacitor. As a result, when
pMOSFETs node 322 will initially rise much faster than that ofnode 324. Even if the latch comprising the cross-coupled inverters were not present, the voltage atnode 322 would quickly charge to VDDCT1/CL, where CL is the capacitance loading the drain ofpMOSFET 356, and CT1 is given by 1/CT1=(1/C1+1/CL) where C1 is the capacitance of the first capacitor. Because C1 is relatively large, the voltage VDDCT1/CL is close to VDD. (The voltage atnode 322 would eventually continue to rise all the way to VDD because of the selected memorycell pulling bitline 340 to VDD.) But with the latch present,pMOSFET 312 will also chargenode 322, which further speeds up the process of chargingnode 322 to VDD. - If the cross-coupled inverters were not present, the voltage at
node 324 would rise no higher than VDDCT3/CL, where for simplicity the same symbol CL is used for the capacitance loading the drain ofpMOSFET 358, which substantially equals the capacitance loading the drain ofpMOSFET 356, and CT3 is given by 1/CT3=(1/C3+1/CL) where C3 is the capacitance of the third capacitor. Because C3 is relatively small, the voltage VDDCT3/CL is much smaller than the voltage VDDCT1/CL. But with the cross-coupled inverters present,nMOSFET 318 will kick in, which will start to dischargenode 324, so thatnode 324 is eventually pulled to Vss and may not even have a chance to rise all the way to VDDCT3/CL. - The charge transfer scheme discussed above causes the differential voltage between
nodes inverter comprising pMOSFET 312 andnMOSFET 314 is never reached, which may further increase the speed of the latch and improve its reliability to latch to the correct value. Simulations have shown that the cross-coupled inverters in FIG. 3 latch quicker than the cross-coupled inverters of the prior art latch in FIG. 2. This increased latching speed contributes to less power consumption. Furthermore, note that unlike the prior art scheme of FIG. 2, when enableline 320 is driven LOW so thatnMOSFET 314 is OFF but pMOSFETs 312 and 350 are ON, there is no current path from the VDD potential to the VSS potential, which also helps contribute to less power consumption. - As discussed above, as the voltage potential at the source of gate-biased
pMOSFET 310 approaches VB+|VT|, gate-biasedpMOSFET 310 will go into its sub-threshold region. As a result, the charge stored onbitline 342 will discharge to VSS supply rail 304 through the selected memory cell. The nMOSFET (not shown) in the selected memory cell is relatively weak, and this discharge occurs relatively slowly. Because read operations occur relatively fast, when the next read operation is performed on this memory cell,bitline 342 may not have fully discharged. As a result, voltage swings on the bitlines may be substantially less than VDD−VSS. This reduction in bitline voltage swing also contributes to a reduction in power consumption. Simulation results have shown that this contribution to reduction in power consumption is fairly insensitive to variations in the bias voltage VB. - The speed of the charge transfer to
node 322 increases with increasing first capacitance. The first capacitance increases as the number of bitlines multiplexed to the sense amplifier via column-select transistors increases. As a result, the speed of the sense amplifier of FIG. 3 is expected to increase as the number of multiplexed bitlines increases. This is in contrast to the prior art sense amplifier of FIG. 2, where its speed decreases as the number of multiplexed bitlines increases. - Various modifications may be made to the disclosed embodiment without departing from the scope of the invention as defined below. For example, latches other than that shown in FIG. 3 may be used. Also, other types of pass transistors may be used in place of
pMOSFETs pMOSFET 356 orpMOSFET 358, where the gate of the nMOSFET is driven so that the nMOSFET is OFF during the pre-charge phase and switches ON during the enable phase. Likewise, a pMOSFET may be used in place ofnMOSFET 352 ornMOSFET 354, where the gate of the pMOSFET is driven so that the pMOSFET is ON during the pre-charge phase and switches OFF during the enable phase. - Thus, in the above description, the term “pass transistor” may be used in place of
pMOSFET 356,pMOSFET 358,nMOSFET 352, ornMOSFET 354, provided it is understood that any pass transistors substituted fornMOSFETs pMOSFETs
Claims (13)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/305,703 US6751141B1 (en) | 2002-11-26 | 2002-11-26 | Differential charge transfer sense amplifier |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/305,703 US6751141B1 (en) | 2002-11-26 | 2002-11-26 | Differential charge transfer sense amplifier |
Publications (2)
Publication Number | Publication Date |
---|---|
US20040100844A1 true US20040100844A1 (en) | 2004-05-27 |
US6751141B1 US6751141B1 (en) | 2004-06-15 |
Family
ID=32325492
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/305,703 Expired - Fee Related US6751141B1 (en) | 2002-11-26 | 2002-11-26 | Differential charge transfer sense amplifier |
Country Status (1)
Country | Link |
---|---|
US (1) | US6751141B1 (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070171747A1 (en) * | 2006-01-23 | 2007-07-26 | Freescale Semiconductor, Inc. | Memory and method for sensing data in a memory using complementary sensing scheme |
US20080170441A1 (en) * | 2007-01-12 | 2008-07-17 | Gabriele Pelli | Sense architecture |
EP2798638A4 (en) * | 2011-12-28 | 2016-05-04 | Intel Corp | Apparatus and method for improving power delivery in a memory, such as, a random access memory |
US20160247555A1 (en) * | 2015-02-23 | 2016-08-25 | Qualcomm Incorporated | P-type field-effect transistor (pfet)-based sense amplifiers for reading pfet pass-gate memory bit cells, and related memory systems and methods |
US9490760B2 (en) * | 2014-11-27 | 2016-11-08 | Chingis Technology Corporation | Self-timed differential amplifier |
US20160358645A1 (en) * | 2013-07-25 | 2016-12-08 | Renesas Electronics Corporation | Semiconductor integrated circuit device |
TWI731521B (en) * | 2019-09-04 | 2021-06-21 | 日商鎧俠股份有限公司 | Semiconductor memory device |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7113433B2 (en) * | 2005-02-09 | 2006-09-26 | International Business Machines Corporation | Local bit select with suppression of fast read before write |
US7570192B2 (en) * | 2007-01-19 | 2009-08-04 | Kenet Incorporated | Charge-domain pipelined analog-to-digital converter |
EP2106586B1 (en) * | 2007-01-23 | 2014-11-12 | Kenet, Inc. | Analog error correction for a pipelined charge-domain a/d converter |
US20200335151A1 (en) * | 2019-04-17 | 2020-10-22 | Qualcomm Incorporated | Low-power memory |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5297090A (en) * | 1990-12-13 | 1994-03-22 | Sgs-Thomson Microelectronics, Inc. | Semiconductor memory with column decoded bit line equilibrate |
US5771190A (en) * | 1996-02-23 | 1998-06-23 | Nec Corporation | Semiconductor static random access memory device having memory cells coupled to discharging line different in potential level to discharging line for write-in circuit |
US6075729A (en) * | 1997-09-05 | 2000-06-13 | Hitachi, Ltd. | High-speed static random access memory |
US6442060B1 (en) * | 2000-05-09 | 2002-08-27 | Monolithic System Technology, Inc. | High-density ratio-independent four-transistor RAM cell fabricated with a conventional logic process |
-
2002
- 2002-11-26 US US10/305,703 patent/US6751141B1/en not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5297090A (en) * | 1990-12-13 | 1994-03-22 | Sgs-Thomson Microelectronics, Inc. | Semiconductor memory with column decoded bit line equilibrate |
US5771190A (en) * | 1996-02-23 | 1998-06-23 | Nec Corporation | Semiconductor static random access memory device having memory cells coupled to discharging line different in potential level to discharging line for write-in circuit |
US6075729A (en) * | 1997-09-05 | 2000-06-13 | Hitachi, Ltd. | High-speed static random access memory |
US6442060B1 (en) * | 2000-05-09 | 2002-08-27 | Monolithic System Technology, Inc. | High-density ratio-independent four-transistor RAM cell fabricated with a conventional logic process |
Cited By (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070171747A1 (en) * | 2006-01-23 | 2007-07-26 | Freescale Semiconductor, Inc. | Memory and method for sensing data in a memory using complementary sensing scheme |
US8077533B2 (en) | 2006-01-23 | 2011-12-13 | Freescale Semiconductor, Inc. | Memory and method for sensing data in a memory using complementary sensing scheme |
US8456935B2 (en) | 2006-01-23 | 2013-06-04 | Freescale Semiconductor, Inc. | Memory and method for sensing data in a memory using complementary sensing scheme |
US20080170441A1 (en) * | 2007-01-12 | 2008-07-17 | Gabriele Pelli | Sense architecture |
US7561485B2 (en) | 2007-01-12 | 2009-07-14 | Atmel Corporation | Sense architecture |
EP2798638A4 (en) * | 2011-12-28 | 2016-05-04 | Intel Corp | Apparatus and method for improving power delivery in a memory, such as, a random access memory |
US20160358645A1 (en) * | 2013-07-25 | 2016-12-08 | Renesas Electronics Corporation | Semiconductor integrated circuit device |
US9830977B2 (en) * | 2013-07-25 | 2017-11-28 | Renesas Electronics Corporation | Semiconductor integrated circuit device |
US9947393B2 (en) | 2013-07-25 | 2018-04-17 | Renesas Electronics Corporation | Semiconductor integrated circuit device |
US20180204613A1 (en) | 2013-07-25 | 2018-07-19 | Renesas Electronics Corporation | Semiconductor integrated circuit device |
US10304527B2 (en) | 2013-07-25 | 2019-05-28 | Renesas Electronics Corporation | Semiconductor integrated circuit device |
US10580484B2 (en) | 2013-07-25 | 2020-03-03 | Renesas Electronics Corporation | Semiconductor integrated circuit device |
US9490760B2 (en) * | 2014-11-27 | 2016-11-08 | Chingis Technology Corporation | Self-timed differential amplifier |
US20160247555A1 (en) * | 2015-02-23 | 2016-08-25 | Qualcomm Incorporated | P-type field-effect transistor (pfet)-based sense amplifiers for reading pfet pass-gate memory bit cells, and related memory systems and methods |
US10163490B2 (en) * | 2015-02-23 | 2018-12-25 | Qualcomm Incorporated | P-type field-effect transistor (PFET)-based sense amplifiers for reading PFET pass-gate memory bit cells, and related memory systems and methods |
TWI731521B (en) * | 2019-09-04 | 2021-06-21 | 日商鎧俠股份有限公司 | Semiconductor memory device |
Also Published As
Publication number | Publication date |
---|---|
US6751141B1 (en) | 2004-06-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20130286705A1 (en) | Low power content addressable memory hitline precharge and sensing circuit | |
JP3416062B2 (en) | Content addressable memory (CAM) | |
TW423218B (en) | Charge-redistribution low-swing differential logic circuit | |
Lorenzo et al. | Single bit‐line 11T SRAM cell for low power and improved stability | |
US6798688B2 (en) | Storage array such as a SRAM with reduced power requirements | |
US6952118B2 (en) | Gate-clocked domino circuits with reduced leakage current | |
US6707708B1 (en) | Static random access memory with symmetric leakage-compensated bit line | |
US6195277B1 (en) | Multiple signal detection circuit | |
US20110305099A1 (en) | Hierarchical buffered segmented bit-lines based sram | |
US6751141B1 (en) | Differential charge transfer sense amplifier | |
JPH07202679A (en) | Cmos circuit | |
JPH11510944A (en) | Charge transfer sense amplifier | |
Wang et al. | Charge recycling 8T SRAM design for low voltage robust operation | |
US6847569B2 (en) | Differential current sense amplifier | |
JPH10511796A (en) | Bit line level insensitive sense amplifier | |
JP2013218783A (en) | Accelerated single-ended sensing for memory circuit | |
US7391633B2 (en) | Accelerated searching for content-addressable memory | |
US20030012074A1 (en) | Semiconductor memory with improved soft error resistance | |
Shibata et al. | A 1-V, 10-MHz, 3.5-mW, 1-Mb MTCMOS SRAM: with charge-recycling input/output buffers | |
Gavaskar et al. | Design and analysis of 8-bit stable SRAM for ultra low power applications | |
US6084455A (en) | High-speed CMOS latch | |
US6909652B2 (en) | SRAM bit-line reduction | |
Date et al. | 1-V, 30-MHz memory-macrocell-circuit technology with a 0.5-/spl mu/m multi-threshold CMOS | |
JPH07134896A (en) | Buffer circuit of semiconductor memory device | |
JPH04326814A (en) | Logic circuit |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INTEL CORPORATION, CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ALVANDPOUR, ATILA;SINHA, MANOJ;KRISHNAMURTHY RAM K.;REEL/FRAME:013875/0496;SIGNING DATES FROM 20030127 TO 20030210 |
|
CC | Certificate of correction | ||
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
REMI | Maintenance fee reminder mailed | ||
FPAY | Fee payment |
Year of fee payment: 8 |
|
REMI | Maintenance fee reminder mailed | ||
LAPS | Lapse for failure to pay maintenance fees | ||
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20160615 |