US20030120475A1 - Method of generating asic design database - Google Patents
Method of generating asic design database Download PDFInfo
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- US20030120475A1 US20030120475A1 US10/025,788 US2578801A US2003120475A1 US 20030120475 A1 US20030120475 A1 US 20030120475A1 US 2578801 A US2578801 A US 2578801A US 2003120475 A1 US2003120475 A1 US 2003120475A1
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- rtl description
- header portion
- design
- entity
- power consumption
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
Definitions
- the present invention relates to a method of generating an ASIC design database, which is important when a large-scale integrated circuit device such as a system LSI is to be designed.
- ASIC Application Specific Integrated Circuit
- a designer In designing an ASIC (Application Specific Integrated Circuit), a designer first analyzes given design specifications, examines architecture candidates, selects a most prospective architecture, and describes the selected architecture using a hardware description language. The act of the describing is called “operation description”. The obtained operation description is an operation-level design result. The operation-level design is verified by applying an operation-level simulator or a verifier to this operation-level design result.
- RTL Register Transfer Level
- the RTL description is automatically generated from the operation description by means of an operation synthesis tool.
- the generated RTL description is also based on a hardware description language (HDL).
- HDL hardware description language
- the RT level design is verified by applying an RT level simulation tool, etc. to the RTL description.
- a net list (gate-level logic circuit description), in which the object of design is described in a gate level on the basis of the RTL description, is generated by means of a logic synthesis tool.
- the gate-level design is verified by applying a logic simulation tool, etc. to the net list, following which a floor plan is carried out.
- blocks constituting gate-level logic circuits are generally arranged and wired.
- the gate-level design represented by the net list is evaluated. Specifically, using the information on the arrangement of blocks constituting logic circuits and the information on the wiring of the blocks, the layout area, timing, power consumption, etc. are calculated.
- the specification data contains data on the process time, layout area, power consumption, test cost, etc.
- the RTL description data is an RTL description file in units of an entity.
- the object of the present invention is to provide a method of generating an ASIC design database, the method being capable of generating a database necessary for re-use design and efficient information collection, which are necessary when a large-scale integrated circuit device such as a system LSI is to be designed.
- the present invention may provide a method of generating an ASIC design database, comprising: extracting, when a function design using description data comprising a header portion and an entity portion has been performed, information necessary for reuse design from various execution results of the entity portion; writing the extracted information necessary for reuse design in the header portion of the description data; and storing, as one file at a predetermined location, the description data comprising the header portion in which the information necessary for reuse is written, and the entity portion.
- FIG. 1 is a block diagram schematically showing the structure of an IC design support apparatus according to the present invention
- FIG. 2 is a flow chart illustrating the generation of a database and operations for collecting information
- FIG. 3 shows an example of a function design using RTL description
- FIG. 4 shows an example of a simulation result
- FIG. 5 shows an example of an analysis support (area information);
- FIG. 6 shows an example of an analysis report (timing information).
- FIG. 7 shows an example of a power consumption calculation result.
- FIG. 1 schematically shows the structure of an integrated circuit design support apparatus according to an ASIC design database generating method of the present invention.
- the hardware of this IC circuit design support apparatus is a computer system such as a work station.
- the IC design support apparatus comprises a CPU 1 , a ROM 2 , a RAM 3 , a memory 4 , a hard disk drive (HDD) 5 , a display 6 , a keyboard 7 , a mouse 8 , and a printer 10 .
- the CPU 1 controls the entirety of the apparatus.
- the ROM 2 stores control programs, etc.
- the RAM 3 temporarily stores data.
- the memory 4 stores data mentioned below.
- the hard disk drive (HDD) 5 is a database to be reused for ASIC design, as will be described below in detail.
- the HDD 5 stores software tools, i.e. a simulation tool 5 a, a logic synthesis tool 5 b, a timing analysis tool 5 c, a logic simulation tool 5 d and a power consumption calculation tool 5 e, which are executed by the CPU 1 .
- the display 6 displays various information.
- the keyboard 7 and mouse 8 function as input devices.
- the printer 10 performs a print-out operation as a printing apparatus.
- FIG. 3 shows an example of the function design by RTL description according to the present invention.
- the RTL description in this invention comprises a header portion and an entity portion.
- the RTL description is written in the HDD 5 as a reuse design database.
- the CPU 1 generates a simulation result list (ST 2 ).
- the list may be printed out by the printer 10 or displayed on the display 6 .
- FIG. 4 shows an example of a simulation result.
- “#799996” represents a simulation time.
- the CPU 1 extracts the simulation time (step) from the simulation result list and writes it in the header portion of the executed RTL description (ST 3 ).
- the simulation time “#799996” nS shown in FIG. 4 is written in the header portion of the RTL description shown in FIG. 3.
- the CPU 1 inputs the entity portion of the RTL description to the logic synthesis tool 5 b and executes logic synthesis (ST 4 ), and outputs a gate-level net list (ST 5 ).
- the CPU 1 inputs the net list to the timing analysis tool 5 c and executes a timing analysis (ST 6 ), and outputs an analysis report as an analysis result (ST 7 ).
- the analysis report may be printed out by the printer 10 or displayed on the display 6 .
- FIGS. 5 and 6 show examples of the analysis report.
- FIG. 5 shows area information, and the total area is “31387.996094”.
- FIG. 6 shows timing information, and the data arrival time is “ ⁇ 7.70”.
- the CPU 1 compares the values in the analysis report with pre-input desirable specifications (conditions for design) (ST 8 ). If conditions for timing or layout area of the desirable specifications are not satisfied (area violation), the logic synthesis is executed once again (ST 4 ).
- step ST 8 the CPU 1 extracts the timing information and layout area information and writes the information in the header portion of the executed RTL description (ST 9 ).
- the layout area information “31387.996094” gate in the area information shown in FIG. 5 and the timing information “ ⁇ 7.70” ns shown in FIG. 6 are written in the header portion of the RTL description shown in FIG. 3.
- the CPU 1 executes a logic simulation for the gate-level net list by the logic simulation tool 5 d (ST 10 ).
- the CPU 1 then inputs the simulation data to the power consumption calculation tool 5 d, carries out a power consumption calculation process (ST 11 ) and outputs a power consumption calculation result list (power consumption data) (ST 12 ).
- the list may be printed out by the printer 10 or displayed on the display 6 .
- FIG. 7 shows an example of the power consumption calculation result.
- PowerAVERAGE “5.00071” is a total power consumption.
- the CPU 1 extracts power consumption information from the power consumption calculation result list and writes it in the header portion of the executed RTL description (ST 13 ).
- the power consumption “5.00071” mA in FIG. 7 is written in the header portion of the RTL description in FIG. 3.
- the CPU 1 stores the RTL description comprising the header portion and entity portion, as shown in FIG. 3, at a designated location of the HDD 5 as one file (ST 14 ).
- the processes of steps ST 1 - 3 , 4 - 9 , 10 - 13 and 14 are automated.
- the reuse design data comprises the header portion (information portion) and the RTL description portion (entity portion) and contains data in the same file.
- the reuse design database can easily be managed in a unified manner.
- the four data items i.e. simulation time, layout area, timing, and power consumption, are written in the information portion (header portion) of the database. Additionally, other necessary information may be written.
- the management of the database can easily be made by unifying the information portion (header portion) and RTL description portion (entity portion) of the database in the same file.
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
- The present invention relates to a method of generating an ASIC design database, which is important when a large-scale integrated circuit device such as a system LSI is to be designed.
- There is known a conventional design method, which uses a database in order to avoid useless repetition at the time of re-designing or disability of design, when a system LSI is to be developed.
- In designing an ASIC (Application Specific Integrated Circuit), a designer first analyzes given design specifications, examines architecture candidates, selects a most prospective architecture, and describes the selected architecture using a hardware description language. The act of the describing is called “operation description”. The obtained operation description is an operation-level design result. The operation-level design is verified by applying an operation-level simulator or a verifier to this operation-level design result.
- Based on the operation description, the designer then produces an RTL (Register Transfer Level) description in which the object of design is described in a register transfer level. The RTL description is automatically generated from the operation description by means of an operation synthesis tool. The generated RTL description is also based on a hardware description language (HDL). The RT level design is verified by applying an RT level simulation tool, etc. to the RTL description.
- Following the verification, a net list (gate-level logic circuit description), in which the object of design is described in a gate level on the basis of the RTL description, is generated by means of a logic synthesis tool. The gate-level design is verified by applying a logic simulation tool, etc. to the net list, following which a floor plan is carried out. In the floor plan for the net list, blocks constituting gate-level logic circuits are generally arranged and wired.
- Subsequently, based on the result of the floor plan, the gate-level design represented by the net list is evaluated. Specifically, using the information on the arrangement of blocks constituting logic circuits and the information on the wiring of the blocks, the layout area, timing, power consumption, etc. are calculated.
- In general, when the data mentioned above is stored, it is divided into specification data and RTL description data.
- The specification data contains data on the process time, layout area, power consumption, test cost, etc.
- The RTL description data is an RTL description file in units of an entity.
- In the methods of constituting the databases, it is necessary to perform a process for extracting the content of specifications after the design is finished. This results in useless procedures in constituting the database.
- The object of the present invention is to provide a method of generating an ASIC design database, the method being capable of generating a database necessary for re-use design and efficient information collection, which are necessary when a large-scale integrated circuit device such as a system LSI is to be designed.
- In order to achieve the object, the present invention may provide a method of generating an ASIC design database, comprising: extracting, when a function design using description data comprising a header portion and an entity portion has been performed, information necessary for reuse design from various execution results of the entity portion; writing the extracted information necessary for reuse design in the header portion of the description data; and storing, as one file at a predetermined location, the description data comprising the header portion in which the information necessary for reuse is written, and the entity portion.
- Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.
- The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred embodiments of the invention, and together with the general description given above and the detailed description of the preferred embodiments given below, serve to explain the principles of the invention.
- FIG. 1 is a block diagram schematically showing the structure of an IC design support apparatus according to the present invention;
- FIG. 2 is a flow chart illustrating the generation of a database and operations for collecting information;
- FIG. 3 shows an example of a function design using RTL description;
- FIG. 4 shows an example of a simulation result;
- FIG. 5 shows an example of an analysis support (area information);
- FIG. 6 shows an example of an analysis report (timing information); and
- FIG. 7 shows an example of a power consumption calculation result.
- An embodiment of the present invention will now be described with reference to the accompanying drawings.
- FIG. 1 schematically shows the structure of an integrated circuit design support apparatus according to an ASIC design database generating method of the present invention. The hardware of this IC circuit design support apparatus is a computer system such as a work station.
- The IC design support apparatus comprises a
CPU 1, aROM 2, aRAM 3, amemory 4, a hard disk drive (HDD) 5, adisplay 6, a keyboard 7, amouse 8, and aprinter 10. - The
CPU 1 controls the entirety of the apparatus. - The
ROM 2 stores control programs, etc. - The
RAM 3 temporarily stores data. - The
memory 4 stores data mentioned below. - The hard disk drive (HDD)5 is a database to be reused for ASIC design, as will be described below in detail. The HDD 5 stores software tools, i.e. a
simulation tool 5 a, alogic synthesis tool 5 b, atiming analysis tool 5 c, alogic simulation tool 5 d and a powerconsumption calculation tool 5 e, which are executed by theCPU 1. - The
display 6 displays various information. - The keyboard7 and
mouse 8 function as input devices. - The
printer 10 performs a print-out operation as a printing apparatus. - As regards the above-described structure, the generation of a database and operations for information collection using the IC design support apparatus will now be described with reference to a flow chart of FIG. 2.
- When a function design by RTL description made in a register transfer level has been carried out using HDL (VHDL, VERILOG) language, the
CPU 1 of the IC design support apparatus executes simulation by means of thesimulation tool 5 a stored in the HDD 5 (ST1). - FIG. 3 shows an example of the function design by RTL description according to the present invention. The RTL description in this invention comprises a header portion and an entity portion. The RTL description is written in the HDD5 as a reuse design database.
- The
CPU 1 generates a simulation result list (ST2). In this case, the list may be printed out by theprinter 10 or displayed on thedisplay 6. - FIG. 4 shows an example of a simulation result. In FIG. 4, “#799996” represents a simulation time.
- The
CPU 1 extracts the simulation time (step) from the simulation result list and writes it in the header portion of the executed RTL description (ST3). The simulation time “#799996” nS shown in FIG. 4 is written in the header portion of the RTL description shown in FIG. 3. - Subsequently, the
CPU 1 inputs the entity portion of the RTL description to thelogic synthesis tool 5 b and executes logic synthesis (ST4), and outputs a gate-level net list (ST5). - The
CPU 1 inputs the net list to thetiming analysis tool 5 c and executes a timing analysis (ST6), and outputs an analysis report as an analysis result (ST7). In this case, the analysis report may be printed out by theprinter 10 or displayed on thedisplay 6. - FIGS. 5 and 6 show examples of the analysis report. FIG. 5 shows area information, and the total area is “31387.996094”. FIG. 6 shows timing information, and the data arrival time is “−7.70”.
- The
CPU 1 compares the values in the analysis report with pre-input desirable specifications (conditions for design) (ST8). If conditions for timing or layout area of the desirable specifications are not satisfied (area violation), the logic synthesis is executed once again (ST4). - If the conditions for timing and layout area of the desirable specifications are satisfied in step ST8, the
CPU 1 extracts the timing information and layout area information and writes the information in the header portion of the executed RTL description (ST9). The layout area information “31387.996094” gate in the area information shown in FIG. 5 and the timing information “−7.70” ns shown in FIG. 6 are written in the header portion of the RTL description shown in FIG. 3. - The
CPU 1 executes a logic simulation for the gate-level net list by thelogic simulation tool 5 d (ST10). TheCPU 1 then inputs the simulation data to the powerconsumption calculation tool 5 d, carries out a power consumption calculation process (ST11) and outputs a power consumption calculation result list (power consumption data) (ST12). In this case, the list may be printed out by theprinter 10 or displayed on thedisplay 6. - FIG. 7 shows an example of the power consumption calculation result. In FIG. 7, PowerAVERAGE “5.00071” is a total power consumption.
- The
CPU 1 extracts power consumption information from the power consumption calculation result list and writes it in the header portion of the executed RTL description (ST13). The power consumption “5.00071” mA in FIG. 7 is written in the header portion of the RTL description in FIG. 3. - At last, the
CPU 1 stores the RTL description comprising the header portion and entity portion, as shown in FIG. 3, at a designated location of theHDD 5 as one file (ST14). - As has been described above, according to the embodiment, the processes of steps ST1-3, 4-9, 10-13 and 14 are automated. Thereby, the reuse design data comprises the header portion (information portion) and the RTL description portion (entity portion) and contains data in the same file. Thus, the reuse design database can easily be managed in a unified manner.
- In the above embodiment, the four data items, i.e. simulation time, layout area, timing, and power consumption, are written in the information portion (header portion) of the database. Additionally, other necessary information may be written.
- According to the above-described embodiment of the invention, there is no need to consume time in constructing a database after the completion of development of an ASIC, and efficient development can be made.
- The management of the database can easily be made by unifying the information portion (header portion) and RTL description portion (entity portion) of the database in the same file.
- Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.
Claims (7)
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US10/025,788 US20030120475A1 (en) | 2001-12-26 | 2001-12-26 | Method of generating asic design database |
US11/352,288 US7444602B2 (en) | 2001-12-26 | 2006-02-13 | Method of generating ASIC design database |
Applications Claiming Priority (1)
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US10/025,788 US20030120475A1 (en) | 2001-12-26 | 2001-12-26 | Method of generating asic design database |
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Cited By (11)
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CN100454196C (en) * | 2005-02-28 | 2009-01-21 | 株式会社东芝 | Method for verifying safety apparatus and safety apparatus verified by the same |
US20140208217A1 (en) * | 2013-01-22 | 2014-07-24 | Splunk Inc. | Interface for managing splittable timestamps across event records |
US9582557B2 (en) | 2013-01-22 | 2017-02-28 | Splunk Inc. | Sampling events for rule creation with process selection |
US20170139887A1 (en) | 2012-09-07 | 2017-05-18 | Splunk, Inc. | Advanced field extractor with modification of an extracted field |
US20170255695A1 (en) | 2013-01-23 | 2017-09-07 | Splunk, Inc. | Determining Rules Based on Text |
US10019226B2 (en) | 2013-01-23 | 2018-07-10 | Splunk Inc. | Real time indication of previously extracted data fields for regular expressions |
US10282463B2 (en) | 2013-01-23 | 2019-05-07 | Splunk Inc. | Displaying a number of events that have a particular value for a field in a set of events |
US10394946B2 (en) | 2012-09-07 | 2019-08-27 | Splunk Inc. | Refining extraction rules based on selected text within events |
US20210042118A1 (en) * | 2017-04-28 | 2021-02-11 | Tenstorrent Inc. | Processing Core with Meta Data Actuated Conditional Graph Execution |
US11651149B1 (en) | 2012-09-07 | 2023-05-16 | Splunk Inc. | Event selection via graphical user interface control |
US11972203B1 (en) | 2023-04-25 | 2024-04-30 | Splunk Inc. | Using anchors to generate extraction rules |
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US10282463B2 (en) | 2013-01-23 | 2019-05-07 | Splunk Inc. | Displaying a number of events that have a particular value for a field in a set of events |
US10019226B2 (en) | 2013-01-23 | 2018-07-10 | Splunk Inc. | Real time indication of previously extracted data fields for regular expressions |
US20170255695A1 (en) | 2013-01-23 | 2017-09-07 | Splunk, Inc. | Determining Rules Based on Text |
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Also Published As
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US20060130005A1 (en) | 2006-06-15 |
US7444602B2 (en) | 2008-10-28 |
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