US20020098649A1 - Method for fabricating a mos transistor of an embedded memory - Google Patents
Method for fabricating a mos transistor of an embedded memory Download PDFInfo
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- US20020098649A1 US20020098649A1 US09/764,330 US76433001A US2002098649A1 US 20020098649 A1 US20020098649 A1 US 20020098649A1 US 76433001 A US76433001 A US 76433001A US 2002098649 A1 US2002098649 A1 US 2002098649A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823835—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/981—Utilizing varying dielectric thickness
Definitions
- the present invention relates to a method of manufacturing a MOS transistor of an embedded memory, and more particularly, to a method of manufacturing a MOS transistor with different deposition thicknesses of the gate conductors in a memory array area and in a periphery circuit region of an embedded memory.
- FIG. 1 to FIG. 9 are cross-sectional diagrams of a prior art method for manufacturing a metal-oxide-semiconductor (MOS) transistor of an embedded memory on a semiconductor wafer 10 .
- MOS metal-oxide-semiconductor
- FIG. 1 the surface of a silicon substrate 16 is divided into a memory array area 12 and a periphery circuit region 14 , with each region separated by several shallow trench isolation (STI) structures 11 .
- the prior art method involves the formation of a dielectric layer 18 , a polysilicon layer 20 and an etching barrier layer 22 , respectively, on the surface of the semiconductor wafer 10 . Then, as shown in FIG.
- a mask layer 24 is formed over the etching barrier layer 22 in the periphery region 14 , and an isotropic wet etching process is used to remove both the etching barrier layer 22 and the polysilicon layer 20 in the memory array area 12 .
- the mask layer 24 above the etching barrier layer 22 is then removed, followed by the stripping away of the dielectric layer 18 in the memory array region 12 to expose the substrate surface 16 .
- a dielectric layer 26 is formed over the exposed substrate 16 , and serves as a gate oxide layer in the memory array area 12 .
- a polysilicon layer 28 , a tungsten silicide layer 30 and a silicon nitride layer 32 are formed, respectively, over the surface of the semiconductor wafer 10 .
- a photoresist layer 34 is deposited over the silicon nitride layer 32 and a lithographic process is performed to define gate patterns in both the memory array area 12 and the periphery circuit region 14 .
- the photoresist layer 34 as a mask, the silicon nitride layer 32 , the tungsten silicide layer 30 and the polysilicon layer 28 are then etched to expose the dielectric layer 26 in the memory array area 12 as well as the etching barrier layer 22 in the periphery circuit region 14 .
- the photoresist layer 34 is then removed, followed by the deposition of another photoresist layer 36 in the memory array area 12 to protect the gate 33 .
- the gate 33 includes the dielectric layer 26 , the polysilicon layer 28 , the tungsten silicide layer 30 and the silicon nitride layer 32 .
- the photoresist layer 36 and the silicon nitride layer 32 of the periphery circuit region 14 are used as hard masks to remove both the etching barrier layer 22 and the polysilicon layer 20 in the periphery circuit region 14 not covered by the silicon nitride layer 32 .
- the photoresist layer 36 is used again as a hard mask to remove the silicon nitride layer 32 , the tungsten silicide layer 30 and the polysilicon layer 28 in the periphery circuit region 14 .
- a gate 35 is formed in the periphery circuit region 14 , followed by the removal of the photoresist layer 36 .
- an ion implantation process is then performed to form lightly doped drains (LDD) 38 of a MOS transistor.
- LDD lightly doped drains
- a silicon nitride layer 43 is deposited over the semiconductor wafer 10 .
- An anisotropic etching process is used to remove the silicon nitride layer 43 in the periphery circuit region 14 as well as to form spacers 44 on the walls of the gate 35 structures, whereby the remaining etching barrier layer 22 is removed after the formation of the spacers 44 .
- a source 40 and drain 42 of a MOS transistor is then formed in the periphery circuit region 14 .
- a self-aligned silicide operation is carried out to form salicide layers 46 above each source 40 , drain 42 and gate 35 structure in the periphery circuit region 14 .
- SAC self-aligned contact
- a salicide process is also needed to form the salicide layer 46 on the surfaces of the source 40 , the drain 42 and the gate 35 in the periphery circuit region 14 to reduce the contact interface resistance and improve the electrical performance of the logic circuits.
- problems such as a large difference in gate height between the memory array area 12 and the periphery circuit region 14 are produced.
- a thicker polysilicon layer 20 is deposited on the semiconductor wafer 10 to avoid boron penetration from the boron doped in the NMOS gate.
- a much thicker polysilicon layer is produced than one made by an ordinary memory process. Consequently, over-hanging and void bridges are easily formed between the two adjacent gates in the memory array area 12 during the deposition of an inter-layer dielectric (ILD) layer. As a result, short circuiting may occur when an electrical connection of the contact plug is formed between the two adjacent gates with the conductors filling in the voids.
- ILD inter-layer dielectric
- the prior method of fabricating an embedded memory suffers from a serious topographical problem of the inter-layer dielectric (ILD) layer. More specifically, the prior art method encounters a problem resulting from a large difference in the height of the ILD layer between the memory array area 12 and the periphery circuit region 14 of an embedded memory.
- ILD inter-layer dielectric
- ILD inter-layer dielectric
- the method of the present invention involves first defining a memory array area and a periphery circuit region on the surface of a semiconductor wafer and to sequentially deposit a gate oxide layer, a polysilicon layer and a dielectric layer. Next, the polysilicon layer in the memory array area is implanted to form a doped polysilicon layer. Thereafter, the doped polysilicon layer in the memory array area is etched to a predetermined thickness and the dielectric layer in the memory array area is removed. A silicide layer and a protection layer are formed on the surface of the semiconductor wafer. A photo-etching-process (PEP) is used to etch portions of the protection, silicide, undoped and doped polysilicon layers to form a plurality of gates. Finally, a lightly doped drain and a spacer of each MOS transistor, and a source and drain of each MOS transistor in the periphery circuit region are formed.
- PEP photo-etching-process
- the step height difference between the periphery circuit region and the memory array area is reduced since the doped polysilicon layer in the memory array area is etched to only half the normal thickness. As a result, short-circuiting due to the formation of void bridges and boron penetration are both prevented.
- FIG. 1 to FIG. 9 are cross-sectional diagrams of manufacturing a MOS transistor of an embedded memory according to the prior art.
- FIG. 10 to FIG. 15 are cross-sectional diagrams of manufacturing a MOS transistor of an embedded memory according to the present invention.
- FIG. 10 to FIG. 15 are cross-sectional diagrams of manufacturing a MOS transistor of an embedded memory on semiconductor wafer 60 according to the present invention.
- a semiconductor wafer 60 has both a memory array area 62 and a periphery circuit region 64 defined on the surface of a silicon substrate 61 .
- the memory array area 62 comprises at least one cell-well 66
- the periphery circuit region 64 comprises at least one N-well 68 and at least one P-well 70 .
- STI shallow trench isolation
- the present invention involves first forming a dielectric layer 72 and an undoped polysilicon layer 74 on the surface of the semiconductor wafer 60 , respectively.
- a photolithographic and a P-type ion implantation process are performed to transform the undoped polysilicon layer 74 positioned above the N-well 68 into a P + doped polysilicon layer 75 .
- a photoresist layer (not shown) is formed on the surface of the semiconductor wafer 60 followed by a photholithographic, exposure and development process so that a mask layer 76 is formed above the N-well 68 in the periphery circuit region 64 .
- An etching process is performed to remove the undoped polysilicon layer 74 uncovered by the mask layer 76 down to approximately half of the total thickness of the undoped polysilicon layer 74 , which is about 1000 ⁇ 1900 angstroms ( ⁇ ).
- a N-type ion implantation process is performed on the undoped polysilicon layer 74 uncovered by the mask layer 76 , to transform the undoped polysilicon layer 74 positioned in both the memory array area 62 and on the P-well 70 in the periphery circuit region 64 into a N + doped polysilicon layer 78 .
- the N-type ion implantation process can be performed on the undoped polysilicon layer 74 , uncovered by the mask layer 76 , prior to its etching to transform the undoped polysilicon layer 74 positioned on both the memory array area 62 and the P-well 70 in the periphery circuit region 64 into the N ⁇ doped polysilicon layer 78 . Thereafter, an etching process is performed to remove the N + doped polysilicon layer 78 uncovered by the mask layer 76 down to approximately half the total thickness of the undoped polysilicon layer 74 .
- the silicon-oxy-nitride layer is used as an anti-reflection coating (ARC) layer and hence can be selectively formed or replaced by other anti-reflective materials.
- a photolithographic process is performed so as to define a plurality of gate 86 patterns in the photoresist layer 84 positioned on the surface of the semiconductor wafer 60 .
- the patterns in the photoresist layer 84 are used as a hard mask to etch the silicon nitride layer 82 , the silicon-oxy-nitride layer, the silicide layer 80 , the doped polysilicon layers 75 , 78 , and the dielectric layer 72 down to the surface underlying the dielectric layer 72 .
- at least one MOS transistor gate 86 is simultaneously formed above the cell-well 66 , the N-well 68 and the P-well 70 .
- LDD lightly doped drains
- a photolithographic process is used to define the NMOS position in the periphery circuit region 64 , followed by the use of an ion implantation process to form a source 92 and a drain 94 of the NMOS transistor on the P-well 70 .
- another photolithographic process is used to define the PMOS position in the periphery circuit region 64 followed by the use of an ion implantation process to form a source 92 and a drain 94 of the PMOS transistor on the N-well 68 .
- a metal layer (not shown) made of Co, is formed on the surface of the semiconductor wafer 60 .
- the metal layer covers the surfaces of the sources 92 and the drains 94 in the periphery circuit region 64 .
- a first rapid thermal process RTP is performed at a temperature between 400° C. and 600° C. for a duration of 10 to 50 seconds, such that a salicide layer 96 is formed on the surfaces of each source 92 and drain 94 in the periphery circuit region 64 .
- a wet etching process is then performed to remove the portions of the metal layer that do not react with the surface of the semiconductor wafer 60 .
- a second rapid thermal process is performed at a temperature between 600° C. and 800° C. for a duration of 10 to 50 seconds.
- RTP rapid thermal process
- the Co 2 Si and CoS of the salicide layer 96 react to form CoSi 2 , which has a lower resistance.
- the Co metal layer can also be replaced by a Ti, Ni, or Mo metal layer.
- the method of the present invention for manufacturing a MOS transistor of an embedded memory involves first etching the undoped polysilicon layer positioned on both the memory array area and the P-well in the periphery circuit region down to about half of the normal thickness.
- the thickness of the gates of both the pass transistor in the memory array area and the NMOS in the periphery circuit region is thus significantly reduced.
- the height difference of gates between the periphery circuit region and the memory array area is also reduced to prevent both boron penetration and short-circuiting due to the formation of void bridges.
- the height of the gates in the memory array area of the present invention is decreased by about 1000 ⁇ 1900 ⁇ . Hence, the difference in height between the periphery circuit region and the memory array area is clearly reduced. Consequently, when filling the ILD layer, the formation of void bridges between two neighboring gates due to the high aspect ratio of the gates in the memory array area is avoided.
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Abstract
Description
- 1. Field of the Invention
- The present invention relates to a method of manufacturing a MOS transistor of an embedded memory, and more particularly, to a method of manufacturing a MOS transistor with different deposition thicknesses of the gate conductors in a memory array area and in a periphery circuit region of an embedded memory.
- 2. Description of the Prior Art
- With increasing integration, the present trend of manufacturing semiconductor integrated circuits has been to integrate memory cell arrays and high-speed logic circuit elements onto a single chip. An embedded memory composed of memory arrays and logic circuits significantly reduces the circuit area and increases the signal processing speed.
- Please refer to FIG. 1 to FIG. 9. FIG. 1 to FIG. 9 are cross-sectional diagrams of a prior art method for manufacturing a metal-oxide-semiconductor (MOS) transistor of an embedded memory on a
semiconductor wafer 10. As shown in FIG. 1, the surface of asilicon substrate 16 is divided into amemory array area 12 and aperiphery circuit region 14, with each region separated by several shallow trench isolation (STI)structures 11. The prior art method involves the formation of adielectric layer 18, apolysilicon layer 20 and anetching barrier layer 22, respectively, on the surface of thesemiconductor wafer 10. Then, as shown in FIG. 2, amask layer 24 is formed over theetching barrier layer 22 in theperiphery region 14, and an isotropic wet etching process is used to remove both theetching barrier layer 22 and thepolysilicon layer 20 in thememory array area 12. - As shown in FIG. 3, the
mask layer 24 above theetching barrier layer 22 is then removed, followed by the stripping away of thedielectric layer 18 in thememory array region 12 to expose thesubstrate surface 16. As shown in FIG. 4, adielectric layer 26 is formed over the exposedsubstrate 16, and serves as a gate oxide layer in thememory array area 12. Thereafter, apolysilicon layer 28, atungsten silicide layer 30 and asilicon nitride layer 32 are formed, respectively, over the surface of thesemiconductor wafer 10. - In the next step, as shown in FIG. 5, a
photoresist layer 34 is deposited over thesilicon nitride layer 32 and a lithographic process is performed to define gate patterns in both thememory array area 12 and theperiphery circuit region 14. Using thephotoresist layer 34 as a mask, thesilicon nitride layer 32, thetungsten silicide layer 30 and thepolysilicon layer 28 are then etched to expose thedielectric layer 26 in thememory array area 12 as well as theetching barrier layer 22 in theperiphery circuit region 14. As shown in FIG. 6, thephotoresist layer 34 is then removed, followed by the deposition of anotherphotoresist layer 36 in thememory array area 12 to protect thegate 33. Thegate 33 includes thedielectric layer 26, thepolysilicon layer 28, thetungsten silicide layer 30 and thesilicon nitride layer 32. - As shown in FIG. 7, the
photoresist layer 36 and thesilicon nitride layer 32 of theperiphery circuit region 14 are used as hard masks to remove both theetching barrier layer 22 and thepolysilicon layer 20 in theperiphery circuit region 14 not covered by thesilicon nitride layer 32. Next, thephotoresist layer 36 is used again as a hard mask to remove thesilicon nitride layer 32, thetungsten silicide layer 30 and thepolysilicon layer 28 in theperiphery circuit region 14. Then, agate 35 is formed in theperiphery circuit region 14, followed by the removal of thephotoresist layer 36. - As shown in FIG. 8, an ion implantation process is then performed to form lightly doped drains (LDD)38 of a MOS transistor. Next, a
silicon nitride layer 43 is deposited over thesemiconductor wafer 10. An anisotropic etching process is used to remove thesilicon nitride layer 43 in theperiphery circuit region 14 as well as to form spacers 44 on the walls of thegate 35 structures, whereby the remainingetching barrier layer 22 is removed after the formation of thespacers 44. Asource 40 and drain 42 of a MOS transistor is then formed in theperiphery circuit region 14. Finally, as shown in FIG. 9, a self-aligned silicide operation is carried out to form salicide layers 46 above eachsource 40, drain 42 andgate 35 structure in theperiphery circuit region 14. To satisfy the requirements of process integration and production yield rate, a self-aligned contact (SAC) process is now widely used during the formation of the contact plug in thememory array area 12 to increase misalignment tolerances. However, a salicide process is also needed to form thesalicide layer 46 on the surfaces of thesource 40, thedrain 42 and thegate 35 in theperiphery circuit region 14 to reduce the contact interface resistance and improve the electrical performance of the logic circuits. As a result, problems such as a large difference in gate height between thememory array area 12 and theperiphery circuit region 14 are produced. - In addition, a
thicker polysilicon layer 20 is deposited on thesemiconductor wafer 10 to avoid boron penetration from the boron doped in the NMOS gate. When simultaneously forming thepolysilicon layer 20 in both thememory array area 12 and in theperiphery circuit region 14, a much thicker polysilicon layer is produced than one made by an ordinary memory process. Consequently, over-hanging and void bridges are easily formed between the two adjacent gates in thememory array area 12 during the deposition of an inter-layer dielectric (ILD) layer. As a result, short circuiting may occur when an electrical connection of the contact plug is formed between the two adjacent gates with the conductors filling in the voids. - In addition, the prior method of fabricating an embedded memory suffers from a serious topographical problem of the inter-layer dielectric (ILD) layer. More specifically, the prior art method encounters a problem resulting from a large difference in the height of the ILD layer between the
memory array area 12 and theperiphery circuit region 14 of an embedded memory. - It is a primary objective of the present invention to provide a method of manufacturing a MOS transistor with different deposition thicknesses of the gate conductors in a memory array area and in a periphery circuit region of an embedded memory.
- It is another objective of the present invention to provide a method of manufacturing a MOS transistor of an embedded memory to reduce the step height difference of gates between the periphery circuit region and the memory array area so as to improve planarization of an inter-layer dielectric (ILD) layer.
- It is still another objective of the present invention to provide a method of manufacturing a MOS transistor of an embedded memory to prevent the formation of void bridges between two gates when filling the ILD layer in the memory array area.
- The method of the present invention involves first defining a memory array area and a periphery circuit region on the surface of a semiconductor wafer and to sequentially deposit a gate oxide layer, a polysilicon layer and a dielectric layer. Next, the polysilicon layer in the memory array area is implanted to form a doped polysilicon layer. Thereafter, the doped polysilicon layer in the memory array area is etched to a predetermined thickness and the dielectric layer in the memory array area is removed. A silicide layer and a protection layer are formed on the surface of the semiconductor wafer. A photo-etching-process (PEP) is used to etch portions of the protection, silicide, undoped and doped polysilicon layers to form a plurality of gates. Finally, a lightly doped drain and a spacer of each MOS transistor, and a source and drain of each MOS transistor in the periphery circuit region are formed.
- According to the present invention, the step height difference between the periphery circuit region and the memory array area is reduced since the doped polysilicon layer in the memory array area is etched to only half the normal thickness. As a result, short-circuiting due to the formation of void bridges and boron penetration are both prevented.
- These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.
- FIG. 1 to FIG. 9 are cross-sectional diagrams of manufacturing a MOS transistor of an embedded memory according to the prior art.
- FIG. 10 to FIG. 15 are cross-sectional diagrams of manufacturing a MOS transistor of an embedded memory according to the present invention.
- Please refer to FIG. 10 to FIG. 15. FIG. 10 to FIG. 15 are cross-sectional diagrams of manufacturing a MOS transistor of an embedded memory on
semiconductor wafer 60 according to the present invention. Asemiconductor wafer 60 has both amemory array area 62 and aperiphery circuit region 64 defined on the surface of asilicon substrate 61. Thememory array area 62 comprises at least one cell-well 66, and theperiphery circuit region 64 comprises at least one N-well 68 and at least one P-well 70. Several shallow trench isolation (STI)structures 71 are formed to separate each region. - As shown in FIG. 10, the present invention involves first forming a
dielectric layer 72 and anundoped polysilicon layer 74 on the surface of thesemiconductor wafer 60, respectively. Next, as shown in FIG. 11, a photolithographic and a P-type ion implantation process are performed to transform theundoped polysilicon layer 74 positioned above the N-well 68 into a P+ dopedpolysilicon layer 75. Next, a photoresist layer (not shown) is formed on the surface of thesemiconductor wafer 60 followed by a photholithographic, exposure and development process so that amask layer 76 is formed above the N-well 68 in theperiphery circuit region 64. An etching process is performed to remove theundoped polysilicon layer 74 uncovered by themask layer 76 down to approximately half of the total thickness of theundoped polysilicon layer 74, which is about 1000˜1900 angstroms (Å). As shown in FIG. 12, a N-type ion implantation process is performed on theundoped polysilicon layer 74 uncovered by themask layer 76, to transform theundoped polysilicon layer 74 positioned in both thememory array area 62 and on the P-well 70 in theperiphery circuit region 64 into a N+ dopedpolysilicon layer 78. - Alternatively, the N-type ion implantation process can be performed on the
undoped polysilicon layer 74, uncovered by themask layer 76, prior to its etching to transform theundoped polysilicon layer 74 positioned on both thememory array area 62 and the P-well 70 in theperiphery circuit region 64 into the N− dopedpolysilicon layer 78. Thereafter, an etching process is performed to remove the N+ dopedpolysilicon layer 78 uncovered by themask layer 76 down to approximately half the total thickness of theundoped polysilicon layer 74. - Subsequently, as shown in FIG. 13, after removing the
mask layer 76 in theperiphery circuit region 64, asilicide layer 80 to reduce the contact interface resistance of the doped polysilicon layers 75 and 78, a silicon-oxy-nitride (SiOxNy) layer (not shown), asilicon nitride layer 82 functioning as a protection layer, and aphotoresist layer 84 are formed, respectively, on the surface of thesemiconductor wafer 60. Therein, the silicon-oxy-nitride layer is used as an anti-reflection coating (ARC) layer and hence can be selectively formed or replaced by other anti-reflective materials. - As shown in FIG. 14, a photolithographic process is performed so as to define a plurality of
gate 86 patterns in thephotoresist layer 84 positioned on the surface of thesemiconductor wafer 60. Thereafter, the patterns in thephotoresist layer 84 are used as a hard mask to etch thesilicon nitride layer 82, the silicon-oxy-nitride layer, thesilicide layer 80, the doped polysilicon layers 75, 78, and thedielectric layer 72 down to the surface underlying thedielectric layer 72. Thus, at least oneMOS transistor gate 86 is simultaneously formed above the cell-well 66, the N-well 68 and the P-well 70. - Then, as shown in FIG. 15, an ion implantation process is performed to form lightly doped drains (LDD)88 for each MOS transistor. After removing the
photoresist layer 84, a silicon nitride layer (not shown) is formed on the surface of thesemiconductor wafer 60 to cover the surface of eachgate 86, followed by an etching process to etch back portions of the silicon nitride layer as well as to form aspacer 90 on either side of eachgate 86. Thereafter, a photolithographic process is used to define the NMOS position in theperiphery circuit region 64, followed by the use of an ion implantation process to form asource 92 and adrain 94 of the NMOS transistor on the P-well 70. Next, another photolithographic process is used to define the PMOS position in theperiphery circuit region 64 followed by the use of an ion implantation process to form asource 92 and adrain 94 of the PMOS transistor on the N-well 68. - After the formation of the
source 92 and thedrain 94 of each MOS transistor in theperiphery circuit region 64, a metal layer (not shown) made of Co, is formed on the surface of thesemiconductor wafer 60. The metal layer covers the surfaces of thesources 92 and thedrains 94 in theperiphery circuit region 64. Then, a first rapid thermal process (RTP) is performed at a temperature between 400° C. and 600° C. for a duration of 10 to 50 seconds, such that asalicide layer 96 is formed on the surfaces of eachsource 92 and drain 94 in theperiphery circuit region 64. A wet etching process is then performed to remove the portions of the metal layer that do not react with the surface of thesemiconductor wafer 60. Finally, a second rapid thermal process (RTP) is performed at a temperature between 600° C. and 800° C. for a duration of 10 to 50 seconds. As a result, the Co2Si and CoS of thesalicide layer 96 react to form CoSi2, which has a lower resistance. However, the Co metal layer can also be replaced by a Ti, Ni, or Mo metal layer. - The method of the present invention for manufacturing a MOS transistor of an embedded memory involves first etching the undoped polysilicon layer positioned on both the memory array area and the P-well in the periphery circuit region down to about half of the normal thickness. The thickness of the gates of both the pass transistor in the memory array area and the NMOS in the periphery circuit region is thus significantly reduced. As a result, the height difference of gates between the periphery circuit region and the memory array area is also reduced to prevent both boron penetration and short-circuiting due to the formation of void bridges.
- In contrast to the prior art method for manufacturing a MOS transistor of an embedded memory, the height of the gates in the memory array area of the present invention is decreased by about 1000˜1900 Å. Hence, the difference in height between the periphery circuit region and the memory array area is clearly reduced. Consequently, when filling the ILD layer, the formation of void bridges between two neighboring gates due to the high aspect ratio of the gates in the memory array area is avoided.
- Those skilled in the art will readily observe that numerous modifications and alterations of the device may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
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