US20010022519A1 - Programmable logic array integrated circuit architectures - Google Patents
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1733—Controllable logic circuits
- H03K19/1735—Controllable logic circuits by wiring, e.g. uncommitted logic arrays
- H03K19/1736—Controllable logic circuits by wiring, e.g. uncommitted logic arrays in which the wiring can be modified
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1733—Controllable logic circuits
- H03K19/1737—Controllable logic circuits using multiplexers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17724—Structural details of logic blocks
- H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17736—Structural details of routing resources
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17736—Structural details of routing resources
- H03K19/17744—Structural details of routing resources for input/output signals
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17748—Structural details of configuration resources
- H03K19/1776—Structural details of configuration resources for memories
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Abstract
A programmable logic array integrated circuit device has a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of regions. The output signals of several regions share a group of drivers for applying region output signals to interconnection conductors that convey signals between regions. This conserves driver resources and increases signal routing flexibility. Various approaches can be used for configuring the interconnection conductors to also conserve interconnection conductor resources. Logic regions may be used to directly drive specific input/output cells, thereby simplifying signal routing to the I/O cells and also possibly simplifying the structure of the I/O cells (e.g., by allowing certain I/O cell functions to be performed in the associated logic region). Region output signal routing flexibility may also be enhanced to facilitate simultaneous performance of combinatorial logic and a separate “lonely register” function in modules of the regions.
Description
- This is a continuation of U.S. patent application Ser. No. 09/328,704, filed Jun. 9, 1999, which is a division of U.S. patent application Ser. No. 08/807,561, filed Feb. 28, 1997 (now U.S. Pat. No. 5,963,049), which is a continuation-in-part of U.S. patent application Ser. No. 08/442,795, filed May 17, 1995 (now U.S. Pat. No. 5,689,195) and which claims the benefit of U.S. provisional patent application No. 60/021,449, filed Jul. 10, 1996. All of these prior applications are hereby incorporated by reference herein in their entireties.
- This invention relates to programmable logic array integrated circuit devices, and more particularly to the manner in which such devices are organized.
- Programmable logic array integrated circuit devices are well known, as is shown, for example, by Cliff et al. U.S. Pat. No. 5,260,611 and Cliff et al. U.S. Pat. No. 5,689,195, both of which are hereby incorporated by reference herein. Typical devices of these general kinds include a plurality of regions of programmable logic, each region being programmable to perform any of a plurality of relatively elementary logic functions on input signals applied to the region. A network of interconnection conductors is also provided on the device for programmably conveying signals to, from, and between the logic regions. By interconnecting the logic regions in various ways, the elementary logic functions performed by the individual regions can be concatenated to perform very complex logic.
- The basic logic of the logic regions may be look-up table logic (as is discussed for the most part in the two references mentioned above), product term type logic (as is discussed for the most part in Wong et al. U.S. Pat. No. 4,871,930 (which is also hereby incorporated by reference herein)), or any other suitable type of logic. Any of these technologies may be used in the devices of this invention.
- Programmable logic devices are usually intended as general-purpose devices. The designer of the device therefore does not know how much circuitry to provide for interconnecting the logic regions of the device. Some users may require large amounts of interconnection resources, while other users may require smaller amounts of such resources. Although it is theoretically possible to provide completely universal interconnection resources (which would allow any connection to be made no matter what other connections were also required), that is generally regarded as wasteful because only a small fraction of such completely universal interconnection resources are ever likely to be used. Thus one of the problems that the designer of programmable logic devices must deal with is to devise interconnection resources that are sufficient to meet the needs of most probable applications of the device without being wastefully more than will generally be needed. It is also important to avoid requirements for passing signals through large numbers of interconnection elements because such elements tend to slow down signal transmission and therefore reduce the operating speed of the device.
- In view of the foregoing, it is an object of this invention to provide improved interconnection resources for programmable logic array integrated circuit devices.
- It is a more particular object of the invention to provide interconnection resources for programmable logic array integrated circuit devices that provide a high degree of interconnection flexibility at relatively low cost in terms of “overhead” such as space occupied by interconnection conductors, programmable interconnections and the programmable elements required to control them, etc.
- These and other objects of the invention are accomplished in accordance with the principles of the invention by grouping region output signals in groups of such signals, each of which groups has associated drivers for selectively applying signals to interconnection conductors of the device. Each driver can output any of the associated region output signals. This sharing of several drivers by several region output signals conserves driver resources and increases output signal routing flexibility.
- The regions are disposed on the device in a two-dimensional array of intersecting rows and columns of regions. Horizontal interconnection conductors are associated with and extend along each row of regions. Vertical interconnection conductors are associated with and extend along each column of regions. Region-feeding conductors are provided for bringing signals into each region. Direct programmable connections are provided from both the horizontal and vertical conductors adjacent to a region to the region-feeding conductors associated with that region to avoid the need to route signals from a vertical conductor, for example, to a horizontal conductor and then to a region-feeding conductor.
- Vertical conductors may be segmented and provided with programmable interconnections between the segments so that each segment can be used separately to provide a relatively short interconnection, or so that two (or more) segments can be interconnected to provide one relatively long interconnection.
- If the device has only a relatively small number of rows, each region output in each column may have its own dedicated vertical conductor, thereby eliminating the need for tri-state driving of the vertical conductors.
- In a device with a column of random access memory (“RAM”) usable by the user of the device (in addition to the previously described columns of programmable logic regions), greater use may be made of the vertical conductors associated with the RAM column by connecting those vertical conductors to the horizontal conductors of the device in such a way as to render the RAM column vertical conductors usable as alternate paths for transmitting signals between the rows of the device.
- To simplify the structure for routing signals to input/output (“I/O”) cells of the device, each I/O cell may always be driven directly by a particular subregion of a particular region. This may also allow the structure of the I/O cells to be simplified by performing some I/O cell functions in the associated subregions.
- An additional function for the region-feeding conductors may be to make programmable connections between various segments of segmented horizontal conductors.
- To facilitate use of subregions for both combinatorial logic and to perform a separate “lonely-register” function, both a combinatorial output and a registered output of each subregion may be connectable to conductors which can provide local or global interconnections.
- Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description of the preferred embodiments.
- FIG. 1 is a simplified schematic block diagram of a representative portion of an illustrative embodiment of a programmable logic array integrated circuit device constructed in accordance with this invention.
- FIG. 2 is a simplified schematic block diagram showing a representative portion of the device of FIG. 1 in more detail.
- FIG. 3 is similar to FIG. 2, but shows an alternative embodiment of the invention.
- FIG. 4 is similar to FIG. 1, but shows another alternative embodiment of the invention.
- FIG. 5 is similar to a portion of FIG. 2, but shows yet another alternative embodiment of the invention.
- FIG. 6 is a more simplified depiction of a structure which can be generally like that shown in FIG. 1, with another possible feature of the invention added.
- FIG. 7a is a simplified schematic block diagram showing an illustrative way in which the feature of FIG. 6 can be provided.
- FIG. 7b is similar to FIG. 7a, but shows another illustrative way of providing the feature of FIG. 6.
- FIG. 7c is also similar to FIG. 7a, but shows still another illustrative way of providing the feature of FIG. 6.
- FIG. 7d is again similar to FIG. 7a, but shows yet another illustrative way in which the feature of FIG. 6 can be provided.
- FIG. 8 is another more simplified depiction of a structure which can be generally like that shown in FIG. 1, with still another possible feature of the invention added.
- FIG. 9 is a simplified schematic block diagram of a representative portion of another illustrative embodiment of a device constructed in accordance with the invention.
- FIG. 10 is a simplified schematic block diagram of a representative portion of yet another illustrative embodiment of a device constructed in accordance with the invention.
- FIG. 11 is a simplified schematic block diagram of a representative portion of still another illustrative embodiment of a device constructed in accordance with the invention.
- FIG. 12 is a simplified schematic block diagram of a representative portion of yet another illustrative embodiment of a device constructed in accordance with the invention.
- FIG. 13 is a simplified schematic block diagram of a representative portion of still another illustrative embodiment of a device constructed in accordance with the invention.
- FIG. 14 is more detailed, but still simplified, schematic block diagram of a representative portion of FIG. 13.
- FIG. 15 is a simplified schematic block diagram of another illustrative implementation of the feature shown in FIGS. 13 and 14.
- A representative portion of an illustrative embodiment of a programmable logic array integrated
circuit device 10 constructed in accordance with this invention is shown in FIG. 1.Device 10 includes a plurality ofregions 20 of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Eachregion 20 includes a plurality ofsubregions 30 of programmable logic. In particular, in the depicted embodiment there are eightsubregions 30 in eachregion 20. Eachsubregion 30 receives a plurality of input signals on input leads 40 and is programmable to perform any of a plurality of logic functions on those input signals. For example, eachsubregion 30 may include a look-up table which is programmable to provide any logical combination of fourinputs 40 applied to the subregion. Eachsubregion 30 may produce anoutput signal 50 which can be fed back to theinputs 40 of the associatedregion 20 viaconductors 60. Programmable logic connectors (“PLCs”) 62 preferably allow any or substantially anyconductor 60 associated with aregion 20 to be connected to any or substantially anyconductor 40 associated with that region. - A plurality of
horizontal interconnection conductors 70 is associated with each row ofregions 20. Some of conductors 70 (elsewhere identified as conductors 70 a) extend along the entire length of the associated row and are therefore sometimes referred to as global horizontal (“GH”) conductors. Others of conductors 70 (elsewhere identified asconductors 70 b) extend along only either the left or right half of the associated row and are therefore sometimes referred to as half horizontal (“HH”) conductors. - A plurality of
vertical interconnection conductors 80 is associated with each column ofregions 20. In the embodiment shown in FIG. 1conductors 80 extend the entire length of the associated column and are therefore sometimes referred to as global vertical (“GV”) conductors. - A plurality of region-feeding
conductors 90 is associated with each ofregions 20. The region-feedingconductors 90 associated with eachregion 20 are programmably connectable byPLCs 72 to thehorizontal conductors 70 associated with the row that includes that region. Only a partial population ofPLCs 72 is preferably provided. For example, associated with eachregion 20 eachconductor 70 may be connectable to any of several, but substantially less than all,conductors 90. Correspondingly, eachconductor 90 may receive a signal from any of several, but substantially less than all,conductors 70. Theconductors 90 associated with eachregion 20 are programmably connectable byPLCs 92 to theconductors 40 of that region. LikePLCs 62, the population of each group ofPLCs 92 is preferably a full or substantially full population (i.e., any or substantially anyconductor 90 is connectable to any or substantially any intersecting conductor 40). Theconductors 90 associated with each region 20 (in cooperation with the associatedPLCs conductors 70 to be applied to the inputs of that region. - In addition to being fed back locally via
conductors 60, the output signals 50 of each region are applied to relatively shorthorizontal conductors 100. In the embodiment shown in FIG. 1horizontal conductors 100 extend across three adjacent columns ofregions 20. Thus the columns ofregions 20 are grouped in groups of three adjacent columns, each such group having associatedconductors 100. On the assumption that there are 24 columns ofregions 20,conductors 100 are sometimes referred to as eighth horizontal (“EH”) conductors. - The signals on
conductors 100 can be applied to the associatedconductors 70 viaPLCs 110 anddrivers 120.PLCs 110 can be alternatively controlled to apply signals on associatedconductors 80 todrivers 120 and thus toconductors 70. The signals onconductors 100 can be applied to the associatedconductors 80 viaPLCs 130 anddrivers 140.PLCs 130 can be alternatively controlled to apply signals on associatedconductors 70 todrivers 140 and thus toconductors 80.Drivers Drivers - FIG. 2 shows a representative portion of FIG. 1 in somewhat more detail to better depict the nature and extent of
resources conductors adjacent subregions 30 applies itsoutput signal 50 to a respective one of threeconductors 100 that span the threeregions 20 that include those subregions. Associated with each of these subregions is aPLC 102 that can select the signal on any one of the associatedconductors 100. The output signal of eachPLC 102 is applied to one input terminal of each of two associatedPLCs 110 and one associatedPLC 130. The other input to each pair ofPLCs 110 is a signal from one of twovertical conductors 80 that are associated with the column that includes that pair ofPLCs 110. This one-of-two selection is made by an associatedPLC 82. The other input to eachPLC 130 is a signal from a GH conductor 70 a or anHH conductor 70 b associated with the row that includes thatPLC 130. EachPLC 110 selects one of its two input signals for application to an associated driver 120 (preferably a programmable tri-state driver). The output signal of eachdriver 120 is applied to one of the associatedhorizontal conductors 70. Similarly, eachPLC 130 selects one of its two input signals for application to an associated driver 140 (again preferably a programmable tri-state device and therefore itself a PLC). The output signal of eachdriver 140 is applied to one of the associatedcolumn conductors 80. - The interconnection structure shown in the upper portion of FIG. 2 is repeated for all
other subregions 30 in the three horizontallyadjacent regions 20 that are grouped with one another byconductors 100. For example, the lower portion of FIG. 2 shows this interconnection structure for the next threesubregions 30 down from the above-described subregions. In the lower portion of FIG. 2 the connections fromdrivers 120 tohorizontal conductors 70 are not expressly shown, but they are in fact completed. Similarly, the connections fromhorizontal conductors 70 toPLCs 130 are not expressly shown, but these connections are also in fact completed. - From the foregoing, it will be apparent that each group of
conductors 100 and associated PLCs allows thesubregions 30 that output to those conductors to share a relatively large number ofdrivers subregion output 50 is given a large number of ways out tohorizontal conductors 70 and/or tovertical conductors 80. In particular, eachsubregion output 50 can get to any of sixdrivers 120 and thus to any of six horizontal conductors 70 (assuming that eachdriver 120 associated with a group of threeconductors 100 connects to a different one of the associated horizontal conductors 70). Similarly, eachsubregion output 50 can get to any of threedrivers 140, and moreover these threedrivers 140 connect tovertical conductors 80 associated with three different columns ofregions 20. The interconnection structure thus shown and described greatly increases output routing flexibility for the subregion outputs, and it does so without increasing the requirement for driver resources (such asdrivers 120 and 140). It is generally desirable to conserve driver resources because drivers tend to be relatively large and therefore space-, power-, and signal-propagation-time-consuming. In addition, the ability to useconductors 100 to convey asubregion output signal 50 to avertical conductor 80 associated with another column may help to conserve use ofhorizontal conductor 70 resources for such purposes. - Because
drivers drivers 120 b (toHH conductors 70 b) for each group of threesubregions 30, it may be possible to have only two drivers 120 a and twodrivers 120 b for each group of three subregions. - FIG. 3 shows a possible extension of the concept underlying FIGS. 1 and 2. In the alternative embodiment shown in FIG. 3
conductors 100 are additionally programmably connectable (by PLCs 104) to selectedconductors 90 associated with the threeregions 20 that are served by thoseconductors 100. This allows anysubregion output 50 in a group of threeregions 20 to be applied to the region-feedingconductors 90 of any region in that group without having to use a relatively longhorizontal conductor 70 to make such a relatively short horizontal connection. This may help further conserve the longer horizontal conductor resources represented byconductors 70. In other respects the embodiment shown in FIG. 3 may be similar to the embodiment shown in FIGS. 1 and 2. - It is preferably not necessary for each
conductor 100 to be connectable to all intersectedconductors 90 viaPLCs 104. Instead, only a partial population ofPLCs 104 may be provided. For example, eachconductor 100 may be connectable byPLCS 104 to twoconductors 90 associated with eachregion 20 in the group with which thatconductor 100 is associated. - FIG. 4 shows a possible further extension of the concepts illustrated by FIG. 3. In the illustrative embodiment shown in FIG. 4 dedicated
local feedback conductor 60 and their associatedPLCs 62 are eliminated. Instead,conductors 100 and associated PLCs 104 (as in FIG. 3) are used for all local feedback (as well as for such additional purposes as have been described above in connection with FIGS. 1-3). - Although FIGS.1-4
show regions 30 grouped byconductors 100 in groups of three, it will be understood that any level of segmentation can be employed. For example,regions 20 can be grouped in groups of four, five, or more byconductors 100 spanning such groups. Larger groups generally necessitate larger numbers ofconductors 100. - Another alternative is to have the groups of
regions 20 overlap by havingdifferent conductors 100 overlap one another. An example of this is shown in FIG. 5. In this embodiment theoutput signal 50 of eachsubregion 30 is applied to aconductor 100 which extends to theregion 20 to the left and theregion 20 to the right of the region that includes that subregion. For example, theoutput signal 50 g ofsubregion 30 g is applied toconductor 100 g which extends to thePLCs regions PLC 102 g associated withregion 20 g. - If desired, the type of construction shown in FIG. 5 can be extended as shown in FIG. 3 to have the
conductors 100 that serve a region also programmably connectable (as byPLCs 104 in FIG. 3) to the region-feedingconductors 90 associated with that region. Then if further desired, dedicatedlocal feedback conductors 60 can also be eliminated. As in the embodiments (FIGS. 1-4) in whichconductors 100 extend to mutually exclusive groups ofregions 20, any level of segmentation can be used in embodiments (like FIG. 5) in whichconductors 100 are arranged to produce overlapping groups ofregions 20. In other words, eachconductor 100 can extend to more than three regions 20 (e.g., to four or five such regions) if desired. It will be appreciated that FIG. 5 is simplified (as compared, for example, to FIG. 2) by omitting depiction of elements that are not essential for an explanation of the feature illustrated by FIG. 5. - The embodiment shown in FIG. 6 (which may have additional details as shown in any of FIGS.1-5 or in other FIGS. to be described below) shows the possible addition of
PLCs 84 between thevertical conductors 80 associated with each column ofregions 20 and the region-feedingconductors 90 associated with eachregion 20 in that column. The provision ofsuch PLCs 84 reduces or eliminates the need to usehorizontal conductors 70 to make connections from thevertical conductors 80 in a column to the region-feedingconductors 90 in that column. This conserveshorizontal conductor 70 resources for use in making longer-distance horizontal connections. Only a partial population ofPLCs 84 is preferably needed (i.e., it is preferably sufficient to provide onlyenough PLCs 84 so that eachvertical conductor 80 is connectable to a subset of the region-feedingconductors 90 in each group of conductors 90). - Several possible ways of providing
PLCs 84 are shown in FIGS. 7a-7 d. All of these FIGS. assume a structure like that shown in FIGS. 13 and 14 (described in more detail below) in which one set ofconductors 60/90 provides the functions of (1) local feedback like previously describedconductors 60, (2) region feeding like previously describedconductors 90, and (3) driving out toadjacent conductors conductors PLCs 72′. Also in these FIGS. eachsubregion output 50 is shown with agating PLC 52 such as a programmably controlled pass transistor or other PLC device. - In FIG.
7a PLCs 84 are provided betweenconductors 80 and segments ofconductors 50 extending fromPLCs 52 toconductors 60/90. In FIG.7b PLCs 84 are provided betweenconductors 7c PLCs 84 are connected betweenconductors 80 and only selected ones ofconductors 50. In other words, someconductors 50 have more than onePLC 84, whileother conductors 50 have noPLCs 84. In FIG. 7dhorizontal branches 80′ ofconductors 80 are included, andPLCs 84 are provided between these branches andconductors 60/90. - FIG. 8 shows another possible feature in accordance with this invention. Embodiments of the type shown in FIG. 8 may additionally have any of the features shown in the above-described FIGS. In FIG. 8 each
vertical conductor 80 is divided into upper andlower segments 80 a and 80 b, which are programmably interconnectable, when needed, by PLCs 86 (e.g., pass transistors). If a connection is needed between two upper rows only, an upper segment 80 a can be used to make that connection, leaving the associatedlower segment 80 b free for use in making a connection between two lower rows. On the other hand, if a connection is needed between upper and lower rows, then the upper andlower segments 80 a and 80 b of a vertical conductor are connected by the associatedPLC 86 in order to provide that connection. This may make it possible to reduce the number of vertical conductor tracks that have to be provided in order to provide a given amount of vertical interconnectivity. In connection with the feature illustrated by FIG. 8, see also McClintock et al. U.S. Pat. No. 5,614,840, which is incorporated by reference herein. - In a device with a sufficiently small number of rows, it may be economical to provide each
subregion output 50 with its own dedicatedvertical conductor 80 as shown, for example, in FIG. 9. As an illustration of this, if eachregion 20 includes eightsubregions 30, and the device has only two rows, 16vertical conductors 80 associated with each column are sufficient to provide eachsubregion output 50 with its ownvertical conductor 80. Assuming the same number ofsubregions 30 per region and three rows, 24vertical conductors 80 per column are sufficient to give eachsubregion output 50 its ownvertical conductor 80. This eliminates the need for elements such as 130 and 140 in FIG. 1. Because thevertical conductors 80 are not shared by more than one possible input, there is no need for tri-state drivers on the inputs. - Cliff et al. U.S. Pat. No. 5,689,195 shows programmable logic array integrated circuit devices having several columns of programmable logic regions which may be similar to
regions 20 herein. In addition, the just-mentioned Cliff et al. devices include a column of regions of random access memory (“RAM”) that are usable by the user of the device. The just-mentioned Cliff et al. devices do not include GH to GV connections for the GV conductors associated with the column of RAM regions. Moreover, it has been found that the GV conductors associated with the RAM column are relatively lightly used. In accordance with the present invention, a programmable logic array integrated circuit device that has a column of RAM regions is provided with GH to GV connections for the GV conductors of the RAM region column. This is illustrated by FIG. 10, which will now be discussed. - In FIG. 10 the center column is a column of
RAM regions 20′, which is therefore different from the other columns ofregions 20 of the type that have been described in connection with the other FIGS. herein. In accordance with the present invention, GH-to-GV PLCs 130/140 are provided forconductors 80 associated with the RAM column (regions 20′), just as similar GH-to-GV PLCs are provided for the other columns. These additional GH-to-GV PLCs 130/140 in the RAM column provide additional ways forsubregion outputs 50 ofregions 20 to get to different rows. - Another possible feature of the present devices is shown in FIG. 11. In accordance with this feature, all I/
O cells 160 are driven byparticular subregions 30 in theregions 20 around the periphery of the device. When connecting to an I/O cell 160 configured as an output, the intended output signal is routed to (or possibly produced in) thesubregion 30 associated with that I/O cell. All output register functions for that I/O cell 160 are supported within its drivingsubregion 30. For example, an output register would be implemented in thatsubregion 30 with appropriate clocks, clears, and clock enables. Atri-state driver 150 is connected in series between each I/O cell 160 and its associatedsubregion 30. An input register for an I/O cell 160 can be implemented anywhere on the chip. The I/Os may drive into the device in the same way that they do, for example, in Cliff et al. U.S. Pat. No. 5,260,611 and Cliff et al. U.S. Pat. No. 5,689,195. For example, each I/O along a side edge of the device may drive onto two nearby GH and/orHH conductors 70. Each I/O along a top or bottom edge of the device may drive onto twonearby GV conductors 80. In connection with the feature illustrated by FIG. 11, see also Huang et al. U.S. Pat. No. 5,764,080, which is incorporated by reference herein. - Still another possible feature of devices constructed in accordance with this invention is shown in FIG. 12. This FIG. shows certain aspects of a representative portion of one representative row of an illustrative device. As shown in FIG. 12 each row of
regions 20 is served by a plurality of GH conductors 70 a and a plurality of shorterhorizontal conductors 70 c whose spans are staggered along the length of the row. For example, eachconductor 70 c may nominally extend one quarter of the length of the associated row.Conductors 70 c are therefore sometimes referred to as quarter horizontal (“QH”) conductors. Thus, on the assumption that there are 24regions 20 in the row, eachconductor 70 c extends adjacent to six regions. Moreover, the starting (and ending) points for thevarious conductors 70 c are staggered. Thus there is one depictedconductor 70 c which starts aboveregion 20 b and extends to the right five more regions to end aboveregion 20 g. Similarly, there is another depictedconductor 70 c which starts aboveregion 20 c and extends to the right five more regions to end aboveregion 20 h. - As in earlier-described embodiments, a plurality of block-feeding
conductors 90 serves eachblock 20 by being programmably connectable to theconductors 70 a and 70 c intersected by that group ofconductors 90. For the most part the PLCs that provide these conductor-70-to-conductor-90 connections are not shown in FIG. 12, but they are like thePLCs 72 shown in the previously discussed FIGS. Certain of these PLCs are, however, shown in FIG. 12, and these PLCs are labeled 76 to emphasize them and to identify them as preferably bi-directional connections betweenconductors 70 c andconductors 90.PLCs 76 will now be described in more detail. - Each of
conductors 70 c has aPLC 76 adjacent each of its ends. Each ofPLCs 76 bi-directionally connects to thesame conductor 90 that also has aPLC 76 connection to anotherconductor 70 c. Theconductors 90 with thesePLCs 76 can therefore be used to bi-directionally connectconductors 70 c to one another to make longer horizontal conductors from two or more relativelyshort QH conductors 70 c.PLCs 76 can, of course, also be used to apply signals onconductors 70 c toconductors 90 for feeding to the associatedregions 20. - As an example of use of
PLCs 76 to interconnectconductors 70 c, if it is necessary to transmit a signal fromregion 20 c toregion 20 k, the PLCs in the column that includesregion 20 h may be programmed to interconnect (1) theconductor 70 c that extends to the right from theregion 20 c column and (2) theconductor 70 c that extends to the right from theregion 20 h column. The two thus-interconnectedconductors 70 c can then be used to transmit a signal from theregion 20 c column to theregion 20 k column. Longer interconnections can be made throughconductors 70 c by connecting more than two such conductors together. - Yet another possible feature of the present devices is illustrated by FIGS. 13 and 14. In these FIGS. the functions of
conductors purpose conductors 60/90. Also the connections to, from, and between the GH (70) and GV conductors are organized somewhat differently, but the elements that provide these connections are again generally labeled 110/120/130/140 as in FIG. 1, for example. Eachsubregion 30 includes a look-uptable portion 32 and a register (flip-flop)portion 34. As shown, for example, in FIG. 8 of Cliff et al. U.S. Pat. No. 5,689,195, each look-up table 32 may have four inputs and is programmable to produce anoutput signal 50 a which is any logical combination of those inputs. The associatedregister 34 may registeroutput signal 50 a and produce a registered version as anotheroutput 50 b of the subregion. Alternatively, one of the look-uptable inputs 40 may bypass the look-up table viaPLC 36 and be applied directly to theregister 34 for registration. In that event, the subregion may substantially simultaneously perform two unrelated functions: (1) producing acombinatorial output 50 a, and (2) producing a “lonely register”output 50 b. In the just-mentioned Cliff et al. apparatus, one of these signals is constrained to drive locally (i.e., on a local feedback conductor), while the other of these signals is constrained to drive a global resource such as a GH or GV conductor. These constraints can limit placement of subregions that are to perform the combinatorial and lonely register functions, thereby limiting use of this device capability. - To avoid the above-mentioned constraints, the structure shown in FIGS. 13 and 14 has both the combinatorial50 a and registered 50 b outputs of each subregion programmably connectable by
PLCs 54 torespective conductors 60/90 that can be used either to feed subregions locally or that can be used to convey signals out to the adjacent GH and/or GV conductors. In this way both the combinatorial and registered output signals of eachsubregion 30 can be used either locally, or globally, or both locally and globally. - FIG. 15 shows use of the feature shown in FIGS. 13 and 14 in an embodiment in which separate or dedicated region-feeding
conductors 90,local feedback conductors 60, and moreglobal output conductors 50 y are provided forsubregions 30. For example,output conductors 50 y may be connected to conductors like 100 in FIG. 1 or they may drive more directly toconductors 70 and/or 80 as in above-mentioned Cliff et al. U.S. Pat. No. 5,689,195. PLC 54 x can apply either thecombinatorial output 50 a or the registeredoutput 50 b ofsubregion 30 to thelocal feedback conductor 60 of that subregion. Similarly,PLC 54 y can apply either thecombinatorial output 50 a or the registeredoutput 50 b ofsubregion 30 to the moreglobal output conductor 50 y of the subregion. - In connection with the feature illustrated in FIGS.13-15, see also Cliff et al. U.S. Pat. No. 5,909,126, which is hereby incorporated by reference herein.
- PLCs such as62, 72, 92, 110, 120, 130, and 140 in FIG. 1 and other programmable connections described throughout this specification can be implemented in any of a wide variety of ways. For example, each PLC can be a relatively simple programmable connector such as a plurality of switches for connecting any one of several inputs to an output. Alternatively, each PLC can be a somewhat more complex element which is capable of performing logic (e.g., by logically combining several of its inputs) as well as making a connection. In the latter case, for example, each PLC can be product term logic implementing functions such as AND, NAND, OR, or NOR. Examples of components suitable for implementing PLCs are EPROMs, EEPROMs, pass transistors, transmission gates, antifuses, laser fuses, metal optional links, etc. The components of PLCs can be controlled by various function control elements (“FCEs”) as described in more detail below (although with certain PLC implementations (e.g., fuses and metal optional links) separate FCE devices are not required).
- FCEs (such as the programmable elements that control the PLCs and programmable logic shown throughout the drawings) can also be implemented in any of several different ways. For example, FCEs can be SRAMs, DRAMs, first-in first-out (“FIFO”) memories, EPROMs, EEPROMs, function control registers (e.g., as in Wahlstrom U.S. Pat. No. 3,473,160), ferro-electric memories, fuses, antifuses, or the like.
- It will be understood that the foregoing is only illustrative of the principles of the invention, and that various modifications can be made by those skilled in the art without departing from the scope and spirit of the invention. For example, various technologies can be used to provide the programmable logic and control as has been mentioned. Parameters such as the number of subregions in a region, the number of regions, the numbers of rows and columns of regions, the numbers of the various types of interconnection conductors, the densities of the populations of programmable connections between various kinds of conductors, etc., can all be varied as desired. Directional or orientational terms such as “horizontal”/“vertical”, “row”/“column”, “up”/“down”, “left”/“right”, etc., are selected for use herein arbitrarily and purely for convenience. No fixed or absolute directions or orientations are intended, and the members of these various pairs of terms can be reversed if desired. Terms such as “region” and “subregion” are also arbitrary relative terms, and the term “region” may sometimes be used herein and in the appended claims for what is elsewhere sometimes referred to as a “subregion”.
Claims (16)
1. A programmable logic device comprising:
a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of the regions, each of the regions including a plurality of subregions of programmable logic;
a plurality of interconnection conductors extending parallel to each of the rows;
driver circuitry associated with each of the interconnection conductors and adapted to drive an applied signal onto the associated interconnection conductor; and
selection circuitry associated with each driver circuitry and adapted to select an output signal of any one of at least three of the subregions that are respectively located in three of the columns that are adjacent to one another as the signal applied to the associated driver circuitry.
2. The programmable logic device defined in further comprising:
claim 1
a plurality of second interconnection conductors extending parallel to each of the columns;
second driver circuitry associated with each of the second interconnection conductors and adapted to drive a second applied signal onto the associated second interconnection conductor; and
second selection circuitry associated with each second driver circuitry and adapted to select an output signal of any one of the at least three subregions as the second signal applied to the associated second driver circuitry.
3. The programmable logic device defined in wherein the selection circuitry associated with each driver circuitry is further adapted to alternatively select a signal from one of the second interconnection conductors as the signal applied to the associated driver circuitry.
claim 2
4. The programmable logic device defined in wherein the second selection circuitry associated with each second driver circuitry is further adapted to alternatively select a signal from one of the interconnection conductors as the second signal applied to the associated second driver circuitry.
claim 3
5. The programmable logic device defined in further comprising a plurality of region-feeding conductors associated with each of the regions and adapted to supply signals from the interconnection conductors associated with the row that includes that region to that region; and
claim 1
programmable connections between each selection circuitry and the region-feeding conductors associated with the regions that include the at least three subregions from which that selection circuitry can select an output signal.
6. The programmable logic device defined in wherein at least some of the second interconnection conductors are programmably segmentable so that each segment can convey a signal only between an associated subplurality of the rows.
claim 2
7. A programmable logic device comprising:
a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of the regions, each of the regions including a plurality of subregions of programmable logic, the regions in each row being associated with a multiplicity of subpluralities of the regions in that row, each subplurality including at least three regions;
an output signal conductor associated with each of the subregions, each output conductor extending adjacent to each of the regions in the subplurality that includes the region including that subregion;
selection circuitry associated with each region and adapted to select as an output signal the signal on any one of an associated plurality of the output signal conductors, which plurality includes one output signal conductor associated with a subregion in each region in the subplurality that includes the region associated with that selection circuitry;
a plurality of interconnection conductors associated with each of the rows and adapted to convey signals between the regions in the associated row; and
driver circuitry associated with each selection circuitry and adapted to apply the output signal of that selection circuitry to an interconnection conductor associated with the row that includes the region associated with that selection circuitry.
8. The programmable logic device defined in further comprising;
claim 7
a plurality of second interconnection conductors associated with each of the columns and adapted to convey signals along the associated column;
second selection circuitry associated with each selection circuitry and adapted to select as a second output signal the signal on any of the output signal conductors that the selection circuitry can select the output signal from; and
second driver circuitry associated with each second selection circuitry and adapted to apply the second output signal of that second selection circuitry to a second interconnection conductor associated with the column that includes the region associated with the selection circuitry with which that second selection circuitry is associated.
9. The programmable logic device defined in wherein the selection circuitry associated with each region is further adapted to alternatively select the output signal from a second interconnection conductor associated with the column that includes that region.
claim 8
10. The programmable logic device defined in wherein the second selection circuitry associated with the selection circuitry associated with each region is further adapted to alternatively select the output signal from an interconnection conductor associated with the row that includes that region.
claim 8
11. The programmable logic device defined in further comprising:
claim 7
region-feeding conductors associated with each region and adapted to supply input signals to the subregions in that region;
first programmable connections between the region-feeding conductors associated with each region and the interconnection conductors associated with the row that includes that region; and
second programmable connections between the output signal conductors from which the selection circuitry associated with each region can select the output signal and the region-feeding conductors associated with that region.
12. The programmable logic device defined in wherein at least some of the second interconnection conductors are programmable segmentable so that each segment can convey a signal only between an associated subplurality of the rows.
claim 8
13. A programmable logic device comprising:
a plurality of regions of programmable logic disposed on the device in a plurality of rows of the regions, each region in each row being associated with a plurality of subpluralities of adjacent ones of the regions in that row, each of the subpluralities that each region is associated with including a different number of the regions to at least one side of that region;
at least one interconnection conductor associated with each of the subpluralities and adapted to convey signals between the regions in that subplurality;
region-feeding conductors associated with each of the regions and adapted to supply input signals to the associated region; and
programmable connections between the region-feeding conductors associated with each region and the interconnection conductors associated with the subpluralities that include that region and adapted to allow at least some of those interconnection conductors to be connected to one another via those region-feeding conductors.
14. The programmable logic device defined in wherein each of the subpluralities includes at least three of the regions.
claim 13
15. The programmable logic device defined in further comprising:
claim 13
a plurality of second interconnection conductors associated with each of the rows and adapted to convey signals between any of the regions in the associated row; and
second programmable connections between the region-feeding conductors associated with each region and the second interconnection conductors associated with the row that includes that region.
16. The programmable logic device defined in wherein the regions are additionally disposed on the device in a plurality of columns that intersect the rows, and wherein the device further comprises:
claim 15
a plurality of third interconnection conductors associated with each of the columns, each of the third interconnection conductors being programmably segmentable into a plurality of segments, each of which is adapted to convey a signal between only an associated subplurality of the rows.
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US09/865,227 US6366121B2 (en) | 1995-05-17 | 2001-05-25 | Programmable logic array integrated circuit architectures |
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