US20010015651A1 - Test head assembly utilizing replaceable silicon contact - Google Patents
Test head assembly utilizing replaceable silicon contact Download PDFInfo
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- US20010015651A1 US20010015651A1 US09/842,686 US84268601A US2001015651A1 US 20010015651 A1 US20010015651 A1 US 20010015651A1 US 84268601 A US84268601 A US 84268601A US 2001015651 A1 US2001015651 A1 US 2001015651A1
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- contacts
- printed circuit
- base
- structures
- intermediate structure
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
Definitions
- the present invention relates to the testing of semiconductor chips, particularly chip-sized packages (CSP). More particularly, the invention relates to a test head assembly which obviates the requirement of contacting a device-under-test (DUT) by way of pogo pins or other conventional devices.
- CSP chip-sized packages
- the present invention provides an apparatus for testing semiconductor devices including a base, an intermediate silicon contact structure supported by the base and having a plurality of electrical contacts for mating with the contacts of a DUT and which supplies signals between the DUT and a testing apparatus, and a fixing structure.
- the fixing structure holds the intermediate silicon contact structure to the base.
- the fixing structure has an opening through which a DUT may pass and be connected with the plurality of electrical contacts of the intermediate structure.
- the present invention also provides a system for testing semiconductor devices.
- the system has a testing apparatus, which includes a base having at least one cavity with an opening extending from a cavity surface to a bottom surface of the base, an intermediate silicon contact structure supported by the base within one of the cavities and having a plurality of electrical contacts adapted to provide an electrical connection between the printed circuit board and a DUT, and a fixing structure which holds the intermediate structure to the base.
- the fixing structure has an opening through which a DUT may pass and be connected with the plurality of electrical contacts of the intermediate structure.
- the system further includes a printed circuit board positionable on the cavity surface which is electrically connected with the intermediate structure and with a testing apparatus, and a pick and place device for moving a DUT into electrical connection with the intermediate structure.
- the present invention also provides a method for testing a semiconductor device.
- the method includes the steps of moving a semiconductor device into a semiconductor test apparatus, electrically connecting the semiconductor device to a testing apparatus through the intermediate silicon contact structure, and testing the semiconductor device with the testing apparatus.
- FIG. 1 is an exploded perspective view of a test head assembly constructed in accordance with an embodiment of the present invention.
- FIG. 2 is another exploded perspective view of the test head assembly of FIG. 1.
- FIG. 3 is a perspective view of the test head base and pick and place device of the test head assembly of FIG. 1.
- FIG. 4 is a perspective view of the test head base showing a chip sized package in the test head assembly of FIG. 1.
- FIG. 5 is a perspective view of the test head base showing a silicon contactor in the nest of the test head assembly of FIG. 1.
- FIG. 6 is a perspective view of the test head base showing a printed circuit board substrate and a silicon contactor in the test head assembly of FIG. 1.
- FIG. 7 is a perspective view of the test head base showing an upper pin block in the test head assembly of FIG. 1.
- FIG. 8 is a perspective view of the upper pin block and lower pin block of the test head assembly of FIG. 1.
- FIG. 9 is a cross-sectional view taken along line IX-IX of the pin blocks of FIG. 8.
- FIG. 10 is a perspective view of the silicon contactor and the printed circuit board substrate of the test head assembly of FIG. 1.
- FIG. 11 is a top view of a test head assembly constructed in accordance with another embodiment of the invention.
- FIG. 12 is a partial cross-sectional view taken along line XII-XII of the assembly of FIG. 1.
- FIG. 13 is a top view of a test head assembly constructed in accordance with another embodiment of the invention.
- FIG. 14 is a partial cross-sectional view taken along line XIV-XIV of the assembly of FIG. 13.
- FIG. 15 is a cross-sectional view of a test head assembly constructed in accordance with another embodiment of the invention.
- FIG. 16 is a cross-sectional view of a portion of the assembly of FIG. 15.
- the present invention alleviates, at least to some extent, the deficiencies of conventional test probe apparatuses by providing an intermediate silicon contact structure in the test probe apparatus which acts as an electrical conduit between the electrical contacts of a chip-size package and those of a printed circuit board (PCB).
- the intermediate structure has finely spaced contacts which can be easily sized and configured to mate with the electrical contacts of a DUT and also connects with contact terminals of the PCB, which in turn connect with a testing apparatus.
- FIGS. 1 - 10 illustrate an embodiment of the invention. It should be noted that the invention will be described in the exemplary environment of a test apparatus in which two packaged chips can be tested at the same time. However, the invention can be used to test one, two or more than two packaged chips simultaneously. Accordingly, the discussion herein is not to be considered as a limitation of the invention.
- a contactor test head 10 including a base 12 and a holding fixture 16 .
- the base 12 includes a pair of cavities 14 , each having a cavity surface 15 .
- An opening 11 extends through the cavities 14 from the cavity surfaces 15 to a base lower surface 13 .
- Each cavity 14 has an associated holding fixture 16 , silicon contact structure 30 , printed circuit board 20 , first pin block 70 , pin assembly 60 and second pin block 50 .
- the holding fixture 16 is sized and configured to sit within each cavity 14 of the base 12 .
- Each holding fixture 16 includes an opening 18 extending from an upper surface 19 to a lower surface 17 .
- the holding fixture 16 should be made of a non-conductive material which is stable at high temperatures and resists wear over time. Further, the holding fixture 16 should be formed of a high strength material.
- An example of a suitable material for the holding fixture 16 is a glass-filled plastic, such as, for example, Torlon® 5533, Torlon® 4203, Torlon® 4203L, Torlon® 4301, or Peek®.
- the holding fixture 16 is secured to the base 12 by screws or other fasteners and serves to hold a silicon contact structure 30 and an associated printed circuit board (PCB) 20 in nested relationship to a respective cavity 14 in the base 12 .
- PCB printed circuit board
- a first pin block 70 having a first surface 74 and a second surface 76 sits within an opening 11 of each of the cavities in the base 12 such that a first surface 74 of the first pin block 70 fits against a cavity ledge 73 (FIG. 2).
- the first pin block 70 further includes a plurality of openings 72 for receiving a plurality of pins 60 .
- a second pin block 50 having a plurality of openings 52 , a first surface 54 , and a second surface 56 , further fits within each opening 11 .
- the first and second pin blocks 70 , 50 serve to hold the plurality of pins 60 within the openings 11 .
- each cavity 14 may receive a first and second pin block 70 , 50 .
- the base 12 may be altered to receive more than two sets of pin blocks 70 , 50 .
- the plurality of pins 60 which may be pogo pins or stationary pins, fit within the first and second pin blocks 70 , 50 . Specifically, top portions 62 of the pins 60 fit within the openings 52 of the second pin block 50 . Further, bottom portions 64 of the pins 60 fit within the plurality of openings 72 in the first pin block 70 . Thus, the pins 60 extend through the first pin block 70 to a testing apparatus and up through the second pin block 50 and into the respective cavities 14 of the base 12 (FIGS. 7 - 9 ).
- the openings 52 are counter-bored beneath the first surface 54 of the pin block 50 , and the openings 72 are counter-bored in the second surface 76 of the pin block 70 to accept a non-movable body portion of the pin 60 (FIG. 9).
- the portions of the openings 52 , 72 which are not counter-bored have a diameter sized and shaped so as to securely hold the pins 60 therein.
- the printed circuit board (PCB) substrate 20 having a first surface 22 and a second surface 24 is positioned within the cavity 14 of the base 12 .
- the second surface 24 of the PCB substrate 20 is placed in contact with the plurality of top portions 62 of the pins 60 .
- the top portions 62 of the pins make contact with respective electrical contact points 25 on the second surface 24 of the PCB substrate 20 .
- the electrical contact points 25 are in turn connected to a wiring pattern on the PCB substrate 20 which connects respective contact points 25 on the second surface 24 to electrical connections 27 on the first surface 22 of the PCB substrate 20 (FIGS. 6, 10).
- a silicon contact structure 30 having a top surface 32 and a bottom surface 34 .
- a plurality of electrical contacts 37 are arrayed along two sides of the top surface 32 of the contact structure 30 , the number and pattern of contacts 37 being tailored to a specific DUT or types of DUTs.
- the contacts 37 may be pockets formed in an insulator material and having a thin film conductor, such as tungsten.
- a thin film trace 39 extends from each electrical contact 37 to a respective contact pad 38 .
- Each pad 38 may be formed of a flat conductor.
- the thin film traces 39 fan out from the electrical contacts 37 to the pads 38 .
- Each pad 38 has a wire bond 36 to a respective electrical connection 27 on the top surface 22 of the printed circuit board 20 . For clarity of illustration in FIG. 9, only a few of the wire bonds 36 between the pads 38 and connections 27 are shown.
- FIGS. 1 - 2 and 4 show a chip-size package 40 having a top surface 42 and a bottom surface 44 .
- the bottom surface 44 is placed in direct contact with the contacts 37 on the first surface 32 of the silicon contact structure 30 .
- the chip-size package 40 further includes electrical contacts 43 (FIG. 2) which are electrically connected to the electrical contacts 37 of the silicon contact structure 30 .
- the contacts 43 may be solder balls.
- the electrical contacts 37 of the silicon contact structure 30 are spaced to align with the contacts 43 of the chip-size package (DUT) 40 .
- the electrical contacts 37 may therefore be closely spaced, in accordance with the close spacing of the contacts 43 of the DUT 40 , while still providing good electrical contact between a testing apparatus connected to the PCB 20 through the pins 60 and the DUT 40 .
- different contact structures 30 can easily be produced for different sizes and types of DUTs.
- the pick and place device 80 includes a vacuum head 82 with an extension 84 and a vacuum quill 86 .
- a vacuum is drawn through the head 82 and the quill 86 , which creates a suction force on the chip-sized package 40 .
- the pick and place device 80 moved by a robot, can pick up a package 40 from a tray containing a plurality of packages 40 and place the package 40 within the opening 18 of the holding fixture 16 .
- the vacuum may be disconnected from the vacuum device 80 , thereby eliminating the vacuum force on the package 40 .
- a pressure is maintained by the pick and place device 80 on the package 40 pressing it into electrical contact with the contacts 37 on the silicon contact structure 30 . It should be apparent that for simplicity, only one pick and place device 80 is illustrated. In actual practice, two such devices moving in tandem would be used with each of the holding fixtures 16 associated with the base 12 for the two-at-a-time DUT test assembly shown in the drawings.
- each package 40 By placing each package 40 properly within an opening 18 on a respective one of the contact structures 30 , the contacts 43 electrically connect with the contacts 37 . Further, the traces 39 from the contacts 37 to the pads 38 allow for the electrical connection to continue to the printed circuit board substrate 20 through the wire bonds 36 to the connections 27 , and from there through the pins 60 extending through the block 70 to a testing device 90 (FIG. 1). Through this arrangement, testing of the package 40 can be accomplished without using pogo or other pins to directly contact the DUT package 40 .
- the various conductors of the silicon contact structure 30 must be sufficiently conductive to function as an electrical intermediary between the circuit board 20 and the package 40 .
- the resistance across the conductors of the silicon contact structure 30 is between about 50 milliohms and five ohms.
- the conductors on the silicon contact structure 30 may be formed as a metallized wiring pattern on a silicon substrate or as a pattern of doped polysilicon terminating in a metallized contact pad utilizing conventional integrated circuit conductor fabrication techniques.
- the holding fixture 16 is removable from base 12 to allow removal and/or replacement of the silicon contact structure 30 and the PCB 20 .
- Silicon contact structures 30 are simple and inexpensive to manufacture. Accordingly, if any damage or wear occurs to it during use, it is easily and inexpensively replaced.
- FIGS. 11 - 12 there is shown a test head assembly 110 which is similar in construction to the assembly 10 previously described, except that the pin blocks 70 , 50 and pins 60 are replaced with an alternative structure (described in detail below).
- a silicon contact structure 130 is positioned within the-cavity 14 of the assembly 110 .
- the structure 130 differs from the silicon contact structure 30 in that the structure 130 does not connect with a PCB 20 . Instead, the contacts 37 connect by way of conductive vias 131 with an interposing structure 140 .
- each via 131 contacts a respective contact element 141 , which in turns contacts a first surface 142 of the interposing structure 140 .
- the interposing structure 140 is also preferably formed of silicone (or an electrically non-conductive elastomer), is sized and shaped to snugly fit within the cavity 11 , and has electrically conductive, preferably gold or aluminum, wires 143 embedded within the structure 140 .
- a second surface 144 of the structure 140 is the exit surface for the wires 143 .
- the wires 143 serve to electrically connect the contact elements 141 with a respective contact pad on a testing device.
- the wires 143 may terminate in a bump-like contact, e.g., solder balls, at the surface 144 of the interposing structure 140 .
- the electrical contacts 37 are spaced to align with the contacts 43 of the DUT 40 .
- Bypassing the PCB 20 in the testing of the DUT 40 decreases time delays and decreases the amount of inductance and/or capacitance in the testing arrangement. Further, bypassing the PCB 20 provides manufacturing advantages since the silicon contact structure 130 need not be processed to align with and electrically connect with the PCB 20 .
- FIGS. 13 - 14 another test head assembly 210 is illustrated.
- the assembly 210 differs from the assembly 110 in that a PCB 220 is included within the test arrangement.
- the silicon contact structure 30 has pads 38 electrically connected by wires 36 to respective electrical connections 27 on the PCB 220 .
- the PCB 220 includes a plurality of solder balls, or other suitable contacting structure, 222 on a second surface 224 .
- Each solder ball 222 is connected with a respective connection 227 by a wire bond 221 , and connects with a respective contact element 141 of the interposing structure 140 .
- the wires 143 electrically connect each contact element 141 with a respective contact pad of a testing device.
- FIGS. 15 - 16 Another test head assembly 310 is illustrated in FIGS. 15 - 16 .
- the assembly 310 includes the silicon contact structure 30 electrically connected with the PCB 220 .
- a guide plate 350 Positioned directly beneath the surface 224 of the PCB 220 is a guide plate 350 .
- the plate 350 has a plurality of pockets 351 within a first surface 352 .
- the pockets 351 lead to vias 353 which extend to a second surface 354 .
- a contact structure 355 fits within each via and pierces each solder ball 222 provided for the bottom surface contacts of the PCB 220 , with a flange 356 , to obtain a good electrical connection between the solder balls 222 provided on the lower surface of the silicon contact structure 330 and/or the PCB 220 connected thereto and the contact structures 355 .
- the structures 355 further each electrically connect, at an end 357 , with the wires 243 of an interposing structure 340 .
- the wires 143 each connect with a respective contact pad in a test device.
- the PCB 220 may be eliminated from the testing arrangement illustrated in FIGS. 15 - 16 .
- the structure 30 can be flipped, and the contacts 38 electrically connected through the structures 355 to the wires 243 .
- Elimination of the PCB 220 provides decreases inductance and capacitance in the system and decreases time delays in the testing.
- the contact structure 130 shown in and described in reference with FIGS. 11 - 12 may be used instead of structure 30 .
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Abstract
Description
- The present invention relates to the testing of semiconductor chips, particularly chip-sized packages (CSP). More particularly, the invention relates to a test head assembly which obviates the requirement of contacting a device-under-test (DUT) by way of pogo pins or other conventional devices.
- The testing of semiconductor chips is well known. Some conventional testing apparatus for semiconductor devices, such as CSPs, provide for an electrical contact between the device and a printed circuit board (PCB). The electrical contact is generally made through spring-loaded test probes or through pins extending through an intermediate section of a carrier. An example of spring-loaded test probes may be found in U.S. Pat. No. 5,823,818 (Bell et al.). Examples of the use of contact test pins may be found in U.S. Pat. Nos. 4,764,925 (Grimes et al.) and 5,875,198 (Satoh).
- One potential deficiency in utilizing spring-loaded test probes, also known as pogo pins, or stationary pins, is the difficulty in properly attaching them to the DUTs. With the increasingly smaller device sizes, the electrical contacts are getting closer together, making the manufacture of the test device itself, with pogo pins or stationary pins, and the subsequent testing of the contacts with such a device even more difficult.
- The present invention provides an apparatus for testing semiconductor devices including a base, an intermediate silicon contact structure supported by the base and having a plurality of electrical contacts for mating with the contacts of a DUT and which supplies signals between the DUT and a testing apparatus, and a fixing structure. The fixing structure holds the intermediate silicon contact structure to the base. The fixing structure has an opening through which a DUT may pass and be connected with the plurality of electrical contacts of the intermediate structure.
- The present invention also provides a system for testing semiconductor devices. The system has a testing apparatus, which includes a base having at least one cavity with an opening extending from a cavity surface to a bottom surface of the base, an intermediate silicon contact structure supported by the base within one of the cavities and having a plurality of electrical contacts adapted to provide an electrical connection between the printed circuit board and a DUT, and a fixing structure which holds the intermediate structure to the base. The fixing structure has an opening through which a DUT may pass and be connected with the plurality of electrical contacts of the intermediate structure. The system further includes a printed circuit board positionable on the cavity surface which is electrically connected with the intermediate structure and with a testing apparatus, and a pick and place device for moving a DUT into electrical connection with the intermediate structure.
- The present invention also provides a method for testing a semiconductor device. The method includes the steps of moving a semiconductor device into a semiconductor test apparatus, electrically connecting the semiconductor device to a testing apparatus through the intermediate silicon contact structure, and testing the semiconductor device with the testing apparatus.
- These and other features and advantages of the invention will be more clearly understood from the following detailed description of the invention which is provided in connection with the accompanying drawings.
- FIG. 1 is an exploded perspective view of a test head assembly constructed in accordance with an embodiment of the present invention.
- FIG. 2 is another exploded perspective view of the test head assembly of FIG. 1.
- FIG. 3 is a perspective view of the test head base and pick and place device of the test head assembly of FIG. 1.
- FIG. 4 is a perspective view of the test head base showing a chip sized package in the test head assembly of FIG. 1.
- FIG. 5 is a perspective view of the test head base showing a silicon contactor in the nest of the test head assembly of FIG. 1.
- FIG. 6 is a perspective view of the test head base showing a printed circuit board substrate and a silicon contactor in the test head assembly of FIG. 1.
- FIG. 7 is a perspective view of the test head base showing an upper pin block in the test head assembly of FIG. 1.
- FIG. 8 is a perspective view of the upper pin block and lower pin block of the test head assembly of FIG. 1.
- FIG. 9 is a cross-sectional view taken along line IX-IX of the pin blocks of FIG. 8.
- FIG. 10 is a perspective view of the silicon contactor and the printed circuit board substrate of the test head assembly of FIG. 1.
- FIG. 11 is a top view of a test head assembly constructed in accordance with another embodiment of the invention.
- FIG. 12 is a partial cross-sectional view taken along line XII-XII of the assembly of FIG. 1.
- FIG. 13 is a top view of a test head assembly constructed in accordance with another embodiment of the invention.
- FIG. 14 is a partial cross-sectional view taken along line XIV-XIV of the assembly of FIG. 13.
- FIG. 15 is a cross-sectional view of a test head assembly constructed in accordance with another embodiment of the invention.
- FIG. 16 is a cross-sectional view of a portion of the assembly of FIG. 15.
- The present invention alleviates, at least to some extent, the deficiencies of conventional test probe apparatuses by providing an intermediate silicon contact structure in the test probe apparatus which acts as an electrical conduit between the electrical contacts of a chip-size package and those of a printed circuit board (PCB). The intermediate structure has finely spaced contacts which can be easily sized and configured to mate with the electrical contacts of a DUT and also connects with contact terminals of the PCB, which in turn connect with a testing apparatus.
- FIGS.1-10 illustrate an embodiment of the invention. It should be noted that the invention will be described in the exemplary environment of a test apparatus in which two packaged chips can be tested at the same time. However, the invention can be used to test one, two or more than two packaged chips simultaneously. Accordingly, the discussion herein is not to be considered as a limitation of the invention.
- A
contactor test head 10 is shown including abase 12 and aholding fixture 16. Thebase 12 includes a pair ofcavities 14, each having acavity surface 15. Anopening 11 extends through thecavities 14 from thecavity surfaces 15 to a baselower surface 13. Eachcavity 14 has an associatedholding fixture 16,silicon contact structure 30,printed circuit board 20,first pin block 70,pin assembly 60 andsecond pin block 50. - The
holding fixture 16 is sized and configured to sit within eachcavity 14 of thebase 12. Eachholding fixture 16 includes anopening 18 extending from anupper surface 19 to alower surface 17. Theholding fixture 16 should be made of a non-conductive material which is stable at high temperatures and resists wear over time. Further, theholding fixture 16 should be formed of a high strength material. An example of a suitable material for theholding fixture 16 is a glass-filled plastic, such as, for example, Torlon® 5533, Torlon® 4203, Torlon® 4203L, Torlon® 4301, or Peek®. - The
holding fixture 16 is secured to thebase 12 by screws or other fasteners and serves to hold asilicon contact structure 30 and an associated printed circuit board (PCB) 20 in nested relationship to arespective cavity 14 in thebase 12. As noted, while the invention is described with reference to a device for testing two DUTs at a time, the invention may be adapted to test any number of DUTs simultaneously. - With specific reference to FIGS.1-2, a
first pin block 70 having a first surface 74 and asecond surface 76 sits within anopening 11 of each of the cavities in thebase 12 such that a first surface 74 of thefirst pin block 70 fits against a cavity ledge 73 (FIG. 2). Thefirst pin block 70 further includes a plurality ofopenings 72 for receiving a plurality ofpins 60. - A
second pin block 50, having a plurality ofopenings 52, afirst surface 54, and asecond surface 56, further fits within eachopening 11. The first andsecond pin blocks pins 60 within theopenings 11. Obviously, as there are twocavities 14 in the illustratedbase 12, eachcavity 14 may receive a first andsecond pin block - The plurality of
pins 60, which may be pogo pins or stationary pins, fit within the first and second pin blocks 70, 50. Specifically,top portions 62 of thepins 60 fit within theopenings 52 of thesecond pin block 50. Further,bottom portions 64 of thepins 60 fit within the plurality ofopenings 72 in thefirst pin block 70. Thus, thepins 60 extend through thefirst pin block 70 to a testing apparatus and up through thesecond pin block 50 and into therespective cavities 14 of the base 12 (FIGS. 7-9). - The
openings 52 are counter-bored beneath thefirst surface 54 of thepin block 50, and theopenings 72 are counter-bored in thesecond surface 76 of thepin block 70 to accept a non-movable body portion of the pin 60 (FIG. 9). The portions of theopenings pins 60 therein. - With reference to FIGS.1-2 and 10, the printed circuit board (PCB)
substrate 20, having afirst surface 22 and asecond surface 24 is positioned within thecavity 14 of thebase 12. Specifically, thesecond surface 24 of thePCB substrate 20 is placed in contact with the plurality oftop portions 62 of thepins 60. Thetop portions 62 of the pins make contact with respective electrical contact points 25 on thesecond surface 24 of thePCB substrate 20. The electrical contact points 25 are in turn connected to a wiring pattern on thePCB substrate 20 which connects respective contact points 25 on thesecond surface 24 toelectrical connections 27 on thefirst surface 22 of the PCB substrate 20 (FIGS. 6, 10). - With specific reference to FIGS.5-6 and 10, there is shown a
silicon contact structure 30 having atop surface 32 and abottom surface 34. A plurality ofelectrical contacts 37 are arrayed along two sides of thetop surface 32 of thecontact structure 30, the number and pattern ofcontacts 37 being tailored to a specific DUT or types of DUTs. Thecontacts 37 may be pockets formed in an insulator material and having a thin film conductor, such as tungsten. Athin film trace 39 extends from eachelectrical contact 37 to arespective contact pad 38. Eachpad 38 may be formed of a flat conductor. The thin film traces 39 fan out from theelectrical contacts 37 to thepads 38. Eachpad 38 has awire bond 36 to a respectiveelectrical connection 27 on thetop surface 22 of the printedcircuit board 20. For clarity of illustration in FIG. 9, only a few of thewire bonds 36 between thepads 38 andconnections 27 are shown. - FIGS.1-2 and 4 show a chip-
size package 40 having atop surface 42 and abottom surface 44. Thebottom surface 44 is placed in direct contact with thecontacts 37 on thefirst surface 32 of thesilicon contact structure 30. The chip-size package 40 further includes electrical contacts 43 (FIG. 2) which are electrically connected to theelectrical contacts 37 of thesilicon contact structure 30. Thecontacts 43 may be solder balls. Theelectrical contacts 37 of thesilicon contact structure 30 are spaced to align with thecontacts 43 of the chip-size package (DUT) 40. Theelectrical contacts 37 may therefore be closely spaced, in accordance with the close spacing of thecontacts 43 of theDUT 40, while still providing good electrical contact between a testing apparatus connected to thePCB 20 through thepins 60 and theDUT 40. In addition,different contact structures 30 can easily be produced for different sizes and types of DUTs. - To test the chip-
size package 40, it is placed within theopening 18 of the holdingfixture 16 by way of a pick and place device 80 (FIGS. 1-3). The pick andplace device 80 includes avacuum head 82 with anextension 84 and avacuum quill 86. A vacuum is drawn through thehead 82 and thequill 86, which creates a suction force on the chip-sized package 40. In this way, the pick andplace device 80, moved by a robot, can pick up apackage 40 from a tray containing a plurality ofpackages 40 and place thepackage 40 within theopening 18 of the holdingfixture 16. Once properly placed, the vacuum may be disconnected from thevacuum device 80, thereby eliminating the vacuum force on thepackage 40. A pressure is maintained by the pick andplace device 80 on thepackage 40 pressing it into electrical contact with thecontacts 37 on thesilicon contact structure 30. It should be apparent that for simplicity, only one pick andplace device 80 is illustrated. In actual practice, two such devices moving in tandem would be used with each of the holdingfixtures 16 associated with thebase 12 for the two-at-a-time DUT test assembly shown in the drawings. - By placing each
package 40 properly within anopening 18 on a respective one of thecontact structures 30, thecontacts 43 electrically connect with thecontacts 37. Further, thetraces 39 from thecontacts 37 to thepads 38 allow for the electrical connection to continue to the printedcircuit board substrate 20 through thewire bonds 36 to theconnections 27, and from there through thepins 60 extending through theblock 70 to a testing device 90 (FIG. 1). Through this arrangement, testing of thepackage 40 can be accomplished without using pogo or other pins to directly contact theDUT package 40. - Although the present invention has been described in terms of testing a chip-
sized package 40, it is to be understood that the invention is not so limited. Specifically, all types of semiconductor devices which require testing may be utilized with the present invention. - The various conductors of the
silicon contact structure 30 must be sufficiently conductive to function as an electrical intermediary between thecircuit board 20 and thepackage 40. Preferably, the resistance across the conductors of thesilicon contact structure 30 is between about 50 milliohms and five ohms. - The conductors on the
silicon contact structure 30 may be formed as a metallized wiring pattern on a silicon substrate or as a pattern of doped polysilicon terminating in a metallized contact pad utilizing conventional integrated circuit conductor fabrication techniques. - The holding
fixture 16 is removable frombase 12 to allow removal and/or replacement of thesilicon contact structure 30 and thePCB 20.Silicon contact structures 30 are simple and inexpensive to manufacture. Accordingly, if any damage or wear occurs to it during use, it is easily and inexpensively replaced. - Referring now to FIGS.11-12, there is shown a
test head assembly 110 which is similar in construction to theassembly 10 previously described, except that the pin blocks 70, 50 and pins 60 are replaced with an alternative structure (described in detail below). Asilicon contact structure 130 is positioned within the-cavity 14 of theassembly 110. Thestructure 130 differs from thesilicon contact structure 30 in that thestructure 130 does not connect with aPCB 20. Instead, thecontacts 37 connect by way ofconductive vias 131 with an interposingstructure 140. Specifically, each via 131 contacts arespective contact element 141, which in turns contacts afirst surface 142 of the interposingstructure 140. - The interposing
structure 140 is also preferably formed of silicone (or an electrically non-conductive elastomer), is sized and shaped to snugly fit within thecavity 11, and has electrically conductive, preferably gold or aluminum,wires 143 embedded within thestructure 140. Asecond surface 144 of thestructure 140 is the exit surface for thewires 143. Thewires 143 serve to electrically connect thecontact elements 141 with a respective contact pad on a testing device. Thewires 143 may terminate in a bump-like contact, e.g., solder balls, at thesurface 144 of the interposingstructure 140. - The
electrical contacts 37 are spaced to align with thecontacts 43 of theDUT 40. Bypassing thePCB 20 in the testing of theDUT 40 decreases time delays and decreases the amount of inductance and/or capacitance in the testing arrangement. Further, bypassing thePCB 20 provides manufacturing advantages since thesilicon contact structure 130 need not be processed to align with and electrically connect with thePCB 20. - Referring to FIGS.13-14, another
test head assembly 210 is illustrated. Theassembly 210 differs from theassembly 110 in that aPCB 220 is included within the test arrangement. Specifically, thesilicon contact structure 30 haspads 38 electrically connected bywires 36 to respectiveelectrical connections 27 on thePCB 220. - The
PCB 220 includes a plurality of solder balls, or other suitable contacting structure, 222 on asecond surface 224. Eachsolder ball 222 is connected with arespective connection 227 by awire bond 221, and connects with arespective contact element 141 of the interposingstructure 140. Thewires 143 electrically connect eachcontact element 141 with a respective contact pad of a testing device. - Another
test head assembly 310 is illustrated in FIGS. 15-16. Theassembly 310 includes thesilicon contact structure 30 electrically connected with thePCB 220. Positioned directly beneath thesurface 224 of thePCB 220 is aguide plate 350. Theplate 350 has a plurality ofpockets 351 within afirst surface 352. Thepockets 351 lead tovias 353 which extend to asecond surface 354. Acontact structure 355 fits within each via and pierces eachsolder ball 222 provided for the bottom surface contacts of thePCB 220, with aflange 356, to obtain a good electrical connection between thesolder balls 222 provided on the lower surface of the silicon contact structure 330 and/or thePCB 220 connected thereto and thecontact structures 355. With specific reference to FIG. 16, thestructures 355 further each electrically connect, at anend 357, with the wires 243 of an interposing structure 340. Thewires 143 each connect with a respective contact pad in a test device. - Alternatively, it is to be understood that the
PCB 220 may be eliminated from the testing arrangement illustrated in FIGS. 15-16. By eliminating thePCB 220, thestructure 30 can be flipped, and thecontacts 38 electrically connected through thestructures 355 to the wires 243. Elimination of thePCB 220 provides decreases inductance and capacitance in the system and decreases time delays in the testing. Further, thecontact structure 130 shown in and described in reference with FIGS. 11-12 may be used instead ofstructure 30. - While the invention has been described in detail in connection with the preferred embodiments known at the time, it should be readily understood that the invention is not limited to such disclosed embodiments. Rather, the invention can be modified to incorporate any number of variations, alterations, substitutions or equivalent arrangements not heretofore described, but which are commensurate with the spirit and scope of the invention. Accordingly, the invention is not to be seen as limited by the foregoing description, but is only limited by the scope of the appended claims.
Claims (72)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US09/842,686 US6459286B2 (en) | 1999-08-31 | 2001-04-27 | Test head assembly utilizing replaceable silicon contact |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/386,320 US6246246B1 (en) | 1999-08-31 | 1999-08-31 | Test head assembly utilizing replaceable silicon contact |
US09/842,686 US6459286B2 (en) | 1999-08-31 | 2001-04-27 | Test head assembly utilizing replaceable silicon contact |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US09/386,320 Continuation US6246246B1 (en) | 1999-08-31 | 1999-08-31 | Test head assembly utilizing replaceable silicon contact |
Publications (2)
Publication Number | Publication Date |
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US20010015651A1 true US20010015651A1 (en) | 2001-08-23 |
US6459286B2 US6459286B2 (en) | 2002-10-01 |
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Family Applications (2)
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US09/386,320 Expired - Fee Related US6246246B1 (en) | 1999-08-31 | 1999-08-31 | Test head assembly utilizing replaceable silicon contact |
US09/842,686 Expired - Fee Related US6459286B2 (en) | 1999-08-31 | 2001-04-27 | Test head assembly utilizing replaceable silicon contact |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
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US09/386,320 Expired - Fee Related US6246246B1 (en) | 1999-08-31 | 1999-08-31 | Test head assembly utilizing replaceable silicon contact |
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US (2) | US6246246B1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100315617A1 (en) * | 2009-06-12 | 2010-12-16 | Semicaps Pte Ltd | Wafer stage |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6556030B1 (en) * | 1999-09-01 | 2003-04-29 | Micron Technology, Inc. | Method of forming an electrical contact |
TWI258255B (en) * | 2005-05-20 | 2006-07-11 | Ramtek Technology Inc | Method of testing ball grid array packed device in real system and test socket assembly therefor |
DE102006015363B4 (en) * | 2006-04-03 | 2009-04-16 | Multitest Elektronische Systeme Gmbh | Test device for testing electronic components |
US8466705B1 (en) * | 2012-09-27 | 2013-06-18 | Exatron, Inc. | System and method for analyzing electronic devices having a cab for holding electronic devices |
Family Cites Families (15)
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US4764925A (en) | 1984-06-14 | 1988-08-16 | Fairchild Camera & Instrument | Method and apparatus for testing integrated circuits |
US5640762A (en) | 1988-09-30 | 1997-06-24 | Micron Technology, Inc. | Method and apparatus for manufacturing known good semiconductor die |
US5519332A (en) | 1991-06-04 | 1996-05-21 | Micron Technology, Inc. | Carrier for testing an unpackaged semiconductor die |
US5716218A (en) | 1991-06-04 | 1998-02-10 | Micron Technology, Inc. | Process for manufacturing an interconnect for testing a semiconductor die |
US5500606A (en) * | 1993-09-16 | 1996-03-19 | Compaq Computer Corporation | Completely wireless dual-access test fixture |
US5534784A (en) * | 1994-05-02 | 1996-07-09 | Motorola, Inc. | Method for probing a semiconductor wafer |
US5713744A (en) * | 1994-09-28 | 1998-02-03 | The Whitaker Corporation | Integrated circuit socket for ball grid array and land grid array lead styles |
US5537051A (en) * | 1995-04-24 | 1996-07-16 | Motorola, Inc. | Apparatus for testing integrated circuits |
US5730620A (en) * | 1995-09-08 | 1998-03-24 | International Business Machines Corporation | Method and apparatus for locating electrical circuit members |
US5742481A (en) * | 1995-10-04 | 1998-04-21 | Advanced Interconnections Corporation | Removable terminal support member for integrated circuit socket/adapter assemblies |
US5847293A (en) | 1995-12-04 | 1998-12-08 | Aetrium Incorporated | Test handler for DUT's |
JP2814997B2 (en) | 1996-08-08 | 1998-10-27 | 株式会社アドバンテスト | Semiconductor test equipment |
US5823818A (en) | 1997-01-21 | 1998-10-20 | Dell U.S.A., L.P. | Test probe for computer circuit board test fixture |
US6084421A (en) * | 1997-04-15 | 2000-07-04 | Delaware Capital Formation, Inc. | Test socket |
US6307394B1 (en) * | 1999-01-13 | 2001-10-23 | Micron Technology, Inc. | Test carrier with variable force applying mechanism for testing semiconductor components |
-
1999
- 1999-08-31 US US09/386,320 patent/US6246246B1/en not_active Expired - Fee Related
-
2001
- 2001-04-27 US US09/842,686 patent/US6459286B2/en not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100315617A1 (en) * | 2009-06-12 | 2010-12-16 | Semicaps Pte Ltd | Wafer stage |
US8436631B2 (en) * | 2009-06-12 | 2013-05-07 | Semicaps Pte Ltd | Wafer stage |
Also Published As
Publication number | Publication date |
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US6246246B1 (en) | 2001-06-12 |
US6459286B2 (en) | 2002-10-01 |
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