US20010008284A1 - Silicon-germanium BiCMOS on SOI - Google Patents
Silicon-germanium BiCMOS on SOI Download PDFInfo
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- US20010008284A1 US20010008284A1 US09/768,493 US76849301A US2001008284A1 US 20010008284 A1 US20010008284 A1 US 20010008284A1 US 76849301 A US76849301 A US 76849301A US 2001008284 A1 US2001008284 A1 US 2001008284A1
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- 229910000577 Silicon-germanium Inorganic materials 0.000 title claims abstract description 35
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 title description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 44
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 41
- 239000010703 silicon Substances 0.000 claims abstract description 41
- 238000002955 isolation Methods 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000000151 deposition Methods 0.000 claims description 28
- 238000000034 method Methods 0.000 claims description 27
- 229910045601 alloy Inorganic materials 0.000 claims description 14
- 239000000956 alloy Substances 0.000 claims description 14
- 239000012212 insulator Substances 0.000 claims description 7
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 5
- 229910021332 silicide Inorganic materials 0.000 claims description 5
- 229910021419 crystalline silicon Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 3
- 238000012545 processing Methods 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 42
- 150000004767 nitrides Chemical class 0.000 description 11
- 230000008569 process Effects 0.000 description 10
- 230000008021 deposition Effects 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000000171 gas-source molecular beam epitaxy Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8248—Combination of bipolar and field-effect technology
- H01L21/8249—Bipolar and MOS technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
Abstract
Description
- The field of the invention is silicon on insulator (SOI) integrated circuits incorporating BiCMOS circuitry.
- SiGe (silicon-germanium alloy) heterojunction bipolar transistors (HBTS) integrated with standard silicon CMOS forming the so-called SiGe BiCMOS circuits have been developed for analog/mixed signal applications in high-speed wireless and wired network communications. In SiGe BiCMOS, the base layer of the HBT is formed from SiGe alloy, different from conventional Si-only bipolar transistors which have a silicon base. Because of the narrow bandgap of SiGe alloy compared with the bandgap of the silicon emitter, the base layer can be highly doped to reduce the parasitic resistance without sacrificing the emitter efficiency. As a result, SiGe HBTs exhibit higher response frequency and higher gain as compared to the Si counterpart.
- A major development in the silicon CMOS technology is the use of silicon-on-insulator (SOI) substrates which are now available commercially.
- The integration of BiCMOS with SOI circuits opens another regime of high performance circuits also having low power consumption. Various integration schemes have been proposed previously; e.g. in U.S. Pat. No. 5,587,599 “Bipolar transistor and manufacturing method”, which disclosed a CMOS compatible bipolar transistor on an SOI substrate.
- Some other prior publications such as S. Parke, et al., “A versatile SOI BICMOS technology with complementary lateral BJT's,” IEEE IEDM 92, 453-456 (1992), also provided similar schemes.
- For technologies utilizing the shallow trench isolation and planarization approach, the integration of SOI with SiGe BICMOS suffers from the problem of processing compatibility. For partially depleted SOI silicon CMOS, the thin silicon film on top of the buried oxide should be about 0.1 μm to 0.2 μm thick, whereas the thickness of the silicon collector in the SiGe HBT (underneath the SiGe base layer) should be about 0.5 μm, substantially thicker than the CMOS silicon.
- It is therefore the objective of the present disclosure to provide an integration scheme to fabricate SiGe HBT on a partially depleted silicon SOI CMOS circuits.
- The invention relates to an integrated BiCMOS circuits on SOI, in which the bipolar transistors are formed with a silicon-germanium (SiGe) alloy base and an epitaxial silicon collector. The collector thickness is much thicker than the Si device layer in the SOI wafer.
- An optional feature of the invention is the use of selective implantation of oxygen atoms for the buried oxide layer so that some or all of the bipolar transistors may be separated from the SOI region.
- A feature of the invention is the use of shallow trench isolation on two levels- in the device layer to isolate the CMOS devices, and in the epitaxial silicon collector layer to provide isolation between base and collector junctions within one HBT device, as well as isolation between different devices.
- An added feature of using the shallow trench is the complete isolation of bipolar device from the substrate by etching the shallow trench between devices down to the buried oxide. This eliminates the costly use of deep trench isolation to reduce device coupling to the substrate in the prior art.
- FIGS.1-5 illustrate a portion of an integrated circuit at various steps of the process.
- Referring now to FIG. 1, there is shown a portion of an integrated circuit after the completion of preliminary steps. A
silicon wafer 10 has a buriedoxide insulating layer 100 formed below adevice layer 120 of crystalline silicon. The buried layer can be formed by any convenient method, but SIMOX (Separation by Implantation of OXide) is preferred.Layer 100 does not extend entirely across the circuit and an optional feature of the invention is that portions of the bipolar area may be blocked during oxygen implantation in order to put bipolar transistors over the bulk silicon instead of over the buried oxide. Additional preparatory steps, such as implantation of the device layer to form transistor bodies of the desired polarity and of pad oxide and nitride are included along with forming the buried layer in the term “preparing the substrate”. Such steps may be performed before or after the deposition ofepitaxial layer 220 or after it has been removed in the CMOS transistor area. - An epitaxial deposition of silicon at a temperature of about 1050°C. has deposited
silicon layer 220, nominally 0.5 μm or thicker and doped n-type, that will form the collectors of the bipolar transistors. On the right and left of the Figure,protective layer 222 covers two areas that will contain a bipolar transistor.Protective layer 145 in the center defines a CMOS area.Layers - Referring now to FIG. 2,
silicon layer 220 above the CMOS area has been removed, usinglayer 145 as an etch stop and two sets of shallow isolation trenches (STI) have been formed by patterning the nitride layers to expose the trench area, then etching in a conventional process. The remainder oflayer 145 has been stripped and a set of CMOS field effect transistors (p-type and n-type) has been formed by a conventional CMOS process in the CMOS region of the wafer, havinggates 170,sidewalls 176 for the formation of a low-doped drain, andsalicide areas 174 above the source and drain and 172 above the gate. Any conventional transistor formation process may be used. Simultaneous formation of theupper STI 141 and thelower STI 140 is optional and the upper STI may be formed later if that is desired. Aprotection layer 142, preferably is deposited above the CMOS area, which also serves as an etch stop for a later contact opening etch. - The
STI 140 for CMOS can also be formed before the collector epitaxial silicon deposition, and planarized by chemical-mechanical polishing (CMP), not shown in the Figure, as a part of the substrate preparation. - The preferred thickness of the collector layer is about 0.5 μm to ensure proper breakdown voltage. Since the preferred thickness of the device layer for partial depletion of the CMOS transistors is about 0.1 μm-0.2 μm, the epitaxial layer is required in order to get the correct thickness for the bipolar transistors.
- Next, as in FIG. 3, the space above the CMOS region, is covered with an
insulating layer 180, preferably TEOS (tetra-ethyl ortho-siloxane) and the TEOS is polished to the level ofpolish stop 222. This insulating layer fills trenches 140, the area between the CMOS transistors and the area above the transistors in the CMOS region and thesecondary STI 141. - After the planarization, the remainder of
layer 222 is stripped and an epitaxial deposition of SiGe alloy is put down by a process such as molecular beam epitaxy (MBE), ultra-high vacuum chemical vapor deposition (UHV-CVD), or gas-source MBE, etc. The SiGe alloy base is illustratively 100 nm thick. The Ge content in the SiGe alloy base is typically 10%-20%, which is limited by the allowed critical thickness for high quality epitaxial growth of strained SiGe on Si. The Ge content in the base layer can be graded to form an internal electrical field to accelerate carrier transport through the base region, and hence increase device response speed. - If a selective epitaxial growth of SiGe alloy is used, e.g., via gas source MBE or UHVCVD, such that SiGe alloy only grows on the area of crystalline silicon collector not on
layer 180 in the STI and over the CMOS region, the base is self-aligned to the collector, and no etch back is needed. If a blanket deposition is used, an etch stop layer should be deposited as required and the SiGe alloy on the CMOS region and over the HBT collector contact region will be stripped. The SiGe base is formed to cover the silicon collector, but no critical alignment is necessary. - On the edge of the epi block above the buried oxide, an area denoted by the
numeral 325 will be used for the collector contact of the bipolar transistor, as shown in FIG. 3. The reason forcollector contact 325 is that this bipolar transistor is formed above theSOI layer 100, so thebulk silicon 10 cannot be used as the collector contact. If space and circuit layer considerations permitted, a group of bipolar transistors having the same collector voltage could share a common body contact to a separated portion ofdevice layer 120, thus eliminatingseveral contact areas 325 and saving space. - It is worth mentioning that by aligning the
first STI 140 with thefill oxide 180 as shown in FIG. 3, the bipolar transistors can be completely encapsulated by the oxide, thus achieving device isolation from the substrate. This scheme eliminates the need for deep trench isolation for Si bipolar transistors on a bulk silicon substrate, as used by the prior art, and constitutes a significant cost reduction. - Referring now to FIG. 4, the bipolar transistors have been completed with
collectors 220,SiGe bases 320 andpolysilicon emitters 330. On the right of FIG. 4, a second bipolar transistor is formed above thebulk silicon 10, with the bulk layer being the collector contact. - The extrinsic base/collector and/or emitter will form self-aligned
silicide 476 for a low-resistance contact. As an option, silicide can be formed for CMOS and HBT at the same time, before the TEOS fill and planarization. That will drastically reduce process complexity as compared to a separated silicide process. - The sets of CMOS and bipolar transistors represented by the examples in the figures are then connected to form the desired circuit. FIG. 5 shows a set of
contact vias 420 extending down from asurface 187 ininsulator 185 to the bipolar and CMOS transistors. Abovesurface 187, conventional back end processes may be used to connect up the circuit. - Those skilled in the art will be aware that the level containing the gates could be used for local interconnect, using the same poly that forms the gates, extending between CMOS transistors and/or between a collector and another collector or to a CMOS transistor. Similarly, the
level containing oxide 180 could be used for interconnect, either poly or metal. Planarization could be done in this area by using reflow glass instead of chemical-mechanical polishing used for planarization in the preferred embodiment. In FIG. 3,box 189 schematically represents such an interconnect layer. - If desired, the portion of
layer 120 below a bipolar collector could be implanted with the appropriate polarity to make it part of the collector and the thickness oflayer 220 could be correspondingly reduced. - During the planarization of oxide fill180, conventional overpolishing reduces the level of the fill in
STI 141, bringing the top surface of the fill closer to the top surface oflayer 220. Sincenitride 222 is initially only 50 nm thick, the step between the top surface ofblock 220 and the top of the fill is not significant. If the step does affect the deposition ofbase 320, the remainder oflayer 222 could be partially etched and a touchup polish used to remove the excess fill above the top surface ofcollector 220. - Those skilled in the art will appreciate that various alterations in the processing sequence may be used. Since epitaxial deposition is done at a relatively high temperature, it is preferable, but not essential, that
epi layer 220 be deposited before the CMOS transistors are formed. If a particular transistor process has a thermal budget that can stand the temperature, that process could be performed before the epi deposition. - Also, the
SiGe layer 320 could be deposited before opening the CMOS area and thepolish stop layer 222 could be placed on top of the SiGe. - While the invention has been described in terms of a single preferred embodiment, those skilled in the art will recognize that the invention can be practiced in various versions within the spirit and scope of the following claims.
Claims (20)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US09/768,493 US6288427B2 (en) | 1999-08-31 | 2001-01-24 | Silicon-germanium BiCMOS on SOI |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US09/387,326 US6235567B1 (en) | 1999-08-31 | 1999-08-31 | Silicon-germanium bicmos on soi |
US09/768,493 US6288427B2 (en) | 1999-08-31 | 2001-01-24 | Silicon-germanium BiCMOS on SOI |
Related Parent Applications (1)
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US09/387,326 Division US6235567B1 (en) | 1999-08-31 | 1999-08-31 | Silicon-germanium bicmos on soi |
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US20010008284A1 true US20010008284A1 (en) | 2001-07-19 |
US6288427B2 US6288427B2 (en) | 2001-09-11 |
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US09/387,326 Expired - Fee Related US6235567B1 (en) | 1999-08-31 | 1999-08-31 | Silicon-germanium bicmos on soi |
US09/768,493 Expired - Lifetime US6288427B2 (en) | 1999-08-31 | 2001-01-24 | Silicon-germanium BiCMOS on SOI |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
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US09/387,326 Expired - Fee Related US6235567B1 (en) | 1999-08-31 | 1999-08-31 | Silicon-germanium bicmos on soi |
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US (2) | US6235567B1 (en) |
KR (1) | KR100333582B1 (en) |
TW (1) | TW512523B (en) |
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KR100333582B1 (en) | 2002-04-22 |
TW512523B (en) | 2002-12-01 |
US6235567B1 (en) | 2001-05-22 |
KR20010050168A (en) | 2001-06-15 |
US6288427B2 (en) | 2001-09-11 |
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