US11211403B2 - Nonvolatile memory device having a vertical structure and a memory system including the same - Google Patents
Nonvolatile memory device having a vertical structure and a memory system including the same Download PDFInfo
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- US11211403B2 US11211403B2 US17/073,653 US202017073653A US11211403B2 US 11211403 B2 US11211403 B2 US 11211403B2 US 202017073653 A US202017073653 A US 202017073653A US 11211403 B2 US11211403 B2 US 11211403B2
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- H—ELECTRICITY
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- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
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- H01L27/11582—
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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- H01L27/11565—
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/20—Resistors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/564—Miscellaneous aspects
- G11C2211/5642—Multilevel memory with buffers, latches, registers at input or output
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/081—Disposition
- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
Definitions
- the inventive concept relates to a memory device, and more particularly, to a nonvolatile memory device having a vertical structure and a memory system including the same.
- a nonvolatile memory device comprising: a first semiconductor layer comprising a plurality of first word lines extending in a first direction, a first upper substrate and a first memory cell array; a second semiconductor layer comprising a plurality of second word lines extending in the first direction, second and third upper substrates adjacent to each other in the first direction and a second memory cell array, wherein the second memory cell array comprises a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate, wherein the first semiconductor layer and the second semiconductor layer shares a plurality of bit lines extending in a second direction; and a third semiconductor layer under the second semiconductor layer in a third direction perpendicular to the first and second directions, wherein the third semiconductor layer comprises a lower substrate that comprises a plurality of row decoder circuits and a plurality of page buffer circuits, wherein the first vertical structure comprises a first via area in which a first through-hole via is provided, wherein the first through-
- a nonvolatile memory device comprising: a first semiconductor layer comprising a first upper substrate, and a first memory cell array; a second semiconductor layer comprising a second upper substrate and a third upper substrate that are adjacent to each other in a first direction and a second memory cell array that comprises first and second vertical structures, the first and second vertical structures comprising a plurality of channel layers that vertically extend from the first and second upper substrates and first and second gate conductive layers that are respectively stacked on the second and third upper substrates alongside walls of the plurality of channel layers, wherein the first semiconductor layer and the second semiconductor layer shares a plurality of bit lines extending in a second direction; and a third semiconductor layer located under the second semiconductor layer in a vertical direction, the third semiconductor layer comprising a lower substrate that comprises a plurality of row decoder circuits, and a plurality of page buffer circuits, wherein the first vertical structure further comprises a first through-hole via that passes through the first vertical structure and is connected to
- a nonvolatile memory device comprising: a first semiconductor layer including a first memory cell array; a second semiconductor layer including a first vertical structure and a second vertical structure, each of the first and second vertical structures including gate conductive layers stacked in a first direction wherein the first semiconductor layer and the second semiconductor layer shares a plurality of bit lines extending in a second direction substantially perpendicular to the first direction; and a third semiconductor layer disposed under the second semiconductor layer along the first direction, the third semiconductor layer including a row decoder disposed under the first vertical structure and a page buffer disposed under the second vertical structure, wherein the first vertical structure includes a plurality of first partial blocks and a plurality of first via areas, the second vertical structure includes a plurality of second partial blocks and a plurality of second via areas, and at least one of the first partial blocks overlaps at least one of the second via areas in a third direction substantially perpendicular to the first direction and the second direction.
- FIG. 1 is a block diagram of a memory device according to an exemplary embodiment of the inventive concept
- FIG. 2 is a view illustrating a structure of a memory device according to an exemplary embodiment of the inventive concept
- FIG. 3 is a perspective view illustrating a first memo block from among memory blocks of FIG. 1 according to an exemplary embodiment of the inventive concept;
- FIG. 4 is a circuit diagram illustrating an equivalent circuit of the first memory block from among the memory blocks of FIG. 1 , according to an exemplary embodiment of the inventive concept;
- FIG. 5A is a view illustrating a structure of the memory device including first and second semiconductor layers according to an exemplary embodiment of the inventive concept
- FIG. 5B is a plan view illustrating a top surface of the second semiconductor layer contacting the first semiconductor layer of the memory device, according to an exemplary embodiment of the inventive concept;
- FIG. 5C is a plan view illustrating a top surface of the first semiconductor layer overlapping the plan view of FIG. 5B , according to an exemplary embodiment of the inventive concept;
- FIG. 6 is a cross-sectional view of the memory device according to an exemplary embodiment of the inventive concept
- FIG. 7 is a cross-sectional view of the memory device according to an exemplary embodiment of the inventive concept.
- FIGS. 8A and 8B are views for explaining an operation of a memory device including a partial block according to an exemplary embodiment of the inventive concept
- FIG. 9 is a table for explaining a use of a partial block according to an exemplary embodiment of the inventive concept.
- FIG. 10A is a view illustrating a partial block according to an exemplary embodiment of the inventive concept
- FIG. 10B is a block diagram illustrating various peripheral circuits electrically connected to the partial block of FIG. 10A according to an exemplary embodiment of the inventive concept;
- FIG. 11 is a cross-sectional view illustrating a partial block according to an exemplary embodiment of the inventive concept
- FIG. 12 is a cross-sectional view illustrating a partial block according to an exemplary embodiment of the inventive concept
- FIG. 13 is a plan view illustrating a top surface of the semiconductor layer according to an exemplary embodiment of the inventive concept
- FIG. 14A is a plan view illustrating a top surface of the first semiconductor layer according to an exemplary embodiment of the inventive concept
- FIG. 14B is a plan view illustrating a top surface of the second semiconductor layer according to an exemplary embodiment of the inventive concept.
- FIG. 15 is a block diagram of a solid-state drive (SSD) system including a memory device according to an exemplary embodiment of the inventive concept.
- SSD solid-state drive
- FIG. 16 is a diagram showing the structure of a memory device 200 according to an exemplary embodiment of the inventive concept.
- FIG. 17 is a diagram showing a memory device 600 according to an exemplary embodiment of the inventive concept.
- FIG. 1 is a block diagram of a memory device 100 according to an exemplary embodiment of the inventive concept.
- the memory device 100 may include a memory cell array 110 , a control logic circuit 120 , a row decoder 130 , and a page buffer 140 .
- the memory device 100 may further include a data input/output circuit or an input/output interface.
- the memory device 100 may further include various sub-circuits such as a voltage generating circuit for generating various voltages used to operate the memory device 100 and an error correction circuit for correcting an error in data read from the memory cell array 110 .
- the memory cell array 110 may include a plurality of memory cells, and may be connected to string selection lines SSL, word lines WL, ground selection lines GSL, and bit lines BL.
- the memory cell array 110 may be connected to the row decoder 130 through the string selection lines SSL, the word lines WL, and the ground selection lines GSL.
- the memory cell array 110 may be connected to the page buffer 140 through the bit lines BL.
- the plurality of memory cells included in the memory cell array 110 may be nonvolatile memory cells that retain data even when power is turned off. In other words, the memory cells may retain data in the absence of power.
- the memory device 100 may be an electrically erasable programmable read-only memory (EEPROM), a flash memory, a phase-change random-access memory (PRAM), a resistive RAM (RRAM), a nano-floating gate memory (NFGM), a polymer RAM (PoRAM), a magnetic RAM (MRAM) or a ferroelectric RAM (FRAM).
- EEPROM electrically erasable programmable read-only memory
- PRAM phase-change random-access memory
- RRAM resistive RAM
- NFGM nano-floating gate memory
- PoRAM polymer RAM
- MRAM magnetic RAM
- FRAM ferroelectric RAM
- the memory cell array 110 may include a plurality of memory blocks, e.g., first through z th memory blocks BLK 1 through BLKz, and each memory block may have a planar structure or a three-dimensional (3D) structure.
- the memory cell array 110 may include a single-level cell block including single-level cells (SLC), a multi-level cell block including multi-level cells (MLC), a triple-level cell block including triple-level cells (TLC), or a quad-level cell block including quad-level cells (QLC).
- SLC single-level cell block including single-level cells
- MLC multi-level cell block including multi-level cells
- TLC triple-level cell block including triple-level cells
- QLC quad-level cell block including quad-level cells
- some memory blocks from among the first through z th memory blocks BLK 1 through BLKz may be single-level cell blocks, and other memory blocks may be multi-level cell blocks, triple-level cell blocks, or quad-level cell blocks.
- the memory cell array 110 may include first and second vertical structures located on different upper substrates.
- the first vertical structure may include one or more first via areas and one or more first partial blocks and the second vertical structure may include one or more second via areas and one or more second partial blocks.
- first via area one or more first through-hole vias that pass through the first vertical structure and are connected to a second page buffer 144 are formed.
- second via area one or more through-hole vias that pass through the second vertical structure and are connected to a first page buffer 142 are formed.
- the through-hole vias of the first and second via areas are described below in detail.
- the control logic circuit 120 may receive a command CMD and a control signal CTRL from the outside of the memory device 100 .
- the control logic circuit 120 may control an overall operation of the memory device 100 .
- the control logic circuit 120 may control the memory device 100 to perform a memory operation corresponding to the command CMD applied from a memory controller.
- the control logic circuit 120 may generate various internal control signals used in the memory device 100 in response to the control signal CTRL applied from the memory controller.
- the control logic circuit 120 may adjust a level of a voltage applied to the word lines WL, the bit lines 13 L, and the ground selection lines GSL during a memory operation such as a program operation or an erase operation.
- the control logic circuit 120 may control the row decoder 130 and the page buffer 140 to simultaneously access first and second partial blocks from among the partial blocks.
- the control logic circuit 120 may control the row decoder 130 and the page buffer 140 to independently access the first and second partial blocks.
- the first and second partial blocks may be provided in different vertical structures.
- the first partial block may be accessed by a second row decoder 134 and the first page buffer 142 and the second partial block may be accessed by a first row decoder 132 and the second page buffer 144 , as described below in detail.
- the row decoder 130 may receive an address ADDR from the outside of the memory device 100 .
- the address ADDR may be applied from the memory controller.
- the row decoder 130 may select at least one of the first through z th memory blocks BLK 1 through BLKz in response to the address ADDR applied from the memory controller.
- the row decoder 130 may select at least one word line of the selected memory block in response to the address ADDR.
- the row decoder 130 may apply a voltage for performing a memory operation to the selected word line of the selected memory block. For example, during a program operation, the row decoder 130 may apply a program voltage and a verify voltage to the selected word line and may apply a pass voltage to non-selected word lines. In addition, the row decoder 130 may select some of the string selection lines SSL in response to the address ADDR.
- the row decoder 130 may include the first row decoder 132 and the second row decoder 134 .
- the first row decoder 132 may be connected to the second partial block and the second row decoder 134 may be connected to the first partial block.
- the page buffer 140 may transmit/receive data DATA to/from the outside of the memory device 100 .
- the page buffer 140 may be connected to the memory cell array 110 through the bit lines BL.
- the page buffer 140 may operate as a write driver or a sense amplifier.
- the page buffer 140 may operate as a write driver and may apply a voltage according to the data DATA to be stored in the memory cell array 110 to the bit lines BL.
- the page buffer 140 may operate as a sense amplifier and may sense the data DATA stored in the memory cell array 110 .
- the page buffer 140 may include the first page buffer 142 and the second page buffer 144 .
- the first page buffer 142 may be connected to the first partial block and the second page buffer 144 may be connected to the second partial block.
- FIG. 2 is a view illustrating a structure of a memory device according to an exemplary embodiment of the inventive concept.
- FIG. 2 may illustrate a structure of the memory device 100 of FIG. 1 . The following will be described with reference to FIG. 1 .
- the memory device 100 may include a first semiconductor layer L 1 and a second semiconductor layer L 2 .
- the first semiconductor layer L 1 may be stacked on the second semiconductor layer L 2 in a third direction.
- the memory cell array 110 may be formed on the first semiconductor layer L 1 , and at least one from among the control logic circuit 120 , the row decoder 130 , and the page buffer 140 may be formed on the second semiconductor layer L 2 .
- various circuits may be formed an the second semiconductor layer L 2 by forming semiconductor elements such as transistors and patterns for wiring the semiconductor elements on a lower substrate of the second semiconductor layer L 2 .
- the first semiconductor layer L 1 including the memory cell array 110 may be formed.
- the first semiconductor layer L 1 may include a plurality of upper substrates.
- the memory cell array 110 may be formed on the first semiconductor layer L 1 by forming a plurality of gate conductive layers stacked on each of the upper substrates and a plurality of pillars that pass through the plurality of gate conductive layers and extend in a vertical direction (e.g., the third direction) perpendicular to a top surface of each of the upper substrates.
- patterns for electrically connecting the memory cell array 110 e.g., the word lines WL and the bit lines BL
- the circuits formed on the second semiconductor layer L 2 may be formed on the first semiconductor layer L 1 .
- the word lines WL may extend in a first direction and may be arranged in a second direction.
- the bit lines may extend in the second direction and may be arranged in the first direction.
- the memory device 100 may have a cell-on-peri cell-over-peri (COP) structure in which the control logic circuit 120 , the row decoder 130 , the page buffer 140 , or various other peripheral circuits and the memory cell array 110 are arranged in a stacked direction (e.g., the third direction). Since, for example, circuits are located under the memory cell array 110 , the COP structure may reduce an area on a surface perpendicular to the stacked direction, and thus, the number of memory cells integrated in the memory device 100 may be increased.
- COP cell-on-peri cell-over-peri
- a plurality of pads for electrical connection to the outside of the memory device 100 may be provided.
- a plurality of pads for receiving the command CMD, the address ADDR, and the control signal CTRL from an external device of the memory device 100 may be provided, and a plurality of pads for inputting/outputting the data DATA may be provided.
- the pads may be located adjacent to a peripheral circuit, which processes a signal transmitted to the outside of the memory device 100 or a signal received from the outside of the memory device 100 , in a vertical direction (e.g., the third direction) or a horizontal direction (e.g., the first direction or the second direction).
- FIG. 3 is a perspective view illustrating the first memory block BLK 1 from among the memory blocks of FIG. 1 according to an exemplary embodiment of the inventive concept.
- the first memory block BLK 1 may be formed in a vertical direction perpendicular to a substrate SUB. Although the first memory block BLK 1 includes two selection tines (e.g., the ground selection lure GSL and the string selection line SSL), eight word lines first through eighth word lines WL 1 through WL 8 ), and three bit lines (e.g., first through third bit lines BL 1 through BL 3 ), the first memory block BLK 1 may include more or less of these elements than illustrated in FIG. 3 . In addition, in an exemplary embodiment of the inventive concept, the first memory block BLK 1 may include one or more dummy word lines between the first word line WL 1 and the ground selection line GSL.
- the first memory block BLK 1 may include one or more dummy word lines between the first word line WL 1 and the ground selection line GSL.
- the substrate SUB may be a polysilicon film doped with an impurity of a first conductivity type (e.g., a p-type).
- the substrate SUB may be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or a substrate of an epitaxial thin film obtained by performing selective epitaxial growth (SEG).
- the substrate SUB may include a semiconductor material.
- the substrate SUB may include silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), or a combination thereof.
- a common source line CSL that extends in the first direction and is doped with an impurity of a second conductivity type may be provided in the substrate SUB.
- a plurality of insulating films IL that extend in the first direction may be sequentially provided on a portion of the substrate SUB between two adjacent common source lines CSL in the third direction.
- the plurality of insulating films IL may be spaced apart from each other by a certain distance in the third direction.
- each of the plurality of insulating films IL may include an insulating material such as silicon oxide.
- a plurality of pillars P that are sequentially arranged in the second direction and pass through the plurality of insulating films IL in the third direction may be provided on a portion of the substrate SUB between two adjacent common source lines CSL.
- the plurality of pillars P may pass through the plurality of insulating films IL and may contact the substrate SUB.
- a surface layer S of each of the pillars P may include a silicon material doped with an impurity of the first conductivity type, and may function as a channel region.
- An inside I of each of the pillars P may include an insulating material such as silicon oxide or an air gap.
- a charge storage layer CS may be provided along exposed surfaces of the insulating films IL, the pillars P, and the substrate SUB, in an area between two adjacent common source lines CSL.
- the charge storage layer CS may include a gate insulating layer (e.g., a ‘tunneling insulating layer’), a charge trap layer, and a blocking insulating layer.
- the charge storage layer CS may have an oxide-nitride-oxide (ONO) structure.
- gate electrodes GE such as the ground and string selection lines GSL and SSL and the first through eighth word lines WL 1 through WL 8 may be provided on an exposed surface of the charge storage layer CS, in areas between two adjacent common source lines CSL.
- Drains or drain contacts DR may be respectively provided on the plurality of pillars P.
- each of the drains or the drain contacts DR may include a silicon material doped with an impurity of the second conductivity type.
- the first through third bit lines BL 1 through BL 3 that extend in a second direction and are spaced apart by certain distance in the first direction may be provided on the drain contacts DR.
- FIG. 4 is a circuit diagram illustrating an equivalent circuit of the first memory block BLK 1 from among the memory blocks of FIG. 1 , according to an exemplary embodiment of the inventive concept.
- the first memory block BLK 1 may be a vertical NAND flash memory, and each of the first through z th memory blocks BLK 1 through BLKz of FIG. 1 may be implemented as shown in FIG. 4 .
- the first memory block BLK 1 may include a plurality of NAND strings NS 11 through NS 33 , a plurality of word lines, e.g., the first through eighth word lines WL 1 through WL 8 , a plurality of bit lines, e.g., the first through third bit lines BL 1 through BL 3 , a plurality of ground selection lines, e.g., first through third ground selection lines GSL 1 through GSL 3 , a plurality of string selection fines, e.g., first through third string selection lines SSL 1 through SSL 3 , and the common source line CSL.
- the number of NAND strings, the number of word lines, the number of bit lines, the number of ground selection lines, and the number of string selection lines may be changed in various ways according to exemplary embodiments
- the NAND strings NS 11 , NS 21 , and NS 31 are provided between the first bit line BL 1 and the common source line CSL
- the NAND strings NS 12 , NS 22 , and NS 32 are provided between the second bit line BL 2 and the common source line CSL
- the NAND strings NS 13 , NS 23 , and NS 33 are provided between the third bit line BL 3 and the common source line CSL.
- Each NAND string (e.g., NS 11 ) may include a string selection transistor SST, a plurality of memory cells MC 1 through MC 8 , and a ground selection transistor GST.
- NAND strings commonly connected to one bit line may constitute one column.
- the NAND strings NS 11 , NS 21 , and NS 31 commonly connected to the first bit line BL 1 may correspond to a first column
- the AND strings NS 12 , NS 22 , and NS 32 commonly connected to the second bit line BL 2 may correspond to a second column
- the NAND strings NS 13 , NS 23 , and NS 33 commonly connected to the third bit line BL 3 may correspond to a third column.
- NAND strings connected to one string selection line may constitute one row.
- the NAND strings NS 11 , NS 12 , and NS 13 connected to the first string selection line SS 1 may correspond to a first row
- the NAND strings NS 21 , NS 22 , and NS 23 connected to the second string selection line SSL 2 may correspond to a second row
- the NAND strings NS 31 , NS 32 , and NS 33 connected to the third string selection line SSL 3 may correspond to a third row.
- the string selection transistors SST may be connected to the first through third string selection lines SSL 1 through SSL 3 .
- the plurality of memory cells MC 1 through MC 8 may be respectively connected to the first through eighth word lines WL 1 through WL 8 .
- the ground selection transistors GST may be connected to the first through third ground selection lines GSL 1 through GSL 3 , and the string selection transistors SST may be corrected to the first through third bit lines BL 1 through BL 3 .
- the ground selection transistors GST may be connected to the common source line CSL.
- word lines at the same height are commonly connected, the first through third string selection lines SSL 1 through SSL 3 at the same height are separated from one another, and the first through third ground selection lines GSL 1 through GSL 3 at the same height are separated from one another.
- the inventive concept is not limited thereto, and in other embodiments, the first through third ground selection lines GSL 1 through GSL 3 may be commonly connected.
- FIG. 5A is a view illustrating a structure of the memory device 100 including the first and second semiconductor layers L 1 and L 2 according to an exemplary embodiment of the inventive concept.
- FIG. 5B is a plan view illustrating a top surface of the second semiconductor layer L 2 contacting the first semiconductor layer L 1 of the memory device 100 , according to an exemplary embodiment of the inventive concept.
- FIG. 5C is a plan view illustrating a top surface of the first semiconductor layer L 1 overlapping the plan view of FIG. 5B , according to an exemplary embodiment of the inventive concept.
- the first and second semiconductor layers L 1 and L 2 are spaced apart from each other in the third direction for convenience of explanation. However, a bottom surface of the first semiconductor layer L 1 and the top surface of the second semiconductor layer L 2 actually contact each other as shown in FIG. 2 .
- the first and second row decoders 132 and 134 may extend in a direction (e.g., the second direction in which the word lines WL are arranged) perpendicular to a direction in which the word lines WL extend.
- the first and second page buffers 142 and 144 may extend in a direction (e.g., the first direction in which the bit lines BL are arranged) perpendicular to the bit lines BL.
- the row decoder 130 (see FIG. 1 ) and the page buffer 140 (see FIG. 1 ) may be divided into two or more parts and may be arranged as shown in FIGS. 5A and 5B to increase the area of the row decoder 130 and the page buffer 140 overlapping the memory cell array 110 (see FIG. 1 ) of the first semiconductor layer L 1 in the third direction.
- the second semiconductor layer L 2 may be divided into first through fourth regions R 1 through R 4 by a first virtual line X 0 -X 0 ′ in the first direction parallel to the word lines WL and a second virtual line Y 0 -Y 0 ′ in the second direction parallel to the bit lines BL.
- the first virtual line X 0 -X 0 ′ and the second virtual line Y 0 -Y 0 ′ may overlap the memory cell array 110 (see FIG. 1 ) located on the first semiconductor layer L 1 in the third direction.
- at least a part of each of the first through fourth regions R 1 through R 4 may overlap the memory cell array 110 located on the first semiconductor layer L 1 in the third direction.
- the first and second row decoders 132 and 134 may be respectively located in the second and third regions R 2 and R 3 , and the first and second page buffers 142 and 144 may be respectively located in the first and fourth regions R 1 and R 4 .
- the first through fourth regions R 1 through R 4 have the same area in the present embodiment, the inventive concept is not limited thereto.
- the memory cell array 110 may be located on the first semiconductor layer L 1 , and the memory cell array 110 may include a first vertical structure VS_ 1 and a second vertical structure VS_ 2 . As shown in FIG. 5C , the memory cell array 110 may include a plurality of memory blocks, e.g., first through twelfth memory blocks BLK 1 through BLK 12 formed as the first and second vertical structures VS_ 1 and VS_ 2 . The first through twelfth memory blocks BLK 1 through BLK 12 may be arranged in the second direction. Although the number of memory blocks is 12 in the present embodiment, the inventive concept is not limited thereto.
- the first vertical structure VS_ 1 may include a plurality of first partial blocks SB_ 1 through SB_ 4 and a plurality of first via areas VA_ 1 through VA_ 2 .
- the second vertical structure VS_ 2 may include a plurality of second partial blocks SB_ 5 through SB_ 8 and a plurality of second via areas VA_ 3 and VA_ 4 .
- the inventive concept is not limited to the number of first and second partial blocks and the number of first and second via areas illustrated in the present embodiment.
- first through-hole vias that each pass through the first vertical structure VS_ 1 and are connected to the first page buffer 142 may be formed.
- second through-hole vias that each pass through the second vertical structure VS_ 2 and are connected to the second page buffer 144 may be formed.
- At least one of the first partial blocks SB_ 1 through SB_ 4 may be electrically connected to the second row decoder 134 .
- at least one of the second partial blocks SB_ 5 through SB_ 8 may be electrically connected to the first row decoder 132 .
- At least parts of the first partial blocks SB_ 1 and SB_ 2 may overlap the second via area VA_ 3 in the first direction.
- the second via area VA_ 3 may overlap at least parts of the first partial blocks SB_ 1 and SB_ 2 .
- at least parts of the first partial blocks SB_ 3 and SB_ 4 may overlap the second via area VA_ 4 in the first direction.
- At least parts of the second partial blocks SB_ 5 and SB_ 6 may overlap the first via area VA_ 1 in the first direction.
- at least parts of the second partial blocks SB_ 7 and SB_ 8 may overlap the first via area VA_ 2 in the first direction.
- FIG. 6 is a cross-sectional view of the memory device 100 according to an exemplary embodiment of the inventive concept.
- FIG. 6 is a cross-sectional view taken along line VI-VI′ of FIG. 5C , illustrating configurations of the first and second semiconductor layers L 1 and L 2 .
- FIG. 6 is a cross-sectional view of the first memory block BLK 1 provided on the first semiconductor layer L 1 and the second semiconductor layer L 2 overlapping the first memory block BLK 1 .
- the second semiconductor layer L 2 may include a lower substrate L_SUB, and the second row decoder 134 and the second page buffer 144 formed on the lower substrate L_SUB.
- the second semiconductor layer L 2 may include a plurality of first lower contacts LMC 1 electrically connected to the second row decoder 134 , a first lower conductive line PM 1 electrically connected to the plurality of first lower contacts LMC 1 , and a lower insulating layer IL 1 covering the plurality of first lower contacts LMC 1 and the first lower conductive line PM 1 .
- the lower substrate L_SUB may be a semiconductor substrate including a semiconductor material such as single-crystal silicon or single-crystal germanium, and may be manufactured from a silicon wafer.
- the second row decoder 134 and the second page buffer 144 may be formed on portions of the lower substrate L_SUB.
- the second row decoder 134 and/or the second page buffer 144 may be formed by forming a plurality of transistors on the lower substrate L_SUB.
- the first semiconductor layer L 1 may include a first upper substrate U_SUB_ 1 , a second upper substrate U_SUB_ 2 , the first vertical structure VS_ 1 located on the first upper substrate U_SUB_ 1 , and the second vertical structure VS_ 2 located on the second upper substrate U_SUB_ 2 .
- the first semiconductor layer L 1 may include a plurality of first upper contacts UMC 1 , a plurality of first bit lines BL 1 , a plurality of first edge contacts EC 1 , and a plurality of first upper conductive lines UPM 1 which are electrically connected to the first vertical structure VS_ 1 .
- the first semiconductor layer L 1 may include a plurality of second upper contacts UMC 2 , a plurality of second bit lines BL 2 , a plurality of second edge contacts EC 2 , and a plurality of second upper conductive lines UPM 2 which are electrically connected to the second vertical structure VS_ 2 .
- the first semiconductor layer L 1 may include an tapper insulating layer IL 2 covering the first and second vertical structures VS_ 1 and VS_ 2 and various conductive lines.
- the first and second upper substrates U_SUB_ 1 and U_SUB_ 2 may be support layers that respectively support first and second gate conductive layers GS_ 1 and GS_ 2 .
- the first and second upper substrates U_SUB_ 1 and U_SUB_ 2 may be, for example, base substrates.
- Each of the first and second upper substrates U_SUB_ 1 and U_SUB_ 2 may be a polysilicon film doped with an impurity of a first conductivity type (e.g., a p-type).
- Each of the first and second upper substrates U_SUB_ 1 and U_SUB_ 2 may be a bulk silicon substrate, an SOI substrate, a germanium substrate, a GOI substrate, a silicon-germanium substrate, or a substrate of an epitaxial thin film obtained by performing SEG.
- Each, of the first and second upper substrates U_SUB_ 1 and U_SUB_ 2 may include a semiconductor material.
- each of the first and second upper substrates U_SUB_ 1 and U_SUB_ 2 may include Si, Ge, SiGe, GaAs, InGaAs, AlGaAs, or a combination thereof.
- the first vertical structure VS_ 1 may include the first gate conductive layers GS_ 1 located on the first upper substrate U_SUB_ 1 , and a plurality of pillars P 1 that pass through the first gate conductive layers GS_ 1 and extend in the third direction on a top surface of the first upper substrate U_SUB_ 1 .
- the first gate conductive layers GS_ 1 may include a ground selection line GSL_ 1 , word lines WL 1 _ 1 through WL 4 _ 1 , and a string selection line SSL_ 1 .
- the ground selection line GSL_ 1 , the word lines WL 1 _ 1 through WL 4 _ 1 , and the string selection line SSL_ 1 may be sequentially formed on the first upper substrate U_SUB_ 1 , and an insulating layer 52 may be located under or over each of the first gate conductive layers GS_ 1 . Since the first and second vertical structures VS_ 1 and VS_ 2 have corresponding configurations in the cross-sectional view taken along line VI-VI′ of the first memory block BLK 1 of FIG. 6 , a repeated explanation of elements of the second vertical structure VS_ 2 corresponding to those of the first vertical structure VS_ 1 may not be given.
- the second vertical structure VS_ 2 may include a plurality of pillars P 2 that pass through the second gate conductive layers GS_ 2 .
- Each of the pillars P 2 may include a surface layer S 2 and an inside I 1 .
- the second gate conductive layers GS_ 2 may include a ground selection line GSL_ 2 , word lines WL 1 _ 2 through WL 4 _ 2 , and a string selection line SSL_ 2 .
- An insulating layer 62 may be located under or over each of the second gate conductive layers GS_ 2 .
- word lines are formed in the first vertical structure VS_ 1 in the present embodiment, the inventive concept is not limited thereto.
- a various number of word lines may be stacked between the ground selection line GSL_ 1 and the string selection line SSL_ 1 in a vertical direction (e.g., the third direction) perpendicular to the first upper substrate U_SUB_ 1 and the insulating layer 52 may be located between adjacent word lines.
- two or ore ground selection lines GSL_ 1 and two or more string selection lines SSL_ 1 may be stacked in the vertical direction.
- Each of the plurality of pillars P 1 may include a surface layer S 1 and an inside I 1 .
- the surface layer S 1 of each of the pillars P 1 may include a silicon material doped with an impurity, or a silicon material not doped with an impurity.
- the surface layer S 1 may function as, for example, a channel region.
- the surface layer S 1 may be formed to have a cup shape (or a cylindrical shape with a closed bottom) that extends in the third direction.
- the inside I 1 of each of the pillars P 1 may include an insulating material such as silicon oxide or an air gap.
- the ground selection line GSL_ 1 and a portion of the surface layer S 1 adjacent to the ground selection line GSL_ 1 may constitute the ground selection transistor GST (see FIG. 4 ).
- the word lines WL 1 _ 1 through WL 4 _ 1 and a portion of the surface layer S 1 adjacent to the word lines WL 1 _ 1 through WL 4 _ 1 may constitute the memory cell transistors MC 1 through MC 8 (see FIG. 4 ).
- the string selection line SSL_ 1 and a portion of the surface layer S 1 adjacent to the string selection line SSL_ 1 may constitute the string selection transistor SST (see FIG. 4 ).
- a drain region DR 1 may be formed, on the pillar P 1 .
- a drain region DR 2 may be formed on the pillar P 2 .
- the drain region DR 1 may include a silicon material doped with an impurity.
- the drain legion DR 1 may be a channel pad.
- the drain region DR 1 may be electrically connected to the first bit line BL 1 through the first upper contact UMC 1 .
- An etch-stop film 53 may be formed on a side wall of the drain region DR 1 .
- An etch-stop film 63 may be formed on a side wall of the drain region DR 2 .
- a top surface of the etch-stop film 53 may be formed at the same level as a top surface of the drain region DR 1 .
- the etch-stop film 53 may include an insulating material such as silicon nitride or silicon oxide.
- the first vertical structure VS_ 1 may include an edge region EG 1 .
- the second vertical structure VS_ 2 may include an edge region EG 2 .
- a cross-section of the edge region EG 1 may form a stepped pad structure.
- the stepped pad structure may be referred to as a “word line pad”.
- the plurality of first edge contacts EC 1 may be connected to the edge region EG 1 , and an electrical signal may be applied from a peripheral circuit such as the second row decoder 134 through the first edge contacts EC 1 .
- a contact plug MCP 1 that passes through the first vertical structure VS_ 1 , the first upper substrate U_SUB_ 1 , and a part of the second semiconductor layer L 2 may have one side connected to the first lower conductive line PM 1 and the other side electrically connected to the edge region EG 1 through the first upper conductive lines UPM 1 .
- At least some of the first edge contacts EC 1 may pass through parts of the first and second semiconductor layers L 1 and L 2 in the third direction between the first and second upper substrates U_SUB_ 1 and U_SUB_ 2 and may have one side electrically connected to a contact plug connected to the lower conductive line (e.g., PM 1 ).
- the contact plug MCP 1 may include an insulating film pattern IP 1 and a conductive pattern MP 1 .
- a contact plug MCP 2 that passes through the second vertical structure VS_ 2 , the second upper substrate U_SUB_ 2 , and a part of the second semiconductor layer L 2 may have one side connected to the first lower conductive line PM 1 and the other side electrically connected to the edge region EG 2 through the second upper conductive lines UPM 2 .
- the contact plug MCP 2 may include an insulating film pattern IP 2 and a conductive pattern MP 2 .
- FIG. 7 is a cross-sectional view of the memory device 100 according to an exemplary embodiment of the inventive concept.
- FIG. 7 is a cross-sectional view taken along line VII-VII′ of FIG. 5C , illustrating configurations of the first and second semiconductor layers L 1 and L 2 .
- FIG. 7 may be a cross-sectional view illustrating the first partial block SB_ 1 and the second via area VA_ 3 provided on the first semiconductor layer L 1 and the second semiconductor layer L 2 overlapping the first partial block SB_ 1 and the second via area VA_ 3 .
- a repeated explanation of the same elements in FIG. 6 may not be given in FIG. 7 .
- a plurality of through-hole vias THV passing through the second vertical structure VS_ 2 , the second upper substrate U_SUB_ 2 , and a part of the second semiconductor layer L 2 may be formed in the second via region VA_ 3 .
- Each of the through-hole vias THV may include an insulating film pattern IP 3 and a conductive pattern MP 3 .
- each of the through-hole vias THV may electrically connect the second page buffer 144 and the second upper contact UMC 2 .
- the second upper contact UMC 2 may be connected to the second bit line BL 2 .
- the second bit lines BL 2 may be electrically connected to the second page buffer 144 formed on the second semiconductor layer L 2 through the plurality of through-hole vias THV formed in the second via area VA_ 3 .
- the plurality of trough-hole vias THV may be connected to the second page buffer 144 via second and third lower conductive lines PM 2 and PM 3 , for example.
- the second and third lower conductive lines PM 2 and PM 3 may be connected to the second page buffer 144 via second lower contacts LMC 2 for example.
- conductive patterns such as contacts may not be formed in the edge region EG_V of the second via area VA_ 3 .
- additional dummy conductive patterns may be formed in the edge region EG_V.
- the first partial block SB_ 1 may overlap at least a part of the first via area VA_ 3 in the first direction.
- the first partial block SB_ 1 may include the plurality of pillars P 1 that pass through the first gate conductive layers GS_ 1 and extend in the third direction on a top surface of the first upper substrate U_SUB_ 1 .
- a plurality of edge contacts EC_S may be connected to an edge region EG_S of the first partial block SB_ 1 .
- An electrical signal may be applied from a peripheral circuit such as the second row decoder 134 through the plurality of edge contacts EC_S.
- the first partial block SB_ 1 may include a plurality of strings including a plurality of memory cells and may function as a partial memory block.
- the memory device 100 since the memory device 100 according to an exemplary embodiment of the inventive concept includes partial blocks overlapping a via area where through-hole vias are formed in the first direction, a deuce of integration may be increased. In addition, since the partial blocks may function as spare blocks, the number of additional spare blocks may be reduced. Accordingly, a chip size of the memory device 100 may be reduced.
- FIGS. 8A and 8B are views for explaining an operation of a memory device including a partial block according to an exemplary embodiment of the inventive concept.
- the first memory block BLK 1 from among the first through twelfth memory blocks BLK 1 through BLK 12 may be accessed as a selected memory block SLT_BLK.
- the selected memory block SLT_BLK may be accessed, for example, by the row decoder 130 (see FIG. 1 ) and the page buffer 140 (see FIG. 1 ).
- the memory device 100 in a normal operation, may perform an access operation in units of memory blocks.
- each of the partial blocks SB_ 1 through SB_ 8 may be independently accessed.
- the partial blocks SB_ 1 through SB_ 8 may be accessed by the row decoder 130 (see FIG. 1 ) and the page buffer 140 (see FIG. 1 ) under the control of the control logic circuit 120 (see FIG. 1 ).
- the first partial block SB_ 1 may be accessed as a selected partial block SLT_SB.
- any of the partial blocks SB_ 1 through SB_ 8 may be independently accessed as selected partial blocks SLT_SB, and various memory operations such as a program operation, an erase operation, and a read operation may be performed.
- two partial blocks SB_ 1 and SB_ 8 from among the partial blocks SB_ 1 through SB_ 8 may be simultaneously accessed as the selected partial blocks SLT_SB.
- the row decoder 130 (see FIG. 1 ) and the page buffer 140 (see FIG. 1 ) may simultaneously access one of the first partial blocks SB_ 1 through SB_ 4 and one of the second partial blocks SB_ 5 through SB_ 8 under the control of the control logic circuit 120 (see FIG. 1 ).
- the partial blocks SB_ 1 and SB_ 8 simultaneously accessed as the selected partial blocks SLT_SB may be accessed as memory blocks having the same memory size as that of the selected memory block SLT_BLK.
- the partial blocks SB_ 1 through SB_ 8 may function as spare blocks for the first through twelfth memory blocks BLK 1 through BLK 12 .
- FIG. 9 is a table for explaining a use of a partial block according to an exemplary embodiment of the inventive concept.
- the table of FIG. 9 shows a type of data stored in the partial blocks SB_ 1 through SB_ 8 (see FIG. 8A ) and the number of the partial blocks SB_ 1 through SB_ 8 in which each data is stored when the partial blocks SB_ 1 through SB_ 8 function as spare blocks.
- L, M, N, P, and Q which are natural numbers equal to or greater than 1, may be the same or different from one another.
- the partial blocks SB_ 1 through SB_ 8 when the partial blocks SB_ 1 through SB_ 8 (see FIG. 8A ) function as spare blocks for the first through twelfth memory blocks BLK 1 through BLK 12 (see FIG. 8A ), at least one from among firmware (F/W) data, debug data, security data, meta data, and garbage collection (GC) data may be stored in each of the partial blocks SB_ 1 through SB_ 8 (see FIG. 8A ).
- firmware (F/W) data firmware
- debug data debug data
- security data security data
- meta data meta data
- garbage collection (GC) data garbage collection
- GC garbage collection
- the inventive concept is not limited thereto, and various other pieces of data may be stored in the partial blocks SB 1 through SB_ 8 (see FIG. 8A ).
- the data stored in the partial blocks SB_ 1 through SB_ 8 may be relatively small.
- the data stored in the partial blocks SB_ 1 through SB_ 8 may be data stored according to the number of blocks.
- the F/W data may be stored in L memory blocks
- the debug data may be stored in M memory blocks.
- the security data may be stored in N memory blocks
- the meta data may be stored in P memory blocks
- the GC data may be stored in Q memory blocks.
- FIG. 10A is a view illustrating a partial block according to an exemplary embodiment of the inventive concept.
- FIG. 10B is a block diagram illustrating various peripheral circuits electrically connected to the partial block of FIG. 10A according to an exemplary embodiment of the inventive concept.
- a plurality of contacts MCPa may be formed in partial blocks SB_ 1 a and SB_ 2 a .
- the partial blocks SB_ 1 a and SB_ 2 a may include gate conductive layers (e.g., GS_ 1 of FIG. 7 ), and the plurality of contacts MCPa may pass through the gate conductive layers and may be spaced apart from one another.
- At least some of the plurality of contacts MCPa may be connected to at least one of a plurality of peripheral circuits included in the memory device 100 (see FIG. 1 ) and may function as a capacitor.
- the contact MCPa may constitute an upper electrode or a lower electrode of a capacitor.
- a peripheral circuit 150 uses at least some of the contacts MCPa of FIG. 10A as a capacitor.
- the peripheral circuit 150 may include a column logic 151 , an internal voltage generator 152 _ 1 , a high voltage generator 152 _ 2 , a pre-decoder 153 , a temperature sensor 154 , a command decoder 155 , an address decoder 156 , a moving zone controller 157 , a scheduler 158 , and a test/measurement circuit 159 .
- Elements of the peripheral circuit 150 of FIG. 10B are exemplary, and the peripheral circuit 150 according to an exemplary embodiment of the inventive concept may include elements not illustrated in FIG. 108 and may include elements different from those illustrated in FIG. 10B .
- FIG. 10B will be described with reference to FIG. 1 .
- the column logic 151 may generate a signal for driving the page buffer 140 .
- the pre-decoder 153 may generate a signal to determine a timing of a signal for driving the row decoder 130 .
- the internal voltage generator 152 _ 1 may generate voltages used in the memory device 100 , for example, voltages applied to word lines and bit lines, reference voltages, and power supply voltages.
- the high voltage generator 152 _ 2 may include a charge pump and a regulator, and may generate high voltages used to program or erase memory cells of the memory cell array 110 .
- the temperature sensor 154 may sense a temperature of the memory device 100 and may output a signal corresponding to the sensed temperature.
- the command decoder 155 may latch and decode a command CMD received from the outside of the memory device 100 , and may set an operation mode of the memory device 100 according to the decoded command CMD.
- the address decoder 156 may latch and decode an address signal ADDR received from the outside of the memory device 100 , and may activate a memory block selected according to the decoded address ADDR.
- the moving zone controller 157 may control an operation of applying various voltages to strings, e.g., NAND strings, included in the memory cell array 110 .
- the scheduler 158 may include a processor or a state machine, and may generate a plurality of control signals at appropriate times according to the operation mode set by the command CMD.
- the test/measurement circuit 159 may test or measure characteristics of the memory device 100 to provide information about the characteristics of the memory device 100 in a process of manufacturing the memory device 100 .
- the test/measurement circuit 159 may operate according to the command CMD received from the outside of the memory device 100 .
- a system including the memory device 100 may use the test/measurement circuit 159 to obtain information about the Characteristics of the memory device 100 at the beginning of an operation.
- circuits corresponding to elements of the peripheral circuit 150 of FIG. 10B may be located on the second semiconductor layer L 2 of FIG. 2 or FIG. 5A along with the row decoder 130 and the page buffer 140 of FIG. 1 .
- FIG. 11 is a cross-sectional view illustrating a partial block according to an exemplary embodiment of the inventive concept.
- a configuration of a first partial block SR_ 1 b of FIG. 11 is similar to a configuration of the first partial block SB_ 1 described with reference to FIGS. 5C and 7 .
- pillars e.g., P 1 of FIG. 7
- the gate conductive layers GS_ 1 b and insulating layers 52 b may function as a capacitor.
- the gate conductive layers GS_ 1 b may constitute both electrodes of the capacitor
- the insulating layer 52 b may constitute a dielectric layer of the capacitor.
- the first partial block SB_ 1 b may be connected to a peripheral circuit (e.g., 150 of FIG. 10B ) through upper conductive lines UPM 11 and UPM 12 and a plurality of contacts that electrically connect the upper conductive lines UPM 11 and UPM 12 to the first partial block SB_ 1 b.
- a peripheral circuit e.g., 150 of FIG. 10B
- the gate conductive layers GS_ 1 b may include a ground selection line GSL_ 1 b , word lines WL 1 _ 1 b through WL 4 _ 1 b , and a string selection line SSL_ 1 b on an upper substrate U_SUB_ 1 b .
- An etch-stop film 53 b may be disposed on an uppermost insulating layer 52 b , for example.
- FIG. 12 is a cross-sectional view illustrating a partial block according to an exemplary embodiment of the inventive concept.
- a configuration of a first partial block SB_ 1 c of FIG. 12 is similar to a configuration of the first partial block SB_ 1 described with reference to FIGS. 5C and 7 .
- pillars e.g., P 1 of FIG. 7
- the gate conductive layers GS_ 1 c may function as resistive elements.
- conductive layers of the gate conductive layers GS_ 1 c may constitute resistive elements that are connected in series.
- the first partial block SB_ 1 c may be connected to a peripheral circuit (e.g., 150 of FIG. 10B ) through the upper conductive lines UPM 21 and UPM 27 and a plurality of contacts that electrically connect the first partial block SB_ 1 c and the upper conductive lines UPM 21 and UPM 27 .
- a peripheral circuit e.g., 150 of FIG. 10B
- the gate conductive layers GS_ 1 c may include a ground selection line GSL_ 1 c , word lines WL 1 _ 1 c through WL 4 _ 1 c , and a string selection line SSL_ 1 c on an upper substrate U_SUB_ 1 c .
- An etch-stop film 53 c may be disposed on an uppermost insulating layer 52 c , for example.
- FIG. 13 is a plan view illustrating a top surface of a first semiconductor layer according to an exemplary embodiment of the inventive concept.
- a configuration of a top surface of a first semiconductor layer L 1 d of FIG. 13 is similar to a configuration of a top surface of the first semiconductor layer L 1 described with reference to FIG. 5C .
- a second vertical structure VS 2 _ 2 d may include a plurality of second via areas VA_ 3 d through VA_ 6 d , and first via areas VA_ 1 d and VA_ 2 d included in a first vertical structure VS_ 1 d may overlap the second, via areas VA_ 5 d and VA_ 6 d in the first direction.
- first vertical structure VS_ 1 d from among the first and second vertical structures VS_ 1 d and VS_ 2 d may include partial blocks SB_ 1 d through SB_ 4 d .
- Reference numeral 110 d in FIG. 13 corresponds to a memory cell array.
- FIG. 14A is a plan view illustrating a top surface of a second semiconductor layer L 2 e according to an exemplary embodiment of the inventive concept.
- FIG. 14B is a plan view illustrating, a top surface of a first semiconductor layer L 1 e according to an exemplary embodiment of the inventive concept. A repeated explanation of the same elements in FIGS. 5B and 5C will not be given in FIGS. 14A and 14B .
- the second semiconductor layer L 2 e may be divided into first through fourth regions R 1 e through R 4 e by a first virtual line X 1 -X 1 ′ of the first direction and a second virtual line Y 1 -Y 1 ′ of the second direction.
- areas of at least two regions from among the first through fourth regions R 1 e through R 4 e may be different from each other.
- areas of the first region R 1 e and the fourth region R 4 e may be different from each other.
- areas of the second region R 2 e and the third region R 3 e may be different from each other.
- an area occupied by a first row decoder 132 e on the second semiconductor layer L 2 e and an area occupied by a second row decoder 134 e on the second semiconductor layer L 2 e may be different from each other.
- the area occupied by the first row decoder 132 e on the second semiconductor layer L 2 e may be greater than the area occupied by the second row decoder 134 e on the second semiconductor layer L 2 e.
- an area occupied by the first page buffer 142 e on the second semiconductor layer L 2 e and an area occupied by the second page buffer 144 e on the second semiconductor layer L 2 e may be different from each other.
- the area occupied by the first page buffer 142 e on the second semiconductor layer L 2 e may be greater than the area occupied by the second page buffer 144 e on the second semiconductor layer L 2 e.
- a memory cell array 110 e may be located on the first semiconductor layer L 1 e , and may include a first vertical structure VS_ 1 e and a second vertical structure VS_ 2 e .
- the first vertical structure VS_ 1 e may include a plurality of first partial blocks SB_ 1 e and SB_ 2 e and a plurality of first via areas VA_ 1 e through VA_ 3 e .
- the second vertical structure VS_ 2 e may include a plurality of second partial blocks SB_ 3 e through SB_ 8 e and a second via area VA_ 4 e .
- the number of partial blocks and via areas included in the first vertical structure VS_ 1 e may be different from the number of partial blocks and via areas included in the second vertical structure VS_ 2 e.
- FIG. 15 is a block diagram of a solid-state drive (SSD) system 1000 including a memory device according to an exemplary embodiment of the inventive concept.
- SSD solid-state drive
- the SSD system 1000 may include a host 1100 and an SSD 1200 .
- the SSD 1200 may transmit/receive a signal SIG to/from the host 1100 through a signal connector, and may receive power PWR through a power connector.
- the SSD 1200 may include an SSD controller 1210 , an auxiliary power supply 1220 , and a plurality of memory devices 1230 , 1240 , and 1250 .
- the plurality of memory devices 1230 , 1240 , and 1250 may each be a vertical stacked NAND flash memory device, and may be implemented as described with reference to FIGS. 1 through 14B . Accordingly, each of the memory devices 1230 , 1240 , and 1250 may have a high degree of integration.
- FIG. 16 is a diagram showing the structure of a memory device 200 according to an exemplary embodiment of the inventive concept.
- a memory device 200 may have a chip-to-chip (C2C) structure.
- the C2C structure may refer to a structure formed by manufacturing an upper chip including a cell region CELL on a first wafer, manufacturing a lower chip including a peripheral circuit region PERI on a second wafer, different from the first wafer, and then connecting the upper chip and the lower chip in a bonding manner.
- the bonding manner may include a method of electrically connecting a bonding metal formed on an uppermost metal layer of the upper chip and a bonding metal formed on an uppermost metal layer of the lower chip.
- the bonding metals may be formed of copper (Cu)
- the bonding manner may be a Cu—Cu bonding
- the bonding metals may also be formed of aluminum or tungsten.
- Each of the peripheral circuit region PERI and the cell region CELL of the memory device 40 may include an external pad bonding area PA, a word line bonding area WLBA, and a bit line bonding area BLBA.
- the peripheral circuit region PERI may include a first substrate 210 , an interlayer insulating layer 215 , a plurality of circuit elements 220 a , 220 b , and 220 c formed on the first substrate 210 , first metal layers 230 a , 230 b , and 230 c respectively connected to the plurality of circuit elements 220 a , 220 b , and 220 c , and second metal layers 240 a , 240 b , and 240 c formed on the first metal layers 230 a , 230 b , and 230 c .
- the first metal layers 230 a , 230 b , and 230 c may be formed of tungsten having relatively high resistance
- the second metal layers 240 a , 240 b , and 240 c may be formed of copper having relatively low resistance.
- first metal layers 230 a , 230 b , and 230 c and the second metal layers 240 a , 2440 b , and 240 c are shown and described, they are not limited thereto, and one or more metal layers may be further formed on the second metal layers 240 a , 240 b , and 240 c . At least a portion of the one or more metal layers formed on the second metal layers 240 a , 240 b , and 240 c may be formed of aluminum or the like having a lower resistance than those of copper forming the second metal layers 240 a , 240 b , and 240 c.
- the interlayer insulating layer 215 may be disposed on the first substrate 210 and cover the plurality of circuit elements 220 a , 220 b , and 220 c , the first metal layers 230 a , 230 b , and 230 c , and the second metal layers 240 a , 240 b , and 240 c .
- the interlayer insulating layer 215 may include an insulating material such as silicon oxide, silicon nitride, or the like.
- Lower bonding metals 271 b and 272 b may be formed on the second metal layer 240 b in the word line bonding area WLBA.
- the lower bonding metals 271 b and 272 b in the peripheral circuit region PERI may be electrically connected to c in a bonding manner, and the lower bonding metals 271 b and 272 b and the upper bonding metals 371 b and 372 b may be formed of aluminum, copper, tungsten, or the like.
- the upper bonding metals 371 b and 372 b in the cell region CELL may be referred as first metal pads and the lower bonding metals 271 b and 272 b in the peripheral circuit region PERI may be referred as second metal pads.
- the cell region CELL may include at least one memory block.
- the cell region CELL may include a second substrate 310 and a common source line 320 .
- a plurality of word lines 331 to 338 i.e., 330
- At least one string select line and at least one ground select line may be arranged on and below the plurality of word lines 330 , respectively, and the plurality of word lines 330 may be disposed between the at least one string select line and the at least one ground select line.
- a channel structure CH may extend in a direction, perpendicular to the upper surface of the second substrate 310 , and pass through the plurality of word lines 330 , the at least one string select line, and the at least one ground select line.
- the channel structure CH may include a data storage layer, a channel layer, a buried insulating layer, and the like, and the channel layer may be electrically connected to a first metal layer 350 c and a second metal layer 360 c .
- the first metal layer 350 c may be a bit line contact
- the second metal layer 360 c may be a bit line.
- the bit line 360 c may extend in a first direction (a Y-axis direction), parallel to the upper surface of the second substrate 310 .
- an area in which the channel structure CH, the bit line 360 c , and the like are disposed may be defined as the bit line bonding area BLBA.
- the bit line 360 c may be electrically connected to the circuit elements 220 c providing a page buffer 393 in the peripheral circuit region PERI.
- the bit line 360 c may be connected to upper bonding metals 371 c and 372 c in the cell region CELL, and the upper bonding metals 371 c and 372 c may be connected to lower bonding metals 271 c and 272 c connected to the circuit elements 220 c of the page buffer 393 .
- the plurality of word lines 330 may extend in a second direction (an X-axis direction), parallel to the upper surface of the second substrate 310 , and may be connected to a plurality of cell contact plugs 341 to 347 (i.e., 340 ).
- the plurality of word lines 330 and the plurality of cell contact plugs 340 may be connected to each other in pads provided by at least a portion of the plurality of word lines 330 extending in different lengths in the second direction.
- a first metal layer 350 b and a second metal layer 360 b may be connected to an upper portion of the plurality of cell contact plugs 340 connected to the plurality of word lines 330 , sequentially.
- the plurality of cell contact plugs 340 may be connected to the circuit region PERI by the upper bonding metals 371 b and 372 b of the cell region CELL and the lower bonding metals 271 b and 272 b of the peripheral circuit region PERI in the word line bonding area WLBA.
- the plurality of cell contact plugs 340 may be electrically connected to the circuit elements 220 b providing a row decoder 394 in the peripheral circuit region PERI.
- operating voltages of the circuit elements 220 b providing the row decoder 394 may be different than operating voltages of the circuit elements 220 c providing the page buffer 393 .
- operating voltages of the circuit elements 220 c providing the page buffer 393 may be greater than operating voltages of the circuit elements 220 b providing the row decoder 394 .
- a common source line contact plug 380 may be disposed in the external pad bonding area PA.
- the common source line contact plug 380 may be formed of a conductive material such as a metal, a metal compound, polysilicon, or the like, and may be electrically connected to the common source line 320 .
- a first metal layer 350 a and a second metal layer 360 a may be stacked on an upper portion of the common source line contact plug 380 , sequentially.
- an area in which the common source line contact plug 380 , the first metal layer 350 a , and the second metal layer 360 are disposed may be defined as the external pad bonding area PA.
- Input-output pads 205 and 305 may be disposed in the external pad bonding area PA.
- a lower insulating film 201 covering a lower surface of the first substrate 210 may be formed below the first substrate 210 , and a first input-output pad 205 may be formed on the lower insulating film 201 .
- the first input-output pad 205 may be connected to at least one of the plurality of circuit elements 220 a , 220 b , and 220 c disposed in the peripheral circuit region PERI through a first input-output contact plug 203 , and may be separated from the first substrate 210 by the lower insulating film 201 .
- a side insulating film may be disposed between the first input-output contact plug 203 and the first substrate 210 to electrically separate the first input-output contact plug 203 and the first substrate 210 .
- an upper insulating film 301 covering the upper surface of the second substrate 310 may be formed on the second substrate 310 , and a second input-output pad 305 may be disposed on the upper insulating layer 301 .
- the second input-output pad 305 may be connected to at least one of the plurality of circuit elements 220 a , 220 b , and 220 c disposed in the peripheral circuit region PERI through a second input-output contact plug 303 .
- the second substrate 310 and the common source line 320 may not be disposed in an area in which the second input-output contact plug 303 is disposed.
- the second input-output pad 305 may not overlap the word lines 330 in the third direction (the Z-axis direction).
- the second input-output contact plug 303 may be separated from the second substrate 310 in a direction, parallel to the upper surface of the second substrate 310 , and may pass through the interlayer insulating layer 315 of the cell region CELL to be connected to the second input-output pad 305 .
- the first input-output pad 205 and the second input-output pad 305 may be selectively formed.
- the memory device 200 may include only the first input-output pad 205 disposed on the first substrate 210 or the second input-output pad 305 disposed on the second substrate 310 .
- the memory device 200 may include both the first input-output pad 205 and the second input-output pad 305 .
- a metal pattern in an uppermost metal layer may be provided as a dummy pattern or the uppermost metal layer may be absent, in each of the external pad bonding area PA and the bit line bonding area BLBA, respectively included in the cell region CELL and the peripheral circuit region PERI.
- the memory device 200 may include a lower metal pattern 273 a , corresponding to an upper metal pattern 372 a formed in an uppermost metal layer of the cell region CELL, and having the same shape as the upper metal pattern 372 a of the cell region CELL, in an uppermost metal layer of the peripheral circuit region PERI.
- the lower metal pattern 273 a formed in the uppermost metal layer of the peripheral circuit region PERI may not be connected to a contact.
- an upper metal pattern corresponding to the lower metal pattern formed in an uppermost metal layer of the peripheral circuit region PERI, and having the same shape as a lower metal pattern of the peripheral circuit region PERI, may be formed in an uppermost metal layer of the cell region CELL.
- the lower bonding metals 271 b and 272 b may be formed on the second metal layer 240 b in the word line bonding area WLBA.
- the lower bonding metals 271 b and 272 b of the peripheral circuit region PERI may be electrically connected to the upper bonding metals 371 b and 372 b of the cell region CELL by a Cu—Cu bonding.
- bit line bonding area BLBA an upper metal pattern 392 , corresponding to a lower metal pattern 252 formed in the uppermost metal layer of the peripheral circuit region PERI, and having the same shape as the lower metal pattern 252 of the peripheral circuit region PERI, may be formed in an uppermost metal layer of the cell region CELL.
- a contact may not be formed on the upper metal pattern 392 formed in the uppermost metal layer of the cell region CELL.
- a reinforcement metal pattern having the same shape as the metal pattern may be formed in an uppermost metal layer in another one of the cell region CELL and the peripheral circuit region PERI, and a contact may not be formed on the reinforcement metal pattern.
- the memory device 200 may be implemented according to the embodiments described above with reference to FIGS. 1 to 15 . Compared with the memory device 100 described above with reference to FIGS. 1 to 15 , the memory device 200 may be similar to the one in which the first semiconductor layer of the memory device 400 is vertically inverted and then combined with the second semiconductor layer.
- the second substrate 310 of the memory device 200 may include the first upper substrate and the second upper substrate described above in FIGS. 1 to 15 .
- a first vertical structure may be disposed on the first upper substrate, and a second vertical structure nay be disposed on the second upper substrate of the memory device 200 .
- the first vertical structure may include a first via region in which a through-hole via passing through the first vertical structure and connecting at least some of the bit lines and at least some of the page buffer circuits is disposed.
- the present disclosure is not limited thereto, and the first vertical structure does not include a through-hole via, as shown in FIG.
- the second vertical structure may include one or more partial blocks at least partially overlapping with the first vertical structure.
- the operation of the memory device 200 may be substantially the same as the embodiments described above with reference to FIGS. 1 to 15 , and descriptions identical to those described with reference to FIGS. 1 to 15 will be omitted.
- FIG. 17 is a diagram showing a memory device 600 according to an exemplary embodiment of the inventive concept.
- the memory device 600 may include two or more upper chips, each including a cell region.
- the memory device 600 may include a first upper chip including a first cell region CELL 1 , a second upper chip including a second cell region CELL 2 , and a lower chip including a peripheral circuit region PERI.
- the first upper chip, the second upper chip and the lower chip may be connected by a bonding method.
- the number of upper chips is not limited to thereto.
- Each of the first upper chip, the second upper chip and the lower chip may be referred to as a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer.
- descriptions of the first cell area CELL 1 , the second cell area CELL 2 , and the peripheral circuit area PERI identical to those described with reference to FIG. 16 are omitted.
- the first cell area CELL 1 and the second cell area CELL 2 may share bit lines 630 , the string selection lines and ground selection lines may be disposed may be disposed in each of the upper and lower portions of the word lines 611 , 621 of the first cell area CELL 1 and the second cell area CELL 2 .
- a channel structure extends in a direction perpendicular to the upper surface of the bonding pad 625 , may pass through the common source line 623 and word lines 621 , and is electrically connected to the bit line 630 .
- a channel structure extends in a direction perpendicular to the upper surface of the second substrate 601 , passes through the common source line and word lines, and is electrically connected to the bit lines 630 .
- the peripheral circuit area PERI may include a plurality of row decoder circuits and page buffer circuits.
- an upper metal pattern 641 may be formed at the lower end of the second cell region CELL 2
- a lower metal pattern 642 may be formed at the upper end of the peripheral circuit region PERI.
- the upper metal pattern 641 of the second cell area CELL 2 and the lower metal pattern 642 of the peripheral circuit area PERI may be connected in the external pad bonding area PA in a bonding manner.
- the memory device 600 may be implemented according to the embodiments described above with reference to FIGS. 1 to 15 .
- the first cell area CELL 1 and the peripheral circuit area PERI of the memory device 600 may be similar to the memory device 100 .
- the bonding pads of the memory device 600 may include the first upper substrate and the second upper substrate described above with reference to FIGS. 1 to 15 .
- a first vertical structure may be disposed on the first upper substrate, and a second vertical structure may be disposed on the second upper substrate of the memory device 600 .
- the first vertical structure may include a first via region in which a through-hole via passing through the first vertical structure and connecting at least some of the bit lines and at least some of the page buffer circuits is disposed.
- the second vertical structure may include one or more partial blocks at least partially overlapping with the first vertical structure.
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Abstract
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US16/200,714 US10672791B2 (en) | 2017-11-27 | 2018-11-27 | Nonvolatile memory device having a vertical structure and a memory system including the same |
US16/861,939 US10978481B2 (en) | 2017-11-27 | 2020-04-29 | Nonvolatile memory device having a vertical structure and a memory system including the same |
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JP7340178B2 (en) * | 2020-01-16 | 2023-09-07 | 本田技研工業株式会社 | semiconductor equipment |
US11930634B2 (en) | 2021-06-30 | 2024-03-12 | Micron Technology, Inc. | Methods of forming microelectronic devices |
US11810838B2 (en) * | 2021-06-30 | 2023-11-07 | Micron Technology, Inc. | Microelectronic devices, and related electronic systems and methods of forming microelectronic devices |
US11837594B2 (en) | 2021-06-30 | 2023-12-05 | Micron Technology, Inc. | Microelectronic devices and electronic systems |
US11785764B2 (en) | 2021-06-30 | 2023-10-10 | Micron Technology, Inc. | Methods of forming microelectronic devices |
US11776925B2 (en) | 2021-06-30 | 2023-10-03 | Micron Technology, Inc. | Methods of forming microelectronic devices, and related microelectronic devices and electronic systems |
US11842990B2 (en) | 2021-06-30 | 2023-12-12 | Micron Technology, Inc. | Microelectronic devices and electronic systems |
US11996377B2 (en) | 2021-06-30 | 2024-05-28 | Micron Technology, Inc. | Microelectronic devices and electronic systems |
US11751383B2 (en) | 2021-08-31 | 2023-09-05 | Micron Technology, Inc. | Methods of forming microelectronic devices, and related microelectronic devices and electronic systems |
Citations (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8107312B2 (en) | 2008-01-31 | 2012-01-31 | Samsung Electronics Co., Ltd. | Memory chip array |
US20140036590A1 (en) | 2012-08-01 | 2014-02-06 | Micron Technology, Inc. | Partial block memory operations |
US20140061747A1 (en) | 2012-08-30 | 2014-03-06 | Toru Tanzawa | Memory array having connections going through control gates |
US8811079B2 (en) | 2012-02-01 | 2014-08-19 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
US9087590B2 (en) | 2012-10-30 | 2015-07-21 | Samsung Electronics Co., Ltd. | Nonvolatile memory device and method of programming the same |
US9218882B2 (en) | 2014-03-12 | 2015-12-22 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
US9230981B2 (en) | 2014-02-21 | 2016-01-05 | SK Hynix Inc. | Semiconductor device |
US9378820B2 (en) | 2014-07-30 | 2016-06-28 | Samsung Electronics Co., Ltd. | Nonvolatile memory device and worldline driving method thereof |
US9515087B2 (en) | 2014-10-27 | 2016-12-06 | Samsung Electronics Co., Ltd. | Three-dimensional semiconductor memory device |
US9595346B2 (en) * | 2015-05-21 | 2017-03-14 | Samsung Electronics Co., Ltd. | 3-Dimensional semiconductor memory device and operating method thereof |
US9646981B2 (en) | 2015-06-15 | 2017-05-09 | Sandisk Technologies Llc | Passive devices for integration with three-dimensional memory devices |
US9659959B2 (en) | 2014-05-12 | 2017-05-23 | Samsung Electronics Co., Ltd. | Semiconductor devices |
US20170179026A1 (en) | 2015-12-22 | 2017-06-22 | Sandisk Technologies Llc | Through-memory-level via structures for a three-dimensional memory device |
US9691782B1 (en) | 2016-04-29 | 2017-06-27 | Samsung Electronics Co., Ltd. | Non-volatile memory device |
US9698151B2 (en) | 2015-10-08 | 2017-07-04 | Samsung Electronics Co., Ltd. | Vertical memory devices |
US20170207234A1 (en) | 2013-12-05 | 2017-07-20 | Samsung Electronics Co., Ltd. | Semiconductor device and method of manufacturing the same |
US9716181B2 (en) | 2015-07-23 | 2017-07-25 | Samsung Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
US9721663B1 (en) | 2016-02-18 | 2017-08-01 | Sandisk Technologies Llc | Word line decoder circuitry under a three-dimensional memory array |
US20170236746A1 (en) | 2016-02-16 | 2017-08-17 | Sandisk Technologies Llc | Multi-tier memory device with through-stack peripheral contact via structures and method of making thereof |
US9941009B2 (en) | 2016-05-16 | 2018-04-10 | Samsung Electronics Co., Ltd. | Memory device having vertical structure and memory system including the same |
US20190164991A1 (en) | 2017-11-27 | 2019-05-30 | Samsung Electronics Co., Ltd. | Nonvolatile memory device having a vertical structure and a memory system including the same |
US10446575B2 (en) | 2017-11-07 | 2019-10-15 | Samsung Electronics Co., Ltd | Nonvolatile memory device |
US10510407B2 (en) | 2017-02-16 | 2019-12-17 | Micron Technology, Inc. | Efficient utilization of memory die area |
US10529727B2 (en) | 2017-12-27 | 2020-01-07 | Samsung Electronics Co., Ltd. | Nonvolatile memory device compensating for voltage drop of target gate line |
US10665598B2 (en) | 2018-04-19 | 2020-05-26 | Toshiba Memory Corporation | Semiconductor memory device and method for manufacturing same |
US10672786B2 (en) | 2015-09-02 | 2020-06-02 | SK Hynix Inc. | Semiconductor device and manufacturing method of the same |
US10777571B2 (en) * | 2018-01-31 | 2020-09-15 | Samsung Electronics Co., Ltd. | Three-dimensional semiconductor device having a peripheral connection plug in a through region below a gate stack structure |
US20210098072A1 (en) | 2019-09-27 | 2021-04-01 | Samsung Electronics Co., Ltd. | Nonvolatile memory device with address re-mapping |
US10978465B2 (en) * | 2018-05-18 | 2021-04-13 | Samsung Electronics Co., Ltd. | Three-dimensional semiconductor device having a memory block and separation structures |
US11024638B2 (en) * | 2018-08-29 | 2021-06-01 | Samsung Electronics Co., Ltd. | Three-dimensional semiconductor device |
-
2020
- 2020-10-19 US US17/073,653 patent/US11211403B2/en active Active
Patent Citations (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8107312B2 (en) | 2008-01-31 | 2012-01-31 | Samsung Electronics Co., Ltd. | Memory chip array |
US8811079B2 (en) | 2012-02-01 | 2014-08-19 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
US20140036590A1 (en) | 2012-08-01 | 2014-02-06 | Micron Technology, Inc. | Partial block memory operations |
US20140061747A1 (en) | 2012-08-30 | 2014-03-06 | Toru Tanzawa | Memory array having connections going through control gates |
US9087590B2 (en) | 2012-10-30 | 2015-07-21 | Samsung Electronics Co., Ltd. | Nonvolatile memory device and method of programming the same |
US20170207234A1 (en) | 2013-12-05 | 2017-07-20 | Samsung Electronics Co., Ltd. | Semiconductor device and method of manufacturing the same |
US9230981B2 (en) | 2014-02-21 | 2016-01-05 | SK Hynix Inc. | Semiconductor device |
US9218882B2 (en) | 2014-03-12 | 2015-12-22 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
US9659959B2 (en) | 2014-05-12 | 2017-05-23 | Samsung Electronics Co., Ltd. | Semiconductor devices |
US9378820B2 (en) | 2014-07-30 | 2016-06-28 | Samsung Electronics Co., Ltd. | Nonvolatile memory device and worldline driving method thereof |
US9515087B2 (en) | 2014-10-27 | 2016-12-06 | Samsung Electronics Co., Ltd. | Three-dimensional semiconductor memory device |
US9595346B2 (en) * | 2015-05-21 | 2017-03-14 | Samsung Electronics Co., Ltd. | 3-Dimensional semiconductor memory device and operating method thereof |
US9646981B2 (en) | 2015-06-15 | 2017-05-09 | Sandisk Technologies Llc | Passive devices for integration with three-dimensional memory devices |
US9716181B2 (en) | 2015-07-23 | 2017-07-25 | Samsung Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
US10672786B2 (en) | 2015-09-02 | 2020-06-02 | SK Hynix Inc. | Semiconductor device and manufacturing method of the same |
US9698151B2 (en) | 2015-10-08 | 2017-07-04 | Samsung Electronics Co., Ltd. | Vertical memory devices |
US20170179026A1 (en) | 2015-12-22 | 2017-06-22 | Sandisk Technologies Llc | Through-memory-level via structures for a three-dimensional memory device |
US20170236746A1 (en) | 2016-02-16 | 2017-08-17 | Sandisk Technologies Llc | Multi-tier memory device with through-stack peripheral contact via structures and method of making thereof |
US9721663B1 (en) | 2016-02-18 | 2017-08-01 | Sandisk Technologies Llc | Word line decoder circuitry under a three-dimensional memory array |
US20170243650A1 (en) | 2016-02-18 | 2017-08-24 | Sandisk Technologies Inc. | Word line decoder circuitry under a three-dimensional memory array |
US9691782B1 (en) | 2016-04-29 | 2017-06-27 | Samsung Electronics Co., Ltd. | Non-volatile memory device |
US9941009B2 (en) | 2016-05-16 | 2018-04-10 | Samsung Electronics Co., Ltd. | Memory device having vertical structure and memory system including the same |
US10510407B2 (en) | 2017-02-16 | 2019-12-17 | Micron Technology, Inc. | Efficient utilization of memory die area |
US10446575B2 (en) | 2017-11-07 | 2019-10-15 | Samsung Electronics Co., Ltd | Nonvolatile memory device |
US20190164991A1 (en) | 2017-11-27 | 2019-05-30 | Samsung Electronics Co., Ltd. | Nonvolatile memory device having a vertical structure and a memory system including the same |
US10978481B2 (en) * | 2017-11-27 | 2021-04-13 | Samsung Electronics Co., Ltd. | Nonvolatile memory device having a vertical structure and a memory system including the same |
US20200258911A1 (en) | 2017-11-27 | 2020-08-13 | Samsung Electronics Co., Ltd. | Nonvolatile memory device having a vertical structure and a memory system including the same |
US10672791B2 (en) * | 2017-11-27 | 2020-06-02 | Samsung Electronics Co., Ltd. | Nonvolatile memory device having a vertical structure and a memory system including the same |
US10529727B2 (en) | 2017-12-27 | 2020-01-07 | Samsung Electronics Co., Ltd. | Nonvolatile memory device compensating for voltage drop of target gate line |
US10777571B2 (en) * | 2018-01-31 | 2020-09-15 | Samsung Electronics Co., Ltd. | Three-dimensional semiconductor device having a peripheral connection plug in a through region below a gate stack structure |
US10665598B2 (en) | 2018-04-19 | 2020-05-26 | Toshiba Memory Corporation | Semiconductor memory device and method for manufacturing same |
US10978465B2 (en) * | 2018-05-18 | 2021-04-13 | Samsung Electronics Co., Ltd. | Three-dimensional semiconductor device having a memory block and separation structures |
US11024638B2 (en) * | 2018-08-29 | 2021-06-01 | Samsung Electronics Co., Ltd. | Three-dimensional semiconductor device |
US20210098072A1 (en) | 2019-09-27 | 2021-04-01 | Samsung Electronics Co., Ltd. | Nonvolatile memory device with address re-mapping |
Non-Patent Citations (3)
Title |
---|
German Office Action Issued in Corresponding German Application No. DE 102018129451.4 dated Sep. 1, 2020. |
Notice of Allowance Issued in Corresponding U.S. Appl. No. 16/891,939 dated Dec. 8, 2020. |
Notice of Allowance Issued in Corresponding U.S. Appl. No. 17/193,187 dated Sep. 22, 2021. |
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