US10910339B2 - Flip chip bonding method - Google Patents
Flip chip bonding method Download PDFInfo
- Publication number
- US10910339B2 US10910339B2 US16/533,450 US201916533450A US10910339B2 US 10910339 B2 US10910339 B2 US 10910339B2 US 201916533450 A US201916533450 A US 201916533450A US 10910339 B2 US10910339 B2 US 10910339B2
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- 238000000034 method Methods 0.000 title claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 105
- 239000012790 adhesive layer Substances 0.000 claims abstract description 91
- 238000010438 heat treatment Methods 0.000 claims abstract description 24
- 239000004848 polyfunctional curative Substances 0.000 claims description 10
- 125000002887 hydroxy group Chemical group [H]O* 0.000 claims description 7
- MUBZPKHOEPUJKR-UHFFFAOYSA-N Oxalic acid Chemical compound OC(=O)C(O)=O MUBZPKHOEPUJKR-UHFFFAOYSA-N 0.000 claims description 6
- 239000003638 chemical reducing agent Substances 0.000 claims description 6
- RAXXELZNTBOGNW-UHFFFAOYSA-N imidazole Natural products C1=CNC=N1 RAXXELZNTBOGNW-UHFFFAOYSA-N 0.000 claims description 6
- 239000011800 void material Substances 0.000 claims description 5
- OFOBLEOULBTSOW-UHFFFAOYSA-N Malonic acid Chemical compound OC(=O)CC(O)=O OFOBLEOULBTSOW-UHFFFAOYSA-N 0.000 claims description 4
- 239000000853 adhesive Substances 0.000 claims description 4
- 230000001070 adhesive effect Effects 0.000 claims description 4
- GGNQRNBDZQJCCN-UHFFFAOYSA-N benzene-1,2,4-triol Chemical compound OC1=CC=C(O)C(O)=C1 GGNQRNBDZQJCCN-UHFFFAOYSA-N 0.000 claims description 4
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N phenol group Chemical group C1(=CC=CC=C1)O ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 claims description 4
- 230000001476 alcoholic effect Effects 0.000 claims description 3
- 150000001735 carboxylic acids Chemical class 0.000 claims description 3
- -1 nitrogen-containing compound Chemical class 0.000 claims description 3
- KJCVRFUGPWSIIH-UHFFFAOYSA-N 1-naphthol Chemical compound C1=CC=C2C(O)=CC=CC2=C1 KJCVRFUGPWSIIH-UHFFFAOYSA-N 0.000 claims description 2
- BXGYYDRIMBPOMN-UHFFFAOYSA-N 2-(hydroxymethoxy)ethoxymethanol Chemical compound OCOCCOCO BXGYYDRIMBPOMN-UHFFFAOYSA-N 0.000 claims description 2
- KDYFGRWQOYBRFD-UHFFFAOYSA-N Succinic acid Natural products OC(=O)CCC(O)=O KDYFGRWQOYBRFD-UHFFFAOYSA-N 0.000 claims description 2
- GSEJCLTVZPLZKY-UHFFFAOYSA-N Triethanolamine Chemical compound OCCN(CCO)CCO GSEJCLTVZPLZKY-UHFFFAOYSA-N 0.000 claims description 2
- GTTSNKDQDACYLV-UHFFFAOYSA-N Trihydroxybutane Chemical compound CCCC(O)(O)O GTTSNKDQDACYLV-UHFFFAOYSA-N 0.000 claims description 2
- KDYFGRWQOYBRFD-NUQCWPJISA-N butanedioic acid Chemical compound O[14C](=O)CC[14C](O)=O KDYFGRWQOYBRFD-NUQCWPJISA-N 0.000 claims description 2
- 150000001732 carboxylic acid derivatives Chemical class 0.000 claims description 2
- MTHSVFCYNBDYFN-UHFFFAOYSA-N diethylene glycol Chemical compound OCCOCCO MTHSVFCYNBDYFN-UHFFFAOYSA-N 0.000 claims description 2
- 150000004715 keto acids Chemical class 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims description 2
- 235000006408 oxalic acid Nutrition 0.000 claims description 2
- 239000003822 epoxy resin Substances 0.000 claims 6
- 229920000647 polyepoxide Polymers 0.000 claims 6
- 150000001408 amides Chemical class 0.000 claims 1
- 230000007547 defect Effects 0.000 description 6
- 239000011347 resin Substances 0.000 description 6
- 229920005989 resin Polymers 0.000 description 6
- 229920001187 thermosetting polymer Polymers 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 5
- 239000007789 gas Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 150000001412 amines Chemical class 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 239000004844 aliphatic epoxy resin Substances 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 239000004841 bisphenol A epoxy resin Substances 0.000 description 1
- 239000004842 bisphenol F epoxy resin Substances 0.000 description 1
- 239000001569 carbon dioxide Substances 0.000 description 1
- 229910002092 carbon dioxide Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 239000004845 glycidylamine epoxy resin Substances 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004843 novolac epoxy resin Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
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- C—CHEMISTRY; METALLURGY
- C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
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- C09J5/00—Adhesive processes in general; Adhesive processes not provided for elsewhere, e.g. relating to primers
- C09J5/06—Adhesive processes in general; Adhesive processes not provided for elsewhere, e.g. relating to primers involving heating of the applied adhesive
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- C09J11/00—Features of adhesives not provided for in group C09J9/00, e.g. additives
- C09J11/02—Non-macromolecular additives
- C09J11/06—Non-macromolecular additives organic
-
- C—CHEMISTRY; METALLURGY
- C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
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- C09J163/00—Adhesives based on epoxy resins; Adhesives based on derivatives of epoxy resins
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- C09J5/00—Adhesive processes in general; Adhesive processes not provided for elsewhere, e.g. relating to primers
- C09J5/02—Adhesive processes in general; Adhesive processes not provided for elsewhere, e.g. relating to primers involving pretreatment of the surfaces to be joined
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67092—Apparatus for mechanical treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- C09J2203/00—Applications of adhesives in processes or use of adhesives in the form of films or foils
- C09J2203/326—Applications of adhesives in processes or use of adhesives in the form of films or foils for bonding electronic components such as wafers, chips or semiconductors
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- C09J2301/00—Additional features of adhesives in the form of films or foils
- C09J2301/30—Additional features of adhesives in the form of films or foils characterized by the chemical, physicochemical or physical properties of the adhesive or the carrier
- C09J2301/312—Additional features of adhesives in the form of films or foils characterized by the chemical, physicochemical or physical properties of the adhesive or the carrier parameters being the characterizing feature
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/731—Location prior to the connecting process
- H01L2224/73101—Location prior to the connecting process on the same surface
- H01L2224/73103—Bump and layer connectors
- H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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Definitions
- inventive concepts herein relate to a method of fabricating a semiconductor device, and more particularly to a flip chip bonding method.
- Embodiments of the inventive concepts provide a flip chip bonding method capable of reducing defects such as voids and fillets.
- Embodiments of the inventive concepts provide a flip chip bonding method including obtaining a die that includes a first substrate and an adhesive layer on the first substrate; bonding the die to a second substrate different from the first substrate; and curing the adhesive layer.
- the curing the adhesive layer includes heating the second substrate to melt the adhesive layer, and providing the adhesive layer and the second substrate with air having pressure greater than atmospheric pressure.
- Embodiments of the inventive concepts further provide a flip chip bonding method including obtaining a plurality of dies that each include a first substrate and an adhesive layer on the first substrate; providing the plurality of dies onto a second substrate; heating the plurality of dies and the adhesive layer to a first temperature to melt bumps of the plurality of dies and the adhesive layer; compressing the plurality of dies against the second substrate; determining whether a number of the plurality of dies bonded to the second substrate responsive to the compressing is greater than a reference number; heating the second substrate to a second temperature to re-melt the adhesive layer upon determination that the number of the plurality of dies bonded to the second substrate is greater than the reference number, the second temperature being less than the first temperature; and removing a void from the adhesive layer by providing the adhesive layer and the second substrate with air having pressure equal to or greater than atmospheric pressure.
- Embodiments of the inventive concepts still further provide a flip chip bonding method including placing a die on a second substrate, the die including a first substrate with metallic bumps and an adhesive layer on the substrate; heating the die to a first temperature; compressing the die against the second substrate after the heating to bond the die to the second substrate; heating the second substrate to a second temperature in an oven after the compressing to melt the adhesive layer; and removing voids in the melted adhesive layer by increasing air pressure in the oven to greater than atmospheric pressure.
- FIG. 1 illustrates a flow chart of a flip chip bonding method according to example embodiments of the inventive concepts.
- FIGS. 2, 3, 4, 5, 6, 7, 8, 9, and 10 illustrate cross-sectional views descriptive of the flip chip bonding method of FIG. 1 .
- FIG. 11 illustrates a flow chart of a step of obtaining a die in the flow chart of FIG. 1 .
- FIG. 12 illustrates a flow chart of a step of bonding a die in the flow chart of FIG. 1 .
- FIG. 13 illustrates a flow chart of a step of curing an adhesive layer in the flow chart of FIG. 1 .
- FIG. 14 illustrates a graph showing how a void removal rate depends on air pressure in a housing shown in FIG. 9 .
- FIG. 15 illustrates a cross-sectional view of a fillet of an adhesive layer under typical vacuum pressure.
- Example embodiments will be described more fully with reference to the accompanying drawings, in which some example embodiments are shown. Example embodiments may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of example embodiments of the inventive concepts to those of ordinary skill in the art.
- the thicknesses of layers and regions may be exaggerated for clarity.
- Like reference characters and/or numerals in the drawings denote like elements, and thus their description may be omitted.
- FIG. 1 illustrates a flow chart of a flip chip bonding method according to example embodiments of the inventive concepts.
- FIGS. 2, 3, 4, 5, 6, 7, 8, 9 and 10 illustrate cross-sectional views descriptive of the flip chip bonding method of FIG. 1 .
- a flip chip bonding method includes step S 10 of obtaining a die 40 , step S 20 of bonding the die 40 , step S 30 of determining whether or not a given number of dice (i.e., dies) 40 are bonded, and step S 40 of curing an adhesive layer 30 .
- die 40 may refer both to a singular die or a plurality of dice.
- the die 40 may be prepared from a first substrate 10 .
- the adhesive layer 30 may be used to attach the die 40 to a second substrate 50 (i.e., bonding the die 40 to the second substrate 50 different than the first substrate 10 ).
- determination of whether a given number of the dice 40 are bonded to the second substrate 50 is made.
- defects may be removed from the adhesive layer 30 .
- FIG. 11 illustrates an example of step S 10 of obtaining the die 40 , as shown in the flow chart of FIG. 1 .
- step S 10 of obtaining the die 40 may include step S 12 of forming bumps 20 , step S 14 of forming the adhesive layer 30 , and step S 16 of cutting the adhesive layer 30 and the first substrate 10 .
- a ball attaching apparatus may form the bumps 20 on or over the first substrate 10 (S 12 ).
- the first substrate 10 may include a silicon wafer for example.
- the first substrate 10 may have a plurality of first pads 12 on or over a main upper surface.
- the first pads 12 may be conductive.
- the bumps 20 may be formed on the first pads 12 .
- Each of the bumps 20 may include a solder ball.
- Each of the bumps 20 may be metallic.
- an adhesive coating apparatus may form the adhesive layer 30 on or over the first substrate 10 and the bumps 20 (S 14 ).
- the adhesive layer 30 may be coated on an entirety of a top surface of the first substrate 10 .
- the adhesive layer 30 may include a non-conductive film (NCF) or a non-conductive paste (NCP).
- the adhesive layer 30 may contain a thermosetting resin, a hardener, and a reducer.
- the thermosetting resin may include for example a bisphenol A epoxy resin, a bisphenol F epoxy resin, a novolac epoxy resin, an aliphatic epoxy resin, or a glycidylamine epoxy resin, or the like.
- the hardener may cure the thermosetting resin.
- the hardener may include for example amine or polyimide.
- the thermosetting resin and the hardener may have for example an equivalence ratio of caloric value per unit mass of about 100 joule/gram (J/g) to about 150 J/g.
- the thermosetting resin and the hardener may have for example a mixture ratio of about 10:1 to about 15:1.
- the reducer may react at a temperature of about 100° C. to 150° C. or higher to remove native oxide from the first pads 12 and the bumps 20 .
- the reducer may include in its one molecule one or more alcoholic hydroxyl groups (e.g., dimethanol, diethylen glycol, butanetriol, or triethanolamine), one or more phenolic hydroxyl groups (e.g., naphthol, hydroxyhydroquinone, or trihydroxybenzopyenone), one or more carboxylic acids (e.g., oxalic acid, succinic acid, malonic acid, oxoacid, or carboxylic acid derivative), a nitrogen-containing compound having an unshared electron pair (e.g., imidazole or amine), or a combination thereof.
- alcoholic hydroxyl groups e.g., dimethanol, diethylen glycol, butanetriol, or triethanolamine
- phenolic hydroxyl groups e.g., naphthol, hydroxyhydroquinone, or trihydroxybenzopyenone
- carboxylic acids e.g., oxalic acid, succinic
- the adhesive layer 30 may further contain for example a flux of carboxylic hydrate, hydroxyl hydrate, or phenolic hydrate, or the like.
- the reducer may react at about 150° C. with the native oxide.
- a cutting apparatus 42 may cut the adhesive layer 30 and the first substrate 10 into a plurality of the dice 40 (S 16 ).
- the cutting apparatus 42 may be for example a wafer sawing machine or a laser sawing machine.
- the die 40 may include for example a memory chip, a logic chip, or an application processor (AP), among other components.
- the die 40 may have a rectangular shape when viewed in plan.
- FIG. 12 illustrates an example of step S 20 of bonding the die 40 , as shown in the flow chart of FIG. 1 .
- a thermocompression process may be performed on the die 40 and the adhesive layer 30 .
- the step S 20 of bonding the die 40 may include step S 22 of providing the die 40 , step S 24 of heating the die 40 , and step S 26 of compressing the die 40 .
- a bonding head 60 may provide (i.e., place) the die 40 onto a second substrate 50 (S 22 ).
- the second substrate 50 may have a plurality of second pads 52 on an upper main surface.
- the second pads 52 may be conductive.
- the bumps 20 may be aligned with the second pads 52 .
- the first pads 12 may also be aligned with the second pads 52 .
- the bonding head 60 may align the first pads 12 with the second pads 52 in about 0.5 seconds or less.
- the bonding head 60 may have a first heater 62 .
- the first heater 62 may be connected in series with a first power source 64 and a first switch 66 .
- the first power source 64 may supply the first heater 62 with first heating power.
- the first switch 66 may control the first heating power.
- the first heater 62 when the first switch 66 is closed, the first heater 62 as powered by the first heating power may heat the die 40 and melt the bumps 20 of the die 40 and the adhesive layer 30 (S 24 ).
- the first heater 62 may for example heat the die 40 to a temperature (i.e., a first temperature) of about 150° C. to about 300° C.
- the bonding head 60 may compress the die 40 against the second substrate 50 (S 26 ).
- the bumps 20 may connect the first pads 12 to the second pads 52 .
- the bonding head 60 may bond the die 40 to the substrate 50 at high speed.
- the bonding head 60 may compress the die 40 against the substrate 50 for about 3 seconds to about 4 seconds to bond the die 40 to the substrate 50 .
- a curing reaction between the thermosetting resin and the hardener of the adhesive layer 30 may be weak or incomplete.
- the prompt bonding of the die 40 as described may generate a large number of voids 32 in the adhesive layer 30 .
- the voids 32 may be defects of the adhesive layer 30 .
- the voids 32 may be generated close to a top surface of the second substrate 50 , and may occupy about 4% of the total volume of the adhesive layer 30 .
- the bumps 20 and the adhesive layer 30 may be cooled down. The bumps 20 and the adhesive layer 30 may then be solidified.
- the adhesive layer 30 may be formed on the second substrate 50 , and the die 40 may thereafter be provided onto the adhesive layer 30 .
- the adhesive layer 30 may pollute side and bottom surfaces of the second substrate 50 , and also alignment fault of the die 40 may occur.
- the adhesive layer 30 is formed on the die 40 , and the die 40 with the adhesive layer 30 thereon is thereafter bonded to the second substrate 50 , it may be possible to prevent alignment fault of the die 40 .
- a controller 100 may determine whether or not a given number of the dice 40 are bonded to the second substrate 50 .
- the controller 100 may for example perform well known testing and/or inspection of the dice 40 to determine if the dice 40 are successfully bonded to the second substrate 50 .
- the controller 100 may determine whether a number of the dice 40 that are successfully bonded to the second substrate 50 in step S 20 is greater than a reference number.
- the flip chip method may return to step S 20 and the bonding head 60 may additionally and/or repeatedly perform bonding of at least one die 40 to the second substrate 50 (S 20 ).
- a given number of the dice 40 may be bonded to the second substrate 50 , or in other words the number of dice 40 that are successfully bonded to the second substrate 50 is greater than the reference number (Yes in S 30 ), and the flip chip bonding method may proceed to step S 40 .
- the second substrate 50 is a printed circuit board
- about two hundred to about five hundred dice 40 may be bonded to the second substrate 50
- the duration of the bonding (S 20 ) of the dice 40 may be for example about 6 minutes to about 25 minutes.
- the second substrate 50 is a silicon wafer
- about one thousand dice 40 may be bonded to the second substrate 50 and the duration of the bonding (S 20 ) of the dice 40 may be for example about 50 minutes to about 1 hour.
- FIG. 13 illustrates an example of the step S 40 of curing the adhesive layer 30 , as shown in the flow chart of FIG. 1 .
- a reflow process may be performed on the adhesive layer 30 at step S 40 of curing the adhesive layer 30 .
- the adhesive layer 30 may be successfully cured for about 10 minutes to about 60 minutes.
- Step S 40 of curing the adhesive layer 30 may include step S 42 of heating the second substrate 50 and step S 44 of providing air 82 .
- the second substrate 50 may be heated in an oven 70 (S 42 ).
- the oven 70 may include housing 72 , a plate 74 , second heater 76 , and second power source 78 .
- the housing 72 in which the second substrate 50 is placed may provide a hermetically sealed space.
- the plate 74 may reside or be disposed on a floor side of the housing 72 .
- the second substrate 50 may be loaded or held on the plate 74 .
- the second heater 76 may be installed or disposed in the plate 74 .
- the second power source 78 supplies the second heater 76 with second heating power
- the second heater 76 may heat the second substrate 50 .
- the second heater 76 may heat the second substrate 50 to a temperature (i.e., a second temperature) of for example about 100° C. to about 150° C.
- the second temperature may be less than the first temperature.
- the adhesive layer 30 and/or the bumps 20 may be melted, and the melted adhesive layer 30 may have a viscosity of about 2,000 pascal-second (Pa ⁇ s) to about 3,000 Pa ⁇ s.
- the second substrate 50 may be heated to a temperature of about 50° C. to about 200° C. to melt the adhesive layer 30 , and the melted adhesive layer 30 may have a viscosity of about 500 Pa ⁇ s to about 4,000 Pa ⁇ s.
- the housing 72 may be engaged with an air supply 80 .
- the air supply 80 may provide air 82 (e.g., see FIG. 15 ) to the adhesive layer 30 and the second substrate 50 in the housing 72 , removing the voids 32 from the adhesive layer 30 (S 44 ).
- the air 82 may include for example a nitrogen gas, a helium gas, an oxygen gas, a carbon dioxide gas, or an argon gas, or a combination thereof.
- the air supply 80 may include an air pump. When the air supply 80 provides the air 82 into the housing 72 , the air 82 in the housing 72 may increase in pressure. When the pressure of the air 82 in the housing 72 is increased, the adhesive layer 30 may increase in cohesive force and/or surface tension. When the cohesive force and/or the surface tension of the adhesive layer 30 are increased, the voids 32 may be discharged and removed out of the adhesive layer 30 .
- FIG. 14 illustrates a graph showing how a removal rate of the voids 32 depends on the pressure of the air 82 in the housing 72 .
- the horizontal axis shows air pressure in megapascals, and the vertical axis shows void removal rate.
- the removal rate of the voids 32 may be equal to or greater than about 97%.
- the pressure of the air 82 in the housing 72 is about 7 bars (or 0.7 Mpa) to about 10 bars (or 1.0 Mpa)
- the removal rate of the voids 32 may be almost about 100%.
- the pressure of the air 82 in the housing 72 is equal to or greater than about 4 bars (or 0.4 Mpa)
- the removal rate of the voids 32 may be almost about 98%.
- the pressure of the air 82 in the housing 72 is about 1 bar (or 0.1 Mpa) to about 2 bars (or 0.2 Mpa)
- the removal rate of the voids 32 may be equal to or less than about 95%.
- FIG. 15 illustrates a cross-sectional view of a fillet 34 of the adhesive layer 30 under typical vacuum pressure.
- the voids 32 may be promptly removed or decreased in the adhesive layer 30 .
- the housing 72 may be engaged with an air exhaust 90 to evacuate or pump the air 82 from or out of the housing 72 .
- the air exhaust 90 may include an air pump.
- the pressure of the air 82 in the housing 72 may be reduced to vacuum pressure.
- a fillet 34 of the adhesive layer 30 may be generated and/or increased.
- the fillet 34 is a type of defect formed when a portion of the adhesive layer 30 outwardly protrudes to the outside of the dice 40 . In other words, the fillet 34 of the adhesive layer 30 protrudes above an upper main surface of the dice 40 .
- the air supply 80 may provide the air 82 within the housing 72 as having pressure equal to or greater than atmospheric pressure or 1 bar. Thus, defects such as the voids 32 and the fillet 34 may be reduced or removed from the adhesive layer 30 .
- air having pressure greater than atmospheric pressure may be provided to an adhesive layer between a substrate and a die, which may result in a reduction in defects such as voids and fillets of the adhesive layer.
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
Description
Claims (19)
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KR1020180096743A KR102555721B1 (en) | 2018-08-20 | 2018-08-20 | method for bonding flip chip |
KR10-2018-0096743 | 2018-08-20 |
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US20200058615A1 US20200058615A1 (en) | 2020-02-20 |
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Also Published As
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US20200058615A1 (en) | 2020-02-20 |
KR102555721B1 (en) | 2023-07-17 |
KR20200021230A (en) | 2020-02-28 |
CN110854028A (en) | 2020-02-28 |
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