US10134482B2 - Apparatuses and methods for high speed writing test mode for memories - Google Patents
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- US10134482B2 US10134482B2 US15/408,272 US201715408272A US10134482B2 US 10134482 B2 US10134482 B2 US 10134482B2 US 201715408272 A US201715408272 A US 201715408272A US 10134482 B2 US10134482 B2 US 10134482B2
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/36—Data generation devices, e.g. data inverters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
Definitions
- test system cost tends to increase rapidly, and eventually, as signal quality to the DRAM degrades, existing and affordable test solutions become unable to deliver signals correctly into the memory array for testing.
- a circuit for implementing a test mode is provided which allows write data to be tested at full system speed, e.g. without changing the system clock frequency, but with reduced signal integrity requirements.
- FIG. 1 is a schematic block diagram of a semiconductor device, in accordance with various embodiments.
- FIG. 2 is a schematic block diagram of a GDDR5 interface, in accordance with various embodiments.
- FIG. 3 is a flow diagram of a method for GDDR5 interface training, in accordance with various embodiments.
- FIG. 4 is a schematic block diagram of test mode circuitry in a semiconductor device, in accordance with various embodiments.
- FIG. 5 is a timing diagram of a memory device in test mode, in accordance with various embodiments.
- FIG. 6 is a flow diagram of a method of implementing a test mode, in accordance with various embodiments.
- FIG. 1 illustrates a schematic block diagram of a semiconductor device 100 , in accordance with various embodiments.
- the semiconductor device 100 includes a memory die.
- the memory die may include an address/command input circuit 105 , address decoder 110 , command decoder 115 , clock input circuit 120 , internal clock generator 130 , timing generator 135 , row decoder 140 , column decoder 145 , memory arrays 150 , read/write amplifiers 155 , I/O circuit 160 , ZQ calibration circuit 165 , and voltage generator 170 .
- the semiconductor device 100 may include, without limitation, a DRAM device, such as GDDR5 SGRAM integrated into a single semiconductor chip, for example.
- the die may be mounted on an external substrate, for example, a memory module substrate, a mother board or the like.
- the semiconductor device 100 may further include a memory array 150 .
- the memory array 150 includes a plurality of banks, each bank including a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC arranged at intersections of the plurality of word lines WL and the plurality of bit lines BL.
- the selection of the word line WL is performed by a row decoder 140 and the selection of the bit line BL is performed by a column decoder 145 .
- Sense amplifiers (SA) are located for their corresponding bit lines BL and connected to at least one respective local I/O line, which is in turn coupled to a respective one of at least two main I/O line pairs, via transfer gates (TG), which
- the semiconductor device 100 may employ a plurality of external terminals that include address and command terminals coupled to command/address bus (C/A), clock terminals CK and/CK, data terminals DQ, DQS, and DM, power supply terminals VDD, VSS, VDDQ, and VSSQ, and the ZQ calibration terminal (ZQ).
- C/A command/address bus
- CK and/CK clock terminals CK and/CK
- data terminals DQ, DQS, and DM data terminals
- power supply terminals VDD, VSS, VDDQ, and VSSQ power supply terminals VDD, VSS, VDDQ, and VSSQ
- ZQ ZQ calibration terminal
- the command/address terminals may be supplied with an address signal and a bank address signal from outside.
- the address signal and the bank address signal supplied to the address terminals are transferred, via the address/command input circuit 105 , to an address decoder 110 .
- the address decoder 110 receives the address signal and supplies a decoded row address signal to the row decoder 140 , and a decoded column address signal to the column decoder 145 .
- the address decoder 110 also receives the bank address signal and supplies the bank address signal to the row decoder 140 , the column decoder 145 .
- the command/address terminals may further be supplied with a command signal from outside, such as, for example, a memory controller 105 .
- the command signal may be provided, via the C/A bus, to the command decoder 115 via the address/command input circuit 105 .
- the command decoder 115 decodes the command signal to generate various internal commands that include a row command signal to select a word line and a column command signal, such as a read command or a write command, to select a bit line, and a test mode signal.
- the test mode signal may be provided to a test mode circuit 125 , which will be discussed in greater detail below.
- read data is read from a memory cell in the memory array 150 designated by these row address and column address.
- the read data DQ is output to outside from the data terminals DQ, DQS, and DM via read/write amplifiers 155 and an input/output circuit 160 .
- write data is supplied to the data terminals DQ, DQS, DM, the write data is received by data receivers in the input/output circuit 160 , and supplied via the input/output circuit 160 and the read/write amplifiers 155 to the memory array 150 and written in the memory cell designated by the row address and the column address.
- the clock terminals CK and/CK are supplied with an external clock signal and a complementary external clock signal, respectively.
- the external clock signals (including complementary external clock signal) may be supplied to a clock input circuit 105 .
- the clock input circuit 105 may receive the external clock signals to generate an internal clock signal ICLK.
- the internal clock signal ICLK is supplied to an internal clock generator 130 and thus a phase controlled internal clock signal LCLK is generated based on the received internal clock signal ICLK and a clock enable signal CKE from the address/command input circuit 105 .
- a DLL circuit can be used as the internal clock generator 130 .
- the phase controlled internal clock signal LCLK is supplied to the input/output circuit 160 and is used as a timing signal for determining an output timing of read data.
- the internal clock signal ICLK is also supplied to a timing generator 135 and thus various internal clock signals can be generated.
- the power supply terminals are supplied with power supply potentials VDD and VSS. These power supply potentials VDD and VSS are supplied to an internal voltage generator circuit 170 .
- the internal voltage generator circuit 170 generates various internal potentials VPP, VOD, VARY, VPERI, and the like and a reference potential ZQVREF based on the power supply potentials VDD and VSS.
- the internal potential VPP is mainly used in the row decoder 140
- the internal potentials VOD and VARY are mainly used in the sense amplifiers included in the memory array 150
- the internal potential VPERI is used in many other circuit blocks.
- the reference potential ZQVREF is used in the ZQ calibration circuit 165 .
- the power supply terminals are also supplied with power supply potentials VDDQ and VSSQ. These power supply potentials VDDQ and VSSQ are supplied to the input/output circuit 160 .
- the power supply potentials VDDQ and VSSQ are the same potentials as the power supply potentials VDD and VSS, respectively. However, the dedicated power supply potentials VDDQ and VSSQ are used for the input/output circuit 160 so that power supply noise generated by the input/output circuit 160 does not propagate to the other circuit blocks.
- the calibration terminal ZQ is connected to the ZQ calibration circuit 165 .
- the ZQ calibration circuit 165 performs a calibration operation with reference to an impedance of RZQ, and the reference potential ZQVREF, when activated by the ZQ calibration command signal (ZQ_com).
- An impedance code ZQCODE obtained by the calibration operation is supplied to the input/output circuit 160 , and thus an impedance of an output buffer (not shown) included in the input/output circuit 160 is specified.
- the command decoder 115 decodes the command signal and generates various internal commands. For example, the command decoder 115 may generate the test mode write internal control signal responsive to a test mode write internal command.
- the test mode circuit may output a test mode control signal, such as a test mode write internal control signal (tm_wrint), to the I/O circuit 160 .
- a test mode write internal control signal such as a test mode write internal control signal (tm_wrint)
- the I/O circuit 160 may be configured to enter a test mode configuration such that data may be written to the memory array 150 , and read from the memory array 150 , at high speeds without using data receivers of the I/O circuit 160 .
- test data may be written into the memory array 150 internally, without relying on data receivers, thus allowing write data testing to be performed without input from an external system.
- FIG. 2 is a schematic block diagram of a GDDR5 interface 200 , in accordance with various embodiments.
- FIG. 2 depicts the interface between a controller 205 and GDDR5 SGRAM 210 .
- the GDDR5 SGRAM 210 may include a data bus 215 .
- the data bus 215 may be configured to transmit and receive data, to and from the controller 205 .
- the GDDR5 SGRAM 210 may also include a command/address bus 220 configured to receive commands and address information from the controller 205 .
- the controller 205 may include a memory controller as known in the art, including without limitation, an integrated memory controller, or separate chip.
- the GDDR5 interface 200 may be divided into several channels, each channel being 32-bits wide. Each channel may include a single GDDR5 SGRAM 210 operating in x32 mode, utilizing a single 32-bit data bus 215 . Alternatively, two GDDR5 SGRAM 210 may be operated in x16 or “clamshell” mode. In x16 mode, the data bus 215 may be split into two 16-bit wide buses routed to each of the two GDDR SGRAM 210 devices separately. Address and command pins may be shared between the two GDDR5 SGRAM 210 devices, preserving the total I/O pin count at the controller 205 , without decreasing system performance. Clamshell mode may essentially double memory density on an x32 GDDR5 channel by changing frame buffer size.
- GDDR5 SGRAM 210 utilizes a scheme with direct latching data receivers and no delay matching between the data receiver and differential forwarded clock signal (write clock), WCK.
- the controller 205 determines the optimum phase relationship between write data and the WCK clock for each data pin through a process of data training, as will be described in more detail below with reference to FIG. 3 .
- FIG. 3 is a flow diagram of a method 300 for GDDR5 interface training, in accordance with various embodiments.
- the method 300 begins at block 305 , by first powering up. Upon power up, device configuration in x32 or x16 mode, and on-die terminations for the address/command lines are set.
- an address training procedure may be completed. Address training may be used to center the address input data eye.
- address training mode uses an internal bridge between the device's address input and data outputs. A special READ command is utilized for address capture, which are then synchronously output to the controller via the data output pins, for example, the DQ and DBI_n pins depicted in FIG. 2 . The controller may then compare the address patterns to an expected value and adjust address transmit timings accordingly.
- WCK-to-CK training may be performed.
- WCK and CK clock signals require a specific phase relationship that varies depending on the device. This phase relationship ensures a reliable phase-over of write data from the external WCK clock domain to the internal CK clock domain. Similarly, the same phase relationship ensures a reliable phase-over of read data, from the internal CK clock domain to the external WCK clock domain, and of the output drivers. This helps to define READ and WRITE latencies between the device and the memory controller.
- WCK-to-CK training may be initiated by the controller. The controller may sweep the WCK clocks against the CK clock. The device may respond by a static signal indicating an “early” or “late” clock phase. The optimum phase relationship may be indicated by the transition from early to late phase.
- Read training may enable a controller to find the data eye center and burst frame location for each output from the GDDR5 device.
- read training may align the data bus to the WCK clock. This may include two parts: 1) aligning the latching clock in the memory controller to the center of a read data bit; and 2) detecting burst boundaries out of a continuous read data stream.
- a read buffer may be utilized to function as temporary storage for read data. The read buffer may be preloaded with test data that may be transmitted over a previous trained address bus. Once read buffer is loaded with test data, a read command may be issued by the controller repeatedly. The controller may then sweep its clock phase until the data is correctly sampled.
- write training is performed.
- Write training enables the memory controller to find a data eye center and burst frame location for write data, for each high-speed input of the DRAM.
- write training may be the final step in interface training, aligning the data bus to the WCK clock.
- write training may include two parts: 1) aligning the latching clock in the DRAM to the center of the write data bit; and 2) detecting the burst boundaries of a continuous write data stream.
- test data may be loaded into a write buffer via the address bus, without utilizing data receivers. The test data may then be written into the DRAM, and read from the DRAM into the read buffer. The memory controller may then read the test data from the read buffer, and sweep the write data phase until the data is written correctly. After write training, all data eyes are expected to be centered.
- FIG. 4 is a schematic block diagram of an arrangement of test mode circuitry in a semiconductor device 400 , in accordance with various embodiments. The following discussion will make reference to FIG. 4 regarding a configuration for implementing test mode operations, including write training as described above with respect to FIG. 3 .
- the semiconductor device 400 may be similar to the semiconductor device 100 of FIG. 1 .
- the semiconductor device 400 may include an internal clock generator (PLL) 405 , command buffer/decoder 410 , test circuit 415 , address buffer/decoder 420 , a memory core 485 including a data path 445 and memory array 480 , clock input terminals WCK 455 and CK 460 , command terminal 465 , address terminal 470 , and data terminal 475 .
- PLL internal clock generator
- the I/O circuit 160 may include, without limitation, a data receiver Rx 425 , data transmitter Tx 430 , read buffer 435 , write buffer 440 , and switch 450 .
- the read and write buffers may be first in first out (FIFO) buffers, and may alternatively be referred to as read FIFO 435 and write FIFO 440 .
- WCK 455 may correspond to a write clock signal associated with the data terminal 475
- CK 460 may correspond to a command clock associated with the command terminal 465
- the write buffer 440 may be configured to account for the clock frequency differences.
- the internal clock generator 405 may be configured to generate an internal PLL clock signal derived from WCK 455 .
- the internal PLL clock signal may have the same clock frequency as CK 460 .
- the write buffer 440 may be utilized to transfer data from the WCK 455 domain to the CK 460 domain before writing to the memory array 480 . It is to be understood that in other embodiments, WCK 455 and CK 460 may be synchronized externally, such that a separate write buffer 440 may not be necessary.
- the I/O circuit 160 may enter a test mode.
- the test mode control signals may include, without limitation, tm_wrint and a test mode control signal configured to disable the data receiver Rx 430 .
- Disabling may include, without limitation, shutting off or otherwise preventing the data receiver Rx 430 from outputting data to the write buffer 440 . Therefore, the input of the write buffer 440 may be disconnected from Rx 430 .
- tm_wrint and the test mode control signal for disabling Rx 430 may be separate signals while in other embodiments, a single test mode control signal may be used.
- the I/O circuit 160 may be configured to disable data receiver Rx 430 , and load test data into the read buffer 435 , write buffer 440 , or both read and write buffers 435 , 440 , via the address bus.
- the write buffer 440 may have a second input coupled to the address bus.
- the switch 450 may be optional.
- the I/O circuit 160 may be configured to couple the read buffer 435 to the write buffer 440 via the switch 450 .
- the write buffer 440 may have a second input that may be coupled to the switch 450 .
- the switch 450 may be closed, connecting the read buffer 435 to the second input of the write buffer 440 such that test data may be loaded, from the read buffer 435 , into the write buffer 440 .
- the test mode may be utilized for interface training, as discussed previously with respect to FIG. 2 .
- a load FIFO command (LDFF) may be utilized.
- the LDFF command may cause the read buffer 435 to be loaded with a test data sequence (LDFF data) without accessing the memory array 480 .
- the contents of the read buffer 435 may then be read by the controller in order to find the read data eye.
- the LDFF data may be provided to the read buffer 435 via the address bus.
- the address bus may have half or a quarter of the data rate of the data terminal 475 . It will be appreciated by those of ordinary skill in the art that the speed at which LDFF data is loaded is not critical.
- the LDFF command thus, loads the read buffer 435 of the device 400 and generates an input pointer trigger for the read buffer 435 , wherein the input pointer trigger may enable or disable the input pointer of the read buffer 435 from updating.
- the LDFF command may also be used to load LDFF data into the write buffer 440 via the address bus.
- the LDFF command may disable the input pointer of the write buffer 440 and the data receivers 430 .
- LDFF data may be written directly from the write buffer into the memory array 480 with a full-speed write operation, in order to test the data path 445 . Therefore, in these embodiments, after entering test mode and tm_wrint is enabled, the write buffer 440 may be loaded, via the address bus, by issuing LDFF commands and written to the memory array 480 by issuing write commands.
- test data sequence may be loaded into the write buffer 440 through the data receiver 430 after initializing the test mode. After the write buffer 440 is loaded with the test data sequence through the data receiver 430 , the data receiver 430 may be disabled as described above.
- the test data sequence may be configured to stress the data paths 445 to and from the memory array 150 , 480 .
- the test data sequence may follow a pattern or have the same bit value.
- the read buffer 435 and write buffer 440 in some embodiments, may be a FIFO buffer with a depth of two or more.
- the test data sequence may include alternating A data and B data sequences stored in the write buffer 440 with a depth of two.
- the data terminal 475 may comprise 32 data pins into the write buffer 440 .
- a burst length of 16 bits per input line may be utilized, for a total of 512 bits.
- the write buffer 440 may correspondingly output the 512-bits of the test data sequence to the memory array 480 in parallel, each time a write command is issued.
- two test data sequences, 512-bits each may be stored in the write buffer 440 concurrently.
- the input pointer for the write buffer 440 may also be disabled, preventing further data from being written into the write buffer 440 .
- the output pointer of the write buffer 440 may continue to be updated after each write command. This allows the write buffer 440 to cycle through outputting the one or more test data sequence(s) that are already loaded in the write buffer 440 on subsequent write commands.
- the switch 450 may turn on, entering a conductive state. Consequently, the data stored in read buffer 435 may be loaded into the write buffer 440 .
- the test data sequence may be loaded from the address bus into the read buffer 435 and write buffer 440 concurrently.
- the test data sequence may be loaded into the read buffer 435 and/or write buffer 440 serially, as received through address terminal 470 and via the address bus.
- the test data sequence(s) may be loaded into the write buffer 440 , but not the read buffer 435 .
- the read buffer 435 may, in turn, only be loaded with the test data sequence as read from the memory array 480 .
- a write command may be issued by the controller to write the test data sequence into the memory array 480 , at full speed.
- the test data sequence may be read out from memory array 480 to the read buffer 435 , and out to a memory controller for processing.
- the memory controller may check for and identify errors in the retrieved test data sequence, analyze performance metrics, or perform other test functions as appropriate.
- FIG. 5 is a timing diagram 500 of a memory device in test mode, in accordance with various embodiments.
- the timing diagram 500 includes test mode write internal signal tm_wrint 505 , external receiver data (srwd) 510 , write buffer input pointer (iptr) 515 , write buffer output pointer (optr) 520 , and write buffer output data (lrwd) 525 .
- external data D 0 -D 7 may be received by the data receiver 530 , based on WCK 555 .
- iptr may continue to be cycled, in this case between a first input and second pointer locations. However, when tm_wrint 505 is asserted, the iptr 515 is disabled or otherwise prevented from being updated. As depicted, in some embodiments, D 3 and D 4 may be test data sequences that were loaded into write buffer 540 via the address bus. Thus, tm_wrint 505 may be asserted after the test data sequences have already been loaded into the write buffer 540 .
- optr 520 may be allowed to continually cycle between the first and second pointer locations, outputting data stored in each of the respective pointer locations.
- data may be read from srwd 510 and output by the output buffer.
- tm_wrint 505 is asserted
- data D 4 is loaded into the first pointer location, while data D 3 remains loaded in the second pointer location.
- iptr 515 is not updated, and because connection to the data receiver has disabled, data D 3 and D 4 is not rewritten in the write buffer.
- the write buffer is able to continually switch its output between data D 3 and data D 4 , allowing for full-speed write operations in test mode, without waiting for data to be continually loaded into the write buffer.
- FIG. 6 is a flow diagram of a method 600 of implementing a test mode, in accordance with various embodiments.
- the method 600 begins, at block 605 , by receiving a test mode command.
- the test mode command may be issued externally by the memory controller and received by the test mode circuit.
- test mode control signals are generated by the test mode circuit.
- test mode control signals may include a tm_wrint signal.
- the data receivers may be disconnected from the write buffer input.
- the test mode control signals may disable the data receivers, preventing the write buffer from reading data from the data receivers.
- the test mode control signal may cause the write buffer to switch between different inputs from which the write buffer reads data.
- the write buffer input may be switched from an input coupled to the data receiver, to a second input coupled to the address bus or, alternatively, the read buffer.
- the test mode control signals may both disable the data receivers and cause the write buffer to read data from an input coupled to the address bus.
- the method 600 progresses by receiving a test data sequence on the address bus.
- the test mode control signals may cause a test data sequence to be retrieved, via the address terminal, and output on the address bus.
- the test data sequence may be loaded into the write buffer via the address bus.
- the write buffer input pointer may be disabled. Thus, once the loading of all test data sequences are complete, new data may be prevented from being read into write buffer.
- the test data sequence may be written to the memory array 635 . Because the test data sequence is written from the write buffer, the test data sequence may be written to the memory array at full write speed, with each write command.
- the write buffer output pointer may then be progressed to the next output pointer location. In some embodiments, the write buffer may have a depth of two.
- the output pointer may switch between the two output pointer locations, each of the two output pointer locations corresponding to a respective test data sequence. For example, in some embodiments, writes from the write buffer may alternate between a first test data sequence, Data A, and a second test data sequence, Data B.
- testing it may be determined whether testing is complete. If testing is not complete, the test data sequence may be written, at block 635 , from the write buffer into memory upon receiving a write command, and at optional block 640 , again progress the write buffer output pointer. If testing is completed, the method progresses, at block 650 , to exit test mode.
Abstract
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US20180204630A1 (en) | 2018-07-19 |
US20190051369A1 (en) | 2019-02-14 |
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