UA74712C2 - Multiple-processor system - Google Patents

Abstract

The proposed multiple-processor computing system contains processing units and peripheral devices, which are connected by a common data bus. Each processing unit contains a processor, a random-access memory unit, two switching units, and an instruction register, which are connected by a local data bus, a multiplexer, a buffer memory unit, a control unit, an address register, and additionally, a data translation register. The input of the data translation register is connected to the common data bus, and the output is connected to the input of the control unit. The use of the data translation register allows the processing power of the system to be increased due to the decrease of the rate of the references of the processing unit to the common data bus, which is achieved due to a possibility to transmit identical data, without additional processing, directly from one of the processing units to several specified processing units. The data translation register determines the processing units with which the corresponding processing unit should communicate.

Description

Description of the invention

The invention relates to computer technology and can be applied in the creation of multiprocessor 2 systems.

A multiprocessor system with a common bus is known, which contains processor blocks, a block of common memory, input-output devices connected to each other by means of a common bus. Each processing unit contains a processor, local memory, communication memory, and a switch, which are interconnected by means of a local bus. Access to the communication memory from the side of the common bus is performed using a switch. Data exchange 70 between processor units is performed only through the communication memory. Management of the exchange process is performed by the processor unit, which at this stage switches to the mode of the communication processor |11.

However, this device allows simultaneous data exchange only between two processor units and only after switching both processor units to exchange mode, which significantly reduces the performance of the computer system. 19 A multiprocessor system with a common bus is known, which contains processor units, a common bus, and external devices. In this device, the processor units are connected to each other and to external devices using a common bus. Each processor unit contains a processor, local memory, communication memory, first and second switches, a command register, address and data registers, and a control unit. The processor, the local memory, the first input-output of the first switch, the first input of the second switch, and the first input-output of the command register are interconnected by means of a local bus. The first input-output of the communication memory is connected to the second input-output of the first switch, and the control input of the communication memory is connected to the first output of the control unit. The first output of the address register and the first input-output of the data register are connected to the third and fourth inputs of the first switch, respectively. The second output of the second switch, the second input-output of the command register, the second input of the address register and the second input of the data register are connected to the common bus. The third input of the command register, the third input of the address register, the third input of the data register and the third input of the second switch (U) are connected to the control unit (21.

The disadvantage of this device is that it requires a significant amount of time to exchange data between processor units. This is due, firstly, to the fact that data exchange can only be carried out between two processor units at the same time, secondly, the transfer of one word from one processor unit to another requires two accesses to the common bus, and thirdly, data exchange can only be carried out between communication - che memories of processor units and only after they are disconnected from the local bus.

The closest to the invention in terms of technical essence is a multiprocessor system |C), which includes processor units and external devices connected to each other by means of a common bus. Each processor unit contains a processor, local memory, communication memory, first and second switches, a command register, 3 address and data registers, a next address register, an address modification block, address memory, a multiplexer and a control block . The processor, the local memory, the first input-output of the first switch, the first input-output of the second switch, and the first input-output of the command register are interconnected by means of a local bus.

The first information input-output of the communication memory is connected to the second input-output of the first switch, and the control input of the communication memory is connected to the first output of the control unit. The first output of the Z address register is connected to the first input of the address memory, and the first input-output of the data register is connected to the third input of the first switch and to the first input of the multiplexer. Address memory output is bound

With" the fourth input of the first switch and with the first input of the address modification block. The output of the address modification block is connected to the first input of the register of the next address. The output of the next address register is connected to the second input of the multiplexer. The output of the multiplexer is connected to the second input of the address memory. The second input-output of the second switch, the second input-output of the command register, the second input of the address register and the second input of the data register are connected to a common bus. The second input of the address modification block, the second input of the register "" of the next address, the third input of the address memory, the third input of the multiplexer, the third input of the address register, the third input of the data register, the third input-output of the command register, the third input-output of the second switch and n and the input of the first switch are connected to the control unit. - 70 The disadvantage of this system is that it does not allow the combination of data transfer processes from one processor unit to several processor units at the same time, that is, it is not possible to implement the translational mode of data transfer. The system allows the combination of information exchange processes between processor units only in differential mode, when the exchange takes place in pairs between processors. To transfer the same data from one processor unit to several processor units, multiple repetitions of data transfer processes 52 are necessary.

GF) The invention is based on the task of improving a multiprocessor system by introducing a translation register, which allows to increase the performance of the system due to translational data transfer, namely due to simultaneous data transfer by many processor units, thereby reducing the number of calls to the common bus. 60 The set task is performed by the fact that in a multiprocessor system containing processor units and external devices connected to each other by a common bus, each processor unit contains a processor, local memory, which are connected to each other by a local bus to which the first one is connected the information input-output of the first switch, the first information input-output of the second switch, and the first information input-output of the command register, the second information input-output of the first switch is connected to the information input-output of the communication memory, the control input of which is connected connected to the first output of the control unit, the second output of which is connected to the control input of the first switch, the third output - to the control input of the address register, the fourth output - to the control input of the data register, the fifth input-output - to the input-output of the register control commands, the sixth - with the control input-output of the second switch, the seventh input-output - with the common bus, to which the second information input-output is connected d of the second switch, the second information input-output of the command register, the information input of the address register and the information input of the data register, the output of which is connected to the data input of the first switch and to the first information input of the multiplexer, the output of which is connected to the data input of the address memory, the data output of which is connected to the address input of the first switch and to the information input of the address modification block, the output of which is connected to the information input of the /o register of the next address, the output of which is connected to the second information input of the multiplexer, the output of the address register is connected with the address input of the address memory, the control input of which is connected to the eighth output of the control unit, the ninth, tenth and eleventh outputs of which are connected, respectively, the control input of the address modification block, the control input of the next address register, the control input of the multiplexer, what is new is that that it includes a translation register, the output of which is connected to the input of the control unit, dvan adcyaty /5 The output of which is connected to the control input of the translation register, the information input of which is connected to the common bus.

Increasing the performance of the device is achieved due to the simultaneous transfer of data from one processor unit to the communication memories of several other processor units. For this, a translation register is included in each processor unit, which stores the signs of operation with its communication memory 2o during translation (from one processor unit to several) transmission by other processor units.

If the appropriate sign is set in this register, then during broadcast transmission from another processor unit, data will be written into the communication memory of this processor unit.

In fig. 1 shows a structural diagram of a data processing device for a multiprocessor system; in fig. 2 - example of command register format; in fig. C - an example of the distribution of the address space of the common bus; fig. 4 - section Configuration of connections of the processor unit at the stage of program execution and exchange of results; in fig. 5 - the configuration of connections of the processor unit at the stage of processing the results of the program execution. and)

The data processing device (Fig. 1) for a multiprocessor system includes processor units 1.1,...,1.n, a common bus 2, to which external devices 3.1,...3.K are connected. Each processor unit 1 includes a processor 4, local memory 5, local bus 6, first 7 and second 8 switches, command register 9, communication memory 10, address memory 11, modification block 12 address, register 13 next address, multiplexer 14, register 15 address, register 16 data, register 17 broadcast, unit 18 control. --

In each processor block I.i (i1-1,2,..,1) processor 4 and local memory 5 are connected by means of M local bus b, to which the first information input-output of the first switch 7 is also connected, the first information input-output of the second switch 8 and the first information input-output of the command register 9. "

The local bus b through the second information input-output of the first switch 7 is connected to the information input-output of the communication memory 10, and through the input address of the first switch 7 is connected to the data output of the address memory 11. The data output of the address memory 11 is also connected to the information input of the address modification block 12, the output of which is connected to the information input of the register 13 of the next address, the output of which is connected to the first information input of the multiplexer 14, the output of which is connected to the input of the memory data 11 addresses , to the input address of which the output of register 15 address is connected. The output of the data register 16 from c is connected to the second information input of the multiplexer 14 and to the data input of the first switch 7.

The second information input-output of the second switch 8 is connected to the common bus 2, the second information ;" input-output of the command register 9, information input of the address register 15, information input of the data register 16, information input of the broadcast register 17 and the first input-output of the control block 18, the inputs-outputs of which

Connected to the control input of the first switch 7, the control input-output of the second switch 8, -And the control input-output of the command register 9, the communication memory control input 10, the memory control input 11 of addresses, the control input of the address modification block 12, the input control register 13 next ve address, control input multiplexer 14, control input register 15 address, control input register 16 -And data, control input register 17 broadcast, the information output of which is connected to the control unit input. - The purpose of the control unit 18 is to generate signals that are necessary for the implementation of cycles

Access to the common bus 2 through the second switch 8, control signals for internal nodes of the 1st processor unit, as well as signals for changing connections between functional nodes using the first switch 7. The operating mode of the control unit 18 is determined by the values of the corresponding bits of the register 9 commands and 17 broadcast registers.

A possible register format of 9 commands is shown in fig. 2, and the assignment of each of its digits, respectively, in (F, table. 1. ka The first switch 7 is designed to perform connections in accordance with the value in the OBM digit of the command register 9 between the local bus 6 and the communication memory 10, or between communication memory 10, the output of address memory 11 and the output of data register 16. The first switch can be implemented on the basis of standard microcircuits of multiplexers and bidirectional bus formers.

The address memory 11 is designed to store all the access addresses to the communication memory 10 of the processor unit 1-i from other processor units 1.) (-1,2,...,y1; |i ). At the same time, with the help of the first switch 7, its data output can be connected to the bits of the information input-output address 65 of the communication memory 10. The capacity of the memory 11 of addresses must be no less than n K-bit words, where n is the number of processor blocks in the system, and K is the number of digits of the address of the communication memory 10. The address memory 11, for example, can be built using microcircuits of a static memory of sufficient capacity, in which data inputs and outputs are made separately.

The purpose of the address modification block 12 is to calculate the word address, which will be written into the communication memory 10 at the next access to it by the corresponding processor block 1.). Block 12 address modification, for example, can be built using an adder, which is a standard element of most existing series of microcircuits.

The purpose of the translation register 17 is to store the signs of working with the communication memory of this processor unit 1.th from the block of other processor units of the multiprocessor system during translation 7/o data transmission. This register can be built using standard registers with bit-by-bit recording of information. The number of digits of this register must be at least n, where n is the number of processor units in the system.

A possible version of the distribution of the address space of the common bus is shown in fig. C, where the crossed-out address areas of the common bus represent unused addresses in this device or block. The older addresses of 7/5 of the address space of the common bus are allocated for the local memory of 5 processor units 1.1,..., 1.n, which is accessible only from the side of the processor 4 of the processor unit in which this memory is located and is not accessible from side of other processor units. The following area is allocated for access to the communication memory 10 of each processor unit by other processor units. In the area of the communication memory for addressing the communication memory 10 of the processor unit 1. and from the side of the processor unit 1.| 2n addresses are allocated, n addresses for address windows (BA), n addresses for data windows (VD), marked in fig. With, respectively, as VAYI), VDiY, while the total number of used addresses for all processor blocks 1.1,...,, 1.n is 2n 2. The next area of broadcast transmission addresses is divided into addresses of RTi broadcast registers and broadcast data addresses

DtTI, through which data exchange is directly performed in broadcast mode. Younger addresses of the space of the common bus 2 are distributed among registers of 9 commands of processor units, external devices 3.1,...,3.K and Ga are unused addresses.

The peculiarity of the register 17 of broadcasts of the 1st processor unit is that its information input i9) is connected to the ith bit of data of the common bus 2. Address to RT| ensures recording of data from the ith bit of data of the common bus 2 in the ith bit of the translation register 17 of the 1st processing unit (see Fig. C).

Thanks to such connections of the registers of 17 broadcasts, the recording of the word at the address RT| provides at the same time the recording of all Ge features of the broadcast transmission from the processor unit | in all processor units 1.1,...,1.p.

The device works as follows. After the start of the multiprocessor system (by the external "Start" signal), the processors 4 start executing the programs that are recorded in the local memory 5 of the corresponding rch-processor blocks 1.1,...1.1. The result of these programs is the initialization of each processor unit 1.1,...1.1. Each processor unit 1.1,..,.1.1 executes its information processing program. External devices M Z.41,...3.K of the system provide input and output of information. Access to them from the processor units - 1.1,...1.1 is carried out through the common bus 2. Through external devices 3.1,...3.K, the data necessary for the implementation of the computing process is entered, and the results of the calculations are also output. One of the processor units, for example 1.1, performs the functions of the control processor unit, and the others - subordinate processor units « 1.2,...1.p. This is achieved, for example, by setting the value of the FUNC bit in register 9 of the 70 external "Start" signal to one for the control processor unit and to zero, respectively, for subordinates - s (all others). The functions of the control processor unit 1.1 are to distribute tasks between subordinate "» processor units 1.2,...1.n, to launch these processor units to perform tasks, to prepare subordinate units to exchange results. The functions of subordinate processor units and with the control processor unit block 45..141.-I The operation of the system when solving a given task consists of a series of stages of parallel execution of programs with the exchange of results between the communication memories of processor units 1.1,...1.n, and stages of processor units 1.2,. .,1.0 is the execution of tasks and the exchange of results with other subordinate processing units in -I processor units. At the stage of program execution, each processor unit 1.i has the configuration of Fig. 4, in which processor 4 has access to its local memory 5 and through the second switch 8 to the common bus, and then through register 15

Kz address, memory 11 addresses, register 16 data and the first switch 7 of other processor units to their switching memory 10. Thus, during the execution of the program in the processor 4 of one processor unit 1, the results are formed, which are recorded in the communication memory 10 other processor units 1. Indicated in fig. 4

The connection configuration, in which the communication memory 10 is disconnected from the local bus 6 and connected to the data output of the address memory 11 and the output of the data register 16, is achieved using the first switch 7,

Ф, which is switched under the control of the control unit 18 after writing in the OBM bit of the register 9 commands to one.

At the stage of processing the results, the processor unit 1.i has the configuration of fig. 5, in which the processor 4 has access to its local memory 5 and through the first switch 7 to the communication memory 10. Thus, at the stage of processing the results, the data received in the communication memory 10 of the processor unit 1. and with other processor units, become available to the processor 4 of this processor unit and are forwarded to its local memory 5 for further processing. Indicated in fig. 5, the connection configuration, in which the communication memory 10 is connected to the local bus 6 and is disconnected from the data output of the address memory 11 and the output of the data register 65 16, is achieved with the help of the first switch 7, which is switched under the control of the control unit 18 after recording in the OBM bit of the register 9 zero commands.

After the completion of the stage of processing the results in the 1st processor unit, the processor 4 sets the OBM bit to one in its command register 9U, as a result of which the communication memory 10 is disconnected from the local bus b of the processor unit and becomes available for exchange from the common bus unit 2, that is, other processor units 1.1,..., 1.p.

Consider the operation of processor unit 1 at the stage of exchange between its communication memory 10 and processor unit 1. At the beginning of the exchange, the processor unit 1 writes to the processor unit 1 the address of the communication memory from which the array of results will start. To do this, the processor unit 1. executes a write cycle to the address of the window address ВАЙ| (see Fig. 3) in which it transmits the address of the beginning of the array. After the start of this 7/0 operation, the address of the array is written into register 16 of the data of the processor unit 1.i, and part of the address bits from the common bus is written into register 15 of the address of the same processor unit. At the end of the cycle of recording the addresses of the array from the output of the data register 16 through the second information input of the multiplexer 14, the data through its output is fed to the data input of the address memory 11 and is written in it at the address from the output of the register 15 address.

The switching of bits at the information input of the register 15 address is performed in such a way that when addressing the /5 address of VAYI) or VDC of the address at its output will be equal to |, i.e. coincides with the number of the processor unit that performs the recording. Such conditions can be fulfilled, for example, if several digits are used to assign the number of the processor unit on the common bus.

Results are directly sent to the 1st processor unit in the data recording cycle from the 1st processor unit to the address of the VDc data window (see Fig. 3). At the beginning of the address recording cycle | address memory 11, the address is fixed in the register 15, and the data to be written is fixed in the data register 16. Next, the specified earlier address of the beginning of the array of results is read from the address memory 11, which is fed to the information input-output of the communication memory 10 through the address input of the first switch 7, and the data for writing through the data input of the same switch from the output of the data register 16. At the same time, a recording signal is applied to the control input of the communication memory 10. The address from the data output of the address memory 11 is also fed to the information input of the address modification block 12, which calculates the address of the next word of the array in the communication memory and outputs it to the information input of the next address register 13. After completion of the recording cycle on the common bus 2, a new i) address from the output of the register 13 to the next address through the first information input of the multiplexer 14 is written into the memory 11 of addresses at the address at the output of the register 15 address. Thus, after writing a word of data into the communication memory 10 of the processor unit 1. from the processor unit 1.), the address corresponding to it from the communication memory changes and addresses the next word.

To increase the performance of the processor unit when sending the same data to many processor units in the system, the broadcast transmission mode is used. Consider the operation of the system under M during the transmission of the array of results from the processor unit 1 to the processor units 1.K, 1.t, 1.5 (decK, t, 5 are arbitrary indices). "

At the beginning of the exchange, the 1st processor unit writes to the 1.K, 1.t, 1.5 processor units the addresses of the communication memory from which the result arrays will begin. To do this, the processor unit 1.i performs Z cycles of writing to the addresses of the windows address VAKi, VAti, VApi, respectively, for processor units 1.K, 1.t, 1.5. As a result of this procedure, the addresses of the arrays in the communication memory 10 will be written in the memory 11 of the addresses of the corresponding processor units at the address and. "

The next step is to configure the broadcast registers. To do this, the processor unit 1.i writes to address RTi a word in which ones are written in digits K, t and 5, and zeros in other digits. This leads to the fact that the value in the i-th digits of registers 17 of the translation of processor blocks 1.K, 1.t, 1.5 is equal to one, and in ;" other processor units - zero.

The broadcast transfer of data from the 1st processor unit is performed in the cycle of writing a word to the address DTIi (see Fig. 3). At the beginning of the recording cycle, a word of data from the common bus 2 is written into the data register 16, and the address -I (Y) from the common bus 2 into the address register 15. At the same time, if the i-th digit of the translation register 17 of the processor unit contains a unit (in our example, only in processor units 1.K, 1.t and 1.5), then the control unit 18 produces signals under the influence of which the word from the output of the data register 16 is written into the communication memory at the -I address from the memory output of 11 addresses. After completion of the recording cycle in these processor units, the new address from the output of the register 13 to the next address through the multiplexer 14 is written into the address memory 11. - Synchronization of processor units 1.1,...,1.n during the solution of the given problem is performed using

Ge of information in the register of 9 commands. After the initialization of all processor units by the "Start" signal, their communication memories 10 are connected to the common bus 2 (see Fig. 4), while a unit is written in the OBM bit of the command register 9, which signals the control processor unit 1.1 about the possibility of bypassing data from Subordinate processor units 1.2,....1.1. As a result of this, the controlling processor unit 1.1 loads into the communication memories of 11 subordinate processor units 1.2,....1.n the data they need to start work. (F, Such data, for example, can be numbers of programs that will be solved by subordinate processor units, as well as addresses and dimensions of arrays of results that will be forwarded between processor units.

To remove the possibility of disconnecting the communication memory of the processor unit 1.i from the common bus 2 (for until the completion of the transfer of the entire array of results from the processor unit 1.), the bit indicating the duration of the exchange process OT.Y, which is located in the register 9U of the processor unit commands, can be used 1.i. At the beginning of the exchange, the processor unit 1.| writes a unit to this bit, and a zero after the exchange is completed. Thus, before switching the communication memory 10 from the common bus 2 to the local bus 6 of the processor unit 1.i, its processor 4 must check the identity of zero of all bits OT.K of its command register 9. 65 After transferring all the initial data to the subordinate processor units 1.2,...1.p, the control processor unit 1.1 successively starts them by writing a unit to the START bit of their 9 command register. After starting, the subordinate processor unit connects the communication memory 10 to the local bus 6 and overwrites all the data in its local memory 5, while the OBM bit in the command register 9 is zero, which indicates to other processor units that it is impossible to work with the communication memory yattyu 10 of this processor unit. After forwarding the data, the communication memory is again connected to the common bus 2 and becomes available for exchange with other processor units (OBM-1).

After executing all programs and forwarding all results to other processor units, the subordinate processor unit writes one to the GOT bit of its 9-command register. The controlling processor unit 1.1 expects the readiness of all processor units 1.1,...1.p, for which it analyzes the value of bit 7/0 GOT in register 9 of commands of subordinate processor units using the polling method. It is possible to reduce the time to determine the readiness of all subordinate processors with the help of an interruption signal, which will be generated in the control processor unit 1.1 after writing units to the GOT digits of all subordinate processor units 1.2,..., 1.p.

Let's consider the transmission of a data array with the size of M words in M processor units with the translation method of transmission. What is the time required to perform this task in a multiprocessor system? Mang nom, (1) where 2 is the time of writing a word through the common bus.

The first term 2"M in formula (1) is the time to write array addresses in the communication memory in M processor blocks (one access to the common bus 2 for each processor block); the second term (2 - writing the setting word into the translation register (one access for all processor units); the third term Y2"M is the time to send an array of M words at once to the communication memories of M processor units.

The time for transferring a data array from one processor to several processors in a multiprocessor system that does not support translational data transfer is, respectively, sch t2-i2"MaeM"(2"M). (2) Fr

In formula (2), the second term determines the time of M-fold forwarding of an array of M words to communication memories

M different processor units.

Comparison of expressions (1) and (2) makes it possible to conclude that the proposed multiprocessor c system allows to reduce the time of transmission of one array of data to several processor units by approximately "-

M times, where M is the number of processor units to which these arrays are transferred.

Thus, the introduction of a translation register into a multiprocessor system allows to reduce the number of calls to the common system bus during data exchange due to the simultaneous forwarding of the same data to several processor units, which increases the performance of multiprocessor systems. - local bus b general bus 2 h 4 Z s Bivyborufunschi processing 10000000 FOUCO. " of the corresponding processor unit -1 395 Sources of information: 1. AS of the USSR Mo1571606, class C 06 E 15/16, 1988;

Her 2. A. p. USSR Mo 1683039, cl. at 06 E 15/76, 15/16; -1 3. Dec. stalemate. of Ukraine Mo38850, MKV at 06 E 15/76, 15/16. published 15.05.2001. Bul. Mo4.,

Claims (1)

Formulation of the invention Ko) A multiprocessor system containing processor units and external devices connected to each other by a common bus, each processor unit contains a processor, local memory, which are connected to each other by a local bus to which the first information input is connected - the output of the first switch, the first information input-output GF) of the second switch and the first information input-output of the command register, the second information input-output of the first switch is connected to the information input-output of the communication memory, the control input of which is connected to the first output of the control unit, the second output of which is connected to the control input of the first switch, the third output - to the control input of the address register, the fourth output - to the control input of the 60 data register, the fifth input-output - to the inputM-outputDoM control of the command register , the sixth - with the control input-output of the second switch, the seventh input-output - with the common bus, to which the second information input-output of the second switch is connected, the second information input-output of the command register, the information input of the address register and the information input of the data register, the output of which is connected to the data input of the first switch and to the first information input of the multiplexer, the output of which is connected to the data input of the address memory, the data output of which is connected to the address input of the first switch and to the information input of the address modification block, the output of which is connected to the information input of the next address register, the output of which is connected to the second information input of the multiplexer, the output of the address register is connected to the input of the memory address set of addresses, the control input of which is connected to the eighth output of the control unit, to the ninth, tenth and eleventh outputs of which are connected, respectively, the control input of the address modification block, the control input of the next address register, the control input of the multiplexer, which differs in that the processor unit is introduced the translation register, the output of which is connected to the input of the control unit, the twelfth output i which is connected to the control input of the translation register, the information input of which is connected to the common bus. s schi 6) s «- cha « and - - with . and? -I sh» -I - 70 Ko) ime) 60 b5